[go: up one dir, main page]

TW201100565A - Fabricating method of polycrystalline silicon thin film - Google Patents

Fabricating method of polycrystalline silicon thin film Download PDF

Info

Publication number
TW201100565A
TW201100565A TW099112329A TW99112329A TW201100565A TW 201100565 A TW201100565 A TW 201100565A TW 099112329 A TW099112329 A TW 099112329A TW 99112329 A TW99112329 A TW 99112329A TW 201100565 A TW201100565 A TW 201100565A
Authority
TW
Taiwan
Prior art keywords
film
insulating layer
conductive film
center
amorphous germanium
Prior art date
Application number
TW099112329A
Other languages
Chinese (zh)
Inventor
Jae-Sang Ro
Won-Eui Hong
Original Assignee
Ensiltech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ensiltech Corp filed Critical Ensiltech Corp
Publication of TW201100565A publication Critical patent/TW201100565A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/326—Application of electric currents or fields, e.g. for electroforming

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Silicon Compounds (AREA)

Abstract

A method of fabricating a polycrystalline silicon (poly-Si) thin film is provided. In the method, poweris applied to a conductive thin film to generate Joule heart, and a poly-Si thin film is fabricated by the Joule heat. Thus, the method can provide, at a low voltage, the same crystallization characteristic as at a high voltage and reduce production time and production cost. In the method of fabricating a poly-Si thin film, in which a first insulating layer, an amorphous silicon (a-Si) thin film, a second insulating layer, and a conductive thin film are sequentially formed on a substrate, and the a-Si thin film is crystallized by high heat generated by applying an electric field to the conductive thin film using electrodes, theelectrodes are disposed at the center and both ends of a range in which the electric field will be applied, and the electric field is applied while a predetermined voltage is applied to an electrode disposed at the center and electrode disposed at the ends are grounded.

Description

201100565 六、發明說明： 【發明所屬之技術領域】 剛本發明係關於-種多晶發（poly_Si)薄膜製造方法 特定言之係關於一種藉由施加電力於一導電薄媒而產 焦耳熱的多晶石夕薄膜製造方法，其能夠在—低電壓提供 與在-高電壓下相同的結晶特性，且降低製造時間及生 產成本。 【先前技術】 闺—般而言，非μ (a'Si)的缺點包含作為電荷載子之 電子的低遷移率和—低孔徑_及不適用於互補金屬氣 化物半導體（CMOS)製程的缺點。 另-方面’多晶碎（p〇ly_Si)薄族器件讓將_視訊信號 寫入-像素及-像素薄膜電晶體（TFT)陣列内所需的驅 動電路能夠安裝在同-基板上，此應用在非晶石夕m是不 可行的。 因此’在多晶㈣媒器㈣，不需要複數個端子與一驅 動器積體電路uc)間之—連接，且有可能提升生產率 和可靠度且減小面板厚度。 又’在一多晶石夕TFT製程中，可使用矽大尺寸集成（⑶ )微處理技術’且可形成一微互連部等。 因此，對於安裝在驅動器1C上之膠帶自動接合（TAB)沒 有存在於非晶矽TFT的節距限制，故像素可輕易地縮小且 可在一窄小視角内施行多個像素。 相較於將非晶矽用於一有源層的TFT，在使用此種多晶矽 的TFT中，切換能力為高且有源層之通道位置係由自對準 作用決定，且因此可達成器件之微型化及CMOS器件之施 099112329 表單編號A0101 第4頁/共26頁 〇99ί 201100565 行。 因為這些理由’將多晶矽TFT用作一主動矩陣式平板顯示 器（譬如液晶顯示器（LCD)或有機發先二極體（〇LED) 顯示裝置）之像素切換器件，且已受注目作為大型螢幕 之施行及具有埋入式驅動器之玻璃基板晶片（C〇G)產品 之實際使用的重要器件。 多晶矽TFT可藉由在高溫及低溫二者進行的製程製造。就 一尚溫製程來說’基板必須由昂貴材料譬如石英構成，201100565 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for manufacturing a polycrystalline silicon (poly-Si) film, in particular, a method for producing a Joule heat by applying electric power to a conductive thin medium. A method for producing a spar film capable of providing the same crystallization characteristics at a low voltage and at a high voltage, and reducing manufacturing time and production cost. [Prior Art] In general, the disadvantages of non-μ (a'Si) include low mobility of electrons as charge carriers and low aperture _ and disadvantages not applicable to complementary metal hydride semiconductor (CMOS) processes. . Another aspect of the 'p〇ly_Si' family of thin-film devices allows the _video signal to be written into the pixel-and-pixel thin-film transistor (TFT) array to be mounted on the same substrate. In the amorphous stone eve m is not feasible. Therefore, in the polycrystalline (tetra) medium (four), connection between a plurality of terminals and a driver integrated circuit uc) is not required, and it is possible to improve productivity and reliability and to reduce panel thickness. Further, in a polycrystalline TFT process, a large-scale integrated ((3)) micro-processing technique can be used and a micro-interconnect or the like can be formed. Therefore, since the tape automatic bonding (TAB) mounted on the driver 1C does not exist in the pitch limitation of the amorphous germanium TFT, the pixel can be easily reduced and a plurality of pixels can be performed in a narrow viewing angle. Compared with a TFT using amorphous germanium for an active layer, in a TFT using such a polysilicon, the switching ability is high and the channel position of the active layer is determined by self-alignment, and thus the device can be achieved. Miniaturization and CMOS device application 099112329 Form number A0101 Page 4 of 26 〇99ί 201100565 line. For these reasons, the polycrystalline germanium TFT is used as a pixel switching device for an active matrix flat panel display such as a liquid crystal display (LCD) or an organic light emitting diode (〇LED) display device, and has been attracting attention as a large screen. And an important device for practical use of glass substrate wafer (C〇G) products with embedded drivers. Polycrystalline germanium TFTs can be fabricated by processes performed at both high and low temperatures. For a warm process, the substrate must be made of expensive materials such as quartz.

且因此高溫製程不適合大型螢幕之释行。 因此，已對於大規模地使非晶矽薄膜在低溫下結晶化為 多晶石夕薄膜的方法進行積極研究。 用於形成多晶矽的低溫技術包含固相結晶化（spc)、金 屬誘致結晶化（MIC)、金屬誘致侧向結晶k (milc)、 準分子雷射結晶化（ELC)等技術。 在SPC中，可利用低成本設備獲得一致晶體品質。但是， SPC要求一咼結晶溫度和一長處理時閟，且因此具有低生 ❹ 產率。又，無法使用具有相對較低熱撓曲溫度之基板， 譬如玻璃基板。 在SPC中’非晶矽薄膜通常必須在6〇〇艽至7〇〇<^的溫度 退火大約1至24小時使非晶石夕薄膜能夠結晶化。 此外在SPC中’在從非晶相轉變成晶體相的固態相變過 程中會觀察到雙晶生長。因此，在成型晶粒巾會含有許 多晶格缺陷。 這些因素降低電子遷移率及電洞遷料且提高製得多晶 矽TFT之臨界電壓。 MIC的好處在於結晶化作用係在一遠低於SPC的溫度完成 099112329 表單編號A0101 * - ^ 頁/共 26 頁 0993293765-0 201100565 ’因為非晶矽與一特定金屬保持接觸。 用於MIC的金屬包含Ni、Pd、Ti、A1、Ag、Au、Co、Cu 、Fe ' Mn等’這些金屬與非晶石夕發生反應且形成一共溶 合金相或矽化物相以促進低溫結晶化作用。 但是，當MIC施用於一製造多晶矽TFT的實際製程時，這 些金屬在通道中造成嚴重污染。 MILC是MIC的一種應用技術’其中不沈積金屬而是在一通 道上形成一閘極，使薄金屬在一自對準結構中沈積於一 源極和一没極上以引發金屬誘致結晶化作用，然後誘發 朝該通道之侧向結晶作用。 用於MILC的常見金屬包含Ni和Pd。相較於由SPC形成的 多晶石夕，由ΜILC形成的多晶勢具有較佳結晶度及高場效 遷移率，但已知具有高漏電流。 換句話說，MILC相較於MIC降低金屬污染，但並未完全解 決此問題。 在此同時，有一種場輔助侧向結晶化(FALC)作為MILC 之改良技術。相較於MILC，FALCi：現一高結晶速率及結 晶方向之各向異性，但依然未完全解決金屬污染問題。 上述MIC、MILC及FALC相較於SPC全都有效於降低結晶溫 度’但具有長結晶時間及由金屬誘發結晶化作用的共同 缺點。因此，這些技術全都未能免除金屬污染。 在此同時，新近開發的ELC能夠藉由一低溫製程在玻璃基 板上製得多晶矽薄膜同時避免金屬污染。 換句話說，由低壓化學氣相沈積（LPCVD)或電漿增強化 學氣相沈積（PECVD)沈積的非晶矽薄膜對於準分子雷射 波長的紫外線範圍（又= 308 nm)有極高吸收係數，且 099112329 第6頁/共26頁 表單編號A0101 201100565 因此易於在一適當能量密度溶化。 當此-非晶㈣膜SI準分子雷射而結晶化時，溶化及固 化程序係在-極短時間長度㈣騎。因此之故，嚴格 來說，ELC並非低溫製種。 但在ELC中’結晶化作用係由在__受準分子雷射大幅影響 之局部熔化區域中非常快速地進行的熔化及固化作用完 成。因此，有可能在-極短時間長度（數十個毫微秒） 内形成多晶石夕而不傷到基板。And therefore the high temperature process is not suitable for the release of large screens. Therefore, active research has been conducted on a method of crystallizing an amorphous germanium film into a polycrystalline film at a low temperature on a large scale. Low temperature techniques for forming polycrystalline germanium include solid phase crystallization (spc), metal induced crystallization (MIC), metal induced lateral crystallization k (milc), and excimer laser crystallization (ELC). In SPC, consistent crystal quality can be achieved with low cost equipment. However, SPC requires a crystallization temperature and a long treatment time, and thus has a low yield. Also, substrates having relatively low heat deflection temperatures, such as glass substrates, cannot be used. In the SPC, the amorphous germanium film usually has to be annealed at a temperature of 6 Torr to 7 Torr for about 1 to 24 hours to crystallize the amorphous film. Further, in the SPC, twin growth is observed in the solid phase transition from the amorphous phase to the crystalline phase. Therefore, the molded grain towel will contain many lattice defects. These factors reduce electron mobility and hole relocation and increase the threshold voltage of the monocrystalline TFT. The benefit of the MIC is that the crystallization is done at a temperature well below the SPC. 099112329 Form No. A0101 * - ^ Page / Total 26 Pages 0993293765-0 201100565 'Because the amorphous germanium remains in contact with a particular metal. The metal used for the MIC includes Ni, Pd, Ti, A1, Ag, Au, Co, Cu, Fe' Mn, etc. These metals react with the amorphous phase and form a eutectic alloy phase or a bismuth phase to promote low temperature crystallization. Chemical effect. However, when the MIC is applied to an actual process for fabricating a polycrystalline germanium TFT, these metals cause serious contamination in the channel. MILC is an application technology of MIC, in which a metal is not deposited but a gate is formed on a channel, so that a thin metal is deposited on a source and a gate in a self-aligned structure to induce metal induced crystallization. Lateral crystallization towards the channel is then induced. Common metals for MILC include Ni and Pd. The polycrystalline potential formed by yttrium ILC has better crystallinity and high field-effect mobility compared to polycrystalline spine formed by SPC, but is known to have high leakage current. In other words, MILC reduces metal contamination compared to MIC, but does not completely address this issue. At the same time, there is a field-assisted lateral crystallization (FALC) as an improved technique for MILC. Compared to MILC, FALCi: the anisotropy of high crystallization rate and crystal orientation, but still does not completely solve the metal pollution problem. The above MIC, MILC and FALC are all effective in reducing the crystallization temperature as compared with SPC, but have the common disadvantage of long crystallization time and metal-induced crystallization. Therefore, none of these technologies have been able to eliminate metal contamination. At the same time, the newly developed ELC is capable of fabricating a polycrystalline silicon film on a glass substrate by a low temperature process while avoiding metal contamination. In other words, amorphous germanium films deposited by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) have very high absorption coefficients for the ultraviolet range of the excimer laser wavelength (again = 308 nm). And 099112329 Page 6 of 26 Form No. A0101 201100565 It is therefore easy to dissolve at an appropriate energy density. When this -amorphous (tetra) film SI excimer laser is crystallized, the melting and solidification process is carried out in a very short time length (four). For this reason, strictly speaking, ELC is not a low-temperature seed. However, in ELC, the crystallization is accomplished by melting and solidification very rapidly in the localized melting zone which is greatly affected by the __excimer laser. Therefore, it is possible to form polycrystalline spine in a very short time length (tens of nanoseconds) without injuring the substrate.

換句話說’當-雷射施加於包含一玻璃基板/一絕緣層/ 一非晶矽薄膜的結構之非晶矽極短時間時，僅有該非晶 矽薄膜被選擇择地加熱及結晶牝而不傷到下層玻璃基板 O I.·?. Η 又，相較於由固相結晶化作用形成的多晶發，由液態變 成固態之相變作用形成的多晶矽具有一熱力學穩定的晶 粒結構且顯著地減少晶粒中之晶體缺陷。因此，由ΕΙχ形 成的多晶矽具有優於申其他結晶化技術形成之多晶矽的 特性。 ' ^ ' ί / ' 然而，ELC有幾個關鍵性缺點。 舉例來說，雷射系統之一問題為雷射束輻射的量不一致 ，雷射處理之一問題為用以獲得粗糙大晶粒之雷射能量 密度的處理區域極其有限，另一問題為大面積的照射痕 跡。 這些問題導致建構多晶矽TFT有源層之多晶矽薄膜的晶粒 大小不一致。又’隨著液態變成固態之相變作用產生的 多晶矽涉及體積膨脹，且因此會從形成晶粒邊界之一點 朝一表面形成明顯突起。 099112329 表單煸號A0101 第7頁/共26頁 0993293765-0 201100565 此突起直接影響後續程序中形成之—閘絕緣層，從而因 為多晶石夕與閘絕緣層間之一界面的平坦度不一致導致崩 潰電壓降低且導致器件可靠度譬如熱載子應力降低。 最近已開發出時序侧向固化（SLS)以解決上述ELC之不 穩定性，使得雷射能量密度之處理區域可被成功地穩定 但是，照射痕跡及朝向表面之突起的問題仍未解決。鑑 於當前平板顯示器產業之快速研發的趨勢，將雷射用於 早晚會被大量生產之1 mxl m以上基板之結晶化製程的技 術仍有問題。 此外，用於ELC和SLS的設備非常昂貴，且需要高起始投 資及維護成本。 ; 據此，需要一種用於非晶砍薄膜的結晶化技術，其不僅 要克服輻射量依據一局部處理為不一致、處理區域有限 、且必須使用昂貴設備之雷射結晶化的缺點，還要有下 層基板不因快速處理而受Μ及可籍由高連_變製得幾乎 無瑕之尚品質晶粒的好處。 特定言之，新近引人注目應用於次世代平板顯示器的主 動矩陣式有機發光二極體相較於採用電壓驅動類塑之TFT 液晶顯示器（LCD)係採用電流驅動類型，且因此晶粒大 小之一致性對於大型基板來說係一非常重要的因子° 因此之故，由ELC或SLS進行的低溫結晶化作用面臨其在 當前平板顯示器產業中之極限。有鑑於此，急切需要藉 由不使用雷射之低溫結晶化作用製造高品質多晶矽薄嫉 的新技術。 第 0993293765-0 為解決這些習知問題，本發明人已在韓國專利申請案 099112329 表單編號A0101 第8頁/共26頁 201100565 2007-0021 252號中提出一種結晶方法，其中在矽薄膜上 或底下形成一導電薄膜，然後藉由施加一電場而進行焦 耳加熱作用以完成結晶化作用。 在一習知多晶矽薄膜製造方法中，將一非晶矽薄膜、一 絕緣層及一導電薄膜堆疊於一基板上，在該導電薄膜之 兩端設置電極端子，然後藉由向該等電極端子施加一電 場產生焦耳熱而使該非晶矽薄膜結晶化。 但是，隨著基板大小增加，待施加的電壓逐漸提高，且 必須準備能夠施加高電壓的設備。因此，設備成本及生 產成本提而。 又，當施加一高電壓時，該高電壓可能透過進行結晶化 製程之隔室的外壁對於安裝在該隔室之外的設備造成嚴 重影響。因此，該隔室亦必須使用高性能設備以即使在 高電壓下亦防止電介質崩潰，這提高設備成本及生產成 本。 【發明内容】 [0003] 【技術問題】 本發明針對提出一種多晶矽（poly-Si )薄膜製造方法， 其能夠降低設備成本及生產成本，且即使是施加一低電 壓也會形成具有與在一高電壓下形成之多晶矽薄膜相同 特性的多晶矽薄膜。 【技術解決方案】 本發明之一觀點提出一種多晶矽（poly-Si)薄膜製造方 法，包含在一基板上依序形成一第一絕緣層、一非晶石夕 (a-Si )薄膜、一第二絕緣層、及一導電薄膜，且利用 經由電極施加一電場至該導電薄膜而產生的高熱使該非 099112329 表單編號A0101 第9頁/共26頁 0 201100565 晶碎薄膜結晶化，其中該等電極係設置在欲施加該電場 之一範圍的中心及兩端，且該電場係在一預定電壓施加 於一設置在該中心之電極且設置於兩端之電極接地之時 施加。 本發明之另一觀點係提出一種多晶矽薄膜製造方法，包 含在一基板上依序形成一第一絕緣層、一導電薄膜、一 第二絕緣層、及一非晶矽（a-Si)薄膜，且利用經由電 極施加一電場至該導電薄膜而產生的高熱使該非晶矽薄 膜結晶化，其中該等電極係設置在欲施加該電場之一範 圍的中心及兩端，且該電場係在一預定電壓施加於一設 置在該中心之電極且設置於兩端之電極接地之時施加。 【有利功效】 使用依據本發明一範例實施例之多晶矽（poly-Si)薄膜 製造方法，有可能即使是施加一低電壓也會製得具有與 在一高電壓下形成之多晶矽薄膜相同特性的多晶矽薄膜 〇 又，不需要重複施加一電場，故處理時間可縮短。此外 ，不需要施加一高電壓，且不需要設備之替換或是導電 薄膜、隔室、絕緣層等之材料之改變，故可降低設備成 本及生產成本。 【實施方式】 [0004] 以下將詳細說明本發明之範例實施例。然本發明不侷限 於以下揭示之範例實施例，而是可以多種不同形式施行 。以下範例實施例係為了讓熟習此技藝者有能力實施實 行本發明。 第1圖至第4圖是例示依據本發明一第一範例實施例之非 099112329 表單編號A0101 第10頁/共26頁 0! 201100565 晶矽（a-Si)薄膜結晶方法的剖面圖》 在依據第一範例實施例的非晶矽薄膜結晶方法中，在一 基板10上依序形成一第一絕緣層2〇、一非晶石夕薄媒、 一第二絕緣層40、及一導電薄膜50。 明確地說，在基板1〇上依序形成第一絕緣層2〇、非晶梦 薄膜30、第二絕緣層4〇、及導電薄膜50 ’且藉由施加一 電場至導電薄膜50造成焦耳加熱作用而產生高熱，從而 利用該高熱使非晶矽薄膜30結晶化。 Ο 該電場可經由與導電薄膜50接觸且與一電壓源Vs連接的 電極6 0施加。 其中，該電場係施加於欲施加電場之一範圍的大約中心 及兩端。一正電位電壓施加於中心，且兩端接地。 儘管此範例實施例敘述施加於中心的電壓是一正電位電 壓，施加於中心的電壓可為一負電位電壓。 Ο 基板10之材料不侷限於一特定材料。舉例來說，可使用 一透明基板材料譬如玻璃、石矣或塑膠作為此材料，且 玻璃因經濟因素而為較佳。但注意最近在平板顯示器領 域中的研究趨勢，多數研究係放在塑膠基板等等上，其 具有優異的抗衝擊能力及生產率，且本發明之一範例實 施例亦可施用於塑膠基板》 第一絕緣層20係用來防止基板10内之物質（例如可能在後 續程序中產生之玻璃基板鹼性物質）的洗提作用。一般而 言’第一絕緣層20係由沈積二氧化矽（SiO)或氮化矽 L· 而形成。第一絕緣層20通常可被形成為2000 A至5000 A 之厚度’然厚度不侷限於此等數值。 視科技研發程度而定，非晶矽薄膜3〇可被直接形成在基 099112329 表單編號A0101 第11頁/共26頁 0993293765-0 201100565 板10上而沒有第—絕緣層20。由於依據本發明一範例實 施例之方法可施用於此一結構，應解釋為本發明之範圍 包含此種結構。 換句話說’第—絕緣層20可依據執行製程之環境或條件 而選擇性地施用於本發明。 非晶#薄膜30舉例來說可為藉由低壓化學氣相沈積（LP-CVD) '高壓化學氣相沈積（HPCVD)、電漿增強化學氣 相沈積CPECVD)、賴、或真空縫形成，且較佳使用 PECVD ° —般而言’非晶矽薄膜30之厚度較佳為300 A至 1〇〇〇 A ’然形成方法專厚度不侷限於此範例實施例。 非晶石夕薄膜3〇之一些部分與導電薄膜5〇或電極6〇接觸以 待藉由施加一電場所產生之焦耳熱面結晶化9 第一絕緣層4 0係用來防止非晶矽薄膜3 0在一退火程序期 間被導電薄膜5 G污染及電絕緣非晶碎薄膜3 Q與導電薄膜 50。 般而δ，第二絕緣層4〇可由與第一絕緣層2〇相同的材 料構成，且可使用對於非晶矽薄膜30具有小幅影響、具 有介電特質及高熔點的任何材料。 導電薄膜5G係-導電材料薄膜，且可藉由祕、蒸錢等 方式形成。較佳來說導電薄膜5〇具有一致厚度使得導電 薄膜50可在藉由施加—電場而被隨後進行之焦耳加熱作 用期間被均勻加熱。 在一電場施加於導電薄膜50之前，組件1〇、2〇、3〇、4〇 、及50或者至少基板10可經預熱至一適當溫度範圍。適 當溫度範圍意指於整個製程當中基板1〇不會受損的溫度 。預熱方法沒有限 0993293765-0 範圍且較佳低於基板10之熱撓曲溫度 099112329 表單編號Α0101 第12頁/共26頁 201100565 制，且舉例來說可將基板10導入一通用熱處理爐内、由 一燈之轄射熱加熱、或諸如此類。 如前所述，依據本發明之一範例實施例，當一電場施加 於導電薄膜50以產生一多晶矽（poly-Si )薄膜時，一 正或負電位電壓係施加於將要結晶化之一區域的大約中 心，且兩端係接地。 其中，欲施加正或負電位電壓的位置較佳係設置在接地 兩端的中間。 ❹ 當欲施加正或負電位電壓的位置偏往兩端之一者時，結 晶化作用不會均勻地發生，且依據位置會獲得不同特性 上述方法亦可用來使一小區域結晶化，但更有效率地用 來使一大區域結晶化。 當結晶化作用係藉由施加一電場至兩端的傳統方式進行 時，隨著要被結晶化的面積增加，施加電場的次數必須 增加，或者必須施加相較於小區域之情況為高的電壓。 ❹ 當一電場被重複施加時，電場必須以數秒之時間間隔施 加以防因累積熱量造成不一致。因此，施加電場的次數 越多，結晶化的總處理時間越長。 又，為施加高電壓，必須用一能夠輸出高電壓的裝置取 代一用於施加低電壓的裝置，且因此生產成本提高。此 係因為每個電壓施加裝置有其最大輸出電壓，且用於施 加低電壓的裝置無法施加高電壓。 再者，當施加高電壓時，結晶化作用係藉由高熱完成， 這可能傷到一導電薄膜。當導電薄膜受損時，無法確保 099112329 穩定性。因此，導電薄膜必須是一不因高熱而受損的材 表單編號A0101 第13頁/共26頁 0993293765-0 201100565 料，且必須由一不同於傳統材料的材料構成，這提高生 產成本。 當一非晶矽薄膜或該非晶矽薄膜之—部分具有導電性且 該非晶矽薄膜與一導電薄膜之間的電位差變成大於—絕 緣層之崩潰電壓時，會產生一電弧。 因此，當施加尚電壓時，非晶石夕薄膜3 〇與導電薄膜$ 〇之 間的電位差加大。為避免電弧，安插在非晶矽薄膜3〇與 導電薄膜50之間的絕緣層的崩潰電壓必須提高，且因此 材料特性必須改變。 又，當施加高電壓時，高電座可能透過進行結晶化製程 之隔室的外壁對於安裝在該隔室之外的設備造成嚴重影 響。因此，該隔室亦必須使用高性能設備以即使在高電 壓下亦防止電介質崩潰，這提高設備成本及生產成本。 然而，利用依據本發明一範例實施例之製造方法，有可 能即使是施加一低電壓也會形成具有與在一高電壓下形 . i. ；： 成之多晶石夕薄膜相同特性的多晶梦薄膜。 ’故處理、時間可縮短。此外’ 不需要施加高電壓，且不需要設備乏替換或是導電薄膜 、隔室、絕緣層等之材料之改變，故可降低設備成本及 生產成本。 如第1圖所示，導電薄膜5〇除了形成於第二絕緣層40之上 表面還形成於被提供在第二絕緣層4〇之中心及兩端的空 隙，且經形成於第二絕緣層4〇之中心及兩端的導電薄膜 50係與非晶矽薄膜30接觸。 又，如第2圖所示，該等空隙除了被提供在第二絕緣層40 099112329 又，不需要重複施加電場In other words, when the amorphous laser is applied to a structure comprising a glass substrate/an insulating layer/an amorphous germanium film for a short time, only the amorphous germanium film is selectively heated and crystallized. Does not damage the underlying glass substrate O I.·?. Η Further, compared to the polycrystalline hair formed by solid phase crystallization, the polycrystalline germanium formed by the liquid phase to solid phase transformation has a thermodynamically stable grain structure and Significantly reduce crystal defects in the grains. Therefore, polycrystalline germanium formed by tantalum has characteristics superior to those of polycrystalline germanium formed by other crystallization techniques. ' ^ ' ί / ' However, ELC has several key drawbacks. For example, one problem with laser systems is that the amount of laser beam radiation is inconsistent. One of the problems with laser processing is that the processing area for obtaining the laser energy density of coarse and large grains is extremely limited, and the other problem is large area. Traces of the illumination. These problems have led to inconsistent grain sizes of polycrystalline germanium films which are constructed of polycrystalline germanium TFT active layers. Further, the polycrystalline germanium produced by the phase change of the liquid state into a solid state involves volume expansion, and thus a prominent protrusion is formed from a point where a grain boundary is formed toward a surface. 099112329 Form nickname A0101 Page 7 of 26 0993293765-0 201100565 This protrusion directly affects the gate insulation formed in the subsequent procedure, resulting in a breakdown voltage due to the inconsistent flatness of the interface between the polysilicon and the gate insulation. Reduced and leads to device reliability such as reduced thermal carrier stress. Time-series lateral solidification (SLS) has recently been developed to address the above-described ELC instability such that the processing area of the laser energy density can be successfully stabilized. However, the problem of illumination marks and protrusions toward the surface remains unresolved. In view of the current rapid development trend of the flat panel display industry, there is still a problem in the technology of using a laser for the crystallization process of a substrate of 1 mxl or more which will be mass-produced in the morning and evening. In addition, equipment for ELC and SLS is very expensive and requires high initial investment and maintenance costs. Accordingly, there is a need for a crystallization technique for amorphous chopped film that not only overcomes the disadvantages of the amount of radiation that is inconsistent with a partial treatment, has a limited processing area, and must be laser crystallized using expensive equipment, but also has The underlying substrate is not subject to rapid processing and can be modified to produce virtually flawless quality grain benefits. In particular, the active matrix organic light-emitting diodes that have recently attracted attention for next-generation flat panel displays use current-driven types compared to voltage-driven TFT liquid crystal displays (LCDs), and therefore the grain size Consistency is a very important factor for large substrates. Therefore, low temperature crystallization by ELC or SLS faces its limits in the current flat panel display industry. In view of this, there is an urgent need for a new technology for producing high-quality polycrystalline silicon crucibles without using low-temperature crystallization of lasers. In order to solve these conventional problems, the present inventors have proposed a crystallization method in the Korean Patent Application No. 099112329, Form No. A0101, No. 8/26, No. 201100565, 2007-0021, 252, on or under A conductive film is formed, and then Joule heating is performed by applying an electric field to complete crystallization. In a conventional method for fabricating a polycrystalline silicon film, an amorphous germanium film, an insulating layer and a conductive film are stacked on a substrate, electrode terminals are disposed at both ends of the conductive film, and then applied to the electrode terminals. An electric field generates Joule heat to crystallize the amorphous tantalum film. However, as the substrate size increases, the voltage to be applied gradually increases, and a device capable of applying a high voltage must be prepared. Therefore, equipment costs and production costs are increased. Also, when a high voltage is applied, the high voltage may seriously affect the equipment installed outside the compartment through the outer wall of the compartment in which the crystallization process is performed. Therefore, the compartment must also use high-performance equipment to prevent dielectric breakdown even at high voltages, which increases equipment cost and production cost. SUMMARY OF THE INVENTION [0003] The present invention is directed to a method for fabricating a polycrystalline silicon (poly-Si) film, which can reduce equipment cost and production cost, and even if a low voltage is applied, it is formed with a high A polycrystalline germanium film having the same characteristics as a polycrystalline germanium film formed under a voltage. [Technical Solution] One aspect of the present invention provides a polycrystalline silicon (poly-Si) film manufacturing method comprising sequentially forming a first insulating layer, an amorphous a-Si film, and a first substrate on a substrate. a second insulating layer, and a conductive film, and the high heat generated by applying an electric field to the conductive film via the electrode causes the non-zero layer 9910 329 Form No. A0101 to be crystallized, wherein the electrode system is The center and both ends of a range in which the electric field is to be applied are disposed, and the electric field is applied when a predetermined voltage is applied to an electrode disposed at the center and the electrodes disposed at both ends are grounded. Another aspect of the present invention provides a method for fabricating a polysilicon film comprising sequentially forming a first insulating layer, a conductive film, a second insulating layer, and an amorphous germanium (a-Si) film on a substrate. And crystallizing the amorphous germanium film by using a high heat generated by applying an electric field to the conductive film via an electrode, wherein the electrodes are disposed at a center and both ends of a range in which the electric field is to be applied, and the electric field is at a predetermined time The voltage is applied when an electrode disposed at the center and the electrodes disposed at both ends are grounded. [Advantageous Effects] Using a polycrystalline silicon (poly-Si) thin film manufacturing method according to an exemplary embodiment of the present invention, it is possible to obtain a polycrystalline silicon having the same characteristics as a polycrystalline germanium thin film formed at a high voltage even if a low voltage is applied. In addition, the film does not need to be repeatedly applied with an electric field, so the processing time can be shortened. In addition, there is no need to apply a high voltage, and there is no need to replace the device or change the material of the conductive film, the compartment, the insulating layer, etc., thereby reducing equipment cost and production cost. [Embodiment] Hereinafter, exemplary embodiments of the present invention will be described in detail. However, the present invention is not limited to the exemplary embodiments disclosed below, but can be implemented in many different forms. The following exemplary embodiments are intended to enable those skilled in the art to practice the invention. 1 to 4 are diagrams illustrating a non-zero-single pattern of the first embodiment of the present invention, which is based on a first exemplary embodiment of the present invention, Form No. A0101, Page 10 of 26, 2011! In the amorphous ruthenium film crystallization method of the first exemplary embodiment, a first insulating layer 2, an amorphous thin dielectric, a second insulating layer 40, and a conductive film 50 are sequentially formed on a substrate 10. . Specifically, the first insulating layer 2, the amorphous dream film 30, the second insulating layer 4, and the conductive film 50' are sequentially formed on the substrate 1 and Joule heating is caused by applying an electric field to the conductive film 50. The action generates high heat, and the amorphous germanium film 30 is crystallized by the high heat. Ο The electric field can be applied via an electrode 60 that is in contact with the conductive film 50 and is connected to a voltage source Vs. Here, the electric field is applied to approximately the center and both ends of a range in which an electric field is to be applied. A positive potential voltage is applied to the center and grounded at both ends. Although this exemplary embodiment describes that the voltage applied to the center is a positive potential voltage, the voltage applied to the center can be a negative potential voltage.材料 The material of the substrate 10 is not limited to a specific material. For example, a transparent substrate material such as glass, stone enamel or plastic can be used as the material, and the glass is preferred for economic reasons. However, attention has been paid to recent research trends in the field of flat panel displays. Most of the research is on plastic substrates and the like, which have excellent impact resistance and productivity, and an exemplary embodiment of the present invention can also be applied to plastic substrates. The insulating layer 20 serves to prevent elution of substances in the substrate 10, such as a glass substrate alkaline substance that may be produced in a subsequent process. In general, the first insulating layer 20 is formed by depositing cerium oxide (SiO) or tantalum nitride L·. The first insulating layer 20 can be generally formed to a thickness of 2000 A to 5000 A. However, the thickness is not limited to these values. Depending on the degree of research and development, the amorphous germanium film 3 can be formed directly on the substrate 099112329 Form No. A0101 Page 11 of 26 0993293765-0 201100565 Plate 10 without the first insulating layer 20. Since the method according to an exemplary embodiment of the present invention can be applied to such a structure, it should be construed that the scope of the present invention encompasses such a structure. In other words, the 'first insulating layer 20' can be selectively applied to the present invention depending on the environment or conditions under which the process is performed. The amorphous # film 30 may be formed by low pressure chemical vapor deposition (LP-CVD) 'high pressure chemical vapor deposition (HPCVD), plasma enhanced chemical vapor deposition CPECVD), La, or vacuum slit, for example, and Preferably, PECVD is used. Generally, the thickness of the amorphous germanium film 30 is preferably 300 A to 1 A. The thickness of the method is not limited to this exemplary embodiment. Some portions of the amorphous iridium film 3〇 are in contact with the conductive film 5〇 or the electrode 6〇 to be crystallized by the Joule hot surface generated by applying an electric field. The first insulating layer 40 is used to prevent the amorphous germanium film. 30 is contaminated by the conductive film 5 G and electrically insulating the amorphous film 3 Q and the conductive film 50 during an annealing process. Similarly, δ, the second insulating layer 4〇 may be composed of the same material as the first insulating layer 2, and any material having a small influence on the amorphous germanium film 30, having a dielectric property and a high melting point may be used. The electroconductive thin film 5G is a thin film of a conductive material, and can be formed by secret, steaming, or the like. Preferably, the electroconductive thin film 5 has a uniform thickness such that the electroconductive thin film 50 can be uniformly heated during Joule heating which is subsequently performed by applying an electric field. The components 1〇, 2〇, 3〇, 4〇, and 50 or at least the substrate 10 may be preheated to an appropriate temperature range before an electric field is applied to the conductive film 50. The proper temperature range means the temperature at which the substrate will not be damaged during the entire process. The preheating method is not limited to the range of 0993293765-0 and is preferably lower than the heat deflection temperature of the substrate 10 099112329, the form number Α0101, page 12/26 pages 201100565, and for example, the substrate 10 can be introduced into a general heat treatment furnace, Heated by a lamp, or the like. As described above, according to an exemplary embodiment of the present invention, when an electric field is applied to the conductive film 50 to produce a poly-Si film, a positive or negative potential voltage is applied to a region to be crystallized. It is approximately centered and grounded at both ends. Among them, the position at which the positive or negative potential voltage is applied is preferably set in the middle of both ends of the ground. ❹ When the position where the positive or negative potential voltage is applied is biased to one of the two ends, the crystallization does not occur uniformly, and different characteristics are obtained depending on the position. The above method can also be used to crystallize a small area, but Efficiently used to crystallize a large area. When the crystallization is carried out by a conventional method of applying an electric field to both ends, as the area to be crystallized increases, the number of times the electric field is applied must be increased, or a voltage higher than that in the case of a small area must be applied. ❹ When an electric field is applied repeatedly, the electric field must be applied at intervals of a few seconds to prevent inconsistencies due to accumulated heat. Therefore, the more the number of applied electric fields, the longer the total processing time for crystallization. Further, in order to apply a high voltage, it is necessary to replace a device for applying a low voltage with a device capable of outputting a high voltage, and thus the production cost is increased. This is because each voltage applying device has its maximum output voltage, and the device for applying a low voltage cannot apply a high voltage. Further, when a high voltage is applied, crystallization is completed by high heat, which may damage a conductive film. When the conductive film is damaged, the stability of 099112329 cannot be ensured. Therefore, the conductive film must be a material that is not damaged by high heat. Form No. A0101 Page 13 of 26 0993293765-0 201100565 Material, and must be composed of a material different from the conventional material, which increases the production cost. When an amorphous germanium film or a portion of the amorphous germanium film is electrically conductive and a potential difference between the amorphous germanium film and a conductive film becomes greater than a breakdown voltage of the insulating layer, an arc is generated. Therefore, when a voltage is applied, the potential difference between the amorphous thin film 3 〇 and the conductive film $ 加大 is increased. In order to avoid arcing, the breakdown voltage of the insulating layer interposed between the amorphous germanium film 3A and the conductive film 50 must be increased, and thus the material properties must be changed. Also, when a high voltage is applied, the high potential seat may cause a serious influence on the equipment installed outside the compartment through the outer wall of the compartment in which the crystallization process is performed. Therefore, the compartment must also use high-performance equipment to prevent dielectric breakdown even at high voltages, which increases equipment cost and production cost. However, with the manufacturing method according to an exemplary embodiment of the present invention, it is possible to form a polycrystal having the same characteristics as a polycrystalline film formed at a high voltage even if a low voltage is applied. Dream film. Therefore, the processing and time can be shortened. In addition, there is no need to apply a high voltage, and there is no need for equipment replacement or material changes in conductive films, compartments, insulation layers, etc., thereby reducing equipment costs and production costs. As shown in FIG. 1, the conductive film 5 is formed on the upper surface of the second insulating layer 40, and is formed in a gap provided at the center and both ends of the second insulating layer 4, and is formed on the second insulating layer 4. The conductive film 50 at the center and both ends of the crucible is in contact with the amorphous germanium film 30. Moreover, as shown in FIG. 2, the voids are provided in the second insulating layer 40 099112329, and no repeated application of an electric field is required.

之中心及兩端還可被提供在第二絕緣層40之中心與兩端 表單編號A0101 第14頁/共26頁 0993293765-0 201100565 之間。導電薄膜5 0亦可被形成在此等進一步提供的空隙 内且可為與非晶矽薄膜30接觸。 如第3圖所示，供一電壓施加的電極6〇可被設置於在第二 絕緣層40之中心及兩端提供的空隙以及導電薄膜5〇，且 可為與非晶矽薄膜3〇接觸。The center and both ends may also be provided at the center and both ends of the second insulating layer 40 between Form No. A0101, page 14 of 26, 0993293765-0 201100565. The conductive film 50 may also be formed in the voids further provided and may be in contact with the amorphous germanium film 30. As shown in FIG. 3, the electrode 6A for a voltage application can be disposed at the center and both ends of the second insulating layer 40 and the conductive film 5〇, and can be in contact with the amorphous germanium film 3〇. .

又’如第4圖所示，電極60可包含設置在導電薄膜50底下 的第—電極61及設置在導電薄膜50上的第二電極63。第 一電極61可被設置於在第二絕緣層40之中心及兩端提供 的空隙中且可為與非晶矽薄膜30接觸，且一電壓可施加 於第二電極63。 換句話說，非晶矽薄膜30可如第.1廚和第2圖所示與導電 薄膜50接觸或是如第3圖和第4圖所示與電極60接觸。 其中，該等空隙可為藉由以卞方式提梹於第二絕緣層40 或導電薄膜50中：形成整個第二絕緣層40或整個導電薄 膜50然後去除第二絕緣層40或導電薄膜50之一些部分； 或是在形成第二絕緣層4〇或導電薄膜50的過程當中利用Further, as shown in Fig. 4, the electrode 60 may include a first electrode 61 disposed under the conductive film 50 and a second electrode 63 disposed on the conductive film 50. The first electrode 61 may be disposed in a gap provided at the center and both ends of the second insulating layer 40 and may be in contact with the amorphous germanium film 30, and a voltage may be applied to the second electrode 63. In other words, the amorphous germanium film 30 can be in contact with the conductive film 50 as shown in Fig. 1 and Fig. 2 or in contact with the electrode 60 as shown in Figs. 3 and 4. Wherein, the voids may be lifted in the second insulating layer 40 or the conductive film 50 in a meandering manner: forming the entire second insulating layer 40 or the entire conductive film 50 and then removing the second insulating layer 40 or the conductive film 50 Some portions; or utilized in the process of forming the second insulating layer 4 or the conductive film 50

一遮罩等等防止第二絕緣層40或導電薄膜50之一些部分 形成。 5 第5圖至第8圖是例示依據本發明一第二範例實施例之非 晶矽薄臈結晶方法的剖面圖。 除以下特別詳細敘述的細節外，第二範例實施例的說明 與第一範例實施例相同。 在依據第二範例實施例之非晶石夕薄膜結晶方法中，在一 基板10上依序形成一第一絕緣層20、一導電薄膜50、一 第二絕緣層40、及一非晶矽薄膜30。 更明確地說，在基板1〇上依序形成第一絕緣層20、導電 099112329 表單編號Α0101 第15頁/共26頁 0993293765-0 201100565 薄膜50、第二絕緣層40、及非晶矽薄膜3〇，且藉由施加 一電場至導電薄膜50造成焦耳加熱作用而產生高熱，從 而利用該高熱使非晶矽薄膜30結晶化。 如同第一範例實施例，電場係經由與導電薄膜5 0接觸且 與一電壓源Vs連接的電極60施加。 其中’該電場係施加於欲施加電場之一範圍的大約中心 及兩端，一正電位電壓施加於中心，且兩端接地。 儘管此fe例實施例敛述施加於中心的電壓是一正電位電 壓’施加於中心的電壓可為一負電位電壓。 非晶矽薄膜3 0之一些部分麵導電轉嫉⑽或電極6 〇接觸以 .... . .. ' 待藉由施加一電場所產生之焦耳熱而結晶化。 參照第5圖，在..第二絕緣層40·之中心及兩端提供空隙。形 成用以包圍第二絕緣層40的非晶矽薄膜3〇側表面係與導 電薄膜50接觸’且電極60係與由該等空隙暴露的導電薄 膜5 0接觸以施加·-電場。 參照第6圖’在第二絕緣層40和非晶矽薄骐30之中心及兩 端提供空隙》導電薄膜50形成於在中心提供的空隙以供 與非晶矽薄膜30接觸，且電極60係設置於在兩端提供的 空隙以供與導電薄膜50及非晶矽薄膜30接觸並且與在中 心提供之空隙中所形成的導電薄膜50接觸以施加—電場 〇 參照第7圖，在第二絕緣層40和非晶矽薄膜3〇之中心及兩 端提供空隙’且電極60係設置於該等空隙中以與導電薄 膜50及非晶矽薄膜30接觸及施加一電場。 參照第8圖’在第二絕緣層4 0之中心及兩端提供空隙，且 導電薄膜50形成於在第二絕緣層40提供的空隙。在非晶 099112329 表單編號A0101 第16頁/共26頁 201100565 碎薄膜3G之巾〜、及兩端提供空隙，且非㈣薄膜與在 第二絕緣層40提供之空隙中所形成的導電薄膜5{)接觸。 電極60與在非晶♦相3Q中所提供之空隙暴露的導電薄 膜5〇接觸以施加一電場。 其中該等空隙可為藉由以下方式提供於第二絕緣層4〇 或非晶妙薄膜3G中：形成整個第二絕緣層4ϋ或整個非晶 夕薄膜30然後去除第二絕緣層4〇或非晶碎薄膜3〇之一些 〇P刀，或疋在形成第二絕緣層4〇或非晶梦薄膜的過程 〇 #中利用一遮罩等等防止第二絕緣層40或非晶石夕薄膜30 之一些部分形成。 儘管已參照本發明之某些範例實施例說明本發明，熟習 此技藝者應理解到可不脫離由隨附申請專利滅圍項界定 的發明精神及範圍就形式及細節作各種變化。 【圖式簡單說明】 [0005] 第1圖至第4圖是例示依據本發明一第一範例實施例之非 晶矽（a-Si)薄膜結晶方¥的剖面圖。： Q 第5圖至第8圖是例示依據本發唄一第二範例實施例之非 晶矽薄膜結晶方法的剖面圖。 【主要元件符號說明】 [0006] 10:基板 20 :第一絕緣層 30 :非晶矽薄膜 40 :第二絕緣層 50 :導電薄膜 60 :電極 099112329 表單編號A0101 第17頁/共26頁 0993293765-0 201100565 61 :第一電極 63 :第二電極 099112329 表單編號A0101 第18頁/共26頁 0993293765-0A mask or the like prevents the second insulating layer 40 or portions of the conductive film 50 from being formed. 5 to 8 are cross-sectional views illustrating a non-crystal thin crystallization method according to a second exemplary embodiment of the present invention. The description of the second exemplary embodiment is the same as the first exemplary embodiment except for the details which are specifically described below. In the amorphous crystallization film crystallization method according to the second exemplary embodiment, a first insulating layer 20, a conductive film 50, a second insulating layer 40, and an amorphous germanium film are sequentially formed on a substrate 10. 30. More specifically, the first insulating layer 20 is formed on the substrate 1 、, and the conductive layer is 099112329. Form No. 1010101 Page 15/26 pages 0993293765-0 201100565 The film 50, the second insulating layer 40, and the amorphous germanium film 3 Then, by applying an electric field to the electroconductive thin film 50 to cause Joule heating to generate high heat, the amorphous germanium film 30 is crystallized by the high heat. As with the first exemplary embodiment, the electric field is applied via an electrode 60 that is in contact with the conductive film 50 and is connected to a voltage source Vs. Wherein the electric field is applied to approximately the center and both ends of a range in which an electric field is to be applied, a positive potential voltage is applied to the center, and both ends are grounded. Although the embodiment of this example cites that the voltage applied to the center is a positive potential voltage, the voltage applied to the center may be a negative potential voltage. Some of the surface of the amorphous germanium film 30 is electrically conductive (10) or the electrode 6 is contacted with ..... . . . 'to be crystallized by applying Joule heat generated by an electric field. Referring to Fig. 5, a gap is provided at the center and both ends of the second insulating layer 40·. The surface of the amorphous germanium film 3 which is formed to surround the second insulating layer 40 is in contact with the conductive film 50, and the electrode 60 is in contact with the conductive film 50 exposed by the spaces to apply an electric field. Referring to Fig. 6 'providing a gap between the center and both ends of the second insulating layer 40 and the amorphous thin crucible 30, the conductive film 50 is formed in a gap provided at the center for contact with the amorphous germanium film 30, and the electrode 60 is attached. Provided in the gap provided at both ends for contact with the conductive film 50 and the amorphous germanium film 30 and in contact with the conductive film 50 formed in the gap provided in the center to apply - electric field, refer to Fig. 7, in the second insulation A gap is provided in the center and both ends of the layer 40 and the amorphous germanium film 3, and the electrodes 60 are disposed in the spaces to contact the conductive film 50 and the amorphous germanium film 30 and apply an electric field. Referring to Fig. 8, a gap is provided at the center and both ends of the second insulating layer 40, and the conductive film 50 is formed in the gap provided in the second insulating layer 40. In amorphous 099112329 Form No. A0101 Page 16 of 26 201100565 Shredded film 3G towel ~, and both sides provide a gap, and the non-(iv) film and the conductive film formed in the gap provided by the second insulating layer 5{{ )contact. The electrode 60 is in contact with the conductive film 5A exposed in the void provided in the amorphous ♦ phase 3Q to apply an electric field. Wherein the voids may be provided in the second insulating layer 4 or the amorphous film 3G by forming the entire second insulating layer 4 or the entire amorphous film 30 and then removing the second insulating layer 4 or The ruthenium film 3 〇 some 〇 P knives, or 疋 in the process of forming the second insulating layer 4 非晶 or the amorphous dream film 利用 # using a mask or the like to prevent the second insulating layer 40 or the amorphous shi film 30 Some parts are formed. While the invention has been described with reference to the preferred embodiments of the embodiments of the present invention, it will be understood that various changes in the form and details may be made without departing from the spirit and scope of the invention as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0005] Figs. 1 to 4 are cross-sectional views showing a non-crystal (a-Si) film crystallizing film according to a first exemplary embodiment of the present invention. : Q FIGS. 5 to 8 are cross-sectional views illustrating a method of crystallizing a non-crystalline film according to a second exemplary embodiment of the present invention. [Major component symbol description] [0006] 10: Substrate 20: First insulating layer 30: Amorphous germanium film 40: Second insulating layer 50: Conductive film 60: Electrode 099112329 Form No. A0101 Page 17 of 26 0993293765- 0 201100565 61 : First electrode 63 : Second electrode 099112329 Form number A0101 Page 18 / Total 26 0993293765-0

Claims (1)

201100565 七、申請專利範圍： 1 . 一種製造多晶石夕（poly_Si)薄膜的方法，包括在一基板 上依序形成一第一絕緣層、一非晶梦（a-Si)薄膜、一 第二絕緣層、及一導電薄膜，且利用高熱而結晶化該非晶 矽薄膜，該高熱通過利用電極施加一電場至該導電薄膜而 被產生， 其中該等電極係設置於將被施加的該電場所在之一範圍的 中心及兩端，且該電場係在一預定電壓施加於設置在該中 ^ 心之一電極且設置於兩端之電極接地之時施加。 〇 2 .如申請專利範圍第1項之方法，其中該非晶矽薄膜之一部 分係與該導電薄膜或該等電極接觸。 3 .如申請專利範圍第1項之方法，進一步包括在施加該電場 至該導電薄膜之前預熱該基板。 4.如申請專利範圍第2項之方法，其中在該第二絕緣層之中 心及兩端提供空隙，且 該導電薄膜係形成於該等空隙中以與該非晶矽薄膜接觸。 q 5 .如申請專利範圍第4項之方法，其中該等空隙進一步被提 供在該中心與兩端之間，且 該導電薄膜亦形成於該等進一步提供的空隙中以與該非晶 石夕薄膜接觸。 6 .如申請專利範圍第2項之方法，其中該等電極係設置在提 供於該第二絕緣層及該導電薄膜之中心及兩端的空隙中以 與該非晶矽薄膜接觸。 7 .如申請專利範圍第2項之方法，其中在該第二絕緣層之中 心及兩端提供空隙，且 099112329 表單編號A0101 第19頁/共26頁 0993293765-0 201100565 電極設置在該等空隙中以與該非㈣薄膜接觸。 •:申請專利範圍第7項之方法，其中該等第-電極係設置 在該導電薄膜底下， 第二電極設置在該導電薄膜上，且 —電壓施加至該第二電極。 9 ·如中請專利範圍第4至8項中任—項之方法，其中該等” 係藉由形成整個第二絕緣層或整個導電薄膜然後去除該第 -絕緣層或該導電薄膜之-些部分而提供。 10 .㈣請專利範圍第㈣項中任—項之方法，其中該等空隙 係藉由在形成該第二絕緣層或談導電薄膜之時阻止該第二 絕緣層或該導電薄膜之一些部分形成而提供。 11 .-種製造-多晶梦（pQly_Si)薄膜的方法，包括在一基 板上依序形成-第一絕緣層、一導電薄膜 '一第二絕緣層 、及-非晶矽U-Si)薄膜’且利用高熱而結晶化該非 晶石夕薄膜，該高熱通過利用電極施加一電場至該導電薄膜 而被產生， 其中該等電極係設置於將被施加的該電場所在之一範圍的 中心及兩端，且該電場係#一凝¥董壓施加於設置在該中 心之一電極且設置於兩端之電極接地之時施加。 12 .如申請專利範圍第丨丨項之方法，其中該非晶矽薄膜之一部 分係與該導電薄膜或該等電極接觸。 13 .如申請專利範圍第12項之方法，進—步包括在施加該電場 至該導電薄膜之前預熱該基板。 14 .如申請專利範圍第12項之方法，其中在該第二絕緣層之中 心及兩端提供空隙，且 099112329 被形成來包圍該第二絕緣層的該非晶矽薄膜之—側表面係 表單編號A0101 第20頁/共26頁 0993293765-0 201100565 15 . 16 . 17 . Ο 18 . 19 . ❹ 20 . 21 . 22 . 099112329 表單編號A0101 與該導電薄膜接觸。 如申請專利範圍第14項之方法，其中該等電極與藉由該等 空隙暴露的該導電薄膜接觸。 如申請專利範圍第12項之方法，其中在該第二絕緣層及該 非晶矽薄膜之中心及兩端提供空隙，且 该導電薄膜係形成於在該中心提供的空隙中以與該非晶矽 薄膜接觸。 如申請專利範圍第16項之方法，其中該等電極係設置在提 供於兩端的空隙中以與該導電薄臈及該非晶矽薄膜接觸， 且係與在該中心提供之空隙中所形成的該導電薄膜接觸。 如申請專利範圍第12項之方法，其中在該第二絕緣層及該 非晶矽薄膜之中心及兩端提供空隙，且 該等電極係設置在該等空隙中以與該導電薄膜及該非晶矽 薄膜接觸。 如申請專利範圍第12項之方法，其中在該第二絕緣層之中 心及兩端提供空隙，^ 該導電薄膜係形成於該等空隙中， 在該非晶矽薄膜之中心及兩端提供空隙，且 該非晶矽薄膜係與在該第二絕緣層提供之該等空隙中所形 成的該導電薄膜接觸。 如申請專利範圍第19項之紐，其巾料電㈣與在該非 晶矽薄膜提供之該等空隙所暴露的該導電薄膜接觸。 如申請專利範圍第14至20項中任一項之方法，其中該等 空隙係藉由形成整個第二絕緣層或整個非晶矽薄膜然後去 除該第二絕緣層或該非晶矽薄膜之一些部分而提供。 如申請專利範圍第14至20項中任一項之方法，其中該等 第21頁/共26頁 0993293765-0 201100565 空隙係藉由在形成該第二絕緣層或該非晶矽薄膜之時阻止 該第二絕緣層或該非晶矽薄膜之一些部分形成而提供。 099112329 表單編號A0101 第22頁/共26頁201100565 VII. Patent application scope: 1. A method for manufacturing a polycrystalline silicon (poly_Si) film, comprising: sequentially forming a first insulating layer, an amorphous dream (a-Si) film, and a second on a substrate. An insulating layer, and a conductive film, and crystallizing the amorphous germanium film by high heat, the high heat being generated by applying an electric field to the conductive film by using an electrode, wherein the electrodes are disposed at the electric field to be applied The center and both ends of a range, and the electric field is applied when a predetermined voltage is applied to one of the electrodes disposed at the center and the electrodes disposed at both ends are grounded. The method of claim 1, wherein a portion of the amorphous germanium film is in contact with the conductive film or the electrodes. 3. The method of claim 1, further comprising preheating the substrate prior to applying the electric field to the conductive film. 4. The method of claim 2, wherein a gap is provided in a center and both ends of the second insulating layer, and the conductive film is formed in the spaces to contact the amorphous germanium film. The method of claim 4, wherein the voids are further provided between the center and the both ends, and the conductive film is also formed in the further provided voids to form the amorphous thin film contact. 6. The method of claim 2, wherein the electrodes are disposed in a gap provided between the second insulating layer and the center and both ends of the conductive film to contact the amorphous germanium film. 7. The method of claim 2, wherein a gap is provided at a center and both ends of the second insulating layer, and 099112329 Form No. A0101 Page 19/26 pages 0993293765-0 201100565 electrodes are disposed in the gaps In contact with the non-four film. The method of claim 7, wherein the first electrode is disposed under the conductive film, the second electrode is disposed on the conductive film, and a voltage is applied to the second electrode. The method of any one of clauses 4 to 8, wherein the method comprises forming the entire second insulating layer or the entire conductive film and then removing the first insulating layer or the conductive film. The method of any of the preceding claims, wherein the voids prevent the second insulating layer or the conductive film by forming the second insulating layer or the conductive film. Some parts are formed and provided. 11. A method of manufacturing a polycrystalline dream (pQly_Si) film, comprising sequentially forming a first insulating layer, a conductive film 'a second insulating layer, and a non- a crystalline U-Si film" and crystallizing the amorphous film by high heat, the high heat being generated by applying an electric field to the conductive film using an electrode, wherein the electrodes are disposed at the electric field to be applied At the center and both ends of one of the ranges, and the electric field is applied to one of the electrodes disposed at the center and the electrodes disposed at both ends are grounded. Method of the item, where the non One portion of the wafer film is in contact with the conductive film or the electrodes. 13. The method of claim 12, further comprising preheating the substrate before applying the electric field to the conductive film. The method of claim 12, wherein a gap is provided at a center and both ends of the second insulating layer, and 099112329 is formed to surround the second insulating layer. The side surface of the amorphous germanium film is shown in the form number A0101. / 26 pages 0993293765-0 201100565 15 . 16 . 17 . Ο 18 . 19 . ❹ 20 . 21 . 22 . 099112329 Form No. A0101 is in contact with the conductive film. The method of claim 14, wherein the electrodes In contact with the conductive film exposed by the voids, the method of claim 12, wherein a gap is provided at a center and both ends of the second insulating layer and the amorphous germanium film, and the conductive film is formed on In the gap provided by the center, the method is in contact with the amorphous germanium film. The method of claim 16, wherein the electrodes are disposed in the gap provided at both ends Contacting the conductive thin film and the amorphous germanium film, and contacting the conductive film formed in the gap provided in the center. The method of claim 12, wherein the second insulating layer and the non- A gap is provided in the center and both ends of the wafer film, and the electrodes are disposed in the gaps to contact the conductive film and the amorphous germanium film. The method of claim 12, wherein the second insulation Providing a gap in a center and both ends of the layer, wherein the conductive film is formed in the spaces, a gap is provided at a center and both ends of the amorphous germanium film, and the amorphous germanium film is provided in the second insulating layer The conductive film formed in the voids is in contact. The coating material (4) is in contact with the conductive film exposed by the voids provided by the amorphous film as in the 19th article of the patent application. The method of any one of claims 14 to 20, wherein the voids are formed by forming the entire second insulating layer or the entire amorphous germanium film and then removing the second insulating layer or portions of the amorphous germanium film And provide. The method of any one of claims 14 to 20, wherein the 21st/26th page 0993293765-0 201100565 voids are prevented by forming the second insulating layer or the amorphous germanium film A second insulating layer or portions of the amorphous germanium film are formed to be formed. 099112329 Form Number A0101 Page 22 of 26 ij 0993293765-0Ij 0993293765-0
TW099112329A 2009-04-21 2010-04-20 Fabricating method of polycrystalline silicon thin film TW201100565A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090034791A KR101075261B1 (en) 2009-04-21 2009-04-21 Fabricating method of polycrystalline silicon thin film

Publications (1)

Publication Number Publication Date
TW201100565A true TW201100565A (en) 2011-01-01

Family

ID=43011600

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099112329A TW201100565A (en) 2009-04-21 2010-04-20 Fabricating method of polycrystalline silicon thin film

Country Status (3)

Country Link
KR (1) KR101075261B1 (en)
TW (1) TW201100565A (en)
WO (1) WO2010123263A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI664646B (en) * 2016-09-12 2019-07-01 日商愛發科股份有限公司 Method of manufacturing transparent-conductive-film-attached substrate, apparatus of manufacturing transparent-conductive-film-attached substrate, and transparent-conductive-film-attached substrate

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3407792B2 (en) * 1997-09-10 2003-05-19 株式会社トクヤマ Photoelectric conversion element and manufacturing method thereof
JP4287579B2 (en) * 2000-08-02 2009-07-01 パナソニック株式会社 Plasma processing apparatus and method
KR100543717B1 (en) * 2003-05-27 2006-01-23 노재상 Method for Annealing Silicon Thin Films and Polycrystalline Silicon Thin Films Prepared Therefrom

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI664646B (en) * 2016-09-12 2019-07-01 日商愛發科股份有限公司 Method of manufacturing transparent-conductive-film-attached substrate, apparatus of manufacturing transparent-conductive-film-attached substrate, and transparent-conductive-film-attached substrate

Also Published As

Publication number Publication date
WO2010123263A2 (en) 2010-10-28
WO2010123263A3 (en) 2010-12-23
KR101075261B1 (en) 2011-10-20
KR20100116062A (en) 2010-10-29

Similar Documents

Publication Publication Date Title
KR101602997B1 (en) Polysilicon thin film and manufacturing method thereof, array substrate and display device
KR100946808B1 (en) Method for producing a polycrystalline silicon thin film, manufactured using the same, a crystalline silicon thin film, and a thin film transistor comprising the same
KR100543717B1 (en) Method for Annealing Silicon Thin Films and Polycrystalline Silicon Thin Films Prepared Therefrom
US20090042342A1 (en) Method for crystallization of amorphous silicon by joule heating
US20070155067A1 (en) Method of fabricating polycrystalline silicon film and method of fabricating thin film transistor using the same
KR100729942B1 (en) Method for Annealing Silicon Thin Films Using Conductive Layer and Polycrystalline Silicon Thin Films Prepared Therefrom
KR101009429B1 (en) Polycrystalline silicon film, thin film transistor comprising same, and method for manufacturing same
CN100505274C (en) Active Matrix Electronic Array Device
TW201100565A (en) Fabricating method of polycrystalline silicon thin film
KR100413473B1 (en) Crystallization method for amorphous silicon using hydrogen plasma and electric field
JP4701467B2 (en) Polycrystalline film manufacturing method and semiconductor device manufacturing method
KR101043788B1 (en) Method for manufacturing polycrystalline silicon film and method for manufacturing thin film transistor including same
KR100976593B1 (en) Thin film transistor and its manufacturing method
KR20090084237A (en) Polycrystalline silicon thin film manufacturing apparatus and method
US8128714B2 (en) Apparatus for manufacturing polycrystalline silicon thin film
KR20090084239A (en) Polycrystalline silicon thin film manufacturing apparatus and method
JPH1197713A (en) Manufacture of semiconductor device
KR101336455B1 (en) Structure For Crystallization, Method of Crystallization, Method of Forming Active layer of Semiconductor Amorphous silicon layer, And Manufacturing Method of Thin Film Transistor Using the Same
JP2003197630A (en) Thin film transistor, display device and method of manufacturing the same
KR101031882B1 (en) Polycrystalline silicon thin film manufacturing apparatus and method
JP2002208565A (en) Semiconductor device and method of manufacturing the same, and liquid crystal display
JP2001223367A (en) Method for manufacturing semiconductor device
JP2000082670A (en) Manufacture of semiconductor device
JP2001217432A (en) Method of manufacturing semiconductor device
JP2001320063A (en) Method for forming semiconductor device