201042741 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體結構，尤指一種封裝基板之 電性連接結構及封裝結構。 【先前技術】 • 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能的研發方向。目前用以承載半導體晶片之封裝 基板係包括有打線式封裝基板、晶片尺寸封裝（CSP)基板及 Ο 覆晶基板（FCBGA)等；且為因應微處理器、晶片組、與繪 圖晶片之運算需要，佈有線路之封裝基板亦需提昇其傳遞 晶片訊號之品質、改善頻寬、控制阻抗等功能，以因應高 I/O數封裝件的發展。 在現行封裝技術中，係將半導體晶片電性接置於封裝 基板上’該半導體積體電路（1C)晶片的表面上配置有電極 替（electronic pad )，而該封裝基板具有相對應之電性接 ❹觸墊，且於該半導體晶片以及封裝基板之間可以適當地設 置導電凸塊、其他導電黏著材料，使該半導體晶片電性連 接至該封裝基板上。 請參閱第1A圖，係為習知覆晶封裝結構之剖視示意 圖；如丨圖所示，係提供一封裝基板10，該封裝基板10具 有第一表面10a及第二表面10b，於該第一表面10a上設 有複數第一電性接觸墊101，而於該第二表面l〇b上設有 複數第二電性接觸墊102，於該第二表面10b上接置有半 導體晶片11，於該些第二電性接觸墊102上分別形成焊錫 111202 201042741 凸塊12,而該半導體晶片u之一 焊錫凸塊12的電極墊u〇，且於久〜謂數相對各该 帝几诒η人/ 亥電極塾110上形成導 ^封^其/以半導體晶片11之導電凸塊13電性連接至 =衣餘Η)之焊錫凸塊12，且於該何體 細⑷4，細彡撕結構;封201042741 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure, and more particularly to an electrical connection structure and a package structure of a package substrate. [Prior Art] • With the booming electronics industry, electronic products are gradually entering the direction of multi-functional and high-performance research and development. At present, a package substrate for carrying a semiconductor wafer includes a wire-wound package substrate, a chip-scale package (CSP) substrate, and a flip-chip substrate (FCBGA), etc.; and is required for operation of a microprocessor, a wafer set, and a graphics chip. The package substrate with the line needs to improve the quality of the transmitted chip signal, improve the bandwidth, control the impedance, etc., in response to the development of high I/O number packages. In the current packaging technology, a semiconductor wafer is electrically connected to a package substrate. The surface of the semiconductor integrated circuit (1C) wafer is provided with an electronic pad, and the package substrate has corresponding electrical properties. The contact pads are connected, and conductive bumps and other conductive adhesive materials are appropriately disposed between the semiconductor wafer and the package substrate to electrically connect the semiconductor wafer to the package substrate. 1A is a schematic cross-sectional view of a conventional flip chip package structure. As shown in the drawing, a package substrate 10 is provided. The package substrate 10 has a first surface 10a and a second surface 10b. A plurality of first electrical contact pads 101 are disposed on a surface 10a, and a plurality of second electrical contact pads 102 are disposed on the second surface 10b, and a semiconductor wafer 11 is mounted on the second surface 10b. Solder 111202 201042741 bumps 12 are respectively formed on the second electrical contact pads 102, and the electrode pads u〇 of the solder bumps 12 of the semiconductor wafers u are separated from each other by a long time A solder bump 12 is formed on the human/electrode 塾 110, and is electrically connected to the conductive bump 13 of the semiconductor wafer 11 to the solder bump 12, and the thin body is thin (4) 4 ;seal
成有舰H t Μ該些第一電性接觸墊1〇1上分別形 成有錫球〗5，俾用以電性連接 JiV 該印刷電路板2之车 隔境路板(PCB)2,而 二==有複數對應各該苐-電性接觸 !之弟二電性接觸墊21，令該此 接至各該第：電性接總轨二錫球b對應電性連 分乡弟一包性接觸墊21，俾以將該 接至該印刷電路板2上。 又、口 包性連 惟’上述之封裝結構】之錫球15形成於 且細間距佈局之第一電性接觸墊⑻上導:又佈線 】5之間的間距過小，且當該些錫球二=錫球 ^之第三電性接觸墊21並經迴焊製程心 <，谷易造成該些錫球15之間形成橋接而導致短路。 為避免前述問題發生’業界遂提出 請參閱第1B®，係為習知封 ^板結構， 細血 衣'，，口稱1之該肽第一命u从 觸塾ΗΠ上各設有對應之凸柱16，並^电性接 有烊锡材料η ,令該此__ 17 凸柱16上形成 势 —何科17對應電性連接s# 弟三電性接觸墊21，俾以將該封裝 連接至各这 刷電路板2上。 、 兒性連接至該印 然，前述之兩種習知技術中，該些 錫—17之凸柱16係對應接 _或具有焊 夏万'各5玄封裝結構1之第— Π1202 201042741 電性接觸塾10 ] !·，告i α , 几4 上田该些錫球15或具有焊錫材料17 凸柱16對應接置於該印 W电路板2日可，由於印刷電路板2 • 2 塾21佈設1 巧，且形成於該第三電性接 觸墊U上之防焊層開孔窄小，造 焊錫材料17之凸柱16之由、、，“吻^或具有 刷電路板2之第二電性接㈣=元全對應接置於該印 .的Ή “ 觸墊21中心部位，而有些許偏移 的障況，如此經迴焊製程而達 ο 哎且右俨瓴#』丨_ ^生運接後，该些錫球][5 有知錫材料17之凸柱16因並未完全精確接置 電性接觸墊21中心邮办 、第一 … 導致該些錫球15與第三電性接 觸㈣之間或具有焊錫材料17之凸柱】 曰置i應力，進而可能會造成該錫球15盥第 電性接觸墊】01之間、或該且右俨。舁弟一 第㈣w 材料17之凸柱】6與 乐生接觸塾101之間、或該錫球15與第 ο 21之間、或該焊錫材料〗7與第三電性接觸塾—21之= 面容易產生斷裂剝離的情況，因而影響電性連接。界 因：’如何提供一種封裝基板及封裝結構，以避免習 °技術中，在㊅密度佈線之細間距佈局巾 小容易造成錫球之間形成橋接而導今雜曰過 屬凸柱因未能完全精確接置於第三電=觸=錫球或金 產生之應力，而導致該錫球或全屬觸塾中心部位所 產生斷裂剝離之缺失，實已成 間 【發明内容】Μ待克服之課題。 鑑於上述習知技術之缺失，本發明之 —種封裝純之電㈣接結構及 * 忒…構，能避免迴焊製 111202 5 201042741 私中’該些電性連接 錫球間距過小、錫之間產生偏位應力，以及避免因 路的問題。 東過大造成回焊製程後，錫球間橋接短 為達上述及其他目 性連接社Μ尽七明如供一種封裝基板之電 墊，於該第-電性接觸墊上設有該電电性接觸 電性連接結構以電性連接至印刷電=j ’藉由該 性連接結構係包括：複 構’该電 -電性接觸塾上，且心1二㈣係對應設於各該第 料;以及複數凸柱，二=衝層之材料物錫材 凸柱之炫點高於該金屬緩衝層。 衡增上且4 本發明復提供一種封裝結構， 具有第—表面再係、包括.封裝基板，係 電性接觸塾，於二=二 ^上設有独第一 半導體晶片，係數第二電性接觸塾； 镑㈣^由弟二電性接觸藝，·複數金屬 屬缓T②於各該第—紐接觸墊上，且形成該金 屬:衝層之材料係為焊錫材料；以及複數凸柱，係對岸設 、騎Ik衝層上，域凸柱之_高於該金屬緩衝層。 曰縣結構’财導體晶^則1線結構或覆 曰曰釔構電性連接該些第二電性接觸墊。 依上述之封裝基板之電性連接結構及封裝結構，形成 该焊錫材料之材料係為錫（Sn)、銀(Ag)、銅（Cu)、辞㈣、 姻（In)所組成群組之其中—者；形成該凸柱之材料係為紹 (A])、銅（Cu)、鎳（Ni)所組成群組之其中一者。 ]]]202 6 201042741 接觸墊所奴結構，设可於該金屬緩衝層與第一電性 阻障層，而形成該阻障層之材料係為鎳 凸扭所述’復可於該6柱上形成焊錫材料；或於該 .化射巴浸金（_叫：i^；2錄浸金（獅）、 〇化學鑛銀或電鍍錫。 予鑛錫㈤贿sionTin)、 m=封裝心第-w絕緣保 表面處理：t: 可於外露之凸柱表面上形成該 露出該些凸柱之頂面。 —凸柱側面，亚 ^依上所述，於該凸柱之頂面形成桿錫材料。 係於$封隸板之電性軸結構及㈣結構，主要 G屬緩電性接觸塾上形成低炫點金屬之金 以二:=層上形成高炫點金屬之凸柱， 令該凸^ 迴焊製程中較該凸柱先溶融，俾 ;迴’干衣私中能藉由該先溶 供彈性偏移，以㈣"屬、讀層咏 中避免因偏位所產生層之冷卻過程 回焊德合。目+ 心 6亥些凸柱不若習知錫球經 柃接r: 而導致錫球與錫球間的間距變小產生 ，短路的問題’進而能避免習知所產生之缺失 【貫施方式】 人 下知I曰由4寸定的具體實例說明本發明之實施方 ]11202 7 201042741 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 請參閱第2A至7B圖，係為本發明封裝基板之電性 連接結構的示意圖。 [第一實施例] 請參閱第2A圖，本發明封裝基板之電性連接結構， 係包括有封裝基板31、複數金屬缓衝層32、及複數凸柱 33 ° 所述之封裝基板31係為内部具有複數導電線路及與 其電性連接之導電通孔或導電盲孔（圖式中未表示），而 有關於封裝基板形成導電線路、導電通孔與導電盲孔之製 程技術繁多，惟乃業界所周知之製程技術，其非本案技術 特徵，故未再予贅述；於該封裝基板31上並設有複數第一 電性接觸墊311，該第一電性接觸墊311係為植球墊或植 柱墊，以供接設導電元件而電性連接至印刷電路板或另一 封裝結構。 所述之金屬緩衝層32,係對應設於各該第一電性接觸 墊311上，而形成該金屬緩衝層32之材料係為低熔點金屬 之焊錫材料，該焊錫材料之材料係為錫（Sn)、銀(Ag)、銅 (Cu)、鋅（Zn)、銦（In)所組成群組之其中一者。 所述之複數凸柱33，係對應設於各該金屬緩衝層32 上，且該凸柱33之熔點高於該金屬緩衝層32，而形成該 凸柱3 3之材料係為高炼點金屬，該高熔點金屬之材料係為 鋁（A1)、銅（Cu)、鎳（Ni)所組成群組之其中一者。 8 川202 201042741 請參閱第2B圖，依上述之結構，復可包括於該金屬 緩衝層32與第一電性接觸墊3Π之間形成阻障層34，而 形成該阻障層34之材料係為鎳(Ni)。 [第二實施例] 請參閱第3A及3B圖，與前一實施例之不同處在於 該凸柱33上形成焊錫材料35。 '[第三實施例] 請參閱第4A及4B圖，與前述實施例之不同處在於 〇 該凸柱33之外露表面上形成表面處理層36，而形成該表 面處理層36之材料係為電鍍鎳/金、化學鍍鎳/金、化鎳浸 金（ENIG )、化鎳把浸金（ENEPIG )、化學鑛錫（Immersion Tin)、化學鍍銀或電鍍錫。 [第四實施例] 請參閱第5A及5B圖，與前述實施例之不同處在於 該封裝基板31之第一表面31a上形成絕緣保護層37，並 Q 露出該些凸柱33 ;且可於外露之凸柱33表面上形成該表 面處理層36，如第5A圖所示。 [第五實施例] 請參閱第6A及6B圖，與上述第四實施例之不同處 在於該絕緣保護層37復可形成於該些凸柱33側面，並露 出該些凸柱33之頂面。 [第六實施例] 請參閱第7A及7B圖，與前述第五實施例之不同處 在於該凸柱33之頂面形成焊錫材料35。 9 ]]]202 201042741 《月封裝基板之電性連接結構 之各該第-電性接觸墊形成 /料基板 声上^ I層，且於該金屬緩衝 :上屯成凸柱，糟由該低溶點金屬之金屬 較該高炫點金屬之凸柱先溶融，俾令該凸二 =中能藉由該絲融之金屬緩衝層而提供彈性偏移，以 該些金屬緩衝層之冷卻過程中避免因偏位所 之應力，且該些凸柱不若習知錫球經 而導㈣球與錫__距變小產生橋接短路= 續’進而能避免習知技術中該些電性連接結構所產生之缺 失0 、 請參閱第8Α圖，本發明復提供—種封裝結構〕，係 ^括：封裳基板3!、半導體晶片38、複數金屬緩、 及複數凸柱33。 所述之封裝基板31，係具有第一表面及第二 3!b，於該第一表面31a上設有複數第一電性接觸塾州， ^亥弟二表面3】b上設有複數第二電性接觸墊3】2,而該 苐二電性接觸墊312係可為打線墊或置晶墊。 〆 所述之半導體晶片38’係以打線結構（圖式巾未表示） 或覆晶結構39電性連接該些第二電性接觸墊312。 所述之金屬緩衝層32,係對應設於各該第一電性接觸 墊311上，而形成該金屬緩衝層32之材料係為低熔點金 之焊錫材料，該焊錫材料之材料係為錫（Sn)、銀(Ag)、銅 (Cu)、鋅（zn)、銦（In)所組成群組之其中—者。 所述之複數凸柱33，係對應設於各該金屬緩衝層& 111202 ]0 201042741 上，且該凸柱33之熔點高於該金屬緩衝層32 ,而形成該 •凸柱33之材料係為南炼點金屬，該高炼點金属之材料係為 ，鋁(A1)、銅（Cu)、鎳(Ni)所組成群組之其中一者。 ^依上述之封裝結構，復包括阻障層34 ’係形成於該金 屬緩衝層32與第-電性接觸塾311之間，而形成該阻障層 34之材料係為鎳(Ni)，如第及圖所示。 又，上所述，復可包括於該凸柱33上形成焊錫材料 〇 35,如第3八及邛圖所示；或於該凸柱％之外露表面上 形成表面處理層36,而形成該表面處理層36之 電鍍鎳/金、化學鍍鎳/金、化鎳浸金（ENIG)、化鎳鈀浸 ^enepig)、化學鑛錫（Immersi〇n Tin)、化學鑛銀 或電鍍錫，如第4A及4B圖所示。 如切述，復可於該封裝基板上形成絕緣保護層 ，且该絕緣保護層37並露出該些凸柱33，如第及 ❹ =^所示，且可於外露之凸柱33表面上形成該表面處理 層36,如4 5A圖所示；或該絕緣保護層37 凸板33側面，並露出該些凸柱33之頂面 :方、:玄』 圖所示。 弟从及犯 35 如上所述’復可於該凸柱 如第7A及7B圖所示。 33之頂面形成焊錫材料 ^ Ί衣'3傅J您該些凸柱33 心'對應接置一印刷電路板4(如第8Β圖所示）或另—封壯杜 構3’(如第8C圖所示），而該印刷電路板4之—表面里衣結 數對應各該凸柱33之第三電性接觸墊41，或另—二夂 对裝結 Π1202 201042741 =數對應各該凸…_ 咖上之焊锡材料35對二==錫㈣35,令該些 之第三電性接觸墊4】或一^ 至该印刷電路板4 墊313，俾將該封裝結構3電;構广之第三電性接觸 另—封裝結構3，上；且_ 以印刷電路板4或 之末端上，俾能避免於==崎於該凸柱33 而導致橋接短路的情況。 m錫材料產生溢流 本發明之封裝結構，係於該封裝基板之第 丁線或覆晶方式電性連接該半 、以 之第一電性接觸墊上形成低熔點全厘入於》亥第一表面 該金屬緩衝層上形成高炫點::::金=全;於 衣程中能藉由該先熔融之金屬缤 ' ^ 使該些凸柱於該些金屬緩衝層; ，以 之應力’且該些凸柱不若習知錫球經回焊後 t狀，而導致錫球與錫球間的間距變小產生橋接短i白^ :生=避免習知於迴焊製程中該些電性連接結構之所 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可二不= 背本發明之精神及範脅下，對上述實施例進行修飾盘= 變。因此’本發明之權利保護範圍，應如後述之申 範圍所列。 月 1Π202 12 201042741 【圖式簡單說明】 第1Α及1Β圖係為習知封裝基板結構之剖視示意 圖， 第2Α及2Β圖係為本發明封裝基板之電性連接結構 之第一實施例剖視示意圖； 第3Α及3Β圖係為本發明封裝基板之電性連接結構 之第二實施例剖視示意圖； Ο ❹ 第4Α及4Β圖係為本發明封裝基板之電性連接結構 之第三實施例剖視示意圖； 第5Α及5Β圖係為本發明封裝基板之電性連接結構 之第四實施例剖視示意圖； 第6Α及6Β圖係為本發明封裝基板之電性連接結構 之第五實施例剖視示意圖； 第7Α及7Β圖係為本發明封裝基板之電性連接結構 之第六實施例剖視示意圖；以及 第8Α至8C圖係為本發明封裝結構及其接置於印刷 電路板或另一封裝結構之剖視示意圖。 【主要元件符號說明】 1、3、3’ 封裝結構 10、31 封裝基板 10a ' 31a 10b 、 31b 、 31b， 101 、 311 102 、 312 第一表面 第二表面 第一電性接觸墊 第二電性接觸墊 13 111202 201042741 11、38 半導體晶片 110 電極墊 12 焊錫凸塊 13 導電凸塊 14 底充材料 15 錫球 16、33 凸柱 2 > 4 印刷電路板 21 、 41 、 313 第三電性接觸墊 32 金屬緩衝層 34 阻障層 35、17 焊錫材料 36 表面處理層 37 絕緣保護層 39 覆晶結構The first electrical contact pads 1〇1 are respectively formed with a solder ball 55 for electrically connecting the JiV of the printed circuit board 2 to the vehicle compartment road board (PCB) 2, and Two == There are multiple numbers corresponding to each of the 苐-electrical contacts! The second electrical contact pads 21, so that this is connected to each of the first: the electrical connection of the main rail, the two tin balls b corresponding to the electrical connection, a package of the township The contact pads 21 are bonded to the printed circuit board 2. Moreover, the solder ball 15 of the above-mentioned package structure is formed on the first electrical contact pad (8) of the fine pitch layout, and the spacing between the wires 5 is too small, and when the solder balls are The second electrical contact pad 21 of the solder ball ^ is soldered to the process center <, and the valley causes a bridge between the solder balls 15 to cause a short circuit. In order to avoid the above problems, the industry has proposed to refer to the 1B®, which is a structure of a conventional seal, a fine blood coat, and the first fat of the peptide 1 is provided with corresponding studs from the touchpad. 16, and ^ is electrically connected to the tin-tin material η, so that the potential of the __ 17 pillar 16 is formed - Heke 17 corresponds to the electrical connection s# three electrical contact pads 21, to connect the package to Each of the brush boards 2 is on. , the child is connected to the Yinran, in the above two conventional techniques, the tin-17 pillars 16 are connected to each other or have the welding Xia Wan's 5th package structure 1 - Π 1202 201042741 Contact ] 10 ] !·, i i α , a few 4 Ueda the solder balls 15 or have a solder material 17 studs 16 correspondingly placed on the printed W circuit board 2, due to the printed circuit board 2 • 2 塾 21 layout 1 </ RTI> and the opening of the solder resist layer formed on the third electrical contact pad U is narrow, and the protrusion 16 of the solder material 17 is formed, and the "kiss" or the second electric device having the brush circuit board 2 Sexual connection (4) = elemental corresponding to the Ή "the central part of the touch pad 21, and a slight offset obstacle, so through the reflow process and reach ο 哎 and right 俨瓴 # 丨 _ ^ raw After the transfer, the solder balls][5 have the pillars 16 of the known tin material 17 because they are not completely accurately connected to the electrical contact pads 21, the first post... the solder balls 15 and the third electrical properties Contact (4) or with a stud of solder material 17] i i stress, which may cause the solder ball 15 盥 electrical contact pad 01 01, or the right 俨.舁弟一第(四)w The pillar of material 17 is between 6 and Lesheng contact 塾101, or between the solder ball 15 and ο 21, or the solder material 7 and the third electrical contact 塾-21 The surface is prone to breakage and peeling, thus affecting the electrical connection. Boundary: 'How to provide a package substrate and package structure to avoid the problem that the fine pitch layout of the six-density wiring is small and easy to cause bridging between the solder balls. Completely and accurately placed in the third electric=touch=the stress generated by the tin ball or gold, which leads to the lack of fracture and peeling of the solder ball or the entire center of the touch, which has become an inevitable Question. In view of the above-mentioned lack of the prior art, the present invention is a packaged pure electric (four) connection structure and a * 忒 ... structure, can avoid reflow soldering 111202 5 201042741 privately, the spacing between the electrically connected solder balls is too small, between the tin Produce offset stress and avoid problems with the road. After the over-construction process of the East is too large, the bridging between the solder balls is short. The above-mentioned and other mesh connection companies are fully equipped with an electric pad for a package substrate, and the electro-electric contact is provided on the first-electrode contact pad. The electrical connection structure is electrically connected to the printed circuit=j' by the structural connection structure comprising: a reconstitution 'the electrical-electrical contact 塾, and the core 1 (4) is correspondingly disposed in each of the first materials; The plurality of studs, the material of the second bump layer, the tin of the tin column is higher than the metal buffer layer. The invention provides a package structure having a first surface re-attachment, including a package substrate, and an electrical contact 塾, and a first semiconductor wafer is disposed on the second=two^, the coefficient is second electrical. Contact 塾; Pound (four) ^ by the second two electrical contact art, · multiple metal is slow T2 on each of the first - New contact pads, and the formation of the metal: the material of the punch layer is solder material; and the complex studs, on the other side Set and ride on the Ik layer, the domain pillar is higher than the metal buffer layer. The structure of the Jixian County is the first conductor structure or the structure of the second electrical contact pad. According to the electrical connection structure and the package structure of the package substrate, the material of the solder material is a group consisting of tin (Sn), silver (Ag), copper (Cu), syllabary (4), and marriage (In). The material forming the stud is one of a group consisting of (A), copper (Cu), and nickel (Ni). ]]]202 6 201042741 The structure of the contact pad is provided in the metal buffer layer and the first electrical barrier layer, and the material forming the barrier layer is nickel torsion. Forming a solder material on the surface; or in the chemistry of the immersion gold (_called: i^; 2 recording gold (lion), bismuth chemical silver or electroplating tin. Pre-minening tin (five) bribe sionTin), m = package heart -w insulation surface treatment: t: The top surface of the exposed pillars may be formed on the exposed pillar surface. - The side of the stud, as described above, forms a rod tin material on the top surface of the stud. Attached to the electrical axis structure of the seal plate and (4) structure, the main G is a slow-contact metal on the slow-contacting contact, forming a gold with a high-point metal, and forming a convex column with a high-point metal on the layer. In the reflow process, the stud is first melted, and the back is dry. In the dry coat, the elastic solution can be offset by the first solution, and the cooling process of the layer due to the deviation is avoided in the (4) " Welding deer.目+心六亥 Some of the studs are not known to be soldered by r: The resulting gap between the solder balls and the solder balls is small, and the problem of short circuit can further avoid the lack of conventional knowledge. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2A to 7B are schematic views showing the electrical connection structure of the package substrate of the present invention. [First Embodiment] Referring to FIG. 2A, an electrical connection structure of a package substrate of the present invention includes a package substrate 31, a plurality of metal buffer layers 32, and a plurality of bumps 33. The package substrate 31 is There are a plurality of conductive lines and conductive vias or conductive blind holes (not shown in the drawings), and there are many processes for forming conductive lines, conductive vias and conductive blind vias on the package substrate, but the industry is The well-known process technology, which is not a technical feature of the present invention, is not described again; a plurality of first electrical contact pads 311 are disposed on the package substrate 31, and the first electrical contact pads 311 are ball bump pads or The pillar pad is electrically connected to the printed circuit board or another package structure for connecting the conductive elements. The metal buffer layer 32 is correspondingly disposed on each of the first electrical contact pads 311, and the material forming the metal buffer layer 32 is a solder material of a low melting point metal, and the material of the solder material is tin ( One of a group consisting of Sn), silver (Ag), copper (Cu), zinc (Zn), and indium (In). The plurality of studs 33 are correspondingly disposed on the metal buffer layer 32, and the melting point of the stud 33 is higher than the metal buffer layer 32, and the material forming the stud 33 is a high-refining metal. The material of the high melting point metal is one of a group consisting of aluminum (A1), copper (Cu), and nickel (Ni). 8 川202 201042741 Please refer to FIG. 2B. According to the above structure, a barrier layer 34 is formed between the metal buffer layer 32 and the first electrical contact pad 3, and the material layer of the barrier layer 34 is formed. It is nickel (Ni). [Second Embodiment] Referring to Figures 3A and 3B, the difference from the previous embodiment is that a solder material 35 is formed on the stud 33. [THIRD EMBODIMENT] Referring to Figures 4A and 4B, the difference from the foregoing embodiment is that a surface treatment layer 36 is formed on the exposed surface of the stud 33, and the material forming the surface treatment layer 36 is electroplated. Nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel immersion gold (ENEPIG), chemical tin (Immersion Tin), electroless silver plating or electroplating tin. [Fourth Embodiment] Referring to FIGS. 5A and 5B, the difference from the foregoing embodiment is that an insulating protective layer 37 is formed on the first surface 31a of the package substrate 31, and Q is exposed to the pillars 33; The surface treatment layer 36 is formed on the surface of the exposed stud 33 as shown in Fig. 5A. [Fifth Embodiment] Referring to FIGS. 6A and 6B, the difference from the fourth embodiment is that the insulating protection layer 37 is formed on the side of the protrusions 33 and exposes the top surface of the protrusions 33. . [Sixth embodiment] Referring to Figures 7A and 7B, the difference from the foregoing fifth embodiment is that a solder material 35 is formed on the top surface of the stud 33. 9 ]]]202 201042741 "The first electrical contact pad of the electrical connection structure of the monthly package substrate is formed / the substrate is acoustically layered, and the metal buffer: the upper layer is formed into a stud, and the low is caused by the low The metal of the molten metal is melted first than the convex column of the high-point metal, so that the convex second=middle can provide elastic displacement by the metal buffer layer of the silk, and the metal buffer layer is cooled during the cooling process. Avoid the stress caused by the bias, and the bumps are not known to the solder ball. (4) The ball and the tin__ distance become smaller and the bridge short circuit = continued", thereby avoiding the electrical connection structures in the prior art. The resulting missing 0, please refer to FIG. 8 , the present invention provides a package structure, including: a sealing substrate 3!, a semiconductor wafer 38, a plurality of metal slow, and a plurality of studs 33. The package substrate 31 has a first surface and a second 3!b. The first surface 31a is provided with a plurality of first electrical contacts, and a plurality of first surfaces are provided on the surface. The second electrical contact pad 3 2, and the second electrical contact pad 312 can be a wire pad or a pad. The semiconductor wafer 38' is electrically connected to the second electrical contact pads 312 by a wire bonding structure (not shown) or a flip chip structure 39. The metal buffer layer 32 is disposed on each of the first electrical contact pads 311, and the material forming the metal buffer layer 32 is a low melting point gold solder material, and the solder material is tin ( Among the groups consisting of Sn), silver (Ag), copper (Cu), zinc (zn), and indium (In). The plurality of studs 33 are correspondingly disposed on each of the metal buffer layers & 111202 ] 0 201042741, and the melting point of the studs 33 is higher than the metal buffer layer 32, and the material system forming the studs 33 is formed. For the south refining point metal, the material of the high refining point metal is one of a group consisting of aluminum (A1), copper (Cu), and nickel (Ni). According to the above package structure, the barrier layer 34' is formed between the metal buffer layer 32 and the first electrical contact 311, and the material forming the barrier layer 34 is nickel (Ni), such as The figure and figure are shown. In addition, as described above, the composite material may include a solder material layer 35 formed on the stud 33, as shown in FIG. 3 and FIG. 3; or a surface treatment layer 36 may be formed on the exposed surface of the stud column. The surface treatment layer 36 is electroplated with nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel palladium immersion (enepig), chemical tin (Immersi〇n Tin), chemical silver or electroplated tin, such as Figures 4A and 4B are shown. As described, an insulating protective layer is formed on the package substrate, and the insulating protective layer 37 exposes the studs 33, as shown in the first and second, and can be formed on the surface of the exposed studs 33. The surface treatment layer 36 is as shown in FIG. 45A; or the insulating protection layer 37 has a side surface of the convex plate 33, and exposes the top surfaces of the protrusions 33: square, as shown in the figure. The younger brother and the accomplice 35 are as described above and can be re-applied to the stud as shown in Figures 7A and 7B. The top surface of 33 forms a solder material ^ Ί ' '3 Fu J you have some of the studs 33 heart 'corresponding to a printed circuit board 4 (as shown in Figure 8) or another - seal strong 3" (such as 8C), and the number of the surface of the printed circuit board 4 corresponds to the third electrical contact pad 41 of each of the studs 33, or the other two pairs of the mounting Π 1202 201042741 = the number corresponding to each of the convex ..._ solder material 35 pairs of two == tin (four) 35, such a third electrical contact pad 4 or a ^ to the printed circuit board 4 pad 313, 俾 the package structure 3; The third electrical contact is another - the package structure 3, and the _ can be prevented from being short-circuited by the bridge 33 or the end of the printed circuit board 4 or the like. The m-tin material generates an overflow structure, and the package structure of the present invention is electrically connected to the half in the first or second layer of the package substrate, and the first electrical contact pad is formed on the first electrical contact pad to form a low melting point. a surface of the metal buffer layer is formed with a high-density point::::gold=all; in the coating process, the first molten metal can be used to make the protrusions on the metal buffer layer; Some of the studs are not known to be t-shaped after reflowing, resulting in a smaller spacing between the solder balls and the solder balls. The bridging is short i white ^: raw = avoiding the electrical connections in the reflow process The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Anyone skilled in the art can refrain from modifying the above embodiments with the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth below. 1Π202 12 201042741 [Simplified Schematic] FIGS. 1 and 1 are schematic cross-sectional views of a conventional package substrate structure, and FIGS. 2 and 2 are cross-sectional views showing a first embodiment of an electrical connection structure of a package substrate of the present invention. 3D and 3D are schematic cross-sectional views showing a second embodiment of the electrical connection structure of the package substrate of the present invention; ❹ ❹ 4th and 4th drawings are the third embodiment of the electrical connection structure of the package substrate of the present invention FIG. 5 is a cross-sectional view showing a fourth embodiment of the electrical connection structure of the package substrate of the present invention; and FIGS. 6 and 6 are the fifth embodiment of the electrical connection structure of the package substrate of the present invention. Figure 7 is a schematic cross-sectional view showing a sixth embodiment of the electrical connection structure of the package substrate of the present invention; and Figures 8 to 8C are the package structure of the present invention and its connection to a printed circuit board or A schematic cross-sectional view of another package structure. [Main component symbol description] 1, 3, 3' package structure 10, 31 package substrate 10a ' 31a 10b, 31b, 31b, 101, 311 102, 312 first surface second surface first electrical contact pad second electrical Contact pad 13 111202 201042741 11, 38 semiconductor wafer 110 electrode pad 12 solder bump 13 conductive bump 14 bottom filling material 15 solder ball 16, 33 stud 2 > 4 printed circuit board 21, 41, 313 third electrical contact Pad 32 metal buffer layer 34 barrier layer 35, 17 solder material 36 surface treatment layer 37 insulation protection layer 39 flip chip structure