201039355 六、發明說明： 【發明所屬之技術領域】 本發明係有關記憶體存取，特別是關於一種高記憶體 頻寬使用率及高效率記憶體資料存取的視訊資料排列方 式。 【先前技術】 記憶體頻寬係減存或讀取半導體記憶體裝置資料的 速率，其通常以每秒位元組（bytespersec〇nd)來表示。 由於電子系統中的記憶體裝置往往會共用於各個處理器或 裝置之間，因此記憶體資源通常是很珍貴的，且記憶體頻 寬常常感到缺乏。增進記憶體頻寬的方法之一是讓某個處 理器或裝置有專屬存取權，使其每次得以循序存取一整個 區塊的資料。例如，某些記憶體裝置提供叢發模式（bum mode)，當起始位址及一些必要控制信號提供給記憶體裝 置後’整個區塊資料即可毫無中斷的進行傳送。然而，記 〜體裝置卻經*需要進行隨機的存取，以储存或讀取記憶 體=置中各分散位置的資料。對於此種存取方式，由於每 二貝料存取時均祕費相當㈣於提供存純址及控制信 號因此°己憶體頻寬的使用效率不大。 201039355 當記憶體裝置作為視訊緩衝器（或訊框緩衝器）以存 放視訊資料（特別是高密度視訊資料）或者涉及即時影像 處理時，前述記憶體裝置的隨機存取缺失將變得更為惡化。 鑑於視訊資料之記憶體頻寬使用效率不佳，且無法實 現即時的影像應吊，因此亟需提出一種新穎機制，用以增 進記憶體資料存取的效率。 【發明内容】 鑑於上述，本發明的目的之一在於提出一種記憶體存 取系統及方法，用以有效地利用記憶體頻寬而不會犧牲視 訊的品質。 根據本發明實施例，資料安排單元將視訊資料安排成至 少一主區塊及一附加區塊，其分別儲存於記憶體裝置内。 視訊資料經特別安排後，使得記憶體裝置内之主區塊視訊 資料得以被一裝置或處理器循序讀取。在一實施例中，資 料安排單元移除相鄰二像素的至少一色度成分（例如u或 V成分），而維持像素之亮度成分（例如Y成分），因而形 成主區塊。 5 201039355 【實施方式】 第一圖方塊圖顯示本發明實施例之高記憶體頻寬 率的記憶體存㈣統。f料排列單元10自視訊資:琢用 收視訊資料，並將所接收的視訊資料重新排列成至少二接 訊資料區塊—主區塊及附加區塊。主區塊的 硯 汽竹經牲 別排列後，使得視訊資料於後續得以循序且連續地進行、 取’且視訊資料量可調適於—已知記憶體頻寬而不會2 了視訊品質。附加區塊的視訊資料可用以補 (complement)主區塊視訊資料的不足。簡單來講主 區塊和附加區塊共同組成來自視訊資料源的完整視訊資 料。經排列之視訊資料可藉由資料匯流排寫入記憶體裝置 仏接著’裝£ μ或處理器可有效地藉纟資料匯流排以 存取或讀取記憶體裝置12的視訊資料。由於視訊資料係 特別地排列於記憶體裝置12内，因此資料的存取即可以 使用循序方式來進行。藉此，得以增進記憶體頻寬的使用 率’也可降低存取時間，因而使得即時影像處理應用（例 如衫像縮放（image scaling)、去交錯（de-interlacing) 或框速率（fraine rate up conversion))得以實 201039355 在一實施例中’來自視訊資料源的視訊資料採用yuv 色彩空間格式’其中Y代表亮度（luma或brightness ) 成分’而U和V則代表色度（chrolninance或color )成 分。和YUV格式類似的有γ，υν、YCbCr及TPbPr等。 雖然本實施例以YUV色彩空間格式為例，然而本發明也適 用於其他的色彩空間。第二圖例示γυν格式之部分視訊資 料的資料排列。其中’所接收的視訊資料1〇〇( YiUlVl )、 ❹（Y2U2V2)、（Y3U3V3)及（Y4U4V4)分別表示第一像 素、第二像素、第二像素及第四像素之成分。資料排列單 元10將所接收視訊資料1〇〇重新排列成二視訊資料區 塊一主區塊100A及附加區塊1〇〇B ^在本實施例中，移 除偶次像素的色度成分U和v，以形成主區塊τοοα。一 般來說，移除相鄰二像素當中的至少一色度成分。被移除 之色度成分u和v則用以構成附加區塊1〇〇B。主區塊 ❹100A的視訊資料及附加區塊i咖的視訊資料分別儲存 於記憶提裝置12内，如圖所示。接著，記憶體裝置12即 可被裝置14或處理器有欵地存取。 在第一例示實施例中，僅讀取記憶體裝置12的主區 塊100。由於-般觀者對於色度成分較不敏感， 因而不會 感知到被移除之色度成分U和v。在第二例示實施例中， 藉由内插法以回復被移除之色度成分。例如，被移 201039355 除之U2V2可藉由U1V1及U3V3之間進行内插而回復得 到。一般來說，被移除之色度成分可藉由前一像素及後一 像素之間進行内插而回復得到。在第三例示實施例中，依 序讀取主區塊100A的視訊資料及附加區塊1 oob的視訊 資料《如果記憶體裝置12具有多重埠（multi_p〇rt)功 能’則可同時讀取主區塊1 〇〇A及附加區塊1 oob的視訊 資料。 可依據記憶體頻寬的大小、允許的存取時間和影像品 質的要求來選擇第一、第二或第三例示實施例之作法。例 如，當記憶體頻寬不夠或者涉及即時應用時，可以選擇第 一例示實施例之作法。又例如，當影像品質要求很高且記 憶體頻寬不夠時，則可選擇第二例示實施例之作法。 第三圖顯示本發明實施例之資料排列單元10的詳細 方塊圖。在本實施例中，解多工器（demultiplexer ) 101 (或是控制開關）接收來自視訊資料源的視訊資料。經安 排之視訊資料（例如Y1U1V1Y2Y3U3V3Y4)從解多工器 101的第一輸出埠102A傳送至第一緩衝器l〇3A。被移 出之視訊資料（例如U2V2U4V4)則從解多工器1〇1的 第二輸出埠102B傳送至第二緩衝器103B。第一緩衝器 103A内的視訊資料及第二緩衝器103B内的視訊資料饋 201039355 . 至多工器（multiplexer) 105 (或是控制開關），筹依序 選擇第一緩衝器103A和第二緩衝器103B，並將視訊資 料分別儲存於記憶體裝置12的個別位置。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請專 利範圍内。 〇 【圖式簡單說明】 ， 第一圖方塊圖顯示本發明實施例之高記憶體頻寬使用率的 記憶體存取系統。 第二圖例示YUV格式之部分視訊資料的資料排列。 第三圖顯示本發明實施例之資料排列單元的詳細方塊圖。 Ο 201039355 【主要元件符號說明】 10 資料排列單元 12 記憶體裝置 14 裝置 100 視訊資料 100A 主區塊 100B 附加區塊 101 解多工器 102A 第一輸出埠 102B 第二輸出埠 103A 第一緩衝器 103B 第二緩衝器 105 多工器201039355 VI. Description of the Invention: [Technical Field] The present invention relates to memory access, and more particularly to a method of arranging video data for high memory bandwidth usage and high efficiency memory data access. [Prior Art] The memory bandwidth is the rate at which the semiconductor memory device data is depleted or read, which is usually expressed in bytes per second. Since memory devices in electronic systems are often used in common between processors or devices, memory resources are often very valuable and memory bandwidth is often perceived to be lacking. One way to increase the bandwidth of a memory is to have a processor or device have exclusive access to sequentially access the entire block of data each time. For example, some memory devices provide a bum mode, and the entire block data can be transmitted without interruption when the start address and some necessary control signals are supplied to the memory device. However, the device is required to perform random access to store or read the data in the memory = centered position. For this type of access, since the access fee is equivalent to every two materials, (four) to provide the memory and control signals, the use efficiency of the memory bandwidth is not large. 201039355 When the memory device acts as a video buffer (or frame buffer) for storing video data (especially high-density video data) or involves instant image processing, the random access loss of the aforementioned memory device will become worse. . In view of the inefficient use of memory bandwidth for video data and the inability to implement instant image playback, a novel mechanism is needed to increase the efficiency of memory data access. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a memory access system and method for efficiently utilizing memory bandwidth without sacrificing video quality. According to an embodiment of the invention, the data arrangement unit arranges the video data into at least one main block and an additional block, which are respectively stored in the memory device. The video data is specially arranged to enable the main block video data in the memory device to be sequentially read by a device or a processor. In one embodiment, the data scheduling unit removes at least one chrominance component (e.g., u or V component) of adjacent two pixels while maintaining a luminance component (e.g., a Y component) of the pixel, thereby forming a primary block. 5 201039355 [Embodiment] The first block diagram shows a memory storage (four) system of a high memory bandwidth according to an embodiment of the present invention. The f-arrangement unit 10 is self-viewing video: the video data is collected and the received video data is rearranged into at least two communication data blocks - a primary block and an additional block. After the main blocks are arranged, the video data is sequentially and continuously performed, and the amount of video data is adjusted to be suitable for the known memory bandwidth without the video quality. The video data of the additional block can be used to compensate for the lack of video data of the main block. Simply put, the main block and the additional block together form a complete video material from the video source. The aligned video data can be written to the memory device by means of a data bus. Then, the processor can effectively borrow data buffers to access or read the video data of the memory device 12. Since the video data is particularly arranged in the memory device 12, access to the data can be performed in a sequential manner. In this way, the use of memory bandwidth can be increased to reduce access time, thus enabling instant image processing applications (such as image scaling, de-interlacing or fran rate up). Conversion)) 201031355 In one embodiment, 'video data from a video source uses a yuv color space format' where Y represents brightness (luma or brightness) component and U and V represent chroma (color) (chrolninance or color) components . Similar to the YUV format, there are γ, υν, YCbCr, and TPbPr. Although the present embodiment takes the YUV color space format as an example, the present invention is also applicable to other color spaces. The second figure illustrates the data arrangement of some of the video data in the γυν format. The received video data 1 〇〇 ( YiUlVl ), ❹ (Y2U2V2), (Y3U3V3), and (Y4U4V4) represent components of the first pixel, the second pixel, the second pixel, and the fourth pixel, respectively. The data arranging unit 10 rearranges the received video data 1 into two video data blocks, a main block 100A and an additional block 1 〇〇 B. In this embodiment, the chrominance component U of the even-order pixel is removed. And v to form the main block τοοα. In general, at least one chroma component of adjacent two pixels is removed. The removed chrominance components u and v are used to form additional blocks 1 〇〇 B. The video data of the main block ❹100A and the video data of the additional block i coffee are respectively stored in the memory lifting device 12 as shown in the figure. The memory device 12 can then be accessed by the device 14 or processor. In the first exemplary embodiment, only the main block 100 of the memory device 12 is read. Since the viewer is less sensitive to chroma components, the removed chroma components U and v are not perceived. In the second exemplary embodiment, the removed chrominance component is recovered by interpolation. For example, U2V2, which was moved by 201039355, can be recovered by interpolating between U1V1 and U3V3. In general, the removed chrominance component can be recovered by interpolating between the previous pixel and the next pixel. In the third exemplary embodiment, the video data of the main block 100A and the video data of the additional block 1 oob are sequentially read, and if the memory device 12 has the multi_p〇rt function, the main reading can be simultaneously performed. Block 1 〇〇A and additional block 1 oob video data. The first, second or third exemplary embodiment can be selected depending on the size of the memory bandwidth, the allowed access time, and the quality of the image. For example, when the memory bandwidth is insufficient or involves immediate application, the first exemplary embodiment can be selected. For another example, when the image quality is high and the memory bandwidth is insufficient, the second exemplary embodiment can be selected. The third figure shows a detailed block diagram of the data arrangement unit 10 of the embodiment of the present invention. In this embodiment, a demultiplexer 101 (or a control switch) receives video material from a video source. The arranged video material (e.g., Y1U1V1Y2Y3U3V3Y4) is transmitted from the first output port 102A of the demultiplexer 101 to the first buffer 103A. The removed video material (e.g., U2V2U4V4) is transferred from the second output port 102B of the demultiplexer 101 to the second buffer 103B. The video data in the first buffer 103A and the video data in the second buffer 103B are fed to the multiplexer 105 (or the control switch), and the first buffer 103A and the second buffer are sequentially selected. 103B, and the video data is stored in individual locations of the memory device 12. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1 is a block diagram showing a memory access system for high memory bandwidth usage in an embodiment of the present invention. The second figure illustrates the data arrangement of some video data in the YUV format. The third figure shows a detailed block diagram of the data arrangement unit of the embodiment of the present invention. Ο 201039355 [Description of main component symbols] 10 Data arrangement unit 12 Memory device 14 Device 100 Video data 100A Main block 100B Additional block 101 Demultiplexer 102A First output port 102B Second output port 103A First buffer 103B Second buffer 105 multiplexer