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TW201039090A - Bandgap reference circuits - Google Patents

Bandgap reference circuits Download PDF

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Publication number
TW201039090A
TW201039090A TW98112618A TW98112618A TW201039090A TW 201039090 A TW201039090 A TW 201039090A TW 98112618 A TW98112618 A TW 98112618A TW 98112618 A TW98112618 A TW 98112618A TW 201039090 A TW201039090 A TW 201039090A
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Taiwan
Prior art keywords
transistor
coupled
voltage
resistor
gate
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TW98112618A
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Chinese (zh)
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TWI380154B (en
Inventor
Jr Rogelio L Erbito
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Vanguard Int Semiconduct Corp
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Abstract

A bandgap reference circuit is provided. An input node receives a supply voltage. An output node provides a reference voltage. A first transistor is coupled between the input node and the output node and has a first control terminal. A resistor is coupled between the input node and the first control terminal. A second transistor is coupled to the first control terminal and has a second control terminal coupled to the output node. A third transistor is coupled between the second transistor and a ground terminal and has a third control terminal. A voltage dividing unit provides a first voltage and a second voltage according to the reference voltage. A differential amplifier provides a signal to the third control terminal according to a difference between the first and second voltages.

Description

201039090 六、發明說明: 【發明所屬之技術領域】 本發明係有關於一種能隙(bandgap)參考電路,特別 是有關於一種高壓且低靜止電流的能隙參考電路。 【先前技術】 電子電路,例如類比對數位轉換器、線性或切換電壓 穩壓器(regulator)等’通常需要使用到參考電壓來進行 正常操作’其中參考電壓為不會受到溫度及供應電壓變化 影響的一種穩定電壓。一般而言,能隙參考電路為一種常 見的參考電路,其可提供與溫度及供應電壓無關之參考電 壓,亦稱為能隙電壓。 第1圖係顯不一種傳統之能隙參考電路1〇〇。能隙參考 電路100係使用回授迴路方式來建立操作點,使得輸出電 壓VREF可藉由第-電壓以及第二電壓而產生。其中,第 電壓係與操作在不同電流密度之電晶體對^及Q2的基 極對射極電壓差UVBE)之倍數有關,而第二電壓係與電 ❾晶體Q3的基極對射極電壓(Vbe)有關。在第i圖中,電 曰曰體Ql、Q2及Q3皆為NPN型雙極性接面電晶體(bip〇iar junction transistor,BJT)。此外,第一電壓 AVbe 與絕對 溫度(PTAT)成比例,因此具有正溫度係數,而第二電壓 vBE具有負溫度係數。因此,KAVbe (κ為倍數)與基極對 射極電壓VBE的總和會產生幾乎與溫度及供應電壓無關之 電壓。 ,一般而s,為了適當的效能,類比電路需要一個穩定 之能隙電壓。然而,大多數之高壓類比電路的能隙電壓容 VISS004/0516-A41825twf . 201039090 易受到溫度及供應電壓的影響。因此,需要一種能提供高 電壓以及低靜止電流之能隙參考電路以供高壓類比電路使 用。 【發明内容】 本發明提供一種能隙參考電路,包括:一輸入節點, 用以接收一供應電壓;一輸出節點,用以提供一參考電壓; ' 一第一電晶體,耦接於上述輸入節點以及上述輸出節 • 點之間,具有一第一控制端;一第一電阻,耦接於上述輸 〇❹入節點以及上述第一控制端之間;一第二電晶體,耦接於 上述第一控制端,具有一第二控制端耦接於上述輸出節 點;一第三電晶體,耦接於上述第二電晶體以及一接地端 之間,具有一第三控制端;一分壓單元,根據上述參考電 壓提供一第一電壓以及一第二電壓;以及,一差動放大器, 根據上述第一電壓以及上述第二電壓之間的一電壓差提供 一信號至上述第三控制端。 再者,本發明提供另一種能隙參考電路,包括:一輸 〇 〇 入節點,用以接收一供應電壓;一輸出節點,用以提供一 ' 參考電壓;一第一電晶體,耦接於上述輸入節點以及上述 • 輸出節點之間,具有一閘極;一第一電阻,耦接於上述輸 入節點以及上述第一電晶體的閘極之間;一第一 NPN型雙 極性接面電晶體,耦接於上述第一電晶體之閘極,具有一 基極耦接於上述輸出節點;一第二電晶體,耦接於上述第 一 NPN型雙極性接面電晶體以及一接地端之間,具有一閘 極;一分壓單元,根據上述參考電壓提供一第一電.壓以及 一第二電壓;以及,一差動放大器,根據上述第一電壓以 VISS004/0516-A41825twf 5 201039090 及上述第二電壓之間的一電壓差提供一信號至上述第二電 晶體之閘極,其中上述第一電晶體以及上述第二電晶體為 N型金氧半導體電晶體,以及上述第—電日日日體之崩潰電壓 係高於上述第二電晶體之崩潰電壓。 【實施方式】 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳 • 細說明如下: °〇 實施例: 對電源應用元件而言,雙極性(Bipolar) _互補金氧半 導體(Complementary Metal Oxide Semiconductor,CMOS) 雙擴散金屬氧化物半導體(Double diffused Metal Oxide Semiconductor ’ DMOS)製程,亦簡稱為BCD製程,係一 種廣泛使用的半導體製程。藉由使用BCD製程,可同時在 一電路/元件内提供低壓金氧半導體電晶體、高壓金氧半導 〇 Ο 體電晶體(DMOS )以及雙極性接面電晶體(bipolar junction transistor,BJT ) ( NPN 型及 PNP 型皆可)。BCD 製程的 • 優點之一是可使用高壓元件。此外,藉由BCD製程所提供 之NPN型雙極性接面電晶體,亦可達成好的元件匹配特 性,以便降低在差動放大器之輸入端上的偏移量。 第2圖係顯示根據本發明一實施例所述之能隙參考電 路200之方塊圖。能隙參考電路200可從輸入節點Nin接收 供應電壓.VCC,並於輸出節點Nm提供參考電壓VREF。 能隙參考電路200包括電晶體Ml、M2及Q1、電阻R1、 VISS004/0516-A41825twf 6 201039090 差動放大器210以及分壓單元220。分厭留_ 一 ^ no -η^ I半疋220包括三 電阻R2、幻及R4以及電晶體Q2 體⑷及電晶體Μ2為Ν型金氧半導體電晶體。 晶體Q1為ΝΡΝ型雙極性接面電晶體, 剂雔故以从 &amp; Α 遐而電晶體Q2為ΡΝΡ 型雙極性接面電晶體。在能隙參考雷201039090 VI. Description of the Invention: [Technical Field] The present invention relates to a bandgap reference circuit, and more particularly to a bandgap reference circuit for high voltage and low quiescent current. [Prior Art] Electronic circuits, such as analog-to-digital converters, linear or switching voltage regulators, etc., usually require a reference voltage for normal operation. The reference voltage is not affected by temperature and supply voltage variations. A stable voltage. In general, the bandgap reference circuit is a common reference circuit that provides a reference voltage independent of temperature and supply voltage, also known as bandgap voltage. Figure 1 shows a conventional bandgap reference circuit. The bandgap reference circuit 100 uses a feedback loop mode to establish an operating point such that the output voltage VREF can be generated by the first voltage and the second voltage. Wherein, the voltage system is related to a multiple of the base-to-emitter voltage difference UVBE of the transistor pair and Q2 operating at different current densities, and the second voltage system is opposite to the base-to-emitter voltage of the electro-optical crystal Q3 ( Vbe) related. In the figure i, the electrodes Ql, Q2 and Q3 are NPN type bipolar junction transistors (BJT). Further, the first voltage AVbe is proportional to the absolute temperature (PTAT) and thus has a positive temperature coefficient, and the second voltage vBE has a negative temperature coefficient. Therefore, the sum of KAVbe (k is a multiple) and the base-to-emitter voltage VBE produces a voltage that is almost independent of temperature and supply voltage. In general, s, for proper performance, the analog circuit requires a stable bandgap voltage. However, the voltage gap voltage of most high voltage analog circuits is VISS004/0516-A41825twf . 201039090 is susceptible to temperature and supply voltage. Therefore, there is a need for a bandgap reference circuit that provides high voltage and low quiescent current for use in high voltage analog circuits. SUMMARY OF THE INVENTION The present invention provides a bandgap reference circuit comprising: an input node for receiving a supply voltage; an output node for providing a reference voltage; and a first transistor coupled to the input node And a first control terminal between the output node and the point; a first resistor coupled between the input node and the first control terminal; and a second transistor coupled to the first a control terminal having a second control terminal coupled to the output node; a third transistor coupled between the second transistor and a ground terminal, having a third control terminal; a voltage dividing unit, And providing a first voltage and a second voltage according to the reference voltage; and a differential amplifier providing a signal to the third control terminal according to a voltage difference between the first voltage and the second voltage. Furthermore, the present invention provides another energy gap reference circuit comprising: an input node for receiving a supply voltage; an output node for providing a 'reference voltage; a first transistor coupled to The input node and the output node have a gate; a first resistor coupled between the input node and the gate of the first transistor; a first NPN-type bipolar junction transistor a gate coupled to the first transistor, having a base coupled to the output node; a second transistor coupled between the first NPN-type bipolar junction transistor and a ground terminal Having a gate; a voltage dividing unit, providing a first voltage and a second voltage according to the reference voltage; and a differential amplifier, according to the first voltage, VISS004/0516-A41825twf 5 201039090 and the above a voltage difference between the second voltages provides a signal to the gate of the second transistor, wherein the first transistor and the second transistor are N-type MOS transistors, and the above Day day crash electrical system voltage is higher than the body of the breakdown voltage of the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Example: For a power application component, a Bipolar CMOS-Complementary Metal Oxide Semiconductor (CMOS) Double Diffusion Metal Oxide Semiconductor (DMOS) process, also referred to as a BCD process, A widely used semiconductor process. By using the BCD process, a low-voltage MOS transistor, a high-voltage MOS transistor, and a bipolar junction transistor (BJT) can be simultaneously provided in one circuit/element ( NPN type and PNP type are available). One of the advantages of the BCD process is the availability of high voltage components. In addition, the NPN-type bipolar junction transistor provided by the BCD process can achieve good component matching characteristics to reduce the offset at the input of the differential amplifier. Figure 2 is a block diagram showing a bandgap reference circuit 200 in accordance with an embodiment of the present invention. The bandgap reference circuit 200 can receive the supply voltage .VCC from the input node Nin and provide the reference voltage VREF at the output node Nm. The bandgap reference circuit 200 includes transistors M1, M2 and Q1, a resistor R1, a VISS004/0516-A41825twf 6 201039090 differential amplifier 210, and a voltage dividing unit 220. The sub-relationship _ a ^ no - η ^ I half 疋 220 includes three resistors R2, phantom and R4, and the transistor Q2 body (4) and the transistor Μ 2 are Ν-type MOS transistors. The crystal Q1 is a ΝΡΝ-type bipolar junction transistor, and the transistor is a ΡΝΡ-type bipolar junction transistor from &amp; Α 遐 and the transistor Q2. Reference gap in the energy gap

峪200内,電晶體Ml 係耦接於輸入節點Nin以及輸出節點N iN〇ut之間。雷P且R1将 耦接於輸入節點Nin以及電晶體]Vfl &amp; '、 的閘極之間。電晶體In the 峪200, the transistor M1 is coupled between the input node Nin and the output node N iN〇ut. Thunder P and R1 will be coupled between the input node Nin and the gate of the transistor]Vfl &amp; '. Transistor

Q1係耦接於電晶體Ml的閘極以及雷曰触λ ^ 入电日日體M2之間,盆中 電晶體Q1的基極係耦接至輸出節點Ν 接於電晶體Q1以及接地端GND之間,甘丄 ± 间其中電晶體M2的 閘極係耦接至差動放大器210的輪出她各、 询。在分壓單元220 内,電阻R2係耦接於輸出節點N〇m以及電阻幻之間,而 電阻R4係耦接於電阻R3以及電晶體Q2之間,其^電晶 體Q2的基極係耦接至接地端GND。 /' 90 參考第2圖’當電流流經分壓單元22〇時,分壓單元 220會產生參考電壓VREF、電壓vi以及電壓v2。此外, 跨在電阻R3上的電壓(即電壓VI與電壓V2之間的電壓 差)可藉由差動放大器210放大’以便產生信號ampout 來控制電晶體M2 ’進而改變流過電晶體M2之電流的大 小。由於在電晶體M2上電流的改變,電阻Ri上的跨壓亦 會隨著改變。電阻R1上跨壓的改變可調整電晶體Ml之閘 極對源極電壓,接著流經電晶體Ml的電流亦會跟著改變, 進而最後將參考電壓VREF穩壓於所想要的電壓值。值得 注意的是,電晶體Ml之崩潰電壓係高於電晶體M2以及差 . 動放大器210内電晶體之崩潰電壓。此外,雖然供應電壓 VISS004/0516-A41825twf 7 201039090 vcc會從低電壓位準改變至高電M位準,然而藉由穩定電 晶體M2之汲極對源極電壓,電晶體Q1可斟 ’ J电日日體]M2接 供保護。 第3圖係顯示根據本發明另一實施例所述之能隙參考 電路300之方塊圖。能隙參考電路300可從輪入節點 接收供應電壓VCC ’並於輸出節點Nout提供參考電壓 VREF。能隙參考電路300包括電晶體]VH、M2及Qi、電 • 阻R卜差動放大器310、分壓單元320以及啟動電路33〇。 〇 Ο 差動放大器310包括電晶體Μ5-Μ8及Q3-Q6與電阻 R7-R9,其中電晶體Μ5及電晶體Μ6為Ρ型金氧半導體電 晶體,而電晶體Μ7及電晶體Μ8為Ν型金氧半導體電晶 體’以及電晶體Q3-Q6為ΝΡΝ型雙極性接面電晶體。如先 前所描述,分壓單元320包括三電阻R_2、R3及R4以及電 晶體Q2。啟動電路330包括電阻R5和R6以及電晶體M3 和Μ4,其中電晶體M3和電晶體Μ4為Ν型金氧半導體電 ❹ 晶體。值得注意的是’電晶體Ml之崩潰電壓係高於電晶 體M2以及差動放大器310和啟動電路33〇内電晶體之崩 潰電壓。再者,電容C1係耦接於電晶體m2之閘極以及輸 ' 出節點Nout之間。電容C1係作為補償,以便綠認能隙參考 電路3 00為穩定狀態。 在啟始電路330中,電阻R6係耦接於電阻R5以及電 晶體M4之間。電晶體M4的閘極係耦接於電阻R5以及電 阻R6之間。電晶體M3係耦接於電晶體M2之閘極以及接 地端GND之間’其中電晶體M3之閘極係搞接於電卩且R6 以及電晶體M4之間。在差動放大器31〇中,電阻R7、R8 VISS004/0516-A41825twf 8 201039090 和R9係分職接至輪出節點Ν_。電晶體_係輕接 阻R8以及電晶體Μ8之間’其中電晶體Μ6之閘極係耦接 至接地端GND。電晶體Μ5係耗接於電阻R7j^電晶體 M7之間八中電曰曰體μ5之閘極係轉接至接地端gnd。 此外,電晶體Q 6係㈣於電阻R 9卩及接地端⑽D之間, 而電晶體Q5係耗接於接地端咖以及一節點之間,其中 上述節點係位於電晶體Q3和電晶體Q4之間。電晶體Q3 Ο ◎ 係麵接於上述節點以及電阻R8之間,其中電晶體Q3之基 極,接於電阻R3和電阻R4之間,並用以接收電壓v2。 電曰曰體Q 4 _接於上述節點以及電阻R7之間,其中電晶 體Q4之基極係麵接於電阻R2和電阻幻之間,並用以接 收電壓VI。 參考第3 ® ’首先’當供應電壓VCC從GV開始攸升 時’能隙參考電路300内的全部信號皆位於低電壓位準。 接著’電晶體Ml的閘極會隨著供應電壓vcc而改變,因 ❹ 此電晶體Ml之閘極對源極電壓會增加。當供應電壓vcc •◎增加時,流經電晶體M1之電流亦會開始跟著增加,其中 上述電流會被供應至能隙參考電路3〇〇内耦接於電晶體 Ml之全部分支電路内。接著,#上述電流流經分壓單元 320時’參考電壓VREF會開始爬升而電壓V1和V2亦會 跟著產生。因此,電阻R3上的跨壓(即電壓V1和電壓 V2之間的電壓差)會跟著增加,並與參考電壓VREF之上 升值成比例。 接著’電阻R3上的跨壓可改變差動放大器31〇内差動 對電晶體Q4和Q3之間電流的差異。在差動放大器31〇内, VISS004/0516-A41825twf „ 201039090 :1Q3為甘電晶體Q4的N倍大’用以形成基極對射極電 BE,,、為電晶體Q4之基極對射極電壓以及電晶體 Q3之基極對射極電壓之間的電壓差,其中流經電晶體印 之電流係大於流經電晶體Q 4之電流。當電阻R 3之跨壓小 於基極對射極電壓差么乂抑時,基極對射極電壓差△、扯可 根據下列算式(1)而求得: hVBE=Vtx\nN ( 1 )The Q1 is coupled between the gate of the transistor M1 and the lightning contact λ ^ between the input and the solar body M2. The base of the transistor Q1 in the basin is coupled to the output node Ν connected to the transistor Q1 and the ground GND. Between the Ganzi±between the gate of the transistor M2 is coupled to the differential amplifier 210 for her turn. In the voltage dividing unit 220, the resistor R2 is coupled between the output node N〇m and the resistor phantom, and the resistor R4 is coupled between the resistor R3 and the transistor Q2, and the base of the transistor Q2 is coupled. Connect to ground GND. /' 90 Reference Fig. 2 When the current flows through the voltage dividing unit 22, the voltage dividing unit 220 generates the reference voltage VREF, the voltage vi, and the voltage v2. In addition, the voltage across the resistor R3 (ie, the voltage difference between the voltage VI and the voltage V2) can be amplified by the differential amplifier 210 to generate the signal ampout to control the transistor M2' to thereby change the current flowing through the transistor M2. the size of. Due to the change in current on transistor M2, the voltage across the resistor Ri will also change. The change in the voltage across the resistor R1 adjusts the gate-to-source voltage of the transistor M1, and then the current flowing through the transistor M1 also changes, and finally the reference voltage VREF is regulated to the desired voltage value. It is worth noting that the breakdown voltage of the transistor M1 is higher than that of the transistor M2 and the breakdown voltage of the transistor in the dynamic amplifier 210. In addition, although the supply voltage VISS004/0516-A41825twf 7 201039090 vcc will change from the low voltage level to the high power M level, by stabilizing the drain voltage of the transistor M2 to the source voltage, the transistor Q1 can be used Japanese body] M2 is available for protection. Figure 3 is a block diagram showing a bandgap reference circuit 300 in accordance with another embodiment of the present invention. The bandgap reference circuit 300 can receive the supply voltage VCC' from the wheel-in node and provide the reference voltage VREF at the output node Nout. The bandgap reference circuit 300 includes transistors [VH], M2, and Qi, an electric resistance R-differential amplifier 310, a voltage dividing unit 320, and a starting circuit 33A.差 The differential amplifier 310 includes transistors Μ5-Μ8 and Q3-Q6 and resistors R7-R9, wherein the transistor Μ5 and the transistor Μ6 are Ρ-type MOS transistors, and the transistor Μ7 and the transistor Μ8 are Ν-type The MOS transistor 'and the transistor Q3-Q6 are ΝΡΝ-type bipolar junction transistors. As described earlier, the voltage dividing unit 320 includes three resistors R_2, R3, and R4 and a transistor Q2. The start-up circuit 330 includes resistors R5 and R6 and transistors M3 and Μ4, wherein the transistor M3 and the transistor Μ4 are Ν-type MOS transistors. It is worth noting that the breakdown voltage of the transistor M1 is higher than that of the transistor M2 and the breakdown voltage of the transistor in the differential amplifier 310 and the startup circuit 33. Furthermore, the capacitor C1 is coupled between the gate of the transistor m2 and the output node Nout. Capacitor C1 is used as a compensation so that the green bandgap reference circuit 300 is in a steady state. In the start circuit 330, the resistor R6 is coupled between the resistor R5 and the transistor M4. The gate of the transistor M4 is coupled between the resistor R5 and the resistor R6. The transistor M3 is coupled between the gate of the transistor M2 and the ground GND. The gate of the transistor M3 is connected between the gate and the transistor M4. In the differential amplifier 31〇, the resistors R7, R8 VISS004/0516-A41825twf 8 201039090 and the R9 are assigned to the wheel node Ν_. The transistor _ is connected between the light resistor R8 and the transistor Μ8, wherein the gate of the transistor Μ6 is coupled to the ground GND. The transistor Μ5 series is connected to the resistor R7j^ transistor M7. The gate of the zhongzhong electric body μ5 is switched to the ground terminal gnd. In addition, the transistor Q 6 is (four) between the resistor R 9 卩 and the ground terminal (10) D, and the transistor Q5 is consumed between the ground terminal and a node, wherein the node is located in the transistor Q3 and the transistor Q4. between. The transistor Q3 Ο ◎ is connected between the above node and the resistor R8, wherein the base of the transistor Q3 is connected between the resistor R3 and the resistor R4 and is used to receive the voltage v2. The electric body Q 4 _ is connected between the above node and the resistor R7, wherein the base of the electromorph Q4 is connected between the resistor R2 and the resistor illusion and is used to receive the voltage VI. Referring to the 3 ® 'first' when the supply voltage VCC starts to rise from the GV, all signals in the bandgap reference circuit 300 are at a low voltage level. Then, the gate of the transistor M1 changes with the supply voltage vcc because the gate-to-source voltage of the transistor M1 increases. When the supply voltage vcc • ◎ is increased, the current flowing through the transistor M1 will also start to increase, and the above current will be supplied to the band gap reference circuit 3 to be coupled to all the branch circuits of the transistor M1. Then, when the above current flows through the voltage dividing unit 320, the reference voltage VREF starts to climb and the voltages V1 and V2 are also generated. Therefore, the voltage across resistor R3 (i.e., the voltage difference between voltage V1 and voltage V2) will increase and is proportional to the rise above reference voltage VREF. Then, the voltage across the resistor R3 changes the difference in current between the differential amplifier 31 and the current between the transistors Q4 and Q3. In the differential amplifier 31〇, VISS004/0516-A41825twf „ 201039090 : 1Q3 is N times larger than the Q4 of the galvanic crystal Q to form the base-to-pole E, which is the base-to-emitter of the transistor Q4. Voltage and voltage difference between the base-to-emitter voltage of transistor Q3, wherein the current flowing through the transistor is greater than the current flowing through transistor Q4. When the voltage across resistor R3 is less than the base-to-emitter When the voltage difference is suppressed, the base-to-emitter voltage difference Δ and pulsation can be obtained according to the following formula (1): hVBE=Vtx\nN ( 1 )

〇〇 其中Vt為熱電壓(thermal voltage )。由於流經電晶體q3 之電流大於流經電晶體Q4之電流且電阻R7和電阻R8具 有相同的電阻值’電阻R8上的跨壓會大於電阻R7上的跨 壓。因此,流經電晶體M6之電流會小於流經電晶體M5 之電流’然後電晶體M8會將電晶體M2之閘極下拉,以便 將電晶體M2關閉。當沒有電流流經電晶體M2、電晶體 Q1以及電阻R1時,電晶體Ml的閘極會隨著供應電壓VCC 持續增加。接著,參考電壓VREF會隨著供應電壓VCC增 加直到電阻R3上的跨壓稍微大於基極對射極電壓差 △Vbe 0 當電阻R3上的跨壓稍微大於基極對射極電壓差AVbe 時’流經電晶體Q4的電流會變的比流經電晶體Q3的電流 還大。接著,電阻R7上的跨壓會大於電阻R8上的跨壓。 因此’流經電晶體M6的電流將會大於流經電晶體M5的電 流,然後電晶體M6會將電晶體M2之閘極上拉。接著,對 電晶體M2而言,閘極對源極電壓的增加將會得到更多的 電流,而電阻R1上的跨壓亦會隨著增加。電阻R1上跨壓 的增加意謂著電晶體Ml具有穩定之閘極對源極電壓,其 VISS004/0516-A41825twf 10 201039090 當流經電晶體M1 VREF可根據下列 將使得流經電晶體]νπ之電流變為穩定。 之電流沒有長時間的增加時,參考電壓 算式(2)而求得: vREF=vBEQ2+[^yVtXlnN (2) 其中VBEQ2為電晶體Q2之基極對射極電壓。基極對射極電 壓V卿具有負溫度係數’而熱電壓\的倍數具有正溫度〇〇 where Vt is the thermal voltage. Since the current flowing through transistor q3 is greater than the current flowing through transistor Q4 and resistor R7 and resistor R8 have the same resistance value, the voltage across resistor R8 will be greater than the voltage across resistor R7. Therefore, the current flowing through the transistor M6 will be less than the current flowing through the transistor M5' and then the transistor M8 will pull down the gate of the transistor M2 to turn off the transistor M2. When no current flows through the transistor M2, the transistor Q1, and the resistor R1, the gate of the transistor M1 continues to increase with the supply voltage VCC. Then, the reference voltage VREF increases with the supply voltage VCC until the voltage across the resistor R3 is slightly larger than the base-to-emitter voltage difference ΔVbe 0 when the voltage across the resistor R3 is slightly larger than the base-to-emitter voltage difference AVbe' The current flowing through the transistor Q4 becomes larger than the current flowing through the transistor Q3. Then, the voltage across the resistor R7 will be greater than the voltage across the resistor R8. Therefore, the current flowing through the transistor M6 will be greater than the current flowing through the transistor M5, and then the transistor M6 will pull up the gate of the transistor M2. Next, for transistor M2, the increase in gate-to-source voltage will result in more current, and the voltage across resistor R1 will also increase. The increase in voltage across resistor R1 means that transistor M1 has a stable gate-to-source voltage, which is VISS004/0516-A41825twf 10 201039090. When flowing through transistor M1 VREF, it can flow through the transistor according to the following] The current becomes stable. When the current does not increase for a long time, the reference voltage is calculated by the equation (2): vREF=vBEQ2+[^yVtXlnN (2) where VBEQ2 is the base-to-emitter voltage of the transistor Q2. The base-to-emitter voltage Vqing has a negative temperature coefficient' and the multiple of the thermal voltage has a positive temperature

係數。因此,算式⑺巾參數之總和可使得能隙參考電路 300不會受到溫度及供應電壓影響。 在啟動狀態巾’當參考電壓VREF小於傳統上導通之 雙極性接面電晶體的基極對射極電壓時,由於電晶體q5 之集極對射極電壓為低電壓,使得電晶體Q5之^0極電流 會非常小。電晶體Q5之基極電流相同於流經電晶體及 電阻R9之電流。再者,由於電晶體Q5是操作在飽和區, 因此電晶體Q5之集極電流會小於電晶體Q6之集極電流。 相似地,電晶體Q3及電晶體Q4之集極對射極電壓亦為 電壓,所以電晶體Q3及電晶體Q4皆操作在飽和區。此》時; 由於差動放大器310為不工作,電晶體Q3及電晶體Q4 之間沒有電流差’因此電晶體M2的閘極將會被設定成任 意值。因為雜訊或元件不匹配的問題可能存在於能隙參考 電路3 00内,電晶體M2的閘極上的電壓可能會被拉高至 足以引進電流至電晶體M2内。因此’電阻ri上的跨壓會 增加’而流經電晶體Ml之電流會減少。如此,參考電壓 VREF將停止增加,並停留在低於想要電壓值之值。 當參考電壓VREF低於傳統上導通之雙極性接面電晶 VISS004/0516-A41825twf 11 201039090 體的基極對射極電壓時,啟動電路330會下拉電晶體Μ2 之閘極’以確保電流仍流經電晶體Ml。藉由將電晶體Μ2 關閉’電晶體Ml之閘極上的電壓會相等於供應電壓 VCC’因而可提供電流至能隙參考電路3〇〇之全部分支 内。當參考電壓VREF達到傳統上導通之雙極性接面電晶 體的基極對射極電壓時’差動放大器31〇會開始工作,而 電晶體M3會被關閉。既然差動放大器31〇開始工作,則 參考電壓VREF會被穩定至上述算式(2)所得到之電壓值。coefficient. Therefore, the sum of the parameters of equation (7) can make the bandgap reference circuit 300 unaffected by temperature and supply voltage. In the startup state, when the reference voltage VREF is smaller than the base-to-emitter voltage of the conventionally turned-on bipolar junction transistor, since the collector-to-emitter voltage of the transistor q5 is at a low voltage, the transistor Q5 is The 0 pole current will be very small. The base current of transistor Q5 is the same as the current flowing through the transistor and resistor R9. Furthermore, since transistor Q5 is operating in the saturation region, the collector current of transistor Q5 will be less than the collector current of transistor Q6. Similarly, the collector-to-emitter voltages of transistor Q3 and transistor Q4 are also voltages, so both transistor Q3 and transistor Q4 operate in the saturation region. At this time; since the differential amplifier 310 is inoperative, there is no current difference between the transistor Q3 and the transistor Q4' so that the gate of the transistor M2 will be set to an arbitrary value. Since the problem of noise or component mismatch may exist in the bandgap reference circuit 300, the voltage on the gate of the transistor M2 may be pulled high enough to introduce current into the transistor M2. Therefore, the voltage across the resistor ri will increase and the current flowing through the transistor M1 will decrease. Thus, the reference voltage VREF will stop increasing and stay below the desired voltage value. When the reference voltage VREF is lower than the base-to-emitter voltage of the conventionally-conducting bipolar junction transistor VISS004/0516-A41825twf 11 201039090 body, the startup circuit 330 pulls down the gate of the transistor Μ2 to ensure that the current still flows. Via transistor Ml. By turning the transistor Μ2 off, the voltage on the gate of the transistor M1 is equal to the supply voltage VCC' and thus supplies current to all branches of the bandgap reference circuit 3''. When the reference voltage VREF reaches the base-to-emitter voltage of the conventionally turned-on bipolar junction transistor, the differential amplifier 31 will start operating and the transistor M3 will be turned off. Since the differential amplifier 31 〇 starts operating, the reference voltage VREF is stabilized to the voltage value obtained by the above formula (2).

〇 Ο 如先剛所描述,對BCD製程而言,能隙參考電路為穩 定的電路。此外,能隙參考電路能提供高電壓以及低靜止 電机。再者,在各種電源供應電壓範圍内,能隙參考電路 能達到低參考電壓變並且具有低靜止電流。 本發明雖以較佳實施例揭露如上,然其並非用以 ^發明=範圍,任何熟習此項技藝者,在不脫離本發明= 精神和範圍内,當可做些許的更動與潤倘, 保護範圍當視後附之申請專利範圍所界 發明之 【圖式簡單說明】 省·為率。 第1圖係顯示一種傳統之能隙參考電路· 第2圖係顯示根據本發明一實 路之方塊圖;以及 施例所述之能隙參考〇 Ο As described earlier, for the BCD process, the bandgap reference circuit is a stable circuit. In addition, the bandgap reference circuit provides high voltage and low static motors. Furthermore, the bandgap reference circuit can achieve low reference voltage variations and low quiescent current over a wide range of supply voltages. The present invention has been disclosed in the above preferred embodiments. However, it is not intended to be construed as limiting the scope of the invention. The scope of the invention is defined by the scope of the patent application. 1 is a conventional energy gap reference circuit. FIG. 2 is a block diagram showing a real circuit according to the present invention; and the energy gap reference described in the embodiment.

實施例所述之能隙參考 第3圖係顯示根據本發明另 電路之方塊圖。 【主要元件符號說明】 100、200、300〜能隙參考電路; 210、310〜差動放大器; VISS004/G516·Α41825twf 12 201039090 220、320〜分壓單元; 330〜啟動電路; AMP OUT〜信號; C1〜電容; GND〜接地端;Energy Gap Reference as described in the embodiment Fig. 3 is a block diagram showing another circuit in accordance with the present invention. [Major component symbol description] 100, 200, 300 ~ bandgap reference circuit; 210, 310~ differential amplifier; VISS004/G516·Α41825twf 12 201039090 220, 320~ voltage divider unit; 330~ start circuit; AMP OUT~ signal; C1~capacitor; GND~ground;

M1-M8、Q1-Q6〜電晶體; Nin〜輸入節點; N〇ut〜輸出節點; R1-R9〜電阻; VCC〜供應電壓;以及 VREF〜參考電壓。M1-M8, Q1-Q6~ transistor; Nin~ input node; N〇ut~ output node; R1-R9~ resistor; VCC~ supply voltage; and VREF~ reference voltage.

VISS004/0516-A41825twf 13VISS004/0516-A41825twf 13

Claims (1)

201039090 七、申請專利範圍: 1.一種能隙參考電路,包括: 一輸入節點,用以接收一供應電壓; 一輸出節點,用以提供一參考電壓; 一第一電晶體,耦接於上述輸入節點以及上述輸出節 點之間,具有一第一控制端; 一第一電阻,耦接於上述輸入節點以及上述第一控制 端之間;201039090 VII. Patent application scope: 1. A bandgap reference circuit comprising: an input node for receiving a supply voltage; an output node for providing a reference voltage; and a first transistor coupled to the input The node and the output node have a first control end; a first resistor coupled between the input node and the first control end; 一第二電晶體,耦接於上述第一控制端,具有一第二 控制端耦接於上述輸出節點; 一第三電晶體,耦接於上述第二電晶體以及一接地端 之間,具有一第三控制端; 一分壓單元,根據上述參考電壓提供一第一電壓以及 一第二電壓;以及 一差動放大器,根據上述第一電壓以及上述第二電壓 之間的一電壓差提供一信號至上述第三控制端。 2. 如申請專利範圍第1項所述之能隙參考電路,其中上 述第一電晶體以及上述第三電晶體為N型金氧半導體電晶 體,以及上述第一電晶體之崩潰電壓係高於上述第三電晶 體之崩潰電壓。 3. 如申請專利範圍第1項所述之能隙參考電路,其中上 述第二電晶體為NPN型雙極性接面電晶體。 4. 如申請專利範圍第1項所述之能隙參考電路,其中上 述分壓單元包括: . 一第二電阻,耦接於上述輸出節點; VISS004/0516-A41825twf 14 201039090 一第二電阻,耦接於上述第二電阻; 一第四電阻,耦接於上述第三電阻;以及 - PNP型雙極性接面電晶體,祕於上述第四電阻以 及上述接地端之間,具有一基極耦接於上述接地端, 其中上述第-電愿以及上述第二電壓之間的上述電壓 差係上述第三電阻之跨壓。a second transistor coupled to the first control terminal, having a second control terminal coupled to the output node; a third transistor coupled between the second transistor and a ground terminal, a third control terminal; a voltage dividing unit, providing a first voltage and a second voltage according to the reference voltage; and a differential amplifier providing a voltage difference between the first voltage and the second voltage The signal is to the third control terminal. 2. The gap reference circuit of claim 1, wherein the first transistor and the third transistor are N-type MOS transistors, and the breakdown voltage of the first transistor is higher than The breakdown voltage of the above third transistor. 3. The gap reference circuit of claim 1, wherein the second transistor is an NPN type bipolar junction transistor. 4. The gap reference circuit of claim 1, wherein the voltage dividing unit comprises: a second resistor coupled to the output node; VISS004/0516-A41825twf 14 201039090 a second resistor, coupled Connected to the second resistor; a fourth resistor coupled to the third resistor; and a PNP-type bipolar junction transistor, having a base coupling between the fourth resistor and the ground terminal And the voltage difference between the first power source and the second voltage is a voltage across the third resistor. 5. 如申請專利範圍第1項所述之能隙參考電路,更包括 一電容耦接於上述輸出節點以及上述第三控制端之間。 6. 如申請專利範圍第1項所述之能隙參考電路,更包 括: 一啟動電路’耦接於上述輸出節點以及上述第三控制 端之間。 I 7. 如申請專利範圍第6項所述之能隙參考電路,其中上 述啟動電路包括: ~ 第四電晶體’耦接於上述第三控制端以及上述接地 端之間,具有一第四控制端; 一第五電阻’耦接於上述輸出節點; 一第六電阻’耦接於上述第五電阻以及上述第四控制 端之間;以及 一第五電晶體’耦接於上述第四控制端以及上述接地 端之間’具有~第五控制端耦接於上述第五電阻以及上述 第六電阻之間。 8. 如申請專利範圍第1項所述之能隙參考電路,其中上 述差動放大器包括: 一第七電阻、一第八電阻以及一第九電阻分別耦接於 VISS004/0516-A41825twf 15 201039090 上述輸出節點,· 具有3:==::—述第增, 以及上述第#半導難m柄接於上述第八電阻 -第1=:=一閉極耦接於上述接地端; 金氧半導體電曰㉑ 電s曰體,耦接於上述第一 P型 °〇 Ο 於上二第:心二間’具有,_ 端以及上述接地端之門,且,曰體耦接於上述第三控制 金氧半導體電晶體之門極了 一閘極耦接於上述第一 N型 一節點【間雙3接!電晶體,耦接於上述第八電阻以及 一第用以接收上述第二電壓; 上述節點之間,具有:::曰曰體’耦接於上述第七電阻以及 -第三雙極性:面ίί用以接收上述第-電壓; 接地端之間,4 L:輕接於上述節點以及上述 ,、有一基極耦接於上述第九電阻;以及 匕、沉接祕山雙極性接面電晶體’耦接於上述第九電阻以及 ,l ^之間’具有一基極輕接於上述第九電阻。 述第,申第請專;範圍第8項所述之能隙參考電路,其中上 雙極性接面以曰^:以及第四雙極性接面電晶體為咖型 上利範圍第8項所述之能隙參考電路,其中 上述第-2極性接面電晶體係大於上述第二雙極性接 晶體’使得上述第—雙極性接面電晶體之基極對射極電壓 VISS004/0516-A41825twf 丨丄电! 201039090 與上述第二雙極性接面電晶體之基極對射極電壓之間有電 壓差存在。 11.一種能隙參考電路,包括: 一輸入節點,用以接收一供應電壓; 一輸出節點,用以提供一參考電壓; 一第一電晶體,耦接於上述輸入節點以及上述輸出節 點之間,具有一閘極; • 一第一電阻,耦接於上述輸入節點以及上述第一電晶 體的閘極之間; 一第一 NPN型雙極性接面電晶體,耦接於上述第一電 晶體之閘極,具有一基極耦接於上述輸出節點; 一第二電晶體,耦接於上述第一 NPN型雙極性接面電 晶體以及一接地端之間,具有一閘極; 一分壓單元,根據上述參考電壓提供一第一電壓以及 一第二電壓;以及 q —差動放大器,根據上述第一電壓以及上述第二電壓 〇 之間的一電壓差提供一信號至上述第二電晶體之閘極, 其中上述第一電晶體以及上述第二電晶體為N型金氧 ' 半導體電晶體,以及上述第一電晶體之崩潰電壓係高於上 述第二電晶體之崩潰電壓。 12·如申請專利範圍第11項所述之能隙參考電路,其中 上述分壓單元包括: 一第二電阻,耦接於上述輸出節點; 一第三電阻,耦接於上述第二電阻; 一第四電阻,耦接於上述第三電阻;以及 VISS004/0516-A41825twf 17 201039090 PNP型雙極性接面電晶體,耦接於上述第四電阻以 及上述接地端之間,具有一基極耦接於上述接地端, 其中上述第一電壓以及上述第二電壓之間的上述雷厭 差係上述第三電阻之跨磨。 錢 13.如申請專利範圍第u項所述之能隙參考電路, 括一電谷耦接於上述輸出節點以及上述第二電晶體 匕 之間。 叼閘極 %括14.如申請專利範圍帛11項所述之能隙參考電路,更包 電晶 一啟動電路,耦接於上述輸出節點以及上述第 體的閘極之間。 15. 如申請專利範圍第14項所述之能隙參考電路,复 上述啟動電路包括: ’,、中 一第三電晶體,耦接於上述第二電晶體的閘極以 述接地端之間,具有一閘極; 上 〇 〇 一第五電阻,耦接於上述輸出節點; 一第六電阻,耦接於上述第五電阻以及上述第三 體的閘極之間;以及 C電晶 一第四電晶體,耦接於上述第三電晶體的閘極以及 述接地端之間,具有一閘極耦接於上述第五電阻以 上 第六電阻之間。 上述 16. 如申請專利範圍第15項所述之能隙參考電路,复 上述第一電晶體之崩潰電壓係高於上述第三電晶體以’、中 述第四電晶體之崩潰電壓。 及上 17. 如申請專利範圍第u項所述之能隙參考電路,复 VISS004/0516-A41825twf /、中 201039090 上述差動放大器包括: 一第七電阻、一筮x雨 上述輸出節點;/電阻以及—第九電阻分職接於 一第五電晶體’轉接於上 接於上述接地端; a弟七電阻’具有-閘極輕 一第六電晶體,輕拣於 曰舻夕η 接於上述第八電阻以及上述第二電 日日體的閉極之間’具有—閑極麵接於上述接地端; 一第七電晶體,耦接 D 端之門,且古一心 述第五電晶體以及上述接地 為之間4有-閘極耦接於上述第五電晶體; 一第八電晶體’耦接於上述第二電晶體的閘極以及上 述接地端之間,具有一闡托鈿杜# 阄位Μ及上 ]極耦接於上述第七電晶體 一第二ΝΡΝ型雙極性拉而带s±上 阻以及-赴w 耦接於上述第八電 阻以及-即點之間’具有—基極用以接收 一第三卿型雙極性接面電晶體,輕接於上述第Ϊ電 阻以及上述節點之間,具有一基極用以接收上述第一第電 顧f雙極性接面電晶體,_於上述節_ ^途接地&amp;之間’具有一基極耦接於上述第九電阻;以 一第五㈣型雙極性接面電晶體,耦接於上述第九雷 阻以及上述接地端之間,具有—基_接於上述第九電阻電 如申請專利範圍帛17項所述之能隙參考電路 上述第五電晶體以及上述第六電晶體為?型金氧體 晶體,而上述第七電晶體以及上述第八電 半導體電晶體。 . 勹以尘金虱 19.如申請專利範圍第17項所述之能隙參 VISS004/0516-A41825twf 电塔’其中 ° 10 201039090 上述第二NPN型雙極性接面電晶體係大於上述第三NPN 型雙極性接面電晶體,使得上述第二NPN型雙極性接面電 晶體之基極對射極電壓與上述第三NPN型雙極性接面電 晶體之基極對射極電壓之間有電壓差存在。 20.如申請專利範圍第17項所述之能隙參考電路,其中 上述第一電晶體之崩潰電壓係高於上述第五、第六、第七 以及第八電晶體之崩潰電壓。5. The gap reference circuit of claim 1, further comprising a capacitor coupled between the output node and the third control terminal. 6. The gap reference circuit of claim 1, further comprising: a start circuit coupled to the output node and the third control terminal. I. 7. The energy gap reference circuit of claim 6, wherein the starting circuit comprises: ~ a fourth transistor coupled between the third control terminal and the ground terminal, having a fourth control a fifth resistor 'coupled to the output node; a sixth resistor 'coupled between the fifth resistor and the fourth control terminal; and a fifth transistor 'coupled to the fourth control terminal And the fifth control terminal is coupled between the grounding terminal and the fifth resistor and the sixth resistor. 8. The gap reference circuit of claim 1, wherein the differential amplifier comprises: a seventh resistor, an eighth resistor, and a ninth resistor respectively coupled to VISS004/0516-A41825twf 15 201039090 The output node, has a 3:==::-the first increase, and the ## semi-conductive hard m handle is connected to the eighth resistor - the first =: = a closed pole is coupled to the ground end; the MOS semiconductor The electric 曰 21 electric 曰 body is coupled to the first P type 〇Ο 上 上 上 上 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : a gate of the MOS transistor is coupled to the first N-type node (the double-connected 3-connector transistor, coupled to the eighth resistor and the first to receive the second voltage; Between the nodes, the ::: body is coupled to the seventh resistor and the third bipolar: the surface is used to receive the first voltage; between the ground, 4 L: lightly connected to the node and In the above, a base is coupled to the ninth resistor; and the 匕, sink Hill bipolar junction transistor 'coupled between said ninth resistor and, l ^' having a base connected to the ninth light resistance. Said, the application of the application, the bandgap reference circuit of the eighth item, wherein the upper bipolar junction is 曰^: and the fourth bipolar junction transistor is the coffee type. The gap reference circuit, wherein the second-th polarity junction electro-crystal system is larger than the second bipolar-connected crystal 'the base-to-emitter voltage of the first bipolar junction transistor is VISS004/0516-A41825twf 丨丄Electricity! 201039090 There is a voltage difference between the base-to-emitter voltage of the second bipolar junction transistor described above. 11. A bandgap reference circuit comprising: an input node for receiving a supply voltage; an output node for providing a reference voltage; a first transistor coupled between the input node and the output node a first resistor, coupled between the input node and the gate of the first transistor; a first NPN-type bipolar junction transistor coupled to the first transistor a gate having a base coupled to the output node; a second transistor coupled between the first NPN-type bipolar junction transistor and a ground terminal, having a gate; a unit, providing a first voltage and a second voltage according to the reference voltage; and q-differential amplifier, providing a signal to the second transistor according to a voltage difference between the first voltage and the second voltage 〇 a gate, wherein the first transistor and the second transistor are N-type gold oxide semiconductor transistors, and the breakdown voltage of the first transistor is higher than the second The breakdown voltage of the crystal. The energy gap reference circuit of claim 11, wherein the voltage dividing unit comprises: a second resistor coupled to the output node; a third resistor coupled to the second resistor; The fourth resistor is coupled to the third resistor; and the VISS004/0516-A41825twf 17 201039090 PNP type bipolar junction transistor is coupled between the fourth resistor and the ground end, and has a base coupled to the base The grounding end, wherein the lightning lag between the first voltage and the second voltage is a cross-grinding of the third resistor. The energy gap reference circuit as described in claim 5, wherein a valley is coupled between the output node and the second transistor 匕. The gate electrode includes a bandgap reference circuit as described in claim 11, and further includes a start-up circuit coupled between the output node and the gate of the first body. 15. The energy gap reference circuit of claim 14, wherein the starting circuit comprises: ', a third transistor, and a gate coupled to the second transistor to be between the ground terminals Having a gate; a fifth resistor coupled to the output node; a sixth resistor coupled between the fifth resistor and the gate of the third body; and C-Crystal The fourth transistor is coupled between the gate of the third transistor and the ground, and has a gate coupled between the fifth resistor and the sixth resistor. The above-mentioned 16. The energy gap reference circuit of claim 15, wherein the breakdown voltage of the first transistor is higher than the breakdown voltage of the fourth transistor by the fourth transistor. And 17. The energy gap reference circuit according to the scope of claim 5, the complex VISS004/0516-A41825twf /, 201039090, the differential amplifier comprises: a seventh resistor, a x x rain output node; / resistor And the ninth resistor is connected to a fifth transistor 'transferred to the grounding end; the third seven resistors have a gate light and a sixth transistor, which is lightly picked up at the 曰舻 η The eighth resistor and the closed pole of the second electric solar cell are connected to the ground end; the seventh transistor is coupled to the gate of the D terminal, and the fifth transistor is described in the past. And the grounding is between 4 and the gate is coupled to the fifth transistor; an eighth transistor is coupled between the gate of the second transistor and the grounding end, and has an explanation #阄阄 and upper] poles are coupled to the seventh transistor, the second type of bipolar pull, and the s±upper resistance and -to w are coupled to the eighth resistor and - the point between the 'has- The base is used to receive a third type of bipolar junction transistor, which is lightly connected Between the first Ϊ resistor and the node, there is a base for receiving the first galvanic bipolar junction transistor, and _ has a base coupling between the section _ ^ way ground &amp; Connected to the ninth resistor; a fifth (four) type bipolar junction transistor coupled between the ninth lightning resistance and the ground terminal, having a base _ connected to the ninth resistor as claimed in the patent application The energy gap reference circuit described in item 17 is the fifth transistor and the sixth transistor described above. A type of gold oxide crystal, and the seventh transistor and the eighth electric semiconductor transistor described above.勹以尘金虱 19. The energy gap as described in claim 17 of the scope of the VISS004/0516-A41825twf electric tower 'where ° 10 201039090 the above second NPN type bipolar junction electro-crystal system is larger than the third NPN The bipolar junction transistor has a voltage between the base-to-electrode voltage of the second NPN-type bipolar junction transistor and the base-to-emitter voltage of the third NPN-type bipolar junction transistor The difference exists. 20. The bandgap reference circuit of claim 17, wherein the first transistor has a breakdown voltage that is higher than a breakdown voltage of the fifth, sixth, seventh, and eighth transistors. VISS004/0516-A41825twf 20VISS004/0516-A41825twf 20
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI451226B (en) * 2011-02-23 2014-09-01 Himax Tech Inc Bandgap circuit and complementary start-up circuit
TWI470399B (en) * 2012-12-20 2015-01-21 Integrated Circuit Solution Inc Low voltage bandgap reference circuit
TWI569123B (en) * 2015-03-26 2017-02-01 晨星半導體股份有限公司 Ldo with high power conversion efficiency
CN111221370A (en) * 2018-11-16 2020-06-02 力旺电子股份有限公司 Bandgap reference start circuit and reference voltage generator

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI451226B (en) * 2011-02-23 2014-09-01 Himax Tech Inc Bandgap circuit and complementary start-up circuit
TWI470399B (en) * 2012-12-20 2015-01-21 Integrated Circuit Solution Inc Low voltage bandgap reference circuit
TWI569123B (en) * 2015-03-26 2017-02-01 晨星半導體股份有限公司 Ldo with high power conversion efficiency
CN111221370A (en) * 2018-11-16 2020-06-02 力旺电子股份有限公司 Bandgap reference start circuit and reference voltage generator
TWI711251B (en) * 2018-11-16 2020-11-21 力旺電子股份有限公司 Band-gap reference start-up circuit and voltage reference generator
US10847218B2 (en) 2018-11-16 2020-11-24 Ememory Technology Inc. Band-gap reference start-up circuit with greater noise margin for start-up
CN111221370B (en) * 2018-11-16 2021-11-09 力旺电子股份有限公司 Band-gap reference starting circuit and reference voltage generator

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