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TW201034078A - Methods for forming conformal oxide layers on semiconductor devices - Google Patents

Methods for forming conformal oxide layers on semiconductor devices Download PDF

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Publication number
TW201034078A
TW201034078A TW99100844A TW99100844A TW201034078A TW 201034078 A TW201034078 A TW 201034078A TW 99100844 A TW99100844 A TW 99100844A TW 99100844 A TW99100844 A TW 99100844A TW 201034078 A TW201034078 A TW 201034078A
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Taiwan
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substrate
plasma
oxide layer
chamber
cooling
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TW99100844A
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Chinese (zh)
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TWI442474B (en
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Agus S Tjandra
Christopher S Olsen
Johanes F Swenberg
Yoshitaka Yokota
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Applied Materials Inc
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Abstract

Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. In one or more embodiments, plasma oxidation is used to form a conformal oxide layer by controlling the temperature of the semiconductor substrate at below about 100 DEG C. Methods for controlling the temperature of the semiconductor substrate according to one or more embodiments include utilizing an electrostatic chuck and a coolant and gas convection.

Description

201034078 六、發明說明: 【發明所屬之技術領域】 本發明實施例大體而言係有關於半導體製造,並且更 明確地說,係有關於半導體裝置或其零組件的氧化以形 成共形氧化物層。 【先前技術】 • 半導體裝置在其若干製造階段需形成薄氧化物層。例 如’在電晶體中’一薄閘極氧化物層可形成為一閘極堆 疊結構的一部分,包含側壁,如會在後方詳加描述者。 此外’在某些應用中,例如在快閃記憶體薄膜堆疊的製 造中,可在整個閘極堆疊周圍形成薄氧化物層,例如, 藉由將該堆疊暴露在氧化製程中。此類氧化製程習知上 係以熱方法執行或利甩電漿執行。 形成氧化物層,例如,該閘極氧化物層或該閘極堆疊 籲 氧化層,的熱製程在過去所使用的較大特徵結構尺寸半 導體裝置的製造中成效相當好。不幸地,隨著特徵結構 尺寸大幅度縮小並且在下世代的先進技術中使用不同氧 化物,熱氧化製程所需的高晶圓或基材溫度會因為矽晶 圓内的掺質(井摻雜及接合面)在較高溫度下(例如高於約 7〇〇°c )擴散而造成問題。此種摻質輪廓及其他特徵結構 的失真可導致不良的裝置效能或失效。 用來形成氧化物層的電漿製程擁有類似問題。例如, 201034078 在南腔室壓力下(例如1GG毫托耳),形成期間污染物有 匯聚在該閘極氧化物層内的傾向,造成閘極氧化物結構 的嚴重缺陷,例如懸鍵(dangling b〇nds)或移動電荷而 ,低腔室壓力下(例如數十毫托耳),增加的電衆離子能 量造成離子轟擊傷害和其它擴散問題。例如習知氧化 製程常造成稱為鳥嘴的缺陷。鳥嘴係指氧化物層從相鄰 層之間介面處的側邊擴散進入薄膜堆疊結構的層内環 繞該等相鄰層的角落。所造成的缺陷具有類似鳥嘴的輪 該氧化層侵入該記憶單元(例如在快閃記憶趙應用中) 的主動區會縮小該記憶單元的主動寬度,因此不預期縮 小該單元的有效寬度,並降低該快閃記憶體裝置的效能。 =現行低zm電漿製程的另一限制在於氧化似乎優先在與 該晶圓或基材面平行的表面上發生,也就是說,結構的 頂部和底部’例如藉由堆疊材料層所形成的閘極以及形 成在該等閘極之間的溝槽。咸信這是緣於與該晶圓垂直 • 的氧離子和自由基流通量。無論成因為何,該等堆叠側 壁上發生有限的氧化,在該等閘極堆疊上產生薄到令人 無法接受的側壁層和極差的共形性。因此,需要一種改 善的在半導體基材上形成氧化物層的方法。 【發明内容】 本發明之一態樣係有關於一種處理形成在一半導體基 材上的氧化物層的方法。根據一或多個實施例,該方法 201034078 包含將此種基材置於一電漿反應室内一基材支撐件上。 在一或多個實施例中使用的腔室包含一離子產生區。該 方法也可包含通入或流入一製程氣體進入該腔室,其 中,在該離子產生區内,一電漿係經產生在該腔室的離 子產生區内,並用來在該基材上形成一氧化物層。根據 一或多個實施例形成的電漿可含氧或一氧物種。在一或 多個實施例中,該氧化物層係在該基材主動冷卻期間由 該電漿形成。在此實施例中,主動冷卻該基材增加某些 電漿内所含氧物種之黏滯係數。 根據一或多個實施例,該基材係經冷卻至低於約1 〇〇 °c的溫度。在一具體實施例中,該基材係經冷卻至範圍 在約-50°C至約100°C内的溫度。在一更具體的實施例 中,該基材係經冷卻至範圍在約_25。〇至75 °C内的溫度, 並且在一甚至更具體的實施例中,該基材係經冷卻至範 圍在約0 °C至約5 0 °C内的溫度。 如在此所使用者,“主動冷卻,’一詞表示在該基材鄰近 流通一冷卻流體。在一實施例中,利用一靜電夾盤(ESC) 在該基材鄰近流通一冷卻流體。在另一實施例中,供應 一對流氣體至該腔室並在該基材鄰近流通。 根據一或多個實施例’該基材係藉由使一冷卻劑流經 該基材支撐件來主動冷卻。在一具體實施例十,該冷卻 劑係在該基材和基材支樓件間循環。該基材也可,例如, 透過接觸該基材表面來冷卻’其中,在一具體實施例中, 其含有複數個冷卻導管。在一更具體的實施例中,該基 6 201034078 材支來供應-冷卻劑至該等冷卻導 管。適用於此種實施例#冷卻齊^含u,其他惰性氣 體及其組合物。 -或多㈣他實施例藉由流通—對流氣體進入該反應 室内來主動冷卻該基材。在一具體實施例中,一氦氣係 經流入該反應室内以主動冷卻該基材。在一更具體的實 施例中,對流氣體係以範圍從約500 sccm至約3〇〇〇sccm 的流速流人該反應室。在—或多個實施例中使用的對流 氣體包含氧氣,並且也可包含—或多種其他惰性氣體。 前面已相當廣泛概述本發明之某些特徵結構。熟知技 藝者應領會所揭示的具體實施例可輕易用做調整或設計 落在本發明範圍内之其他結構或製程的基礎。熟知技藝 者也應理解此種等效結構並不背離在附屬申請專利範圍 中提出之本發明精神及範圍。 Φ 【實施方式】 本發明實施例提供藉由氧化半導體基材形成共形氧化 物層的方法。下述具體實施例係關於利用低溫氧化法形 成的氧化物層描述。 如在此所使用者,低溫氧化表示在低於約700〇c的溫 度下之氧化。習知電漿氧化因為傳送至該基材的電漿功 率而在高於100 C的溫度下發生。在高於! 的溫度 下,氧離子流通量支配該氧化製程,因此僅有半數的氧 7 201034078 化流通量抵達垂直側壁,與抵達寬度為5〇奈米之結構的 水平壁(也可稱為頂和底表面或閘極和溝槽)的氧化流通 量相比。據此,當共形性係定義為一侧壁上的成長及一 頂或底表面上的成長之比例時,在大於25埃的厚度下, 習知電漿氧化僅達到50%的共形性。 已發現在電漿氧化期間主動冷卻基材至約_5〇。〇至1〇〇 C範圍内的溫度,例如在約_25〇c至75它的具體範圍内, 並且更具體地在約〇°C至50°C範圍内,可改善利用矽結 ® 構之低溫氧化所形成的薄膜之共形性。更明確地說厚 度低於約100奈米的較小特徵結構之薄膜共形性顯著改 善。共形性係定義為形成在一結構側壁上的薄膜厚度對 形成在一結構的水平表面,包含頂及底表面,上之薄膜 厚度間的比例。根據本發明之一或多個實施例,可達到 至少約75%的共形性,並且更明確地說至少約8〇%,並 且在具體實施例中至少約90%。在一或多個實施例中, ❹ 藉由以上述方法處理,咸信該較低溫度增加該氧物種對 一結構側壁的黏滯係數。 本發明實施例可在適當配備的電漿反應器内執行,例 如可從加州聖塔克拉拉的應用材料公司取得之去耗電讓 氮化(DPN)反應器。也可使用其他適合的電漿反應器,包 含但不限於,輻射狀排列槽形天線電漿設備及中空陰極 電漿設備。第1圖示出適於執行根據本發明實施例之氧 化物形成製程的例示電漿反應器。該反應器可透過由連 續波(CW)功率產生器驅動的感應耦合電漿電源應用器 201034078 提供低離子能量電漿及高離子能量電衆。 第1圖所示反應器11包含一腔室10,其具有一圓柱 狀侧壁12及一頂板14,其可以是圓頂狀(如圖中所示 者)、平板狀、或其他幾何形狀。一電漿電源應用器包含 一線圈天線10,設置在該頂板14上方並透過一第一阻 抗匹配網絡18耦合至一功率源。該功率源包含一 RF# 率產生器20和一閘極22在該產生器2〇的輸出處。 該反應器也包含一基材支#座26,其可以是一靜電夹 盤或其他適合的基材支撐件,以抓持一半導體基材27, 例如200毫米或300毫米半導體晶圓或諸如此類者。通 常,擁有一加熱設備,例如一加熱器34在該基材支撐座 26頂表面下方。該加熱器34可以是單或多區域加熱器, 例如具有徑向内部及外部加熱元件3牦和34b的雙徑向 區域加熱器,如第1圖所示者。 此外,該反應器包含一氣體注入系統28及與該腔室 φ 1 〇的内°*5空間連結的真空幫浦30。該氣體注入系統28 係由一氣源供應,其可包含氧氣瓶32、氫氣瓶62或惰 氣瓶70。可包含其他製程氣源’例如水蒸氣源和惰性氣 體源(未示出)。在一或多個實施例中,可使用多於一個 氣源流量控制閥66、64和68分別與該氧氣瓶32、該 氫氣瓶62和該惰氣瓶7〇連結,並且可用來在處理期間 選擇挫提供製程氣體或製程氣體混合物至該腔室1〇的 内部空間。也可提供供應例如氮氣、氣體混合物、或諸 此類者之額外氣體的其他氣源(未示出)。可利用該真 201034078 空幫浦30的節流閥38來控制該腔室ι〇内的麼力。 可藉由控制其輸出與該閘極22連結的脈衝產生器36 的工作週期來控制該閘極22處的脈衝RF功率輸出之工 作週期。電聚係在一離子產生區39内產生,其對應該頂 板14下方被該線圈天線16 g繞的空間。因為電漿係在 i腔至ίο之上半部區域與該基材27有一段距離處產 生,該電漿遂被稱為類遠端電漿(例如,該電漿具備遠端 漿形成的優勢,但係在與該基材27相同的腔室内 胃形成)》 操作時,可用該電漿反應器來執行根據本發明實施例 之氧化製程,以沈積高品質氧化物層,其在形成於一基 材上的氧化物堆疊之側壁上具有增量的氧化物層。 例如’第2 A-B圖示出含有形成在半導體基材2〇2上之 薄琪堆疊240的半導體結構200之製造階段。在一或多 個實施例中’該基材2〇2可包含多個薄膜堆疊24〇,其 〇 在該等堆疊之間形成溝槽25〇。在此所述用來製造該半 導鱧結構200的製程可在,例如’上面關於第1圖所述 之反應器11内執行。 基材202具有一薄膜堆疊240沈積在其上。該薄膜堆 整24〇將被氧化。該基材202 —般對應於第1圖的基材 27 ’並且通常係支撐在該電漿反應器11的腔室10内該 基材支撐件26上。該基材202可擁有各種尺寸,例如直 徑200毫米或3〇〇毫米的晶圓,以及矩形或方形面板。 在某些實施例中,該薄膜堆疊240可形成在該基材202 201034078 上,然後提供給該腔室1〇進行該氧化製程。例如,可在 與-群集工具連結的一或多個製程腔室内製造該薄膜堆 疊240,其也擁有該電漿反應器u連結至其上。一適人 的群集工具之範例是可從加州聖塔克拉拉的應用材料公 司取得之閘極堆疊CENTURA®。201034078 VI. Description of the Invention: [Technical Field] The present invention relates generally to semiconductor fabrication and, more particularly, to oxidation of a semiconductor device or its components to form a conformal oxide layer. . [Prior Art] • A semiconductor device needs to form a thin oxide layer at several stages of its fabrication. For example, a thin gate oxide layer can be formed as part of a gate stack structure, including sidewalls, as will be described later. Further, in some applications, such as in the fabrication of a flash memory film stack, a thin oxide layer can be formed around the entire gate stack, for example, by exposing the stack to an oxidizing process. Such oxidation processes are conventionally performed by thermal methods or by slurry processing. The thermal process of forming an oxide layer, e.g., the gate oxide layer or the gate stack oxide layer, works reasonably well in the fabrication of larger feature size semiconductor devices used in the past. Unfortunately, as feature sizes shrink dramatically and different oxides are used in next-generation advanced technologies, the high wafer or substrate temperature required for thermal oxidation processes can be due to dopants in the germanium wafer (well doping and The joint surface) diffuses at higher temperatures (e.g., above about 7 〇〇 °c) causing problems. Distortion of such dopant profiles and other features can result in poor device performance or failure. The plasma process used to form the oxide layer has similar problems. For example, 201034078 under south chamber pressure (eg, 1 GG mTorr), the tendency of contaminants to converge within the gate oxide layer during formation, causing serious defects in the gate oxide structure, such as dangling b 〇nds) or moving charges, under low chamber pressure (eg, tens of millitors), increased electrical ion energy causes ion bombardment damage and other diffusion problems. For example, conventional oxidation processes often cause defects known as bird's beak. A bird's beak refers to an oxide layer that diffuses from the sides at the interface between adjacent layers into the layers of the film stack to surround the corners of the adjacent layers. The resulting defect has a beak-like wheel. The active region of the oxide layer invading the memory cell (eg, in a flash memory application) reduces the active width of the memory cell, and thus is not expected to reduce the effective width of the cell, and Reduce the performance of the flash memory device. Another limitation of the current low zm plasma process is that oxidation appears to occur preferentially on the surface parallel to the wafer or substrate surface, that is, the top and bottom of the structure, such as the gate formed by stacking layers of material a pole and a trench formed between the gates. This is due to the oxygen ion and free radical flux perpendicular to the wafer. Regardless of the cause, limited oxidation occurs on the side walls of the stack, resulting in an unacceptable sidewall layer and poor conformality on the gate stack. Therefore, there is a need for an improved method of forming an oxide layer on a semiconductor substrate. SUMMARY OF THE INVENTION One aspect of the present invention is directed to a method of processing an oxide layer formed on a semiconductor substrate. In accordance with one or more embodiments, the method 201034078 includes placing such a substrate on a substrate support within a plasma reaction chamber. The chamber used in one or more embodiments includes an ion generating region. The method may also include introducing or flowing a process gas into the chamber, wherein in the ion generating region, a plasma is generated in the ion generating region of the chamber and used to form on the substrate. An oxide layer. The plasma formed in accordance with one or more embodiments may contain oxygen or an oxygen species. In one or more embodiments, the oxide layer is formed from the plasma during active cooling of the substrate. In this embodiment, actively cooling the substrate increases the viscosity coefficient of the oxygen species contained in certain plasmas. According to one or more embodiments, the substrate is cooled to a temperature of less than about 1 〇〇 ° C. In a specific embodiment, the substrate is cooled to a temperature ranging from about -50 ° C to about 100 ° C. In a more specific embodiment, the substrate is cooled to a range of about _25. The temperature is ramped to within 75 °C, and in an even more specific embodiment, the substrate is cooled to a temperature in the range of from about 0 °C to about 50 °C. As used herein, the term "active cooling," means flowing a cooling fluid adjacent to the substrate. In one embodiment, an electrostatic chuck (ESC) is used to circulate a cooling fluid adjacent the substrate. In another embodiment, a pair of flowing gas is supplied to the chamber and is circulated adjacent to the substrate. According to one or more embodiments, the substrate is actively cooled by flowing a coolant through the substrate support. In a specific embodiment, the coolant is circulated between the substrate and the substrate support member. The substrate may also be cooled, for example, by contacting the surface of the substrate, wherein in a particular embodiment , which comprises a plurality of cooling conduits. In a more specific embodiment, the base 6 201034078 is supplied with a coolant to the cooling conduits. Suitable for use in such embodiments #cooling, containing u, other inert gases And its composition. - or more (d) his embodiment actively cools the substrate by passing a convection gas into the reaction chamber. In a specific embodiment, a helium gas is flowed into the reaction chamber to actively cool the substrate. Material. In a more specific In an embodiment, the convection system flows into the reaction chamber at a flow rate ranging from about 500 sccm to about 3 〇〇〇 sccm. The convection gas used in the embodiment or embodiments comprises oxygen and may also comprise - or multiple Other Inert Gases Some of the features of the present invention are fairly broadly described. It will be appreciated by those skilled in the art that the presently disclosed embodiments can be readily utilized as a basis for adapting or designing other structures or processes falling within the scope of the invention. It is to be understood by those skilled in the art that the equivalent structure does not depart from the spirit and scope of the invention as set forth in the appended claims. Φ [Embodiment] Embodiments of the present invention provide a conformal oxide layer formed by oxidizing a semiconductor substrate. The following specific examples are described with respect to oxide layers formed by low temperature oxidation. As used herein, low temperature oxidation means oxidation at temperatures below about 700 ° C. Conventional plasma oxidation is transmitted The plasma power to the substrate occurs at temperatures above 100 C. At temperatures above !, the oxygen ion flux dominates the oxidation process, thus Only half of the oxygen 7 201034078 flux reaches the vertical sidewalls compared to the oxidized flux of horizontal walls (also referred to as top and bottom surfaces or gates and trenches) that reach a width of 5 nanometers. Accordingly, when the conformality is defined as the growth on one side wall and the growth ratio on a top or bottom surface, conventional plasma oxidation achieves only 50% conformality at thicknesses greater than 25 angstroms. It has been found that the substrate is actively cooled during plasma oxidation to a temperature in the range of about _5 〇 to 1 〇〇C, for example in the specific range of about _25 〇 c to 75, and more specifically in about In the range of 〇 ° C to 50 ° C, the conformality of the film formed by the low temperature oxidation of the yttrium structure can be improved, more specifically, the film conformality of the smaller features having a thickness of less than about 100 nm. Significantly improved. The conformality is defined as the ratio of the thickness of the film formed on the sidewalls of a structure to the horizontal thickness of the film formed on the horizontal surface of a structure comprising the top and bottom surfaces. According to one or more embodiments of the invention, at least about 75% conformality, and more specifically at least about 8%, and in particular embodiments at least about 90%, can be achieved. In one or more embodiments, 较低 by treating in the manner described above, the lower temperature increases the viscosity coefficient of the oxygen species to the sidewalls of a structure. Embodiments of the invention may be practiced in a suitably equipped plasma reactor, such as a depleted nitriding (DPN) reactor available from Applied Materials, Inc. of Santa Clara, California. Other suitable plasma reactors can also be used, including, but not limited to, radial array trough antenna plasma equipment and hollow cathode plasma equipment. Figure 1 shows an exemplary plasma reactor suitable for carrying out an oxide formation process in accordance with an embodiment of the present invention. The reactor delivers low ion energy plasma and high ion energy to the inductively coupled plasma power application 201034078 driven by a continuous wave (CW) power generator. The reactor 11 shown in Figure 1 includes a chamber 10 having a cylindrical side wall 12 and a top plate 14, which may be dome-shaped (as shown), flat, or other geometric shape. A plasma power supply application includes a coil antenna 10 disposed above the top plate 14 and coupled to a power source via a first impedance matching network 18. The power source includes an RF# rate generator 20 and a gate 22 at the output of the generator 2''. The reactor also includes a substrate support 26, which may be an electrostatic chuck or other suitable substrate support for grasping a semiconductor substrate 27, such as a 200 mm or 300 mm semiconductor wafer or the like. . Typically, a heating device is provided, such as a heater 34 below the top surface of the substrate support 26. The heater 34 can be a single or multi-zone heater, such as a dual radial zone heater having radial inner and outer heating elements 3A and 34b, as shown in Figure 1. In addition, the reactor includes a gas injection system 28 and a vacuum pump 30 coupled to the inner space of the chamber φ 1 空间. The gas injection system 28 is supplied from a source of gas, which may include an oxygen cylinder 32, a hydrogen cylinder 62, or an inert gas cylinder 70. Other process gas sources may be included, such as a water vapor source and an inert gas source (not shown). In one or more embodiments, more than one air source flow control valve 66, 64, and 68 can be used to couple the oxygen cylinder 32, the hydrogen cylinder 62, and the inert gas cylinder 7 respectively, and can be used during processing. The frustration is provided to provide a process gas or process gas mixture to the interior of the chamber. Other sources of gas (not shown) that supply additional gases such as nitrogen, gas mixtures, or the like may also be provided. The throttle valve 38 of the true 201034078 air pump 30 can be utilized to control the force within the chamber ι. The duty cycle of the pulsed RF power output at the gate 22 can be controlled by controlling the duty cycle of the pulse generator 36 whose output is coupled to the gate 22. The electropolymer is generated in an ion generating region 39 corresponding to the space under the top plate 14 surrounded by the coil antenna 16g. Since the plasma is generated at a distance from the substrate 27 to the upper half of the cavity, the plasma is referred to as a far-end plasma (for example, the plasma has the advantage of distal slurry formation). , but in the same chamber as the substrate 27, when the operation is performed, the plasma reactor can be used to perform an oxidation process according to an embodiment of the present invention to deposit a high quality oxide layer, which is formed in a There is an incremental oxide layer on the sidewalls of the oxide stack on the substrate. For example, '2A-B shows a stage of fabrication of a semiconductor structure 200 comprising a thin stack 240 formed on a semiconductor substrate 2〇2. In one or more embodiments, the substrate 2〇2 may comprise a plurality of film stacks 24〇, 〇 forming trenches 25〇 between the stacks. The process for fabricating the semiconductor structure 200 described herein can be performed, for example, in the reactor 11 described above with respect to Figure 1. Substrate 202 has a thin film stack 240 deposited thereon. The film will be oxidized 24 堆. The substrate 202 generally corresponds to the substrate 27' of Figure 1 and is typically supported on the substrate support 26 within the chamber 10 of the plasma reactor 11. The substrate 202 can be of various sizes, such as wafers having a diameter of 200 mm or 3 mm, and rectangular or square panels. In some embodiments, the film stack 240 can be formed on the substrate 202 201034078 and then provided to the chamber 1 for the oxidation process. For example, the film stack 240 can be fabricated in one or more process chambers coupled to the -cluster tool, which also has the plasma reactor u coupled thereto. An example of a suitable clustering tool is the gate stack CENTURA® available from Applied Materials, Inc., Santa Clara, California.

該基材202可包含一材料,例如結晶矽(例如,矽 或石夕<U卜)、氧切、應變梦、錄㈣、摻雜或未接雜 的多晶矽、摻雜或未摻雜的矽晶圓、圖案化或未圖案化 的晶圓、絕緣層上梦(SOI)、推雜碳的氧切、氮化妙、 捧雜的梦、鍺、砂化鎵、破璃、藍寶石或諸如此類。 會了解該薄膜堆疊240並不受限於上述特定材料。因 此,該薄膜堆疊24G可以是欲氧化的任何種材料堆叠。 例如’在某些實施例中,例如在快閃記憶體應用中,該 堆疊200可以是一快閃記憶單元的閘極堆疊其含有穿 随氧化物層204、浮置閘極層206、單或多層介電層,其 含有多晶梦間介電層(IPD)2!〇(該IpD之一非限制性範例 係—多層ΟΝΟ層,其含有一氧化物層212、一氮化物層 214、以及一氧化物層216,在帛2Α Β _中例示性示出)、 以及控制閘極層220。該等氧化物層2〇4、⑴、川 通常含梦和氧例如氧化⑦(Si〇2)、氧氣化_(Si〇N)、或 諸如此類者。該氣化物層通常含砍及氮,例如氣化梦 (SiN) <諸如此類者。在某些實施例中也可用一含有The substrate 202 can comprise a material such as crystalline germanium (eg, germanium or stellite), oxygen cut, strain dream, recorded (four), doped or undoped polycrystalline germanium, doped or undoped矽 Wafer, patterned or unpatterned wafers, SOI on insulators, oxygen cuts on carbon, nitriding, dreams, cockroaches, gallium silicate, broken glass, sapphire or the like . It will be appreciated that the film stack 240 is not limited to the particular materials described above. Thus, the film stack 24G can be any type of material stack to be oxidized. For example, 'in some embodiments, such as in a flash memory application, the stack 200 can be a gate stack of a flash memory cell that includes a pass-through oxide layer 204, a floating gate layer 206, a single or a multilayer dielectric layer comprising a polycrystalline dream dielectric layer (IPD) 2! 〇 (one non-limiting example of the IpD - a multilayer ruthenium layer comprising an oxide layer 212, a nitride layer 214, and An oxide layer 216, exemplarily shown in 帛2Α _ _, and a gate layer 220 are controlled. The oxide layers 2〇4, (1), and chuan usually contain dreams and oxygen such as oxidized 7 (Si〇2), oxygenated _(Si〇N), or the like. The vapor layer typically contains chopped nitrogen, such as a gasification dream (SiN) < In some embodiments, a

Si02/A12〇3/Si〇2的多層來做為該ipD層21〇。該浮置 閘極層206和該括在丨丨β 肝x徑制閘極層220通常含有一導電材料, 201034078 例如多晶矽、金屬、或諸如此類者。預期在其他應用中 的薄膜堆疊可根據在此提供的教示有利地氧化,例如動 態隨機存取記憶體(DRAM)金屬電極/多晶矽閘極堆 疊、用於非揮發性記憶體(NVM)的電荷擷取快閃記憶體 (CTF)、或諸如此類者。該drAM金屬電極通常是鎢(w), 具有氮化鈦(TiN)或氮化鎢(WN)之中間層在該等鎢及多 晶矽層之間。用於非揮發性記憶艎(NVM)的電荷擷取快 閃記憶體(CTF)使用Si〇2/sm/Al2〇3閘極堆疊’具有 氮化组(TaN)或氮化鈦(TiN)的金屬電極,其也可從閘極 蝕刻後的側壁氧化受益。在某些實施例中,該製程氣體 可包含水蒸氣,並且在一或多個具體實施例中,該水蒸 氣可與氫氣及/或氧氣的至少一者混合。做為另一種選 擇或合併使用,該水蒸氣可與至少一種惰性氣體混合, 例如氛氣(He)、氬氣(Ar)、氪氣(Kr)、氖氣(Ne)、或諸如 此類者。 在某些實施例中,可提供總流速約1〇〇_2〇〇〇 seem 之 間’或約400 seem,的製程氣體(或氣體混合物例如, 在提供氧氣(〇2)和氫氣(H2)兩者的實施例中,可提供總流 速約100-2000 seem之間的氧氣(〇2)和氳氣(h2),或約400 seem ’在上述百分比範圍内。在提供水蒸氣的實施例中, 可通入流速約5-1000 SCCm之間的水蒸氣,連同一或多 種惰性載氣’例如氦氣、氬氣、氪氣、氖氣或其他適合 情性氣體。可依需要供應該等惰性氣體,以提供約 100-2000 seem之間的總流速,並提供擁有多至約50%水 12 201034078 蒸氣的製程氣體混合物。惰性氣體添加也可與H2〆〇2 混合物並用,以避免離子化氧氣及/或氦氣的再結合。 激發的雙原子分子通常傾向在電漿内與自身再結合因 添加隋14乳體(例如氬氣、氦氣、氪氣、氖氣、或諸如 此類)可促進較高氧化速率。 一電漿係在該腔室10内從該等製程氣體產生,以在該 薄膜堆疊240上形成一氧化物層23(^該電漿係形成在 .第1圖所示腔室10的離子產生區39内,利用感應耦合 來自故置在該頂板14上方的線圈天線16之RF能量,因 此有利地提供低離子能量(例如就脈衝電漿而言低於約5 eV,並且就cw電漿而言低於15 eV)。該電漿的低離子 能量限制離子轟擊傷害,並促進該薄膜堆疊24〇的側壁 之氧化,同時限制氧氣在其各層之間擴散,藉此減少鳥 嘴。 在某些實施例中,可以適當頻率提供約25至5000瓦 • 的功率至該線圈天線16,以形成電漿(例如,在MHz或 GHz範圍内’或約13·56μΗζ或更大)。可以連續波或脈 衝模式提供該功率。在一或多個實施例中,係以工作週 期介於約2至70%之間的脈衝模式提供該功率。 例如’在某些實施例中’該電漿可在連續的“開啟,,時 間期間產生,而容許該電漿的離子能量在連續的“關閉,, 區間期間衰變。該“關閉”區間隔離連續的‘‘開啟,,區間, 而該開啟”及“關閉,區間界疋出一可控制的工作週期。 該工作週期將該基材表面處的離子動能限制在低於—預 13 201034078 定臨界能量下》在某些實施例中,該預定臨界能量係在 或低於約5 eV。 例如,在該脈衝RF功率的“開啟,,時間期間,該電漿能 量增加,而在該“關閉”時間期間則降低。在短暫的“開啟,, 時間期間’該電漿係在大約對應於該線圈天線16所圈起 的空間之該離子產生區39内產生。該離子產生區39係 在該基材27上方一段顯著距離LD處。在該“開啟,,時間 期間於該離子產生區39内靠近該頂板14產生的電漿在 ® 該“關閉”時間以一平均速度VD朝該基材27飄移。在每 一個關閉”時間期間,最快速的電子擴散至該等腔室 壁’谷許該電漿冷卻。能量最高的電子以比該電漿離子 飄移速度VD快許多的速度擴散至該等腔室壁。因此, 在該“關閉”時間,該電漿離子能量在該等離子抵達該基 材27之前顯著降低。在下一次“開啟,,時間期間,更多電 漿產生在該離子產生區39,並且整個週期重複,因此, • 抵達該基材27的電漿離子之能量顯著降低。在較低的腔 室壓力範圍下,也就是說約1〇毫托耳和以下,該脈衝 RF情況的電漿能量與該連績RF情況相比大幅降低。 該脈衝RF功率波形的“關閉”時間及該離子產生區39 和該基材27之間的距離LD兩者均應足以容許產生在該 離子產生區39的電漿失去足夠大量的能量,因此其在抵 達該基材27時造成很少或無離子轟擊傷害或缺陷。明確 地說’該“關閉,’時間係由約2和20 kHz之間,或約1〇 kHz,的脈衝頻率以及約5%和2〇%之間的“開啟,,工作週 14 201034078 期界疋目此’在某些實施例中,該“開啟”區間可持續 約5微和至、約50微秒範圍内的時間,或約20微秒,而 該“關閉”區間可持續約5〇微秒至約95微秒範圍内的時 間,或約80微秒·。A multilayer of Si02/A12〇3/Si〇2 is used as the ipD layer 21〇. The floating gate layer 206 and the 丨丨β liver x-diameter gate layer 220 typically contain a conductive material, such as polysilicon, metal, or the like. Film stacks in other applications are expected to be advantageously oxidized according to the teachings provided herein, such as dynamic random access memory (DRAM) metal electrodes/polysilicon gate stacks, charge for non-volatile memory (NVM). Take a flash memory (CTF), or the like. The drAM metal electrode is typically tungsten (w) with an intermediate layer of titanium nitride (TiN) or tungsten nitride (WN) between the layers of tungsten and polysilicon. Charge-extracted flash memory (CTF) for non-volatile memory cartridges (NVM) using Si〇2/sm/Al2〇3 gate stacks with nitrided (TaN) or titanium nitride (TiN) Metal electrodes, which also benefit from sidewall oxidation after gate etching. In certain embodiments, the process gas can comprise water vapor, and in one or more embodiments, the water vapor can be combined with at least one of hydrogen and/or oxygen. Alternatively or in combination, the water vapor may be mixed with at least one inert gas such as atmosphere (He), argon (Ar), helium (Kr), helium (Ne), or the like. In certain embodiments, a process gas (or gas mixture, for example, in the supply of oxygen (〇2) and hydrogen (H2)) may be provided at a total flow rate of between about 1 〇〇 2 〇〇〇 seem' or about 400 seem. In both embodiments, oxygen (〇2) and helium (h2), or about 400 seem', may be provided in the range of the above percentages between about 100 and 2000 seem. In the embodiment providing water vapor. , can pass water vapor with a flow rate of about 5-1000 SCCm, with one or more inert carrier gases such as helium, argon, helium, neon or other suitable gas. These inertia can be supplied as needed. Gas to provide a total flow rate between about 100-2000 seem and to provide a process gas mixture with up to about 50% water 12 201034078 vapor. Inert gas addition can also be combined with H2〆〇2 mixture to avoid ionized oxygen And/or recombination of helium. Excited diatomic molecules generally tend to recombine with themselves in the plasma because the addition of 隋14 milk (such as argon, helium, neon, xenon, or the like) can promote High oxidation rate. A plasma is attached to the chamber 10. From the process gases, an oxide layer 23 is formed on the thin film stack 240. (The plasma is formed in the ion generating region 39 of the chamber 10 shown in Fig. 1, and is inductively coupled by inductive coupling. The RF energy of the coil antenna 16 above the top plate 14 thus advantageously provides low ion energy (e.g., less than about 5 eV for pulsed plasma and less than 15 eV for cw plasma). The low ion energy limits ion bombardment damage and promotes oxidation of the sidewalls of the film stack 24 , while limiting the diffusion of oxygen between its layers, thereby reducing the bird's beak. In some embodiments, about 25 can be provided at an appropriate frequency. Power to 5000 watts to the coil antenna 16 to form a plasma (eg, in the MHz or GHz range 'or about 13.56 μM or greater). This power can be provided in continuous wave or pulse mode. One or more In one embodiment, the power is provided in a pulsed mode with a duty cycle between about 2 and 70%. For example, 'in some embodiments, the plasma can be generated during a continuous "on," period of time. Allowing the plasma's ion energy to Continuous "closed," decay during the interval. The "closed" interval isolates the continuous ''open,' interval, and the open and closed, interval boundaries yield a controllable duty cycle. The ion kinetic energy at the surface of the material is limited to below - pre-13 201034078, the critical energy is in some embodiments, the predetermined critical energy is at or below about 5 eV. For example, in the pulse of the RF power "on, During the time, the plasma energy increases and decreases during the "off" time. During a brief "on, time period" the plasma is approximately corresponding to the space enclosed by the coil antenna 16. It is generated in the ion generating region 39. The ion generating zone 39 is at a significant distance LD above the substrate 27. During the "on" period, the plasma generated in the ion generating region 39 near the top plate 14 drifts toward the substrate 27 at an average speed VD during the "off" time. During each off time, The fastest electrons diffuse to the walls of the chamber, which allows the plasma to cool. The most energetic electrons diffuse to the walls of the chamber at a much faster rate than the plasma ion drift velocity VD. Thus, at this "off" time, the plasma ion energy is significantly reduced before the plasma reaches the substrate 27. During the next "on, time period, more plasma is produced in the ion generating zone 39, and the entire cycle repeats, therefore, • the energy of the plasma ions arriving at the substrate 27 is significantly reduced. At lower chamber pressures In the range, that is, about 1 Torr and below, the plasma energy of the pulsed RF case is greatly reduced compared to the continuous RF case. The "off" time of the pulsed RF power waveform and the ion generating region 39 Both the distance LD with the substrate 27 should be sufficient to allow the plasma generated in the ion generating region 39 to lose a sufficient amount of energy, thus causing little or no ion bombardment damage upon arrival at the substrate 27. Defects. Explicitly the 'this' is off, 'time is between about 2 and 20 kHz, or about 1 kHz, the pulse frequency and between about 5% and 2% of the "on, work week 14 201034078 The term "open" interval may last for about 5 micro and to a time in the range of about 50 microseconds, or about 20 microseconds, and the "closed" interval may last about 5 〇 microseconds to a time in the range of about 95 microseconds, or · 80 microseconds.

在某些實施例中,該離子產生區至基材距離LD係大 於約2公分’或者在約2公分至約2〇公分範圍内。該離 子產生區至基材距離LD可與該等電漿離子在該脈衝RF 癱 功率波形的單一個“關閉,,時間期間行進的距離(vd乘以 參該“關閉”時間)約相同(或更大)。 在連績波和脈衝模式兩者中,該電浆有利地在該腔室 内平衡氧氣和氫氣離子的共生,並且與該基材之間距離 夠近以利用對於離子能量的控制來限制該等離子活性的 流失,以避免離子轟擊造成的傷害或擴散傷害(例如鳥 嘴)。 所產生的電漿可在一低壓製程中形成,藉以減少污染 φ 導致的缺陷之可能性。例如,在某些實施例中,可將該 腔室10保持在約1·500毫托耳之間的壓力下。此外,可 藉由使用類遠端電漿源及,選擇性地,藉由如上所述般 脈衝该電漿電源來限制或避免在如此低的腔室壓力水準 下所能期待的轟擊導致的缺陷。 根據一或多個實施例,該氧化物層23〇可形成至從約 5埃至約50埃範圍内的厚度。該製程可提供每分鐘約7 埃至約50埃範圍内的氧化物薄膜成長速率,或每分鐘至 少約25埃。在此揭示之本發明製程在較低熱預算下提供 15 201034078 上述之氧化物成長速率提升,因而藉由與習知氧化製程 相比減少該基材對於該製程的暴露時間而更加限制擴散 效應。在某些實施例中,該製程可擁有從約5秒至約3卯 秒範圍内的持續時間。 可在該薄膜堆疊240上將該氧化物層23〇形成至一預 期厚度。隨後可依需要進一步處理該基材2〇2以完成在 其上製造的結構。 如上所述,已發現在電漿氧化期間主動冷卻該基材至 ❿ 約_50°c至100°C範圍内的溫度,例如在約_25°c至75〇c 的具體範圍内,並且更具體地在約〇它至50〇c範圍内, 能改善利用矽結構的低溫氧化所形成的薄膜之共形性。 可用若干方法完成冷卻。 根據一第一實施例’該支撐座26可包含靜電夾盤 (ESC) ’其以一冷卻氣醴冷卻或接觸該基材背側,或該基 材與該支撐座26接觸的一側,以在低溫氧化期間維持該 φ 基材溫度。第3圖示出一 ESC 325之一範例實施例。參 考第1圖的反應器11,該ESC 325在該腔室10内支推 一半導體基材27。該ESC325可包含具有孔330穿透其 間的底座。在所示實施例中,一靜電組件333包含一絕 緣體335’其封住一電極350。該靜電組件333包含一上 表面340,以容納並支撐一基材。具有一電壓供應導線 360的電氣連接器355係經電氣連接至該電極350。該電 壓供應導線360沿伸通過該ESC 325的基座之孔330, 並在一電氣接觸3 65終止,其電氣接合一電壓供應終端 16 201034078 370。使用時,將該靜電夾盤325固定在—製程腔室 内的支撐件375上。應了解該ESC 325可與第i圏所示 之反應器11並用。在第3圖所示實施例中,該製程腔室 380(其對應第1圖的腔室ι〇)可包含—製程氣體入口 382(其對應第1圖的氣體注入系統28),其連結一製程氣 源302(其對應秦i圖的氧氣瓶32、氩氣瓶62或惰氣瓶 70)至該腔室380。第3圖的製程腔室38〇更包含連接至 一排氣系統301的排氣出口 384。 ❹ 在第3圖實施例中,一基材345係經抓持在該ESc 325 上,並且從該冷卻劑源或冷卻器3〇〇供應冷卻劑至位於 該絕緣體335上表面34〇内的冷卻導管3〇5,其也包含 冷卻導管或溝渠。在一或多個實施例中,該冷卻劑包含 一傳導氣體,例如氦氣、氬氣以及週期表第8族中的大 刀惰性元素。抓持在該ESC 325上的基材345覆蓋並 密封該等冷卻導管305,避免該冷卻劑外漏。該等冷卻 • 導管305内的冷卻劑從該基材345除熱,並在處理期間 將該基材345保持在固定溫度下。 在一或多個實施例中’該等冷卻導管3〇5係利用一系 列通道連結至該冷卻劑源3〇〇 ’其可延伸通過整個絕緣 體和電極。該等冷卻導管可經隔開、按一定尺寸製作及 分散’而使保持在其中的冷卻劑可實質上冷卻整個基材 345 〇 I —或多個實施例中,可使用電漿脈衝技術來最小化 肇因於傳輸至該基材的電漿功率之基材加熱。根據該等 201034078 實施例,在電漿氧化期間可使用電漿脈衝技術來將該基 材保持在約-50°c至100°C範圍内的溫度下,例如在約-25 C至75°c的具體範圍内,並且更具體地在約〇°c至5〇°C 範圍内。 可以若干適合方法來實現電漿脈衝。在一實施例中, 可開關循環該電漿以將該基材保持在此間所述溫度範圍 内。在另一實施例中,該電漿可以是範圍從約2 kHz 至約50 kHz的kHz頻率脈衝電漿。 ❹ 使用開關循環該電漿之電漿脈衝技術的實施例包含藉 由脈衝或時間調變該RF電漿電源訊號來調整平均電漿 電子/m度及化學❶此技術也稱為RJ?電漿電源調變,並獨 立於該RF電漿電源水準控制電子溫度,因為在脈衝之間 的功率關閉時間期間,電子溫度以比電漿密度快許多的 速率降低^ RF電漿電源調變包含實體上連續或依照一預 定順序開啟及關閉該電漿產生。在一或多個實施例中, Φ RF電漿電源調變包含開啟和關閉產生該離子產生區和 該電漿的功率源。 根據一或多個實施例,該電漿脈衝技術包含在一第一 頻率及一第二頻率之間替換該尺?功率源的頻率。在一或 多個實施例中,也可以該第-及/或第二頻率供應不同 量的功率。在使用此電漿脈衝法來維持或冷卻該基材溫 度至-50它和100。(;之間的一或多個實施例中包含將一基 材置於-電聚反應器的一腔室内,並通入含氫氣、氧氣 或惰氣的氣體至該腔室内。之後以一第一頻率供應功率 18 201034078 至該反應器以在該腔室内產生一第一雷难。缺^ 电浆。然後以一第 二頻率供應功率以在該腔室内產生一篦_ 矛一電漿。此類實 施例也可供應頻率與該第一及第二頻率不同的功: 一或多個實施例中,以該第一或第二頻率供應的=率= 可不同,並且可關於該等頻率的一或兩者週期性增加或 減少或保持固定。也可控制以該第一或第二頻率供應的 功率量之改變率以調節或降低該基材的溫度。In certain embodiments, the ion generating zone to substrate is greater than about 2 centimeters from the LD system or from about 2 centimeters to about 2 centimeters. The ion generating zone-to-substrate distance LD can be about the same as the plasma ion in the pulse RF 瘫 power waveform for a single "off, the distance traveled during the time (vd multiplied by the "off" time) (or Larger. In both the continuous wave and the pulse mode, the plasma advantageously balances the symbiosis of oxygen and hydrogen ions within the chamber and is close enough to the substrate to utilize control of the ion energy. Limiting the loss of activity of the plasma to avoid damage or diffusion damage caused by ion bombardment (eg, bird's beak). The generated plasma can be formed in a low pressure process to reduce the possibility of defects caused by contamination φ. For example, In some embodiments, the chamber 10 can be maintained at a pressure of between about 1.500 mTorr. Further, by using a remote-like plasma source and, optionally, by The plasma power source is pulsed to limit or avoid defects caused by bombardment that can be expected at such low chamber pressure levels. According to one or more embodiments, the oxide layer 23 can be formed to from about 5 angstroms to About 50 angstroms The thickness of the film. The process provides an oxide film growth rate in the range of from about 7 angstroms to about 50 angstroms per minute, or at least about 25 angstroms per minute. The process of the invention disclosed herein provides for a lower thermal budget. 201034078 The above oxide growth rate is increased, thereby further limiting the diffusion effect by reducing the exposure time of the substrate to the process compared to conventional oxidation processes. In some embodiments, the process can have from about 5 seconds. The duration to the range of about 3 sec. The oxide layer 23 can be formed on the film stack 240 to a desired thickness. The substrate 2 〇 2 can then be further processed as needed to complete the fabrication thereon. As described above, it has been found that the substrate is actively cooled during plasma oxidation to a temperature in the range of about _50 ° C to 100 ° C, for example, in a specific range of about _25 ° c to 75 ° C, And more specifically in the range of about 〇 to 50 〇c, the conformality of the film formed by the low temperature oxidation of the ruthenium structure can be improved. The cooling can be accomplished in several ways. According to a first embodiment, the support 26 can be Contains static electricity Disk (ESC) 'cools or contacts the back side of the substrate with a cooling gas, or the side of the substrate in contact with the support 26 to maintain the temperature of the φ substrate during low temperature oxidation. An exemplary embodiment of an ESC 325 is shown. Referring to the reactor 11 of Figure 1, the ESC 325 supports a semiconductor substrate 27 within the chamber 10. The ESC 325 can include a base having a hole 330 therethrough. In the illustrated embodiment, an electrostatic component 333 includes an insulator 335' that encloses an electrode 350. The electrostatic component 333 includes an upper surface 340 for receiving and supporting a substrate. An electrical connector having a voltage supply lead 360 The 355 is electrically coupled to the electrode 350. The voltage supply wire 360 extends along the aperture 330 of the base extending through the ESC 325 and terminates at an electrical contact 3 65 that electrically engages a voltage supply terminal 16 201034078 370. In use, the electrostatic chuck 325 is secured to the support member 375 in the process chamber. It will be appreciated that the ESC 325 can be used in conjunction with the reactor 11 shown in Figure IX. In the embodiment shown in FIG. 3, the process chamber 380 (which corresponds to the chamber ι of FIG. 1) may include a process gas inlet 382 (which corresponds to the gas injection system 28 of FIG. 1), which is coupled to A process gas source 302 (which corresponds to an oxygen cylinder 32, an argon gas cylinder 62 or an inert gas cylinder 70) is supplied to the chamber 380. The process chamber 38 of Figure 3 further includes an exhaust outlet 384 coupled to an exhaust system 301. ❹ In the embodiment of Fig. 3, a substrate 345 is grasped on the ESc 325, and coolant is supplied from the coolant source or cooler 3 to cooling in the upper surface 34 of the insulator 335. The conduit 3〇5 also contains a cooling conduit or ditch. In one or more embodiments, the coolant comprises a conducting gas such as helium, argon, and a broad inert element of Group 8 of the Periodic Table. Substrate 345 gripping the ESC 325 covers and seals the cooling conduits 305 to prevent leakage of the coolant. The cooling • the coolant in the conduit 305 removes heat from the substrate 345 and maintains the substrate 345 at a fixed temperature during processing. In one or more embodiments, the cooling conduits 3〇5 are coupled to the coolant source 3〇〇' by a series of passages that extend through the entire insulator and electrode. The cooling conduits can be spaced apart, sized and dispersed to keep the coolant held therein substantially cool the entire substrate 345I - or in various embodiments, using plasma pulse technology to minimize The ruthenium is heated by the substrate of the plasma power delivered to the substrate. According to these 201034078 embodiments, plasma pulse techniques can be used during plasma oxidation to maintain the substrate at a temperature in the range of about -50 ° C to 100 ° C, for example, at about -25 C to 75 ° C. Within the specific range, and more specifically in the range of about 〇 ° c to 5 ° ° C. Plasma pulses can be implemented in a number of suitable ways. In one embodiment, the plasma can be cycled to maintain the substrate within the temperature range therebetween. In another embodiment, the plasma can be a kHz frequency pulsed plasma ranging from about 2 kHz to about 50 kHz.实施 An embodiment of a plasma pulse technique that uses a switch to cycle the plasma includes adjusting the average plasma electron/m degree and chemistry by pulse or time modulation of the RF plasma power signal. This technique is also known as RJ? The power supply is tuned and controls the electronic temperature independently of the RF plasma power level because during the power off time between pulses, the electron temperature is reduced at a much faster rate than the plasma density ^ RF plasma power modulation includes physical The plasma generation is turned on and off continuously or in a predetermined sequence. In one or more embodiments, the Φ RF plasma power modulation includes turning the power source that produces the ion generating region and the plasma on and off. In accordance with one or more embodiments, the plasma pulse technique includes replacing the ruler between a first frequency and a second frequency. The frequency of the power source. In one or more embodiments, the first and/or second frequencies may also be supplied with different amounts of power. This plasma pulse method is used to maintain or cool the substrate temperature to -50 it and 100. One or more embodiments include placing a substrate in a chamber of the electro-polymerization reactor and introducing a gas containing hydrogen, oxygen or inert gas into the chamber. A frequency is supplied to power 18 201034078 to the reactor to create a first thunderstorm in the chamber. The plasma is not supplied. Then a power is supplied at a second frequency to generate a plasma in the chamber. The class embodiment may also supply a different frequency of work than the first and second frequencies: in one or more embodiments, the = rate = supplied at the first or second frequency may be different and may be related to the frequencies One or both are periodically increased or decreased or remain fixed. The rate of change of the amount of power supplied at the first or second frequency may also be controlled to adjust or lower the temperature of the substrate.

在另一實施例中,可透過氣體對流將該基材溫度保持 在或冷卻至-50°C和100°C之間’藉由流通一冷卻或對流 氣體至該反應腔室内。在一或多個實施例中,一冷卻氣 體可流經該基材頂部而非該基材背側。在此類實施例 中’可調整該腔室以提供另一個氣體入口,使該冷卻氣 體流入該腔室内以冷卻該基材。在一或多個實施例中, 可設置該入口以使該冷卻氣體可她鄰該基材表面流動。 在一或多個實施例中,該冷卻氣體係一惰性氣體,其係 從一冷卻氣源供應至該腔室。在一或多個實施例中,該 惰性氣體係一種傳導氣體,例如氦氣、氬氣及週期表第 8族内的其他惰性元素。 第4圖示出第1圖之反應器11,更包含與該腔室10 的内部空間連結的冷卻氣體輸送系統29。該冷卻氣體輸 送系統29係由一冷卻氣源82供應,並流通一冷卻氣髏 至該腔室10内。在一或多個實施例中,該冷卻氣源可包 含一氦氣瓶。在一具體實施例中,該冷卻氣源可包含一 惰氣混合氣體瓶。冷卻流量控制閥80係經連結至該冷卻 19 201034078 乳源82。在第4圖所示實施例中該冷卻氣體係經供應 至該腔至並以所示方向毗鄰該基材流動,以冷卻該基材 溫度。 根據本發明之一或多個實施例,可使用若干方法在一 堆疊中形成氧化物層,例如閘極氧化物堆疊。第5圖示 出利用兩個閘極堆疊241、242和一基材203之間的空間 形成的溝槽250,如第2a_b圖所示者。該等閘極堆疊 • 242 了如上面參考第2A-B圖及/或薄膜堆疊240 所示般形成。該基材203也可包含在此參考第2A-B圖所 述之材料。在第5圖中,一氧化物層231係經形成在該 基材203上該等閘極堆疊241、242及該溝槽250上方》 該氧化物層係在一電漿反應器内形成,例如關於第1圖 所述之反應器11,利用不包含冷卻該基材的習知處理技 術。 發明人判定藉由將該基材保持在約-50。〇至l〇〇«c範圍 Φ 内,可改善利用低溫氧化法形成的薄膜或氧化物層的共 形性。在一或多個實施例中,可改善共形性而使該等側 壁上和該溝槽上的二氧化矽層厚度之間的比例高於至少 75%。 第5圖示出利用根據先前技藝之電漿氧化製程形成的 氧化物層231。第5圖具體示出閘極長度為65奈米並且 間隔為65奈米之淺溝槽隔離或“STI”結構的底部溝槽。 第5圖的氧化物層231係經沈積在形成在兩個薄膜堆疊 之間的溝槽250内,例如第2B圖所示之薄膜堆疊240。 20 201034078 該溝槽250係由兩個側壁251、252界定。半導體結構 200通常包含多個例如第2B圖所示之薄膜堆疊具有溝 槽250在薄膜堆疊之間。形成在第5圖所示溝槽25〇内 的氧化物層231在該溝槽250底部處的厚度大於在該等 侧壁25卜252處。第5圖的石夕結構係藉由利用快速熱氧 化法成長厚度75埃的通道氧化物,然後成長厚度12〇〇 埃的掺雜的多晶矽層形成。利用低壓化學氣相沈積或 “LPCVD”製程在該多晶層上形成厚度5〇埃的高溫氧化 攀物或“HTO”層以及最終—厚纟4⑼埃的氮切層。所形 成結構的高度大約《340_380奈米。該閘極長度和間距 是65奈米。 該氧化物層231在該等側壁25卜252處的厚度係介於 1.9奈米和2.1奈米之間。形成在該基材2〇3上該溝槽25〇 底表面處的氧化物層231的厚度約為3 2奈米。該氧化 物層231的共形性,也就是該等側壁251、252處該氧化 瘳 物層231的厚度對於該基材203上的厚度之間的比例係 在從約0.59至0.66之範圍内。 第6Α圖示出形成在與第5圖所用者相同類型的基材及 結構上的氧化物層232,但是,形成該氧化物層232的 方法包含利用一 ESC冷卻或保持該基材203的溫度,如 此間所述者。該基材203係置放在一腔室内一 Esc上, 如此說明書内他處所述般’並且在一電漿氧化製程期 間’該基材203背側或該基材與該ESC接觸的一側係利 用氦氣冷卻。在第6A圖所示實施例中,該氧化物層232 21 201034078 係藉由室溫電漿氧化製程利用約2000瓦的電源及含有 80。/。氫氣並且總流速為2〇〇 sCcm的製程氣體形成。用於 該ESC内的氦冷卻氣體係經設定在4t時間,並且該基材 係經冷卻至從約30eC至約50。(:範圍内的溫度。 所形成的氧化物層232在該等側壁251、252處的厚度 係介於2.5奈米和2.7奈米之間《該氧化物層232在該溝 槽250底表面處的厚度是2 7奈米。該氧化物層232的 共形性係介於0.93和1 .〇之間。 ® 參見第6B圖’利用此間所述之電漿脈衝法在與第5 圖所用者相同類型的基材及結構上形成一氧化物層 233 ’以保持或冷卻該基材溫度。如此間他處所述般,RF 電楽·電源訊號係藉由循環供應至該反應器的功率來脈 衝°利用一巨脈衝製程根據如下配方實體開關該電漿功 率··開啟4次持續25秒以及關閉4次持續120秒。運用 使用2000瓦的功率源之rt去耦電漿氧化或“Dp〇”腔室 φ 來形成該氧化物層。用來形成該氧化物層的製程氣體包 含80%的氣氣,並且係以約2〇〇 sccni的流速流入該腔室 内。該基材溫度係經冷卻至從約2〇°C和約-30°C範圍内的 溫度》 所形成的氧化物層233在該等側壁251、252處的厚度 是2.8奈来《該氧化物層233在該溝槽25〇底表面處的 厚度是3.1奈米,產生〇.9〇的共形性。如上面結果清楚 示出者’發現在電漿氧化期間將該基材溫度保持在或冷 卻至約-50°C和l〇〇eC範圍内的溫度可產生一共形的氧化 22 201034078 物層。 遍^本說明書所提到的“一個實施例,,、‘‘某些實施 例 或多個實施例”或“-實施例,,表示結合該實施例 所描述之—特定特徵、結構、材料、或特性係包含在本 發明之至少-巾。因此,遍及本㈣書各處之例 如“在-或多個實施例中,,、“在某些實施例中,,、“在一實 施例中,,或“在-個實施例中,,等句子的出現並不必定指 涉本發明之相同實施例。此外,該特^特徵結構材 料或特陡可在一或多個實施例中以任何適當方式組 合。不應將上述方法的描述順序視為限制性,並且該等 方法可不依照順序或以有減省或添加的方式使用所述操 作〇 應了解上面描述旨在說明,而非限制。 明後,對熟知技藝者而言,許多其他實施例會是顯而: 見的。因此,本發明之範圍應參考附屬申請專利範圍, Φ 連同此等申請專利範圍賦予等效物之完整範圍做判定。 【圖式簡單說明】 因此可以詳細暸解上述本發明之特徵結構的方式,即 對本發明更明確的描述,簡短地在前面概述過,可藉由 參考實施例來得到,其中某些在附圖中示出。但應注意 的是,附圓僅示出本發明之一般實施例,因此不應視為 係對其範圍之限制,因為本發明可允許其他等效實施例。 23 201034078 第1圖示出根據本發明之一實施例的電漿反應器; 第2A-B圖示出根據本發明之一或多個實施例的半導 體結構之製造階段; 第3圓示出用於本發明之一實施例的靜電夹盤; 第4圖示出包含一對流氣源的電漿反應器腔室; 第5圖示出利用先前技藝之電漿氧化製程形成的氧化 物層;以及 第6A-6B圖示出利用根據本發明之一或多個實施例之 電漿氧化製程形成的氧化物層。 【主要元件符號說明】 10 、 380 腔室 11 反應器 12 側壁 14 頂板 16 線圈天線 18 第一阻抗匹配網絡 20 RF功率產生器 22 閘極 26 基材支撐座 27、202、345 半導體基材 28 氣體注入系統 29 冷卻氣體輸送系統 24 201034078 30 真空幫浦 32 氧氣瓶 34 加熱器 34a、34b 加熱元件 36 脈衝產生器 38 節流閥 39 離子產生區 62 氫氣瓶 64、66、68 流量控制閥 70 惰氣瓶 80 冷卻流量控制閥 82 冷卻氣源 200 半導體結構 204 穿隧氧化物層 206 浮置閘極層 210 多晶矽間介電層 氧化物層 212 、 216 、 230 、 231 、 232 、 233 214 氮化物層 220 控制閘極層 240 薄膜堆疊 241、242 閘極堆疊 250 溝槽 251、252 側壁 300 冷卻劑源 25 201034078In another embodiment, the temperature of the substrate can be maintained or cooled to between -50 ° C and 100 ° C by gas convection by circulating a cooling or convection gas into the reaction chamber. In one or more embodiments, a cooling gas can flow through the top of the substrate rather than the back side of the substrate. In such embodiments, the chamber can be adjusted to provide another gas inlet that allows the cooling gas to flow into the chamber to cool the substrate. In one or more embodiments, the inlet can be configured to allow the cooling gas to flow adjacent to the surface of the substrate. In one or more embodiments, the cooling gas system is an inert gas supplied to the chamber from a source of cooling gas. In one or more embodiments, the inert gas system is a conducting gas such as helium, argon, and other inert elements within Group 8 of the Periodic Table. Fig. 4 shows the reactor 11 of Fig. 1 and further includes a cooling gas delivery system 29 coupled to the internal space of the chamber 10. The cooling gas delivery system 29 is supplied from a source of cooling gas 82 and circulates a cooling gas into the chamber 10. In one or more embodiments, the source of cooling gas may comprise a helium cylinder. In a specific embodiment, the source of cooling gas may comprise an inert gas mixture gas bottle. Cooling flow control valve 80 is coupled to the cooling source 19 201034078. In the embodiment illustrated in Figure 4, the cooling gas system is supplied to the chamber and flows adjacent the substrate in the direction indicated to cool the substrate temperature. In accordance with one or more embodiments of the present invention, oxide layers, such as gate oxide stacks, may be formed in a stack using a number of methods. The fifth diagram illustrates a trench 250 formed by the space between the two gate stacks 241, 242 and a substrate 203, as shown in Fig. 2a-b. The gate stacks 242 are formed as described above with reference to Figures 2A-B and/or film stack 240. The substrate 203 may also comprise the materials described herein with reference to Figures 2A-B. In FIG. 5, an oxide layer 231 is formed on the substrate 203 over the gate stacks 241, 242 and the trenches 250. The oxide layer is formed in a plasma reactor, for example The reactor 11 described in Fig. 1 utilizes a conventional treatment technique that does not include cooling the substrate. The inventors determined that the substrate was maintained at about -50. The range of 〇 to l〇〇«c Φ improves the conformality of the film or oxide layer formed by the low temperature oxidation method. In one or more embodiments, the conformality can be improved such that the ratio between the thickness of the ceria layer on the sidewalls and the trench is greater than at least 75%. Fig. 5 shows an oxide layer 231 formed using a plasma oxidation process according to the prior art. Figure 5 specifically shows the shallow trench isolation or "STI" structure bottom trench with a gate length of 65 nm and a spacing of 65 nm. The oxide layer 231 of Fig. 5 is deposited in a trench 250 formed between two film stacks, such as the thin film stack 240 shown in Fig. 2B. 20 201034078 The groove 250 is defined by two side walls 251, 252. The semiconductor structure 200 typically comprises a plurality of thin film stacks, such as shown in Figure 2B, having trenches 250 between the thin film stacks. The thickness of the oxide layer 231 formed in the trench 25A shown in Fig. 5 is greater at the bottom of the trench 250 than at the sidewalls 252. The lithium structure of Fig. 5 is formed by growing a channel oxide having a thickness of 75 Å by rapid thermal oxidation and then growing a doped polysilicon layer having a thickness of 12 Å. A high temperature oxide or "HTO" layer having a thickness of 5 angstroms and a nitrogen layer of a final - thick 纟4 (9) angstrom are formed on the polycrystalline layer by a low pressure chemical vapor deposition or "LPCVD" process. The height of the structure formed is approximately 340_380 nm. The gate length and spacing are 65 nm. The thickness of the oxide layer 231 at the sidewalls 25, 252 is between 1.9 nm and 2.1 nm. The thickness of the oxide layer 231 formed on the bottom surface of the trench 25 on the substrate 2〇3 is about 32 nm. The conformality of the oxide layer 231, that is, the ratio of the thickness of the ruthenium oxide layer 231 at the sidewalls 251, 252 to the thickness on the substrate 203 is in the range of from about 0.59 to 0.66. Figure 6 illustrates an oxide layer 232 formed on the same type of substrate and structure as used in Figure 5, however, the method of forming the oxide layer 232 includes cooling or maintaining the temperature of the substrate 203 using an ESC. , so described. The substrate 203 is placed in a chamber, an Esc, as described elsewhere in the specification, and during the plasma oxidation process, the back side of the substrate 203 or the side of the substrate that is in contact with the ESC. It is cooled by helium. In the embodiment illustrated in Figure 6A, the oxide layer 232 21 201034078 utilizes a power supply of about 2000 watts and contains 80 by a room temperature plasma oxidation process. /. A process gas of hydrogen gas and a total flow rate of 2 〇〇 s Ccm is formed. The helium cooling gas system used in the ESC was set at 4 t and the substrate was cooled to from about 30 eC to about 50. (: temperature in the range. The thickness of the formed oxide layer 232 at the sidewalls 251, 252 is between 2.5 nm and 2.7 nm. "The oxide layer 232 is at the bottom surface of the trench 250. The thickness is 27. 7 nm. The conformality of the oxide layer 232 is between 0.93 and 1. ® See Figure 6B 'Using the plasma pulse method described herein in the figure with Figure 5 An oxide layer 233' is formed on the same type of substrate and structure to maintain or cool the substrate temperature. As described elsewhere, the RF power supply signal is supplied by circulating power to the reactor. Pulse ° utilizes a giant pulse process to switch the plasma power according to the following formula. • Turn on 4 times for 25 seconds and turn off 4 times for 120 seconds. Use rt decoupled plasma oxidation or “Dp〇” using a 2000 watt power source. The chamber φ forms the oxide layer. The process gas used to form the oxide layer contains 80% of gas and flows into the chamber at a flow rate of about 2 〇〇 sccni. The substrate temperature is cooled. Oxide formed to a temperature ranging from about 2 ° C and about -30 ° C The thickness of layer 233 at the sidewalls 251, 252 is 2.8. The thickness of the oxide layer 233 at the bottom surface of the trench 25 is 3.1 nm, resulting in a conformality of 〇.9 。. The results clearly show that it was found that maintaining the substrate temperature at or cooling to a temperature in the range of about -50 ° C and l 〇〇eC during plasma oxidation produces a conformal oxidation 22 201034078 layer. References to "an embodiment," "some embodiments or embodiments" or "an embodiment" or "an embodiment," Included in the present invention is at least a towel. Thus, throughout the text of this (4), for example, "in" or "in the embodiment", "in some embodiments,", "in an embodiment," or "In an embodiment, the appearance of a sentence does not necessarily refer to the same embodiment of the invention. Furthermore, the feature material or feature may be combined in any suitable manner in one or more embodiments. The order in which the above methods are described should not be considered as limiting, and such The above description may be used in a manner that is not intended to be limiting or to be added or added, and the description is intended to be illustrative, and not restrictive. After that, many other embodiments will be apparent to those skilled in the art: Therefore, the scope of the present invention should be determined by reference to the scope of the appended claims, and the scope of the claims is to be construed as the scope of the equivalents. That is, a more descriptive description of the present invention, briefly outlined above, may be obtained by reference to the examples, some of which are illustrated in the drawings, but it should be noted that the appendices only show the general implementation of the invention. The scope of the invention is not to be construed as limiting the scope of the invention. 23 201034078 Figure 1 shows a plasma reactor in accordance with an embodiment of the present invention; 2A-B illustrates a stage of fabrication of a semiconductor structure in accordance with one or more embodiments of the present invention; An electrostatic chuck according to an embodiment of the present invention; FIG. 4 shows a plasma reactor chamber including a pair of flow gas sources; and FIG. 5 shows an oxide layer formed by a prior art plasma oxidation process; 6A-6B illustrate an oxide layer formed using a plasma oxidation process in accordance with one or more embodiments of the present invention. [Main component symbol description] 10, 380 Chamber 11 Reactor 12 Sidewall 14 Top plate 16 Coil antenna 18 First impedance matching network 20 RF power generator 22 Gate 26 Substrate support 27, 202, 345 Semiconductor substrate 28 Gas Injection system 29 Cooling gas delivery system 24 201034078 30 Vacuum pump 32 Oxygen cylinder 34 Heater 34a, 34b Heating element 36 Pulse generator 38 Throttle valve 39 Ion generation zone 62 Hydrogen cylinder 64, 66, 68 Flow control valve 70 Inert gas Bottle 80 Cooling Flow Control Valve 82 Cooling Gas Source 200 Semiconductor Structure 204 Tunneling Oxide Layer 206 Floating Gate Layer 210 Polycrystalline Dielectric Dielectric Layer Oxide Layer 212, 216, 230, 231, 232, 233 214 Nitride Layer 220 Control gate layer 240 film stack 241, 242 gate stack 250 trenches 251, 252 sidewall 300 coolant source 25 201034078

301 302 305 325 330 333 335 340 350 355 360 365 370 375 382 排氣系統 製程氣源 冷卻導管 靜電夾盤 孔 靜電組件 絕緣體 上表面 電極 電氣連接器 電壓供應導線 電氣接觸 電壓供應終端 支撐件 製程氣體入口 排氣出口 384301 302 305 325 330 333 335 340 350 355 360 365 370 375 382 Exhaust system process air supply cooling duct electrostatic chuck hole electrostatic component insulator upper surface electrode electrical connector voltage supply wire electrical contact voltage supply terminal support process gas inlet row Gas outlet 384

Claims (1)

201034078 七、申請專利範圍: 1.一種在一半導體基材上處理一氧化物層时法,其至 少包含: 將欲氧化的基材置於具有—離子產生區的—電浆反 應室内一基材支撐件上; 通入裝程氣鍾至該腔室内;以及 在該電漿反應室的離子產生區内產生一電漿以在該 _ 基材上形成一氧化物層,該氧化物層具有一水平表面厚 度及一側壁厚度,同時主動冷卻該基材至約-5(TC至1〇〇 °c範圍内的溫度。 2.如申請專利範圍第丨項所述之方法,其中上述之基材 溫度在該氧化物層形成期間係經主動冷卻至約_25 〇c至 75 °C範圍内的溫度。 I 3.如申請專利範圍第1項所述之方法,其中上述之基材 溫度在該氧化物層形成期間係經主動冷卻至約〇&lt;&gt;(:至5〇 °c範圍内的溫度。 4.如申請專利範圍第1項所述之方法,其中上述之主動 冷卻該基材溫度包含使一冷卻劑流動通過該基材支撐 件。 27 201034078 5.如申請專利範圍第4項所述之方法,其中上述之基材 支撐件包含-表面’其具有複數個冷卻導管並且主動 冷卻該基材溫度包含使該基材㈣基材支料的表面接 ’其中上述之基材 冷卻劑至該等冷卻 6.如申請專利範圍第5項所述之方法 支撐件更包含一系列通道,其供應一 導管。201034078 VII. Patent Application Range: 1. A method for treating an oxide layer on a semiconductor substrate, comprising at least: placing a substrate to be oxidized in a plasma reaction chamber having a source-ion generating region On the support member; introducing a process gas into the chamber; and generating a plasma in the ion generating region of the plasma reaction chamber to form an oxide layer on the substrate, the oxide layer having a horizontal surface The thickness and a thickness of the sidewall, while actively cooling the substrate to a temperature in the range of about -5 (TC to 1 〇〇 °c. 2. The method of claim </ RTI> wherein the substrate temperature is The oxide layer is formed by active cooling to a temperature in the range of about _25 〇c to 75 ° C. The method of claim 1, wherein the substrate temperature is in the oxide The layer is formed by active cooling to a temperature in the range of about 〇 & & 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 主动 主动 主动 主动 主动 主动Passing a coolant through the substrate The method of claim 4, wherein the substrate support comprises a surface comprising a plurality of cooling conduits and actively cooling the substrate temperature comprising comprising the substrate (four) The surface of the material support is connected to the above-mentioned substrate coolant to the cooling. 6. The method of claim 5 further comprises a series of channels for supplying a conduit. 7.如申請專利範圍第4項所述之方法,其中上述之主動 冷卻該基材溫度包含流動-對流氣體至該反應腔室内。 8.如申請專利範圍_ 7項所述之方法,其中上述之對流 氣體包含氦氣。 • 如申請專利範圍冑7項所述之方法,其中上述之對流 氣體包含約500 SCCm至約3000 sccm範圍内的流速。 1〇.—種在一半導體基材上形成一氧化物層的方法,其至 少包含: 將欲氧化的基材置於一電漿反應器之一腔室内一基 材支撐件上,該腔室具有一離子產生區; 通入一製程氣體至該腔室内;以及 在該腔室之該離子產生區内產生一電漿,以在該基材 28 201034078 上形成一氧化物層,同時主動冷卻該基材至低於約100 C的溫度。 11 ·如申請專利範圍第10頊所述之方法,其中上述之電 漿包含一氧物種,並且主動冷卻該基材增加該氧物種的 黏滯係數。 12. 如申請專利範圍第1〇項所述之方法,其中上述之主 ® 動冷卻該基材包含流動一對流氣體至該反應器。 13. 如申請專利範圍第項所述之方法,其中上述之主 動冷卻該基材包含在該基材和該基材支樓件之間循環一 冷卻劑。 14.如申請專利範圍第13 φ 卻劑包含氦氣。 項所述之方法,其中上述之冷 項所述之方法,其中上述之冷 15.如申請專利範圍第14 卻劑更包含一第二惰氣。 297. The method of claim 4, wherein the actively cooling the substrate temperature comprises flowing-convection gas into the reaction chamber. 8. The method of claim 7, wherein the convective gas comprises helium. • The method of claim 7, wherein the convective gas comprises a flow rate in the range of from about 500 SCCm to about 3000 sccm. A method for forming an oxide layer on a semiconductor substrate, comprising: placing a substrate to be oxidized on a substrate support in a chamber of a plasma reactor, the chamber Having an ion generating region; introducing a process gas into the chamber; and generating a plasma in the ion generating region of the chamber to form an oxide layer on the substrate 28 201034078 while actively cooling the The substrate is at a temperature below about 100 C. 11. The method of claim 10, wherein the plasma comprises an oxygen species, and actively cooling the substrate increases a viscosity coefficient of the oxygen species. 12. The method of claim 1, wherein the main cooling of the substrate comprises flowing a pair of flowing gases to the reactor. 13. The method of claim 1 wherein said actively cooling said substrate comprises circulating a coolant between said substrate and said substrate support member. 14. If the patent application scope 13 φ agent contains helium. The method of the above item, wherein the cold method is as described in claim 14, wherein the agent further comprises a second inert gas. 29
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