TW201034055A - Continuous feed chemical vapor deposition - Google Patents

Abstract

Embodiments of the invention generally relate to method for forming a multi-layered material during a continuous chemical vapor deposition (CVD) process. In one embodiment, a method for forming a multi-layered material during a continuous CVD process is provided which includes continuously advancing a plurality of wafers through a deposition system having at least four deposition zones. Multiple layers of materials are deposited on each wafer, such that one layer is deposited at each deposition zone. The methods provide advancing each wafer through each deposition zone while depositing a first layer from the first deposition zone, a second layer from the second deposition zone, a third layer from the third deposition zone, and a fourth layer from the fourth deposition zone. Embodiments described herein may be utilized to form an assortment of materials on wafers or substrates, especially for forming Group III/V materials on GaAs wafers.

Description

201034055 VI. Description of the Invention: [Technical Fields of the Invention] Embodiments of the present invention generally relate to vapor deposition methods and apparatus, and more particularly to chemical vapor deposition processes and chambers. [Prior Art] Chemical vapor deposition (CVD) is performed by reacting a gas phase chemical with a thin film on a substrate such as a wafer. A chemical vapor deposition reactor is used to deposit various constituent films onto the substrate. CVD systems are highly useful in many applications, such as in the fabrication of devices for semiconductors, solar, displays, and other electronic applications. There are many types of CVD reactors for very different applications. For example, a CVD reactor includes an atmospheric pressure reactor, a low pressure reactor, a low temperature reactor, a high temperature reactor, and a plasma enhanced reactor. Different designs address various challenges encountered during CVD processes, such as depletion effects, contamination problems, and reactor maintenance. Although there are many different reactor designs, there is still a need for a novel and improved CVD reactor design. [Inventive] Embodiments of the present invention generally relate to the formation of multiple layers during a continuous chemical vapor deposition (CVD) process. Method of material. In many embodiments, the wafers are advanced or moved horizontally in the same direction while passing the same phase 201034055 through multiple deposition zones within the deposition system. Multiple layers of material are deposited on each wafer, such a layer deposited in each deposition area. Multiple deposit layers on each wafer can have the same composition, but the layers typically have different compositions. The described embodiments can be used in a variety of CVD and/or epitaxial deposition processes to deposit, grow or form various materials onto a wafer or substrate, particularly a Group III/V material on a gallium arsenide wafer.

In one embodiment, a method of forming a multilayer material during a continuous CVD process is proposed 'which includes: continuously advancing a plurality of wafers through a deposition system, wherein the deposition system has a first deposition region, a second deposition region, a third deposition region, and a fourth deposition region; and depositing the first material layer onto the first wafer in the first deposition region. The method further proposes depositing a second material layer onto the first wafer in the second deposition region while depositing the first material layer onto the second wafer in the first deposition region. The method further proposes depositing a third material layer onto the first wafer in the second deposition region while depositing the second material layer onto the second wafer in the second deposition region, and simultaneously depositing the first material layer to the first On the third wafer in the deposition area. The method further proposes depositing a fourth material layer onto the first wafer in the fourth deposition region, simultaneously stacking the first material layer to the second wafer in the third deposition region, and simultaneously depositing the second material layer to On the third wafer in the second deposition region, and simultaneously depositing the first material layer onto the fourth wafer in the first sinking/parent region. In some embodiments, the method further proposes to stack the fifth material layer to the first crystal grain in the fifth deposition region, because the 冋 round 冋 & L L 第四 第四 第四 第四 第四 第四On the second wafer in the area, when the circle is on the other side, the third material layer is stacked on the second r-th cup in the second deposition area, and the second material layer is simultaneously deposited. 201034055 On the fourth wafer in the second deposition region and simultaneously depositing the first material layer onto the fifth wafer in the first deposition region. In some examples, the first material layer, the second material layer, the third material layer, and the fourth material layer have the same composition. In other examples, the first material layer, the second material layer, the third material layer, and the fourth material layer are each different in composition. In many examples, the first material layer, the second material layer, the third material layer, and the fourth material layer each contain arsenic (e.g., gallium arsenide, aluminum arsenide, or aluminum gallium arsenide). The method further proposes heating the wafer to a predetermined temperature in the heated region before proceeding to the first deposition region. The predetermined temperature may be about 5 〇t; to about 75 ° C, preferably about 〇 (TC to about 35 (rc » In some embodiments, the wafer is heated to a predetermined temperature, from about 2 minutes to about 6 Minutes, or from about 3 minutes to about 5 minutes. The method also proposes that after depositing the fourth material layer, the wafer is transferred to the cooling zone β and then the wafer is cooled to a predetermined temperature in the cooling zone. The predetermined temperature may be about 18. (: to about 30 〇 c. In some embodiments, each wafer is cooled to a predetermined temperature, for about 2 minutes to about 6 minutes, or for about 3 minutes to about 5 minutes. „ In other embodiments, enter Before the first deposition region, after the wafer passes through the heating region and exits the fourth deposition region, the wafer passes through the cooling region. The heating region, the first, second, third, and fourth deposition regions, and the cooling region are all shared. A common linear path. The wafers can be continuously and horizontally advanced along a common linear path within the deposition system. In one embodiment, a method of forming a multilayer material during a continuous CVD process is proposed, which includes continuously advancing a plurality of wafers through deposition System, 6 201034055 where sink The system has a first deposition region, a second deposition region, a third deposition region, and a fourth deposition region. The method further proposes depositing a buffer layer onto the first wafer in the first deposition region, depositing the sacrificial layer into the second deposition region On the first wafer, a buffer layer is simultaneously deposited onto the second wafer in the first deposition region. The method further proposes depositing a passivation layer onto the first wafer in the third deposition region, while depositing a sacrificial layer And onto the second wafer in the second deposition region, and simultaneously depositing the buffer layer on the third wafer in the first deposition region. The method further proposes depositing the gallium arsenide active layer to the first crystal in the fourth deposition region Rounding, simultaneously depositing a passivation layer onto the second wafer in the third deposition region, and simultaneously depositing the sacrificial layer onto the second wafer in the second deposition region, and simultaneously depositing the buffer layer into the first deposition region On the fourth wafer, in many examples, the wafer is a gallium antimonide wafer. In some embodiments, the method further proposes depositing a gallium-containing layer onto the first wafer in the fifth deposition region while depositing arsenic Gallium active layer to On the first wafer in the four deposition & field, the purification layer is simultaneously deposited onto the third wafer in the third deposition φ region, and the sacrificial layer is simultaneously deposited onto the fourth wafer in the second deposition region. And depositing a buffer layer on the fifth wafer in the first deposition region at the same time. In some examples, the gallium-containing layer contains cobalt gallium. In some embodiments, the method further advances the wafer to the first deposition region. The wafer is heated to a predetermined temperature in the heated region. The predetermined temperature may be from about 50 ° C to about 750 ° C, preferably from about 100 ° C to about 35 ° C. In other embodiments, the method is further After depositing the active layer of gallium arsenide, the wafer is transferred to the cooling zone. Then, in the cooling zone, the wafer is cooled to about 18 ° C to about 3 (the predetermined temperature of TC. 7 201034055 in other embodiments ' enters the first Before the deposition area, the wafer passes through the heating region, and after leaving the fourth deposition region, the wafer passes through the cooling region. The heating zone, the first, second, third and fourth deposition zones, and the cooling zone all share a common linear path. Additional deposition areas (such as fifth, sixth, seventh or above) also share a common linear path, as the case may be. The method proposes that the wafer can be continuously and horizontally advanced along a common linear path within the deposition system. In other embodiments, the method further suggests flowing at least one gas between the deposition regions to form a gas curtain therebetween. In some embodiments, the gas curtain or screen contains or consists of at least one gas such as hydrogen, helium, a mixture of hydrogen and helium, nitrogen, argon, or a combination thereof. In many instances, a mixture of hydrogen and lung is used. To form a gas curtain or screen. In another embodiment, a method of forming a multilayer material during a continuous CVD process is proposed, comprising continuously advancing a plurality of wafers through a deposition system, wherein the deposition system has a heating region, a first deposition region, a second > a third deposition zone, a fourth deposition zone, and a cooling zone. The method further proposes depositing a gallium antimonide buffer layer onto the first wafer in the first deposition region, and then depositing the arsenic layer onto the first wafer in the second deposition region while depositing a gallium arsenide buffer layer to On the second wafer in the first deposition area. The method further proposes depositing a passivation layer of bismuth-deposited gallium onto the first wafer in the third deposition region, and simultaneously depositing a sacrificial layer of Kunming Ming onto the second wafer in the second deposition region and simultaneously depositing a gallium arsenide buffer. The layer is on the third wafer in the first deposition region. The method is further proposed to deposit the third layer of 201034055 'a door call> 兀 very " τ... Ming gallium passivation layer to the third deposition area (4), and simultaneously deposit the sacrificial layer of the 珅化铭 into the third deposition area A gallium arsenide buffer layer is deposited on the wafer and simultaneously onto the fourth wafer in the first deposition region.

Other embodiments of the invention are generally directed to CVD reactor systems and methods of use thereof. In an embodiment, a CVD system is proposed which includes a cover assembly' such as a top plate having a plurality of projections disposed along the longitudinal axis of the top plate. The system includes a track having a material path (e.g., a channel) disposed along the roadway (4), wherein the material system is adapted to receive a plurality of raised portions of the top plate to form a gap between the plurality of raised portions and the floor of the track, wherein the gap It is configured to receive the substrate. The system includes a heating assembly, such as a heating element, operable to heat the substrate as the substrate moves along the path of the track. In an embodiment, the track is operable to float the substrate along the channel of the track. In an embodiment, the system includes a groove to support the track. The thickness of the gap is from about 0.5 mm to about 5 mm, or from about 5 to about 1. The top plate consists of a turn or quartz, and the track consists of quartz or dioxotomy. The top plate is operable to direct gas to the gap and further includes a plurality of weirs disposed along the longitudinal axis of the top plate and between the plurality of raised portions, thereby defining a path between the plurality of raised portions. One or more jaws are adapted to transport and/or vent gas to the gap between the plurality of raised portions of the top plate and the track floor. Examples of heating elements include heat lamps coupled to the track, a plurality of tracks along the track The heating lamp, the heating lamp group moving along the track along the track of the substrate, the resistance heater coupled to the track, the induction heating source coupled to the substrate and/or the track by the 201034055. The heating element is used to maintain a temperature difference across the substrate' where the temperature difference is less than 耽. In one embodiment, the CVD system is an atmospheric pressure cvd system. In an embodiment, a CVD system is proposed which includes: an inlet isolator operable to prevent contaminants from entering the system from the system population; an outlet isolator 'to prevent contaminants from entering the system from the system outlet; An intermediate isolator between the inlet isolator and the outlet isolator. The system also includes

设置 setting a first deposition area adjacent to the inlet isolator and a first deposition area adjacent to the outlet isolator: an inter-isolator is disposed between each deposition area' and operable to prevent gas in the first deposition area and the second deposition Inter-area mixing In the embodiment, the inlet isolator is more operable to prevent the gas from being diffused back into the first deposition zone, and the intermediate separator is more operable to prevent the gas in the first accumulation region from diffusing back, the outlet isolator It is more operable to prevent the gas injected into the first deposition zone from diffusing back. The isolation region formed by at least one of the separators has a length of from about i meters to about 2 meters. Gases (such as nitrogen milk) are injected into the population with a first-rate catch (such as 3 liters per minute), and gas is freed from the first deposition area. A gas such as helium is injected into the intermediate separator at a first velocity (e.g., 3 liters per minute) to prevent gas from mixing between the first deposition zone and the second deposition zone. A gas (such as nitrogen) is injected into the outlet isolator at a speed of 3 liters per minute to prevent the/loss material from entering the system from the system outlet. In one embodiment, the venting means is positioned adjacent to each of the isolators for discharging the isolator. The discharge device can be placed adjacent to each deposition area to discharge the gas injected into the sinking area of 201034055. In an embodiment, a CVD system is proposed which includes a housing, a track surrounded by a housing, wherein the track defines a guiding path (e.g., a channel) adapted to guide the substrate through the CVD system. The system includes a carrier that moves the base plate along a path of the track, wherein the track system is operable to float along the track of the track. The outer casing is composed of molybdenum, quartz or stainless steel, and the orbit is composed of quartz, molybdenum, molten cerium oxide or ceramic, and the carrier is composed of graphite. In an embodiment, the track includes a plurality of openings and/or conduits disposed along the track floor, each operative to supply a cushion to the channel and the underside of the carrier to lift or float the carrier, and along the track Substantially centered the vehicle. The catheter is V-shaped and the carrier has a recess (e.g., a V-shape) disposed along its bottom surface. Gas is supplied to the recess of the carrier to substantially lift the carrier from the track floor and substantially center the carrier along the path of the track. The track is, for example, inclined less than about 10 degrees, less than about 20 degrees, or between about 1 degree and 5 degrees to move and float the substrate from the first end of the channel to the first end of the channel. The track and/or housing includes a plurality of segments. In one embodiment, the system includes a conveyor operable to automatically introduce the substrate into the channel, a recycler operable to automatically retrieve the substrate from the channel, and/or a heating element operable to heat the substrate. The heating element is coupled to the housing, the substrate, and/or the track. The carrier is operable to carry a substrate strip along the path of the track » In one embodiment, an obstruction assembly for moving the substrate through the CVD system is proposed, which includes a top section having a ground, disposed adjacent The side supports on the ground (such as pairs of rails; a pair 〇f raiis), which in turn define the 201034055 guide path (such as the channel) to guide the substrate along the ground. The bottom section is coupled to the top section to form one or more chambers therebetween. The top section includes a recessed bottom surface that includes a recessed top surface thereby forming a chamber. In one embodiment the 'top section and/or the bottom section are formed of molybdenum, quartz, dioxin, alumina or ceramic. • In one embodiment, the top section has a plurality of openings that extend through the ground to provide fluid communication between the chamber and the passage. The chamber supplies an air cushion (e.g., nitrogen) to the passage to substantially lift the substrate and carry the substrate along the top section of the ground. The ground, for example, is inclined less than about 1 inch, less than about 2 degrees, or between about 1 and 5 degrees to move and float the substrate from the first end of the channel to the second end of the channel. In one embodiment, the top section has a plurality of openings that are threaded through the pair of rails (near the ground). The gas is supplied by a plurality of openings to physically center the substrate moving along the channels of the top section. The floor also includes a tapered profile and/or a gas supply conduit, each operable to substantially center the substrate moving along the passage of the top section. The conduit is V-shaped and/or the substrate has a recess (e.g., a V-shape) to receive an air cushion disposed along the bottom surface of the substrate to substantially center the substrate moving along the passage of the top section. In the embodiment, the track assembly includes a conveyor operable to automatically introduce the substrate into the channel, and/or a recycler operable to retrieve the substrate from the channel. An injection line is coupled to the bottom section to substantially float the substrate along the ground of the top section via the ground supply chamber to the gas. The top section further includes a recess ' adjacent to the rail for receiving a reactor cover assembly, such as a top plate. The track assembly includes a groove for seating the top section and the bottom 12 201034055 section. The grooves are formed of quartz, molybdenum or stainless steel. In one embodiment, a method of forming a multilayer material during a CVD process includes forming a gallium arsenide buffer layer onto a gallium arsenide substrate, forming a sacrificial aluminum sacrificial layer onto the buffer layer, and forming an aluminum gallium arsenide passivation layer. To the sacrifice • on the ground. The method further includes forming an active layer of gallium arsenide (eg, a thickness of about 1000 " nanometer (nm)) onto the passivation layer. The method further includes forming a phosphorous gallium arsenide layer onto the active layer. The method further includes removing the sacrificial layer to separate the active layer from the substrate. φ Kunming Ming sacrificial layer can be exposed to the residual liquid. The epitaxial lift off process separates the active layer of gallium arsenide and the substrate. The method further includes forming an additional multilayer material to a thickness of the beta buffer layer on the substrate during the subsequent CVD process to a thickness of about 300 nm, a passivation layer having a thickness of about 3 nm, and/or a thickness of the sacrificial layer of about 5 nm ^ in one embodiment. 'Proposed method of forming a multilayer epitaxial layer onto a substrate using a CVD system' which includes introducing a substrate from a system inlet into a guiding path (eg, a via) while preventing contaminants from entering the system from the inlet into the system to deposit a first epitaxial layer onto the substrate, At the same time, the substrate moves along the system channel, deposits the second layer onto the substrate, and the substrate moves along the system channel, avoids mixing of the gas between the first deposition step and the second deposition step, and retrieves the substrate of the channel from the system outlet. The method for preventing contaminants from entering the system from the outlet further comprises: heating the substrate before depositing the first epitaxial layer; maintaining the substrate temperature when depositing the first and second epitaxial layers onto the substrate; and/or depositing the second After the epitaxial layer, the substrate is cooled. The substrate is substantially floating along the system channel. The first insect layer includes Sui Huaming, and/or the second stupid layer includes Shenhua Marriage. In the embodiment the substrate is substantially floating along the system channel. 13 201034055 The method further includes depositing a gallium arsenide layer onto the substrate, and/or heating the substrate from about 300 ° C to about 800 when depositing the epitaxial layer. (: The center-to-edge temperature difference of the substrate is within 10 ° C. In an embodiment, a CVD reactor is proposed that includes a lid assembly with a main crucible, and a body with a guide along the longitudinal axis of the body a track assembly of the path. The body of the cover assembly and the body of the track assembly are coupled together to form a gap therebetween for receiving the substrate. The reactor further includes a heating assembly including a plurality of heating lamps disposed along the track assembly. And operable to heat the substrate as the substrate moves along the guiding path. The reactor further includes a track assembly support, wherein the track assembly is disposed in the track assembly support. The body of the track assembly is provided with gas extending along the longitudinal axis of the body. a cavity and a plurality of openings extending from the air pocket to the upper surface of the guiding path to be configured to supply the air cushion along the guiding path. The body of the track assembly comprises quartz. The body of the cover assembly includes a plurality of ports, the mouthpieces are configured Provided to the guiding path (iv) body communication. The g component is operable to maintain a temperature difference across the substrate 'the temperature difference in the crucible is less than the grip. In an embodiment, The CVD reactor is an atmospheric pressure cvd reactor. In an embodiment, a CVD system is proposed that includes an inlet isolator that is operable to prevent contaminants from entering the system from the system inlet, exiting the isolator, and is operable to prevent contaminants from the system An outlet inlet system, and an intermediate separator disposed between the inlet isolator and the outlet isolator. The system further includes a first deposition zone disposed adjacent to the inlet isolator and a second deposition zone disposed adjacent to the outlet isolator. The gas is disposed between the deposition regions to prevent the gas from mixing between the first deposition region and the second deposition region 14 201034055. The gas is injected into the inlet separator at a first flow rate to prevent the gas from diffusing back from the first deposition region, and the gas is The first flow rate is injected into the intermediate isolator 'to prevent gas from mixing between the first deposition zone and the second deposition zone' and/or the gas is injected into the outlet isolator at a first flow rate to prevent contamination from entering the system from the system outlet. Is disposed adjacent to each of the isolated v-' and operable to discharge gas injected into the isolator, and/or set adjacent to each An area that is operable to discharge gas injected into the deposition zone. φ In one embodiment, a CVD system is proposed that includes a housing, a track surrounded by the housing, wherein the track includes a guiding path adapted to guide the substrate through the CVD system And a substrate carrier that moves the substrate along the guiding path, wherein the track system is operable to float the substrate carrier along the guiding path. The track includes a plurality of openings ' operable to supply the air cushion to the guiding path. The air cushion is applied to the substrate a bottom surface of the carrier to lift the substrate carrier track from the ground. The track includes a conduit disposed along the guiding path for substantially centering the substrate carrier along the guiding path of the track. The air cushion is supplied to the base plate carrier via the conduit a bottom surface to substantially lift the substrate carrier from the track surface. The track is tiltable to move the substrate from the first end of the guiding path to the second end of the guiding path. The system includes a heating assembly that includes a plurality of heating along the track. A lamp is operable to heat the substrate as the substrate moves along the guiding path. [Embodiment] The embodiment of the present invention is generally directed to a chemical vapor deposition (CVD) apparatus 15 201034055. As previously stated, embodiments of the invention relate to atmospheric pressure cVD reactors and metal organic precursor gases. It is to be noted that aspects of the invention are not limited to the use of atmospheric pressure CVD reactors or metal organic precursor gases, but may be applied to other types of reactor systems and precursor gases. For a better understanding of the novelty of the apparatus of the present invention and its method of use, reference will now be made to the accompanying drawings.

According to one embodiment of the invention, an atmospheric pressure CVD reactor is provided. A CVD reactor can be used to provide a plurality of epitaxial layers on a substrate, such as a BB circle (e.g., a gallium arsenide wafer). The epitaxial layer includes aluminum gallium arsenide, gallium arsenide, and gallium arsenide. The epitaxial layer can be formed on the gallium arsenide wafer and removed later so that the wafer can be reused to create additional material. In one embodiment, a CVD reactor is used to provide a solar cell. Solar cells also include single junctions, different junctions, or other configurations. In one embodiment, the CVD reactor is configurable to form a wafer that produces about 2.5 watts and is about ι by centimeters (cm) x about 10 cm in size. In one embodiment, the CVD reactor provides a throughput of from about 1 wafer per minute to about 10 wafers per minute. FIG. 1A illustrates an iCVD reactor 10 in accordance with an embodiment of the present invention. Reactor H) & includes reactor cover assembly 20, crystal s carrier track ... gamma carrier traCk) 30, wafer carrier track support 4 〇 and heat lamp assembly 50 » reactor cover assembly 20 may be indium, pin alloy, Stainless steel and quartz are formed. The reactor lid assembly 20 is disposed on the wafer carrier track 3〇. The wafer carrier track 30 can be formed from quartz, molybdenum, cerium oxide (e.g., molten cerium oxide), alumina, or other ceramic materials. The wafer carrier track 3 can be housed in the crystal@carrier track support 40. Wafer carrier track support 16 201034055 Formed from quartz or metal, such as molybdenum, steel alloy, steel, stainless steel, nickel, chromium, iron or alloys thereof. Finally, the heating lamp assembly 50 (which will be matched with the first circle is further described later) is placed on the wafer.

The sundial round carrier rail support is below the 4 inch. The total length of the CVD reactor is from about 18 feet to about when it can be exceeded. 25 suctions, but for various views 1B, 2, 3 and 4, the various views of the embodiment of the cover assembly 20 are explained. Referring to Figure 2, the back-twisting device cover assembly 20 constitutes a rectangular body.

There are side walls 25 extending from the bottom surface of the reaction H-cover assembly 2G and a plurality of convex ar, π. Ϊ 凸起 bulges centered between the side walls 25. Ρ 26 ^ The raised portions 26 extend different lengths from the bottom surface of the top plate along the reactor lid assembly 20. The raised portion 26 is disposed between the side walls 25 to form a gap between the raised portion 26 and the side wall 25. The voids help to couple the reactor lid assembly 20 and the rails 3 (which will be further described later). Side wall 25 and raised portion 26 substantially extend the length of reactor cover assembly 2〇. Reactor cover assembly 20 can be constructed as a single solid structural component or by a plurality of segments coupled together. The raised portions 20 can be of different lengths and numbers to form regions for different CVD process applications. Reactor cover assembly 20 also includes a plurality of raised portions 26 patterns along its length to, for example, develop a multitude of CVD process layouts or platforms. Figure 3 also shows the reactor lid assembly 2〇. As noted above, reactor cover assembly 20 of Figure 3 represents a single segment of the entire roof structure or large roof structure. The figure also shows that a plurality of jaws 21 are disposed through the top surface of the reactor lid assembly 20 and placed centrally along the longitudinal axis of the reactor lid assembly 2〇. The jaws 21 disposed along the top surface of the reactor lid assembly 2 can vary in size, shape, number and location. The mouth 21 can be used as an injection, deposition and 17 201034055 / or discharge vent to transport gas to the CVD reactor 于 ... between two adjacent raised portions 26 (as shown in Figure 2 Injecting, depositing, and/or venting the gas. In one example, the gas is passed to the itch 21 so that the gas is first along the adjacent convex portion % side and then along the bottom surface of the convex portion % to the substrate. Flow. As shown in Figure 3, the side wall 25 encloses the end of the reactor lid assembly 2 to enclose any area and path formed by the jaw 21 and the boss 26 that are delivered to the reactor lid assembly 20. Figure 4 is a top plan view of a reactor cover assembly 2 according to an embodiment, with one or more openings, such as a deposition port 23 disposed through the body 28, a discharge port 22, and an injection port 24 ( The opening is also disposed from the upper surface 29 through the body 28 to the lower surface 27 as shown in Fig. ib. The ports may be provided with a detachable device, a jet head, a discharge device or other gas manifold assembly. Extending over the lower surface 27 of the body 28 to assist in the distribution of gas into and/or out of the CVD The device, in particular, uniformly applies a gas to the wafer below the assembly. In one embodiment, the ports 22, 23, 24 define a circle, a square, a rectangle, or a combination thereof. In one embodiment, the 'jet head The injection hole diameter of the assembly is about 毫米 mm (mm) to about 5 mm, and the injection hole spacing is about imm to about 3 〇 mm. This size range can be exceeded for different applications. Gas manifold assembly and reactor cover assembly 2 It is configured to provide high reactant utilization, meaning that almost 100% of the gas used in the reactor is consumed by the reaction of the CVD process. Figure 19 illustrates a cooling jet head 19 according to the embodiment. 1900 can be incorporated into one or more openings 18 201034055 of the reactor lid assembly 20 'eg, a deposition port 23 . The cooling jet head 1900 has a cooling plate 1902 extending across the upper portion of the cooling jet head 1900 and with at least one gas distribution plate 1904 For thermal communication, each gas distribution plate 1904 includes a plurality of gas vents 1906 for distributing gas or gas therethrough. Cooling the jet head 1900, cooling plate 1902, and distribution The plates 1904 may each contain or be made of steel, stainless steel, aluminum, or other metal. In one example, the cooling jet 1900, the cooling plate 1902, and the sub-φ plate 1904 each contain 316 stainless steel. The thickness of the cooling jet 1900 is about From 20 mm to about 40 mm. Heat is dissipated via the cooling jet head 1900 and produces a temperature gradient across the thickness of the cooling jet head 1900. The cooling jet head 1900 is heated up to about 20 C to about 750 ° C. In one example, the cooling jet head The 19 正面 front surface 1910 is heated to a temperature of about 30 (the temperature of rc (Tl), and the back surface 1912 is cooled to a temperature of about 50 C (Τ2). » In another embodiment, the cooled helium head 19 〇〇 has a plurality of stackable A gas distribution plate 1904, which is bonded together by a braze #layer 1916, constitutes a multi-level distribution or a separate multi-source distribution. The cooling flow 1920 is used to circulate within the cooling plate 1902 and transfer heat away from the front side of the distribution plate 1904 and to the cooling sump (not shown). Water, ethanol solution, ethylene glycol solution, and/or other fluids can be used to transfer heat away from the front side of the cooling jet 19 和 and away from the reactor lid assembly 2 〇. The discharge port 22 and the injection port 24 are used to form a "curtain" or "screen" to assist in avoiding contamination and preventing the gas from being introduced back into the various regions of the CVD reactor. A gas curtain or screen can be used between the front end (inlet) and the back end (outlet) of the 201034055 CVD reactor 10, and (iv) between the various zones within the reactor. In the example, nitrogen or argon is injected into the injection port 24 to remove contaminants in a particular area, such as oxygen, which in turn exits adjacent discharge ports 22. The path and region using the gas curtain or screen and the reactor cover assembly 20 CVD reactor 限制 confines gas isolation to a two-dimensional configuration that protects the various regions and isolates the reactor and external contaminants such as air.

Figures 2, 5, 6, 7, and 8 illustrate various views of an embodiment of a wafer carrier track. The wafer carrier track 3 provides a floating type (ievimi〇n-type) system to float the wafer over the air cushion. (e.g., nitrogen or argon supplied by the air holes 33 of the wafer carrier track 30.) Back to Figure 2, the wafer carrier track 30 is generally a rectangular body having an upper portion 31 and a lower portion 32. The upper portion 31 includes a wafer carrier track. The side surface 35 of the top surface of the crucible extending along the length of the wafer carrier track 30 further constitutes a "guide path" for the wafer to travel through the CVD reactor. The width of the guiding path (such as the distance between the inner sides of the side faces 35) is about 11 〇 mm to 130 mm, the height of the guiding path is about 3 〇 mm to 5 〇 mm, and the length of the guiding path is about 970 mm to i 〇 3 〇 mm ' However, this size range can be exceeded for different applications. The upper portion 31 includes a recessed bottom surface that includes a recessed top surface that, when joined together, forms an air pocket 36 therebetween. The cavitation 36 is used to circulate and distribute the gas injected into the cavitation 36 to the guiding path of the wafer carrier track 30 to create an air cushion. The air pockets 36 disposed along the wafer carrier track 30 can vary in number, size, shape, and location. Both the side 35 and the air pocket 36 substantially extend the length of the wafer carrier track 3〇. 20 201034055 The wafer carrier track 30 can be fabricated as a single solid structural component or by a plurality of segments coupled together. In one embodiment, the wafer carrier track 30 is tilted at an angle such that the inlet is above the exit, allowing the wafer to float below the track by gravity. As described above, the side surface 35 of the wafer carrier can be accommodated in the gap between the boss 26 and the flange member 25 of the reactor cover assembly 20 to enclose the "guide path" along the wafer carrier track 30. And further surrounding the area of the raised portion 26 formed along the wafer carrier track 30. Referring to Figure 5, an embodiment of a wafer carrier track 30 is illustrated. As shown, the wafer carrier track 30 includes a plurality of air holes 33 disposed along the guiding path of the wafer carrier track 3A and between the side faces 35. The air holes 33 are evenly arranged in a plurality of columns (r〇w) along the guiding path of the wafer carrier track 30. The diameter of the air holes 33 is from about 0.2 mm to about 0.1 mm, and the pitch of the air holes 33 is from about 10 mm to about 30 mm. However, this size range can be exceeded for different applications. The vents 33 disposed along the wafer carrier track 30 can vary in number, size & shape and position. In an alternate embodiment, the air vent 33 includes a rectangular slot array or a slit disposed along the guiding path of the wafer carrier track 30. The air holes 33 are in communication with the air pockets 36 below the guiding path of the wafer carrier track 30. The gas supplied to the air pockets 36 is uniformly released through the air holes 33, and an air cushion is formed along the wafer carrier rails 30. The wafer on the guiding path of the wafer carrier track 30 is floated by the gas supplied from below and can be easily transported along the guiding path of the wafer carrier track 3〇. The gap between the floating wafer and the bow guide path of the wafer carrier track 30 is greater than about 〇5, but may vary depending on the application. The floating system reduces the direct drag contact. 201034055 The drag effect caused by the guided path of the wafer carrier track. Further, the port 34 is provided along the side of the side face 35 adjacent to the guiding path of the wafer carrier track 30. The port 34 can be regarded as a discharge means for the gas supplied through the air hole 33. Alternatively, port 34 can be used as ' laterally injecting gas into the center of wafer carrier track 30 to assist in stabilizing & and centering the wafer that is floating along the guiding path of wafer carrier track 30. In an alternate embodiment, the guiding path of the wafer carrier track 30 includes a tapered taPered profile to help stabilize and center the wafer that is floating along the guiding path of the wafer carrier track 30. Figure 6 is a front elevational view of an embodiment of a wafer carrier track 30. As shown, the wafer carrier track 30 includes an upper portion 31 and a lower portion 32. The upper portion 31 includes a side surface 35' which constitutes a "guide path" along the length of the wafer carrier track 3''. The upper portion 31 further includes a side surface 35 which defines a recess 39 at the side of the side surface 35. The recess 39 is adapted to receive the flange member 25 (Fig. 2) of the reactor cover assembly 2' to couple the reactor cover assembly 2 and the wafer carrier/track 3〇 together and enclose the crystal The guiding path of the round carrier track 3〇. Figure 5 also shows that the air vent 33 extends from the guide path of the wafer carrier track % to the air pocket 36. The lower portion 32 serves as a support member for the upper portion 3 i and includes a recessed bottom surface. Injection line 38 is coupled to lower portion 32 such that gas can be injected into cavitation 36 via line 38. Figure 7 is a side elevational view of the wafer carrier track 30 with a single injection line 38 that enters the air pockets 36 along the entire length of the wafer carrier track 30. Alternatively, wafer carrier track 30 includes a plurality of air pockets and a plurality of injection lines 38 along its length. Alternatively, the 'wafer carrier track 3' includes a plurality of sheets 22 201034055 segments, each segment having a single air pocket and a single injection line 38. Still further, the wafer carrier track 30 includes a combination of the above-described air pockets 36 and injection lines 38. Figure 8 is a cross-sectional perspective view of an embodiment of a wafer carrier track 3 having an upper portion 31 and a lower portion 32. The upper portion 31 having the side faces 35, the air holes 33 and the cavitation % is located above the lower portion 32. In this embodiment, the side and lower portions 32 are hollow to substantially reduce the weight of the wafer carrier track 3 and enhance the wafer carrier track 3 relative to the wafer along the wafer carrier track 3. Thermal control. Figure 9 illustrates the reactor cover assembly 2〇 coupled to the wafer carrier track 3〇. A 形 ring is used to seal the interface between the reactor lid assembly 2 and the wafer carrier track 3〇. As shown, the inlet of the CVD reactor 1〇 can be sized to receive wafers of different sizes. In one embodiment, the gap 6 between the raised portion 26 of the reactor cover assembly 2 and the guiding path of the wafer carrier track 30 is used to receive the wafer and is sized to avoid contaminants from either end. The CVD reactor is introduced, the gas between the regions is prevented from diffusing back, and the gas supplied to the wafer during the CVD process is evenly distributed throughout the thickness of the wafer and throughout the wafer. In an embodiment, a gap 60 is formed between the lower surface of the reactor lid assembly 20 and the guiding path of the wafer carrier track 30. In one embodiment, the gap 6 is formed on the lower surface of the gas manifold assembly and on the wafer. Between the guiding paths of the track 3〇. In one embodiment, the gap 6 〇 has a thickness of from about 0.5 mm to about 5 mm and may vary with the length of the reactor cover assembly 20 and the wafer carrier track 30. In one embodiment, the wafer has a length of from about 5 mm to about i5 mm, a width of from about 50 mm to about 23 201034055 15 mm, and a thickness of from about 0 mm to about 5 mm. In one embodiment, the wafer includes a substrate layer having individual strips of layers on the substrate layer. The strip layer is processed in a CVD process. Each strip has a length of about 10 cm (cm) and a width of about 1 cm (but other sizes are also possible), which in this way facilitates removal of the treated strip from the wafer and reduces the processed strip during the CVD process. The stress caused by the band. For different applications, the CVD reactor 10 can be adapted to receive wafers outside the above size range. The CVD reactor 10 can be adapted to provide automatic and continuous wafer supply and exit into and out of the reactor, such as with a conveyor type system. The wafer is transferred from one end of the reactor to the CVD reactor 10, e.g., by a conveyor, using a manual and/or automated system, transported through a CVD process, and removed from the other end of the reactor, e.g., in a retriever. The CVD reactor 10 can be used to fabricate wafers at a rate of from about 1 wafer per 10 minutes to about 1 wafer per 1 second, but can be exceeded for different applications. In one embodiment, CVD reactor 10 can be adapted to produce 6-10 processed wafers per minute. In one embodiment, the wafer is continuously fed into a CVD system or reactor (like CVD reactor 10) and continuously and horizontally moved through a plurality of processing regions within the CVD system. The multilayer layer is grown or formed on each substrate. The composition of each layer is the same as or different from the composition of the layer immediately below. In some embodiments, the wafer passes through the heating zone, the growth zone, and the cooling zone as it passes through the CVD system. In one example, the wafer is passed through the heated zone for about 3 minutes, by the growth zone for about 14 minutes, and then by the cooling zone for about 3 minutes. The deposition zone can be divided into a plurality of sub-areas that are separated by a distance from the isolator 24 201034055, such as a selective gas curtain and a vacuum isolator. In one example, each wafer passes through seven different deposition sub-regions that are separated from one another. The wafer is continuously moved through the sub-areas and spent a predetermined time in each area, for example about 2 minutes. Therefore, a single layer can be deposited on each of the deposition sub-regions onto the wafer.

Figure 10A illustrates another embodiment of a CVD reactor. CVD. Reactor 100 includes reactor body 120, wafer carrier track 130, wafer carrier 140, and heat lamp assembly 15A. The reactor body 12〇 constitutes a moment φ shaped body and may contain molybdenum, quartz, stainless steel or the like. Reactor body 120 encloses the length of wafer carrier track 13 and substantially extended wafer carrier track 130. The wafer carrier track 13〇 also forms a rectangular body and may contain quartz or other low thermal conductivity materials to assist in temperature distribution during processing. The wafer carrier track 13 is configured to provide a floating type system that supplies an air cushion to transport a wafer along the wafer carrier track 13 . As shown, the conduit (e.g., the air pocket 137 having the v-shaped top wall 135) is disposed centrally along the longitudinal axis of the guide path of the dome carrier track 30. The gas is supplied by the gas argon I37 and injected into the pores of the top wall 135 to provide gas enthalpy. The gas rafts floats along the wafer carrier track 13 ,, and the bottom mask corresponds to the V-shaped recess ( Not shown). In one embodiment, the reactor body 12G and the wafer carrier track 13 () are each a single-structural component. In an alternate embodiment, the reactor body m includes a plurality of segments that are joined together to form a complete structural material. In an alternate embodiment, the wafer carrier track 130 includes a plurality of segments that are coupled together to form a complete structural component. FIG. 10A further illustrates a wafer carrier 14〇 adapted to carry a single wafer (not shown) or a wafer strip 16 along the wafer fixture 25 201034055 track 130. The wafer carrier 140 may be graphite or Other similar materials are formed. In one embodiment, the wafer carrier 140 is provided with a v-shaped recess 136 along its bottom surface such that the V-shaped top wall ι:35 β ν-shaped recess 136 of the corresponding wafer carrier track 130 is placed over the top wall 135. Helping to guide the wafer carrier 140 along the wafer carrier track 13A. During the CVD process, the wafer carrier 14 is used to carry the wafer strips 160 to reduce thermal stress on the wafer during processing. The air holes of the top wall 135 of the air pocket % guide the air cushion along the bottom of the wafer carrier 140, which utilizes the corresponding v-shaped feature structure to stabilize and center the wafer carrier 140 and the wafer strip 16 during the CVD process (^ as above As described, the wafer can be placed into strips 160 to facilitate removal of the processed strip from the wafer carrier 14 and to reduce stress generated during the CVD process on the strip. In another embodiment, 10B-10F A wafer carrier 7 is shown for carrying a crystallizer through various processing chambers, including the CVD reactor and other processing chambers for deposition or etching. The wafer carrier 7 has a short # side 71 The long side 73, the upper surface 72, and the lower surface 74. The wafer carrier 70 is depicted as a rectangle 'but it is also square, circular, or other geometric shape. The wafer carrier 70 contains or is formed of graphite or other materials. The wafer carrier 70 usually passes through the CVD reactor with the short side facing forward and the long side 73 facing the side of the cvd reactor. Fig. 10B is a plan view of the wafer carrier 70, wherein the upper surface 72 is provided with three Notch 75. When the wafer is transferred through the CVD reactor: the wafer can be placed in the notch 75 Although the figure shows three notches 75, the upper surface 72 may be provided with more or fewer notches, including no notches. For example, 26 201034055 The upper surface 72 of the wafer carrier 70 is provided with 〇1, 2'3, 4, 5, 6, 7, 8, 9, 1 , 12 or more notches to accommodate the wafer. In some instances, one or more wafers are placed directly in the notch The upper surface 72. The first embodiment is a bottom view of the wafer carrier 7〇 according to the embodiment, wherein the lower surface 74 is provided with a notch 78β after the air cushion is referenced below the wafer carrier 7〇, the notch 78 The floating wafer carrier 70 can be assisted. The gas flow can be directed to the recess 78, which collects gas to form a gas pocket. The lower surface 74 of the wafer carrier 7 can have no recess or a notch 78 (first) 1)c), 2 notches 78 (Fig. 10D-10F), 3 notches 78 (not shown) or above. The notches 78 have straight sides or tapered sides. In one example, the recess 78 has a tapered side such that the side % ratio (slower angle change) side 77 is more oblique or steep. The side 77 of the recess 78 can be tapered to compensate for the span. crystal The circular carrier has a thermal gradient of 7 。. In another example, the 'notch 78 has a flat side and a tapered side so that the side 76 is straight, the side 77 is tapered; or the side 77 is straight The ft side 76 is tapered. Alternatively, the notches 78 are all straight sides, so the sides 76, 77 are straight. In another embodiment, the 10D_10F囷 is the bottom view of the wafer carrier 7〇. 'There are two notches 78 on the lower surface 74. After the air cushion is referenced below the wafer carrier 70, the two notches 78 can assist in floating the wafer carrier 7〇. The gas stream can be directed to a notch 78 which collects gas to form an air cushion. Notch ? 8 has a flat side or a tapered side. In one example, the notches 78 are all straight sides as shown in Fig. 1E, so the sides 76, 77 are straight, such as a plane perpendicular to the lower surface 74. In another example, as shown in FIG. 10F, FIG. 27, 201034055, the notches 78 are all tapered sides, so the side 76 is oblique or steeper than the side 77 where the angle of change is slower. The side edges 77 in the recesses 78 can be tapered to compensate for thermal gradients across the wafer carrier 70. Alternatively, the recess 78 has a combination of a flat side and a tapered side so that the side 76 is straight and the side 77 is tapered; or the side 77 is straight and the side 76 is tapered. • Wafer carrier 70 contains heat flux extending from lower surface 74 to upper surface 72 and any wafer placed thereon. The heat flux can be controlled by the internal pressure and length of the processing system. The profile of the wafer carrier 70 can be tapered to compensate for heat losses from other sources. At the time of processing, heat disappears through the edges of the wafer carrier 70, such as the short side 71 and the long side 73. However, by shortening the guiding path gap in the floating device, more heat flux is introduced into the edge of the wafer carrier 70 to compensate for heat loss. Figure 10A also illustrates the reactor body 120 disposed on the heater lamp assembly 150. The heat lamp assembly 150 is configured to control the temperature distribution within the CVD reactor by increasing and decreasing the temperature of the reactor body 12, the wafer carrier track 130, and particularly the wafer along the length of the cvd reactor. The heater lamp assembly 150 includes a plurality of heater lamps disposed along the length of the wafer carrier. In one embodiment, the heater lamp assembly 15 includes a heat lamp disposed along the length of the wafer carrier track 130 and individually controlled. In an alternate embodiment, the heater lamp assembly 15 includes a set of sand (10)" heat lamps that are movable and follow the wafer along the wafer carrier track 13. Embodiments of the heater lamp assembly 150 can also be used as described above I圏's heater lamp assembly 50. In an alternative embodiment, other types of heating assemblies (not shown) may be used to replace the heater lamp assembly 150 to heat the reactor body 12A. In one embodiment, the heating assembly A resistive heating element, such as a resistive heater, is included, which can be individually controlled along the length of the wafer carrier track 。3 。. In one example, a resistive heating element is bonded or coated to the reactor body 12, . The circular carrier track 130 or wafer carrier 140. In an alternate embodiment, the other type of heating element used to heat the reactor body 120 is an inductive heating element, such as an RF power source (not shown). The components are coupled to the reactor body 120, the wafer carrier track i3, and/or the wafer® carrier U0. The various heating assembly embodiments (including the heat lamp assemblies 50, 150) can be used alone or in conjunction with a CVD reactor. In one embodiment, the 'heat lamp assembly 〇5〇 can be configured to heat the wafer in the Cvd reactor from about 300 ° C to about 800 ° C. In one embodiment, the BB circle is introduced into the deposition of the CVD reactor. Before the zone, the heater lamp assembly 15A can be configured to raise the temperature of the two wafers to a suitable process temperature. In one embodiment, the 'heat lamp assembly 150 can be configured with the CVD reactor to introduce the crystal φ circle into the CVD reactor. Before the deposition area, the wafer temperature is about 300 ° C to about 800 t. In one embodiment, before the wafer enters one or more deposition regions of the CVD reactor, the wafer is heated to a process temperature range _, To facilitate the deposition process, and when the wafer passes through one or more deposition areas, the wafer temperature is maintained within the process temperature range. When the wafer moves along the wafer carrier track, the wafer is heated and maintained at the process temperature range. The center-to-edge temperature difference of the wafer is within 1 〇t. In some embodiments, a method of forming a multilayer material during a continuous CVD process is proposed, which includes continuously moving or advancing a plurality of wafers through a sink 29 201034055 product system The deposition system includes a first deposition region, a second deposition region first/child region, and a fourth deposition region. In some configurations, the system has a fifth deposition region, a sixth deposition region, an additional deposition region, and , , , region, cooling region, and other processing regions. The method further proposes depositing - the first material layer to the first wafer in the first deposition region to move or advance the first wafer to the second deposition region, and The second wafer moves or advances to the first deposition region, and then deposits the second material layer onto the first wafer in the second deposition φ region while simultaneously depositing the first material layer onto the second wafer in the first deposition region A second layer of material is deposited on the first layer of material of each wafer. The method is longer: moving or advancing the first wafer to the third deposition area, moving or advancing the second wafer to the second deposition area, and moving or otherwise advancing the third wafer to the first deposition area, and then Depositing a third material layer onto the first wafer in the first/intervening region while depositing the second material layer onto the second wafer in the second deposition region, and simultaneously depositing the first material layer 至 to the first On the third wafer in the deposition area. The method further proposes moving or advancing the first wafer to the fourth deposition region, moving or advancing the second wafer to the third deposition region, moving or expanding the third wafer to the second deposition region, and making the fourth The wafer is moved or advanced to the first deposition region, and then the fourth material layer is deposited onto the first wafer in the fourth deposition region while depositing the third material layer to the second wafer in the third deposition region, and A second material layer is simultaneously deposited onto the third wafer in the second deposition region, and the first material layer is simultaneously deposited onto the fourth wafer in the first deposition region. 30 201034055 In some embodiments, the method further proposes depositing a fifth material layer onto the first wafer in the fifth deposition region while depositing the fourth material layer to the second wafer in the fourth deposition region, and simultaneously Depositing a third material layer onto a third wafer in the third deposition region, and simultaneously depositing a second material layer onto the fourth wafer in the second deposition region and simultaneously depositing the first material layer to On a fifth wafer in a deposition area. In the proposed example, the wafer or substrate is advanced horizontally in the same direction while passing through multiple deposition regions within the deposition system at the same relative velocity. In some examples, the 'first material layer, the second material layer, the third material layer, and the fourth material layer have the same composition. In other examples, the first material layer, the second material layer, the third material layer, and the fourth material layer each have a different composition. In many instances, the first material layer, the second material layer, the third material layer, and the fourth material layer each contain a quinonic (e.g., koning or aluminum gallium arsenide). The method further proposes to heat the respective wafers to a predetermined temperature in the heating region t before advancing to the first deposition region. The predetermined temperature may be from about 5 passages to about 75 °C, preferably from about hhtc to about 35 passages. In some cases, the wafers are heated to a temperature of about 2 minutes to about 6 minutes, or about 3 minutes to about 5 minutes. The method also proposes transferring the individual wafers to the cooling zone after depositing the fourth material layer. Subsequently, the wafer is cooled to a predetermined temperature in the cooling zone. The predetermined temperature can range from about a fortune to about a ride. In some embodiments, each crystal I is cooled to a predetermined temperature for from about 2 minutes to about 6 minutes, or from about 3 minutes to about 5 minutes. In other embodiments, the wafer passes through the cooling zone after the wafer enters the first deposition zone before the wafer 31 201034055 passes through the heating zone & and exits the fourth deposition zone. The heating zone, the first, second, third and fourth deposition zones, and the cold zone all share a common linear path. The wafers can be continuously and horizontally advanced along a common linear path within the deposition system. In one embodiment, a method of forming a multilayer material during a continuous CVD process is proposed 'which includes continuously advancing a plurality of wafers through a deposition system, wherein the deposition system has a first deposition region, a second deposition region, a third m deposition region, and The fourth deposition area. The method further proposes depositing a buffer layer onto the first wafer in the first region, depositing the sacrificial layer onto the first wafer in the second deposition region, and depositing the buffer layer to the BB circle in the first deposition region. The $* method further proposes depositing a passivation layer onto the first wafer in the third deposition region to simultaneously deposit a sacrificial layer onto the first circle in the second deposition region, and simultaneously depositing the buffer layer into the first deposition region. On the third wafer. The method further proposes depositing the active layer of the gallium arsenide onto the first wafer in the fourth deposition region while depositing the passivation layer onto the second wafer in the third deposition region and simultaneously depositing the sacrificial layer to the second deposition region On the third wafer inside and simultaneously depositing the buffer layer onto the fourth wafer in the first deposition region. In many instances, the wafer is a Kunlunium wafer. The 纟- some implementations method proposes depositing a gallium-containing layer onto the first wafer in the fifth deposition region, while depositing the gallium active layer to the second wafer in the fourth deposition region and simultaneously depositing passivation The layer is on the third wafer in the third deposition region and simultaneously deposits the sacrificial layer onto the fourth wafer in the second deposition region and simultaneously deposits the buffer layer onto the fifth wafer in the first deposition region. In some examples, the gallium-containing layer contains a deified scale. 32 201034055 In some embodiments, the method further proposes heating the individual wafers in the heating zone for a predetermined temperature before the wafer advances to the first deposition zone. The predetermined temperature can be about 50. (: to about 750 ° C, preferably about l〇〇t to about 35 〇r. In other embodiments, the method further proposes to transfer the wafer to the cooling region after depositing the active layer of gallium arsenide. Subsequently, The wafer is cooled in the cooling zone to a temperature of about 18 ° C to about 30 ° (.).

In other embodiments, the wafer passes through the heated region before the wafer enters the first deposition region, and the wafer passes through the cooling region after exiting the fourth deposition region. The heating zone, the first, second, third and fourth deposition zones, and the cooling zone all share a common linear path. Depending on the situation, additional deposition areas (such as fifth, sixth, seventh or above) also share a common linear method to know that the circle can continue continuously and horizontally along a common linear path within the deposition system. In other embodiments, the method further contemplates flowing at least one gas between the deposition zones to form a gas curtain therebetween. In some embodiments, the gas curtain or screen contains or consists of at least one gas, such as hydrogen, arsine, a mixture of hydrogen and helium, nitrogen, argon, or combinations thereof. In many instances, hydrogen and A mixture of crucibles is used to form a gas curtain or screen. In another embodiment, a method of forming a multilayer material during a continuous CVD process is proposed 'which includes continuously advancing a plurality of wafers through a deposition system, wherein the deposition system has a heating region, a first deposition region, a second deposition region, and a third a deposition zone, a fourth deposition zone, and a cooling zone. The method further deposits a gallium antimonide buffer layer onto the first wafer in the first deposition region, and then deposits a sacrificial aluminum arsenide layer onto the first wafer in the second deposition region to simultaneously deposit a gallium arsenide buffer. The layer is on the second wafer in the first deposition area. The method further proposes depositing an aluminum gallium arsenide passivation layer onto the first wafer in the third deposition region, and depositing a sacrificial layer of Kunming Ming onto the second wafer in the second region, and simultaneously depositing a deified marriage The buffer layer is on the third wafer in the first deposition area. The method further proposes depositing a gallium antimonide active layer onto the first wafer in the fourth deposition region to simultaneously deposit a degenerate gallium passivation layer onto the second wafer in the third deposition region, and simultaneously depositing an aluminum arsenide sacrifice. The layer is on the third wafer in the second deposition region, and at the same time, the implantation buffer is spread over the fourth wafer in the first deposition region. Figures 11-17 illustrate different CVD process configurations that can be used with the CVD reactor. 11 illustrates a first configuration 200 having an inlet isolator assembly 220, a first isolator assembly 23A, a second isolator assembly 240, a third isolator assembly 250, and an outlet isolator assembly 26A. A plurality of deposition zones 290 are disposed along the wafer carrier track of the CVD reactor, # and surrounded by the isolator assembly. One or more discharge means 225 are provided between each isolator assembly for removing any gas supplied to the wafers located in each isolator assembly or deposition area. As shown, the precursor gas is injected at the inlet isolator assembly 220, which follows a two-dimensional flow path, e.g., down to the wafer, and then along the length of the wafer carrier track (e.g., flow path 210). The gas is then discharged upwardly through the discharge means 225. The discharge means 225 can be provided on each side of the isolator assembly 22. The gas is directed to the inlet isolator assembly 220, and the money travels along the length of the wafer carrier track (e.g., flow path 215) to prevent contaminants from entering the inlet of the CVD reactor. The gas injected into the 34 201034055 intermediate isolator assembly (e.g., isolator assembly 230) or deposition zone 290 can travel upstream of the wafer flow (e.g., flow path 21 9). The use of adjacent exhaust devices to receive the diffused gas back' avoids contamination and gas mixing between the regions of the wafer carrier track along the CVD reactor. In addition,

Varying the gas flow rate through the isolator assembly (e.g., along the flow path 210) in the direction of wafer flow also further prevents back-diverging gases from entering the isolation region. The laminar flow along the flow path 210 can flow at different flow rates to encounter gas diffusing back, for example, at the confluence 217 below the discharge device 225, thereby preventing gas diffusing back from the isolator assembly 230 from entering the isolator assembly 220. The isolated area that is constructed. In one embodiment, the wafer is heated to a process temperature range before the wafer travels along the wafer carrier track into the deposition zone 290. As the wafer travels along the wafer carrier track through the deposition zone 290, the wafer temperature remains within the process temperature range. After the wafer travels along the remainder of the wafer carrier track leaving the plasmon region 290, the wafer is cooled to a specific temperature range. Changing the length of the isolation and deposition areas reduces the effect of gas diffusion back. In an embodiment, the length of the isolation region is from about 1 meter to about 2 meters, although this range can be exceeded for different applications. It is also possible to vary the flow rate of the gas injected by the isolator to reduce the effect of gas diffusion back. In an embodiment, the population isolator assembly 220 and the outlet isolator assembly 260 supply approximately 30 liters of precursor gas per first gong of the master knife clock 'first isolator assembly 23 〇, cargo 0 second isolator assembly The 240 and third isolator assemblies 250 are formed into a bifurcated plate, supplying approximately 3 liters of precursor gas per clock. The precursor gas supplied in the embodiment </ RTI> and the outlet isolator assembly 35 201034055 260 includes nitrogen. The precursor gases supplied by the first separator set #230, the second separator assembly 24A, and the third isolator assembly 250 in the embodiment include swelling. In one embodiment, the dispenser assembly supplies a total of about 6 liters of air per minute. In the _ real: example, the three isolator assemblies supply a total of about 9 liters of helium per minute. The reference can also change the gap between the isolation regions (such as the thickness of the guide path of the wafer carrier track and the raised portion of the reactor cover assembly, or the space thickness of the crystal CVD reactor) to reduce the diffusion of gas back. In one embodiment, the isolator gap is from about 1 mm to about 5 mm. Figure 8 depicts several flow path configurations 900 provided by the CVD reactor. Flow path configuration 900 is used to inject gas through one or more isolator assemblies, inject gas into the deposition zone, and/or exit the gas of the isolation zone and/or deposition zone. The dual flow path configuration 91〇 displays the gas in the same direction as the wafer flow path and in the opposite direction to the wafer flow path. In addition, because the flow area 911 is wider, a larger flow rate is directed through the dual flow path configuration 910. The wider flow area 911 can be adapted to the other embodiments described. A single flow path configuration 92 〇 shows that the gas is directed in the same direction as it is in the same or opposite direction as the wafer flow path. In addition, because the flow region 921 is narrower, there is a small flow path through the single flow path configuration 920. The narrower flow region 921 can be adapted for use with the other embodiments. The venting flow path configuration 930 shows that gas is vented from adjacent regions through a wider flow region 93 1, such as an adjacent isolation region, an adjacent deposition region, or an isolation region adjacent to the deposition region. In an embodiment, the first drain/injector flow path configuration 940 shows that the dual flow path configuration 941 has a narrow flow region 943 between the discharge flow path 944 and the single injection flow path 945. The figure also shows a narrower gap portion 942 along which the wafer travels through the I CVD reactor. As described above, the gap portion 942 can be varied along the wafer carrier track of the reactor, thereby allowing the gas to be directly and evenly injected into the wafer surface. The narrower gap portion 942 can be used to provide complete or near complete consumption of gas injected into the wafer as the deposition region undergoes a reaction. Additionally, the gap portion 942 can be used to assist in thermal control during the isolation and/or deposition process. When gas is injected into the wafer, the gas injected into the narrower gap portion 942 can maintain a higher temperature. In an embodiment, the first drain/injector flow path configuration 9 5 〇 provides a first discharge flow path 954 having a wide flow region, a first dual flow path configuration 951 having a narrow gap portion 952 and a flow region 953, and a width a first single injection flow path 955 of the flow region, a plurality of single injection flow paths 956 having a narrow flow region and a wide gap portion, a second discharge flow path 957 having a wide flow region φ domain, a narrow gap portion 959 and a flow region A second dual flow path configuration 958, and a second single injection flow path 960 having a wide flow region and a gap portion. In one embodiment, gas is injected through the isolator assembly in the same direction as the wafer flow path. In an alternate embodiment, gas is injected through the isolator assembly in a direction opposite the flow path of the wafer. In an alternate embodiment, the gas is injected through the isolator assembly in the same and opposite directions as the wafer flow path. In an alternate embodiment, the isolator assembly depends on its position in the CVD reactor to direct the gas in different directions. In the actual package example, the gas is directed into the deposition zone in the same direction as the wafer flow path. In an alternate embodiment, the gas boat is directed into the deposition zone in a direction opposite the flow path of the wafer. In an alternate embodiment, &apos;α directs the gas into the /gile region in the same and opposite directions as the wafer flow path. In an alternate embodiment, the gas is directed in different directions depending on the location of the deposition zone of the reactor. φ Figure 12 shows the second configuration 300 green. Wafer 310 introduces the inlet of the CVD reactor and travels along the wafer carrier track of the reactor. The reactor cover assembly 320 provides a plurality of gas barriers 35 设 disposed between the inlet and outlet of the reactor and the deposition zones 340, 380, 390 to avoid contamination and gas mixing between the deposition zone and the isolation zone. The gas isolation curtain and deposition zone may be provided by one or more gas manifold assemblies of the reactor lid assembly 32. The deposition area includes an aluminum arsenide deposition region 34 〇, a gallium arsenide deposition region 380, and a gallium arsenide deposition region 39 〇, which constitute a 多层 multilayer epitaxial deposition process and structure. As the wafer 310 travels along the reactor bottom 330 (which typically includes the wafer carrier track and the heat lamp assembly), the wafer 310 is at the reactor inlet and outlet before entering and exiting the deposition regions 340, 380, 390. After experiencing a temperature ramp of 36 〇 and gradually increasing and lowering the wafer temperature 'to reduce the thermal stress on the wafer 31 〇. Before the wafer enters the deposition areas 340, 380, and 390, the wafer is heated to a process temperature range to facilitate the deposition process. As the wafer 31 passes through the deposition regions 340, 380, 390, the wafer temperature is maintained within the thermal region 37" to facilitate the deposition process. Wafer 310 can be placed on the transport system to continuously feed and receive wafers into and out of the CVD reactor at 38 201034055. FIG. 13 illustrates a third configuration 400. The CVD reactor can be configured to supply nitrogen 410 to the reactor to float the wafer at the inlet and outlet along the wafer carrier track of the reactor. The hydrogen/helium mixture 420 can also be used to float the wafer between the outlet and the inlet along the wafer carrier track of the CVD reactor. The platform of the third configuration 400 can be provided by one or more gas manifold assemblies of the reactor lid assembly. The platform along the wafer carrier track includes an inlet nitrogen isolation region 415, a preheating discharge region 425, a hydrogen/helium mixture preheat isolation region 430, a gallium arsenide deposition region 435, a gallium arsenide discharge region 440, and an aluminum gallium arsenide deposition. A region 445, a gallium arsenide N-layer deposition region 450, a gallium arsenide P-layer deposition region 455, an arsine phosphorous-hydrogen isolation region 460, a first aluminophosphorus aluminide deposition region 465, and a phosphorous-aluminum gallium halide discharge region 470 A second aluminum arsenide aluminum gallium deposition region 475, a hydrogen/helium mixture cooling isolation region 480, a cooling discharge region 485, and an outlet nitrogen isolation region 490. When the wafer travels along the bottom of the reactor (which typically includes the wafer carrier track and the heat lamp assembly), the wafer is at the reactor inlet and before entering and leaving the deposition areas 435, 445, 450, 455, 465, 475 The exit undergoes one or more temperature ramps 411 to gradually increase and decrease the wafer temperature to reduce thermal stress on the wafer. Before the wafer enters the deposition area 435, 445, 450, 455, 465, 475, the wafer heating system is heated to the process temperature range to facilitate the deposition process. As the wafer passes through deposition areas 435, 445, 450, 455, 465, 475, the wafer temperature is maintained within thermal region 412 to facilitate the deposition process. As shown, the wafer temperature traveling through the third configuration 400 will rise when passing through the inlet isolation region 415, 39 201034055, and will remain unchanged through the regions 430, 435, 440, 445, 450, 455, 465, 470, 475. The change, near the hydrogen/helium mixture, cools the isolation region 480 and decreases as it travels along the rest of the wafer carrier track. Figure 14 shows a fourth configuration 5〇〇. The cVE&gt; reactor can be configured to supply • nitrogen 510 to the reactor&apos; to float the wafer at the inlet and outlet along the wafer carrier track of the reactor. The hydrogen/helium mixture 520 can also be used to float ❹ a曰 between the outlet and the inlet along the wafer carrier track of the CVD reactor. The platform of the fourth configuration 5〇〇 can be provided by one or more gas manifold assemblies of the reactor lid assembly. The platform along the wafer carrier track includes an inlet nitrogen isolation region 515, a preheating discharge region 525, a hydrogen/helium mixture preheat isolation region 530, a discharge region 535, a deposition region 540, a discharge region 545, and a hydrogen/helium mixture cooling isolation region. 550. Cooling Discharge Area 555 and Outlet Nitrogen Isolation Area 560. In one embodiment, deposition area 540 includes an oscillating jet head assembly. As the wafer travels along the bottom of the reactor (which typically includes the wafer carrier track and the heat lamp assembly), the wafer undergoes temperature ramps 5, 513 at the reactor inlet and outlet before entering and exiting the deposition zone 540. Gradually increase and lower the wafer temperature' to reduce thermal stress on the wafer. Before the wafer enters the deposition zone 540, the wafer is heated to a process temperature range to facilitate the deposition process. In one embodiment, when the wafer travels through temperature ramp 511, the wafer is heated and/or cooled to a first temperature range. In one embodiment, the wafer is heated through the temperature ramp 513 and the wafer is heated and/or cooled to a second temperature range. The first temperature range can be greater than, less than, and/or equal to the second temperature range. As the wafer passes through the deposition region 540, the wafer temperature remains in 201034055 within the thermal region 512 to facilitate the deposition process. The wafer temperature traveling through the fourth configuration 500 as shown increases as it passes through the inlet isolation region 515, remains unchanged through the deposition region 54, is close to the hydrogen/gas. The mixture cools the isolation region 550 and along the wafer. The rest of the track will fall as it travels. Figure I5 depicts a fifth configuration 6 〇〇e CVD reactor configurable to supply nitrogen 610 to the reactor to float the wafer at the % inlet and outlet along the wafer carrier track of the reactor. The hydrogen/helium mixture 620 can also be used to float the wafer between the outlet and the inlet along the wafer carrier track of the CVD reactor. The platform of the fifth configuration 600 can be provided by one or more gas manifold assemblies of the reactor lid assembly. The platform along the wafer carrier track includes an inlet nitrogen isolation region 615, a preheating discharge and flow balance current limiting region 625, an active hydrogen/helium mixture isolation region 63, a kung gallium deposition region 635, and an aluminum gallium arsenide deposition region 64. A germanium, a gallium arsenide N_ layer deposition region, a gallium arsenide p-layer deposition region 650, a gallium arsenide deposition region 655, a cold-view discharge region 660, and an outlet nitrogen isolation region 665. The wafer undergoes at the reactor inlet and outlet before entering and leaving the deposition areas 635, 640, 645, 650, 655 as the wafer travels along the bottom of the reactor, which typically includes the wafer carrier track and the heat lamp assembly. One or more temperature ramps 611 gradually increase and decrease the wafer temperature to reduce thermal stress on the wafer. Before the wafer enters the deposition area 635, 640, 645, 65 〇, 655, the wafer is heated to the process temperature to promote the deposition process. As the wafer passes through the deposition regions 635, 64, 645, 650, 655, the wafer temperature is maintained within the thermal region 612 to facilitate the deposition process. As indicated by the circle '201034055, the wafer temperature traveling through the fifth configuration 600 will rise as it passes through the inlet isolation region 615 and near the active hydrogen/germanium mixture isolation region 630, and will remain when passing through the regions 635, 640, 645, 650, 655 It does not change, approaches the cooling discharge area 660, and descends as it travels along the rest of the wafer carrier track. FIG. 16 illustrates a sixth configuration 700. The CVD reactor can be configured to supply nitrogen 710 to the reactor to float the wafer at the inlet and outlet along the wafer carrier track of the reactor. The hydrogen/helium mixture 720 can also be used to float the wafer between the outlet and the inlet along the wafer carrier track of the CVD reactor. The platform of the sixth configuration 700 can be provided by one or more gas manifold assemblies of the reactor lid assembly. The platform along the wafer carrier track includes an inlet gas isolation region 715, a preheating and flow balance current limiting region 725, a gallium arsenide deposition region 730, an aluminum gallium arsenide deposition region 735, and a gallium antimonide N-layer deposition region. 740, a gallium arsenide ρ layer deposition region 745, a gallium arsenide deposition region 750, a cooling discharge and flow balance current limiting region 755, and an outlet nitrogen isolation region 76 (μ when the wafer is along the bottom of the reactor (which typically includes As the wafer carrier track and heater lamp assembly travels, the wafer undergoes one or more temperature ramps 711 at the reactor inlet and outlet before entering and exiting the deposition zones 730, 735, 740, 745, 750. And lowering the wafer temperature to reduce the thermal stress on the wafer. Before the wafer enters the deposition area 730, 735, 740, 745, 75, the wafer is heated to the process temperature range to facilitate the deposition process. When the deposition regions 730, 735, 74G, 745, 75G are deposited, the temperature of the crystal g is maintained in the thermal region 712 to facilitate the deposition process. As shown in the figure, the wafer temperature through the sixth 42 201034055 configuration 700 passes through the inlet isolation region. 715 and will rise as it approaches the Kunming gallium deposition area 730, will remain unchanged through the deposition areas 73〇, 735, 740, 745, 750, approach the cooling discharge area 755 and travel along the rest of the aa round vehicle track decline.

Figure 17 Green shows a seventh configuration 80 〇 eCVD reactor configurable to supply nitrogen 810 to the reactor to float the wafer at the inlet and outlet along the wafer carrier track of the reactor. The hydrogen/helium mixture 82〇 can also be used to float the wafer between the outlet and the inlet along the wafer carrier track of the CVD reactor. The platform of the seventh configuration 800 can be provided by one or more gas manifold assemblies of the reactor cover assembly. "The platform along the wafer carrier track includes an inlet nitrogen isolation region 815, a preheating discharge region 825, a deposition region 83", and a cooling discharge. Region 835 and outlet nitrogen isolation region 84A. In one embodiment, deposition zone 830 includes an oscillating jet head assembly. As the wafer travels along the bottom of the reactor (which typically includes the wafer carrier track and the heat lamp assembly), the wafer undergoes temperature ramps 811, 813 at the reactor inlet and outlet before entering and exiting the deposition zone 83. Gradually increase and lower the wafer temperature to reduce thermal stress on the wafer. Before the wafer enters the deposition area 83〇, the wafer is heated to the process temperature range to facilitate the deposition process. In one embodiment, as the wafer travels through the temperature ramp 8, the wafer is heated and/or cooled to a first temperature range. In one embodiment, as the wafer advances through the temperature ramp 813, the wafer is heated and/or cooled to a second temperature range. The first temperature range can be greater than, less than, and/or equal to the second temperature range. As the wafer passes through the deposition area 83, the wafer temperature is maintained within the thermal region 812 to facilitate the deposition process. As shown, the wafer temperature traveling through the 43 201034055 seventh configuration 800 will rise as it passes through the inlet isolation region 815 and near the deposition region 830, will remain unchanged as it passes through the deposition region 830, approach the cooling discharge region 835, and then exit. The outlet nitrogen isolation zone 840 and the remainder of the wafer carrier track will travel down. In one embodiment, a CVD reactor can be configured to form or deposit high quality gallium arsenide and aluminum gallium arsenide double heterostructures at a deposition rate of about 1 micrometer per minute; configured to form or deposit high quality aluminum arsenide. A laterally overgrowth sacrificial layer; and configured to provide about 6 wafers per minute to about 10 wafers per minute.

In some embodiments, the CVD reactor is configured to generate or deposit material to different sized wafers, such as 4 cm x 4 cm or 10 cm x 10 cm. In one embodiment, the CVD reactor is configured to form a 300 nm gallium arsenide buffer layer. In another embodiment, the CVD reactor is configured to form a 30 nm aluminum gallium arsenide passivation layer. In yet another embodiment, the CVD reactor is configured to form a 10,000 nm gallium arsenide active layer at Φ. In still another embodiment, the CVD reactor is configured to form a 30 nm aluminum gallium arsenide passivation layer. In another embodiment, the CVD reactor is configured to provide a dislocation density of less than ixl 04/cm 2 , 99% Photoluminescence efficiency and photoluminescence lifetime of 250 nanoseconds. In yet another embodiment, the CVD reactor is configured to form an epitaxial lateral epitaxial layer having a deposition thickness of 5 nm ± 0.5 nm, etching choice The property is greater than lx 1〇6, no pinhole, and the etching speed of aluminum arsenide is greater than 0.2 mm/hour. In still another embodiment, the CVD reactor is configured to provide a center to 44 201034055 edge temperature non-uniformity above 30 (TC does not exceed 10 ° C, V-III ratio does not exceed 5) And the maximum temperature is 80 (TC. In an embodiment, the CVD reactor is configured to form a deposited layer' including a 300 nm gallium arsenide buffer layer, a 5 nm aluminum arsine sacrificial layer, and a 10 nm deified window layer (window) Layer), 700 nm and containing 2χ1017 chopped (Si) gallium arsenide active layer '30〇11111 and containing 1乂1019 carbon (〇:), ?+ aluminide gallium layer, and 300nm and containing ΐχΐ〇19 c, P+ gallium arsenide layer. In another embodiment, the CVD reactor is configured to form a deposited layer, including a 300 nm gallium arsenide buffer layer, a 5 nm deuterated aluminum sacrificial layer, and a 1 nm nm gallium indium phosphide window layer. , 700 nm and 2x1017 Si gallium arsenide active layer, 100 nm and C, P-containing gallium arsenide layer, 300 nm and P-containing gallium phosphide indium window layer, 20 nm and ΐχίο20 p+ gallium phosphide indium tunneling The tunnel junction layer, 2〇ηηη and containing ΙχΙΟ2. N+ squamized gallium indium through the interface layer, 30nm arsenide aluminum gallium window layer, 400nm and N gallium phosphide indium active layer, 10 〇 nm and P-containing gallium phosphide indium active layer, 3 〇 nm and P-containing Dehua-Gallium window layer, and 300 nm and P+-containing koning gallium contact layer. Embodiments are generally directed to a floating substrate carrier or support. In one embodiment, a substrate carrier is provided for supporting and carrying at least one substrate or wafer through a reactor, including an upper surface and a lower surface. a substrate carrier body and at least one recessed pocket portion disposed in the lower surface. In another embodiment, the substrate carrier includes a substrate carrier main body having an upper surface and a lower surface, and a substrate disposed in the lower surface At least two recessed pockets. In still another embodiment, the substrate carrier includes a substrate carrier body having an upper surface and a lower surface, a recessed region disposed in the upper surface, and a 45 disposed in the lower surface.

At least two concave pockets. In still another embodiment, the substrate carrier includes a substrate carrier body having an upper surface and a lower surface, a recessed region disposed in the upper surface, and at least two recessed pocket portions disposed in the lower surface, wherein each recess The pocket has a rectangular geometry 'and four side walls that extend perpendicular or substantially perpendicular to the lower surface. In another embodiment, the substrate carrier includes a substrate carrier body having an upper surface and a lower surface, and at least two concave pocket portions disposed in the lower surface, wherein each concave pocket portion has a rectangular geometry and four sidewalls extend Vertical or substantially vertical lower surface. In another embodiment, a substrate carrier for supporting and carrying at least one substrate through a reactor is provided, including a substrate carrier body having an upper surface and a lower surface, and at least one concave pocket portion disposed in the lower surface . The substrate carrier body can have a rectangular geometry, a square geometry, or other geometric shape. In one example, the substrate carrier body has two short sides and two long sides, one short side being the front side of the substrate carrier body and the other short side being the back side of the substrate carrier body. The substrate carrier body contains graphite or consists of graphite. In some examples, the upper surface contains at least one notch region. The recessed area in the upper surface is configured to support the substrate thereon. In other examples, the upper surface has at least two, three, four, eight, twelve or more notch regions. In another example, the upper surface does not contain a recessed area. In still another embodiment, the lower surface is provided with at least a recessed pocket portion configured to receive the air cushion. In one case, the lower surface has -, three or more concave pockets. The pocket portion can have a rectangular geometry, a square geometry or other geometric shape. Each pocket portion typically has 46 201034055 two short sides and two long sides "in one example, the short sides and the long sides are straight" and the short sides and long sides are perpendicular to the lower surface. In another example, at least one of the short sides is tapered toward the first angle, and at least one of the long sides is tapered toward the second angle, the first angle being greater or less than the second angle. In still another example, at least one of the short sides is straight and at least one of the long sides is tapered. • In still another example, at least one of the short sides is tapered and at least one of the long sides is straight. In one embodiment, the 'recess pocket portion has a rectangular geometry and the _ pocket portion is configured to receive an air cushion. The recessed pocket has a tapered side wall that tapers away from the upper surface. In another embodiment, 'a method of floating a substrate on an upper surface of a substrate carrier during a vapor deposition process' includes: exposing a lower surface of the substrate carrier to a gas flow; forming an air cushion under the substrate carrier; and floating processing a substrate carrier within the chamber; and moving the substrate carrier along a path within the processing chamber. In many instances, the action of the substrate carrier along the path and/or the speed of the substrate carrier is controlled by adjusting the flow rate of the gas stream. The air cushion may be formed in at least one of the recessed pockets provided in the lower surface. In some examples, the lower surface is provided with at least two recessed pocket portions. The pocket is configured to receive a gas cushion. The upper surface of the substrate carrier includes at least one recessed area for supporting the substrate. The recessed pocket has a tapered side wall that tapers away from the upper surface of the substrate carrier. In still another embodiment, a method of floating a substrate on a substrate carrier during a vapor deposition process is provided, which includes: exposing a lower surface of the substrate carrier to a gas flow, wherein at least one wafer is disposed on the substrate carrier On the surface, the lower surface is provided with at least one concave pocket portion; under the substrate carrier, a gas 47 201034055 形成 is formed; the substrate carrier in the processing chamber is floated; and the substrate carrier is moved along a path in the processing chamber. a method of floating a substrate during a vapor deposition process, comprising: exposing a lower surface of the substrate carrier to a substrate on a further embodiment, wherein the lower surface is provided with at least a concave σ pocket; Forming a gas pocket under the substrate carrier; floating the substrate carrier within the processing chamber; and moving the substrate carrier along a path within the processing chamber.

In another embodiment, a method of floating a substrate carrying a substrate during a vapor deposition process is proposed, which includes: exposing a lower surface of the substrate carrier to a gas flow, wherein at least n portions of the lower surface are provided; Forming an air cushion underneath; floating the substrate carrier within the processing chamber; and moving the substrate carrier along a path within the processing chamber. Embodiments of the invention are generally directed to CVD reactor systems and methods of use thereof. In one embodiment, a CVD system is proposed that includes a cover assembly&apos; such as a top plate that provides a plurality of raised portions along the longitudinal axis of the top plate. The system includes a track having a guiding path (e.g., a channel) disposed along a longitudinal axis of the track, wherein the channel is adapted to receive a plurality of raised portions of the top plate to form a gap between the plurality of raised portions and the floor of the track. The gap is configured to receive the substrate. The system includes a heating element, such as a heating element, to heat the substrate as it moves along the path of the track. In one embodiment, the track is used to float the substrate along the path of the track. In an embodiment, the system includes a groove 'to support the track. The thickness of the gap is from about 55 mm to about 5 mm, or from about 0.5 mm to about imm. The top plate consists of a pin or quartz, and the track consists of quartz or tantalum. Top 48 201034055 The plate is used to direct gas to the gap and further includes a plurality of ports disposed along the longitudinal axis of the top plate and located between the plurality of raised portions, thereby forming a path between the plurality of raised portions. - or a plurality of mouthpieces adapted to transport and/or discharge gas to the gap between the plurality of raised portions of the top plate and the track floor.

Examples of heating elements include a heating lamp that is lightly attached to the track, a plurality of heating lamps disposed along the track, a heating lamp set that moves along the track as the substrate moves along the track, and a resistive heater coupling coupled to the track. An induction heating source connected to the substrate and/or track. The heating element is operable to maintain a temperature differential across the substrate, wherein the temperature difference is less than 1 (rc) In one embodiment, the CVD system is an atmospheric pressure CVD system. In an embodiment, a CVD system is proposed that includes an inlet isolator, Is operable to prevent contaminants from entering the system from the system inlet; the outlet isolator is operable to prevent contaminants from entering the system from the system outlet;

It is placed between the inlet isolator and the second sink including the abutment inlet isolator, and the interoperable region is mixed. The first deposition area of the middle isolator between the outlet isolators. Intermediate isolation to prevent gas in the first isolator. The system is further zoned and disposed adjacent to each deposition zone deposition zone and second sink. In one embodiment, the inlet isolator is more operable to prevent gas injecting into the first deposition zone from diffusing back, the intermediate isolator being more operable To prevent the gas bubbles injected into the second deposition zone from diffusing back, the outlet separator is more operable to prevent gas injected into the second deposition zone from diffusing back. The isolation region formed by at least one of the separators has a length of from about 1 meter to about 2 meters. A gas such as nitrogen is injected at a first flow rate (e.g., 30 liters per minute) into the inlet isolation 49 201034055 to prevent gas from the first deposition zone from diffusing back. A gas such as helium is injected into the intermediate separator at a first flow rate (e.g., 3 liters per minute) to prevent gas from mixing between the first deposition zone and the second deposition zone. A gas (such as nitrogen) is injected into the outlet isolator at a first flow rate (e.g., 30 liters per minute) to prevent contaminants from entering the system from the system outlet. In one embodiment, the venting device is disposed adjacent each isolator and is operable to vent the gas injected into the isolator. A discharge device may be disposed adjacent to each deposition zone for discharging gas injected into the deposition zone. In one embodiment, a CVD system is proposed that includes a housing, a track surrounded by a housing, wherein the track forms a guiding path (e.g., a channel) adapted to guide the substrate through the CVD system. The system includes a carrier that moves the substrate along a path of the track, wherein the track is operable to float the carrier along the path of the track. The outer casing contains molybdenum, quartz or stainless steel or is formed of molybdenum, quartz or stainless steel. The orbit contains quartz, molybdenum, fused ceria or ceramic or is formed of quartz, molybdenum, fused ceria or ceramic. The carrier is formed of graphite. • In one embodiment, the track includes a plurality of openings and/or conduits disposed along the track floor, each operative to supply a cushion to the channel and the underside of the carrier to lift or float the carrier, and along the track The channel is essentially centered on the vehicle. The catheter is V-shaped and the carrier has a recess (e.g., a V-shape) disposed along its bottom surface. The gas is supplied to the recess of the carrier to substantially lift the carrier on the track surface and the passage along the track to substantially center the carrier. The track is, for example, inclined less than about 20 degrees, less than about 10 degrees, or between about 1 degree and 5 degrees to move and float the substrate from the first end of the channel to the second end of the channel® track and/or housing Includes multiple clips. 50 201034055 In an embodiment, the system includes a conveyor operable to automatically introduce the substrate into the channel, a recycler operable to automatically retrieve the substrate from the channel, and/or a heating element operable to heat the substrate. The heating element is coupled to the housing, the substrate, and/or the track. The carrier carries a substrate strip along the path of the track. • In an embodiment, a track assembly for moving a substrate through a CVD system is proposed, comprising a top section having a ground surface, a side edge supporting member disposed adjacent to the ground (eg, a pair of rails; a pair of rails; And, in turn, constitute a guiding path (such as a channel) to guide the substrate along the ground. The bottom section is coupled to the top section to form one or more chambers therebetween. The top section includes a recessed bottom surface. The bottom section includes a recessed top surface thereby forming a chamber. In one embodiment the 'top section and/or the bottom section are formed of tantalum, quartz, ceria, alumina or ceramic. In one embodiment, the 'top section has a plurality of openings 'way through the ground' to provide fluid communication between the chamber and the passage. The chamber supplies gas Φ 塾 (e.g., nitrogen) to the channel to substantially lift the substrate and carry the substrate along the ground of the top section. The ground, for example, is inclined less than about i 〇, less than about 2 、, or between about 1 and 5 degrees to move and float the substrate from the first end of the channel to the second end of the channel. In one embodiment, the 'top section' has a plurality of openings that are threaded through the pair of rails (near the ground). The gas is supplied by a plurality of openings to physically move the substrate of the passage of the top section. The floor also includes a conical section and/or a conduit for supplying gas, each operative to substantially centrally move the substrate along the passage of the top section. The conduit is V-shaped, and / 51 201034055 or the substrate has a notch (e.g., a v-shape) to receive the condensation disposed along the bottom surface of the substrate and is operable to substantially center the substrate moving along the passage of the top section. In one embodiment the 'track assembly includes a conveyor operable to automatically guide the substrate into the channel and/or a recycler operable to automatically retrieve the substrate from the channel. An injection line is coupled to the bottom section to supply chamber gas via the ground and substantially float the substrate along the ground of the top section. The top section ❹ section further includes recesses adjacent the rails and is operable to receive a reactor cover assembly such as a top plate. The track assembly includes a groove for seating the top section and the bottom section. The grooves are formed of quartz, molybdenum or stainless steel. In one embodiment, a method of forming a multilayer material during a CVD process is proposed, which includes: forming a gallium arsenide buffer layer onto a gallium arsenide substrate; forming a sacrificial layer of the Kunming Ming onto the buffer layer; and forming an aluminum gallium arsenide passivation layer Layer to the sacrificial layer. The method further includes forming an active layer of gallium arsenide (eg, a thickness of about 100 nm) onto the passivation layer. The method further includes forming a gallium arsenide layer to the active layer. The method further includes removing the sacrificial layer to separate the active layer from the substrate. The Kumaning sacrificial layer can be exposed to the etchant, and the epitaxial Hft (off) process separates the gallium arsenide active layer from the substrate. The method further includes forming additional layers of material onto the substrate during the subsequent CVD process. The thickness of the buffer layer is about 3 Å. The thickness of the passivation layer is about 3 Å, and/or the thickness of the sacrificial layer is about 5 nm. In one embodiment, 'the method of forming a multi-layer epitaxial layer onto a substrate using a CVD system' includes: introducing a substrate from a system inlet into a guiding path (eg, a channel) while preventing contaminants from entering the system from the inlet; depositing 52, 201034055 An epitaxial layer is on the substrate while the substrate moves along the system channel; depositing a second epitaxial layer onto the substrate while the substrate moves along the system channel; avoiding gas mixing between the first deposition step and the second deposition step; The substrate of the channel is retrieved from the system outlet while preventing contaminants from entering the system from the outlet. The method further includes: heating the substrate before depositing the first epitaxial layer;

The substrate temperature is maintained when depositing the first and second epitaxial layers onto the substrate; and/or after depositing the second epitaxial layer, the substrate is cooled. The substrate is substantially floating along the system channel. The first epitaxial layer comprises aluminum arsenide and/or the second epitaxial layer comprises gallium arsenide. The method further includes depositing a gallium arsenide layer onto the substrate, and/or heating the substrate up to about 30 (rc to about 8 〇〇t) when depositing the epitaxial layer. The center-to-edge temperature difference of the substrate is 1 ( In one embodiment, a CVD reactor is proposed that includes a cover assembly having a body and a rail having a body and a guiding path disposed along a longitudinal axis of the body

Road component. The body and track assemblies of the L assembly are configured to receive the substrate by transferring the bodies together to form a gap therebetween. The reactor further includes a heating assembly including a plurality of heat lamps disposed along the track assembly and operable to heat the substrate as the substrate moves along the (four) conductive path. The reactor further includes a track assembly support member wherein the track assembly is disposed in the track assembly support. The body of the track assembly houses a cavity extending along the longitudinal axis of the body and a plurality of pockets extending from the air pocket to the upper surface of the guiding path and configured to supply the air cushion along the guiding path. The body of the track assembly contains stone. The body of the lid assembly includes a plurality of configurations to provide a 埠〇 temperature difference to the fluid communication of the guiding path, wherein the temperature difference is less than the heating assembly is operable to maintain the substrate throughout

10° In one embodiment, the CVD 53 201034055 reactor is an atmospheric pressure CVD reactor. In an embodiment, a CVD system is proposed comprising: an inlet isolator operable to prevent contaminants from entering the system from a system inlet; an outlet isolator operable to prevent contaminants from entering the system from the system outlet; An intermediate isolator between the inlet isolator and the outlet isolator. The system further includes a first deposition zone adjacent the inlet isolator and a second deposition zone adjacent the isolation isolator. An intermediate separator is disposed between each deposition zone 以 to prevent gas from mixing between the first deposition zone and the second deposition zone. The gas is injected into the inlet isolator at a first flow rate to prevent the gas in the first deposition zone from diffusing back, and the gas is injected into the intermediate separator at a first flow rate to prevent the gas from mixing between the first deposition zone and the second deposition zone, and/ Or the gas is injected into the outlet isolator at a first flow rate to prevent contaminants from entering the system from the system outlet. A discharge device is disposed adjacent each of the separators and is operable to discharge gas injected by the separator and/or disposed adjacent to each of the deposition regions' and operable to discharge gas injected into the deposition region. In one embodiment, a CVD system is proposed that includes a housing, a track surrounded by the housing, wherein the track includes a substrate path for guiding the substrate through the CVD system and moving the substrate along the guiding path, wherein the track system is Operating to float the substrate carrier along the guiding path. The obstruction includes a plurality of openings operable to supply a guide path air cushion. Air is applied to the bottom surface of the substrate carrier to lift the substrate carrier from the track surface. The track includes a conduit disposed along the guide path and is operable to substantially center the substrate carrier along the guide path of the track. The air cushion is supplied to the bottom surface of the substrate carrier via a conduit to substantially lift the substrate from the carrier track ground. 54 201034055 The track can be tilted to move the substrate from the first end of the guiding path to the second end of the guiding path. f. The system includes a heating assembly including a plurality of heating lamps disposed along the track and operable to heat the substrate as the substrate moves along the guiding path. As with the previous embodiments, CVD reactors, chambers, systems, regions, and derivatives of these reactors can be used in a variety of (: 〇 and / or epitaxial deposition processes to form various materials onto wafers or substrates) In one embodiment, _ a Group ν/ν material containing at least one Group III element (such as boron, aluminum, gallium or indium) and at least one Group V 7C (such as nitrogen, phosphorus, arsenic or antimony) Can be formed or deposited on a wafer. Examples of deposition materials include gallium nitride, indium phosphide, indium gallium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, derivatives thereof, alloys thereof, multilayers thereof, or In some embodiments, the deposition material is a parasitic material. The deposition material or the parasitic material contains one layer, but typically comprises multiple layers. In some examples, the 'epitaxial material comprises a layer with gallium arsenide and aluminum arsenide A layer of gallium. In another example, the epitaxial material comprises a gallium antimonide buffer layer, an aluminum gallium arsenide passivation layer, and an active layer of gallium arsenide. The thickness of the gallium antimonide buffer layer is from about 10 nm to about 500 nm. , for example, about 300 nm; the thickness of the sacrificial layer of Kunming is about 1 nm to about 20 nm. For example, about 5 nm; the thickness of the gallium passivation layer of Kunming is about 1 〇 ηηη to about 50 nm, for example about 30 nm; the thickness of the active layer of gallium arsenide is about 500 nm to about 2000 nm, for example about 10 nm. In some examples The epitaxial material further comprises a second quinned aluminum gallium passivation layer. In one embodiment, the process gas for the CVD reactor, chamber, system, region includes helium, argon, helium, nitrogen, hydrogen or Mixture 55 201034055. In one example, the process gas comprises an arsenic precursor, such as ruthenium. In other embodiments, the first precursor comprises a precursor, a gallium precursor, an indium precursor, or a combination thereof, and The second precursor comprises a nitrogen precursor, a pre-filled precursor, an arsenic precursor, a hafnium precursor or a combination thereof. • In an alternate embodiment, as shown in Figure 20, the CVD system 2000 - contains one after another a plurality of jet heads 2010 arranged in a linear path. The jet heads 2010 can be slid together to produce the effect of a larger jet head 'for example to form a large growth area or a large deposition area. During the deposition process 'multiple Wafer 2002 The wafers 2 can be placed on the wafers 2002. The wafers 2002 can also be placed in a stack pattern to move away from any slits between the individual jet heads 2010. In a process embodiment, the CVD system 2000 can be used in various stacks of jet heads. The 2010 exhaust is 'evented from the discharge ports 2, 14, 2016 to slow the flow rate. The CVD system 2000 can also be vented from the discharge ports 2012, 2018. In another alternative embodiment, as shown in Figure 21 The CVD system 2100 设有 is provided with a heating region 2120, a growth region 2130, and a cooling region 2140 along a linear path. A jet head (not shown) is generally disposed in the growth region 213A. A plurality of wafers 2102 are placed on the disk 2104 of each of the processing regions (e.g., the heating region 212, the growth region 2130, and the cooling region 2140). The disk 2104 includes a raised edge 2106 and forms a "pocket portion" around each set of wafers 21A2, such as a processing region 2110. The processing area 211 is such that the wafer 21 〇 2 is held in a semi-enclosed environment of each processing area. The tray 21〇4 is placed on the platform 21〇8, which is provided with a heater, a cooler and a temperature adjustment system (not shown). Therefore, the stage 2108 can individually control and adjust the temperature of the heating zone 212, the growth zone 213 〇 56 201034055, and the cooling zone 2140. The CVD system 2100 provides a narrow gap isolation that is much narrower than the growth region and reduces the overall flow rate required for backflow isolation. In a process embodiment, the heating zone 2120 and the growth zone 2130 are separated by an isolating discharge port 2Π4 therebetween, and likewise, the growth zone 2130 and the cooling zone 2140 are separated by a *islet discharge port 2 11 6 . Although the present invention has been disclosed in the above embodiments, the scope of the present invention is defined by the scope of the appended claims. quasi. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above-described features of the present invention more apparent and easy to understand, reference may be made to the accompanying embodiments. It is to be understood that the invention is not limited by the scope of the invention, and is intended to be example. 1A is a chemical vapor deposition (CVD) reactor according to an embodiment of the present invention; FIG. 1B is a perspective view of a reactor cover assembly according to an embodiment of the present invention; Side stereopsis of a CVD reactor ISI · circle, 57 201034055 FIG. 3 illustrates a reactor cover assembly of a CVD reactor according to the embodiment; FIG. 4 is a CVD reactor according to another embodiment a top view of the reactor cover assembly; FIG. 5 is a wafer carrier track of the CVD reactor according to the embodiment; FIG. 6 is a front view of the wafer carrier track of the CVD reactor according to the embodiment; 7 is a side view of a wafer carrier track of a CVD reactor according to the embodiment; FIG. 8 is a perspective view of a wafer carrier track of a CVD reactor according to the embodiment; FIG. 9 is a view a reactor cover assembly and a wafer carrier track of the CVD reactor of the embodiment; FIG. 10A illustrates a CVD reactor according to the embodiment; and FIGS. 10B-10C illustrate a floating according to the other embodiment Wafer carrier; Figure 10D-10F shows the basis Another floating wafer carrier of still another embodiment; FIG. 11 illustrates a first layout of a CVD reactor according to the embodiment; and FIG. 12 illustrates a second layout of a CVD reactor according to the embodiment; Figure 13 shows a third cloth 58 201034055 of the CVD reactor according to the embodiment; Figure 14 illustrates a fourth layout of the CVD reactor according to the embodiment; Figure 15 shows the implementation according to the embodiment a fifth layout of a CVD reactor; FIG. 16 illustrates a sixth layout of a CVD reactor according to the embodiment; and FIG. 17 is a seventh layout of a CVD reactor not according to the embodiment. A. Figure 14 shows a flow path configuration of a CVD reactor according to the embodiment; FIG. 19 illustrates a cooling jet head according to the embodiment; and FIG. 20 illustrates an alternative embodiment according to the embodiment. 'A CVD system having a plurality of stacked jet heads; and Figure 21 shows a CVD system having a plurality of processing areas according to the alternative embodiment. [Main component symbol description] 10 Reactor 20 Cover assembly 21-24 Mouth opening 25 Side wall/flange member 26 Raised portion 27, 25 &gt; Surface 28 Main body 30 Track 31 Upper 32 Lower part 59 201034055

33 Air vent 34 Air port 35 Side 36 Air pocket 38 Line 39 Concave 40 Support 50 Heat lamp assembly 60 Clearance 70 Carrier 71 Short side 72, 74 Surface 73 Long side 75, 78; Notch 76, 77 Side 100 Reaction 120 Main body 130 Track 135 Top wall 136 Notch 137 Air pocket 140 Carrier 150 Heat lamp assembly 160 Strip 200 Configuration 210, 215, 219 Flow path 217 Confluence 220, 230, 240, 250, 260 Isolator assembly 225 Discharge device 290 Deposition area 300 Configuration 310 Wafer 320 Cover assembly 330 Bottom 340, 380, 390 Zone 350 Curtain 360 Temperature Ramp 370 Thermal Zone 400 Configuration 410 Nitrogen 411 Temperature Ramp 412 Hot Zone 415, 425, 43 0, 435, 440, 445, 450, 455, 460, 465, 470, 475, 480, 485, 490 Zone 60 201034055 420 Hydrogen/Hydrazine Mixture 500 Configuration 510 Nitrogen 511, 513 Temperature ramp 512 Thermal zone 515, 525, 530, 535, 540, 5 45 , 55 0,555,5 60 Zone 520 Hydrogen/胂 Mixture 600 Configuration 610 Nitrogen 611 Temperature ramp 612 Hot zone 615, 625, 63 0, 63 5,640,645, 65 0,65 5,660,665 Zone 620 Hydrogen/胂 mixture 700 Configuration 711 Temperature ramp 715, 725, 730, 73 5,740,7^ 720 Hydrogen/胂 mixture 800 Configuration 811,813 Temperature ramp 815,825,830,835,840 820 Hydrogen/helium mixture 710 Nitrogen i gas 712 Hot zone 5,750,755,760 Zone 810 Nitrogen 812 Hot zone 900,910,920,93 0,940,941,95 0,951,95 8 Path configuration 911,921,93 1,943,953 Flow area 942,952,959 Clearance 944,945,954-957,960 Flow path 1900 Air head 1902 Cooling plate 1904 Distribution plate 1906 Jet hole 1910 Front 1912 Back 201034055 1916 Hard solder layer 1920 Fluid 2000, 2100 System 2002, 2102 Wafer 2004, 2104 Disk 2010 Jet head 2012,2014,2016,2018,2114,2116 埠口2106 Edge 2108 Platform 2110,2120,2130,2140 Area Τι,Τ2 Temperature

62

Claims (1)

201034055 VII. Patent Application Range: K A method of forming a multilayer material during a continuous chemical vapor deposition process, the method comprising: - continuously advancing a plurality of wafers through a deposition system, wherein the sink system comprises a a first deposition region, a second deposition region, a first &gt; redundant region and a fourth deposition region; depositing a buffer layer to a first wafer φ in the first deposition region; depositing a sacrificial layer Depositing the buffer layer onto a circle in the first deposition region on the first wafer in the second deposition region; ~Βθ depositing a passivation layer to the first in the third deposition region Depositing the sacrificial layer on the second wafer in the second deposition region on the wafer, and simultaneously depositing the buffer layer onto the third wafer in the first deposition region; and % a gallium arsenide active layer onto the first positive circle in the fourth deposition region, simultaneously depositing the passivation layer onto the first wafer in the third deposition region, and simultaneously depositing the sacrificial layer to the second deposition region Of the third wafer, while the buffer layer is deposited onto the wafer in a fourth region of the first deposition. For example, the method described in the scope of the patent application, further includes heating each of the wafers 63 201034055 to a predetermined temperature in a heating zone before advancing to the &quot;&quot;L product area. 3. The method of claim 2, wherein the predetermined temperature is from about 50 ° C to about 75 (TC. ' 4. The method of claim 3, wherein the predetermined temperature is about l 〇〇 ° C to about 350. (: φ 5 · The method of claim 2, further comprising transferring each of the wafers to a cooling zone after depositing the active layer of gallium arsenide 6. The method of claim 5, further comprising cooling each of the wafers in the cooling zone to about 18 〇c to about 3 〇 &lt;&gt; (: one predetermined temperature) ❹ 7. The method of claim 1, wherein the wafers pass through a heating zone before entering the first deposition zone, and the wafers exit the fourth &gt; The method of claim 7, wherein the heating zone, the first deposition zone, the second deposition zone, the third deposition zone and the fourth deposition zone, and the cooling zone Sharing a common linear path 'the wafers along the common within the deposition system The method of claim 1, wherein the method further comprises flowing at least one gas between each of the deposition regions to form a gas between each of the deposition regions. The method of claim 9, wherein the at least one gas comprises hydrogen, helium, a mixture of hydrogen and helium, gas, chlorine, or a combination thereof. The method of claim 10, wherein the at least one gas comprises a mixture of hydrogen and helium. 12. The method of claim 1 is a method of depositing a gallium-containing layer to a fifth. Depositing the active layer of gallium arsenide onto the second wafer in the fourth sinking/small area on the first wafer of the gate in the deposition area, and simultaneously depositing the Passivation layer to the 篦-., 扯 第一 first, on the third wafer in the area of the product and simultaneously deposit the sacrificial layer to the 笫 _ _ 硪 硪 — & & & & & & & & Round and simultaneously deposit the buffer The layer wir丄9 is on a fifth wafer in the first deposition region of the primary child. The gallium-containing layer 13. The method according to claim 12 contains deuterated scale gallium. The method of claim 1, wherein the wafers are 65 201034055, a gallium-plated wafer. 15. A method of forming a multilayer material during a continuous chemical vapor deposition process. The method comprises: making a plurality of wafers Continuously advancing through a deposition system, wherein the deposition system includes a heating region, a first deposition region, a second deposition region, a third deposition region, a fourth deposition region, and a cooling region; Depositing a gallium arsenide buffer layer onto a first wafer in the first deposition region; depositing an sacrificial aluminum arsenide layer on the first wafer in the second deposition region while depositing the gallium arsenide a buffer layer is disposed on a second wafer in the first deposition region; the germanium-aluminum gallium passivation layer is deposited on the second circle in the third deposition region, and the sacrificial aluminum sacrificial layer is deposited Depositing a gallium arsenide buffer layer onto a third wafer in the first deposition region; depositing a gallium arsenide active layer to the fourth deposition On the first wafer in the region, the (4) deposition material is faintly fused (four) to the third deposition region = on the second wafer and simultaneously deposits the kunghuaming sacrificial layer into the first product region Flute=曰兰冲层...=: Simultaneous deposition of the deuteration graft onto a fourth wafer in the first % product area. 16. Forming a multilayer material during a process of a multi-layer process. A method of continuous chemical vapor phase. The method comprises: 66 201034055 continuously advancing a plurality of wafers through a deposition system, wherein the deposition system comprises a first deposition zone, a second deposition region, a third deposition region, and a fourth deposition region; a first material layer to a first crystal* circle in the first deposition region; &gt; a second material layer to Depositing the first material layer onto a winning second wafer in the first deposition region on the first wafer in the second deposition region; and stacking the second material layer to the third deposition region Depositing the second material layer onto the second wafer in the second deposition region simultaneously on the first wafer, and simultaneously depositing the first material layer to a third crystal in the first deposition region Depositing a fourth material layer onto the first wafer in the fourth deposition region while depositing the third material layer onto the second wafer in the third deposition region, and simultaneously depositing the Second material layer to the second On the third wafer zone • art product, while depositing the first material layer onto the wafer in a fourth deposition of the first region. 17. The method of claim 16, wherein the first material layer, the second material layer, the third material layer, and the fourth material layer have the same composition. 18. The method of claim 16, wherein the first material layer, the second material layer, the third material layer, and the fourth material layer 67 201034055 each have a different composition. 19. The method of claim a, wherein each of the first material layer, the second material layer, the third material layer, and the fourth material layer comprises an arsenic. 20. The method of claim 16, further comprising depositing a fifth material layer onto the first wafer in a fifth deposition region while depositing the fourth material layer to the fourth deposition Depositing the third material layer onto the third wafer in the third deposition region on the second wafer in the region, and simultaneously depositing the second material layer into the second deposition region Depositing the first material layer onto a fifth wafer in the first deposition region on the fourth wafer. 21. The method of claim 16, further comprising heating each of the wafers to a predetermined temperature in a heated region before advancing into the first deposition zone. The method of claim 2, wherein the predetermined temperature is from about 50 ° C to about 750 ° C. 23. The method of claim 22, wherein the predetermined temperature is from about 100 °C to about 350 °C. The method of claim 22, wherein each of the wafers is heated to the predetermined temperature for a duration of from about 2 minutes to about 6 minutes. 25. The method of claim 24, wherein the duration is from about 3 minutes to about 5 minutes. 26. The method of claim 16, further comprising transferring each of the wafers into a cooling zone after depositing the fourth material layer. 27. The method of claim 26, further comprising cooling the plurality of wafers to a predetermined temperature in the cooling zone. 28. The method of claim 27, wherein the predetermined temperature is from about 18 ° C to about 3 (TC. 29. The method of claim 27, wherein each of the wafers is Cooling to the predetermined temperature, for a duration of from about 2 minutes to about 6 minutes, wherein the wafers are 30. The method described in claim 29 is about 3 minutes to about 5 minutes. 31. The method 69, 201034055, as described in claim 16 of the patent application, passes through a heating zone before entering the first deposition zone, and the wafers pass through a cooling zone after leaving the fourth deposition zone. The method of claim 31, wherein the heating zone-domain, the first deposition zone, the second deposition zone, the third deposition zone, the fourth deposition zone, and the cooling zone share a a common linear path for the wafers to continually and horizontally traverse along a direction within the deposition system 70