201032304 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板以及包含該封裝基板之晶片 封裝結構，並且特別地，根據本發明之封裝基板上的至少 一測試墊具有凹槽’用以容置探針之端部。 【先前技藝】 ® 隨著半導體技術的進步以及使用者需求的提升，越來越 多電子產品需要使用咼效能晶片作為運算核心。晶片效能的 k升通常也代表輸入晶片或由晶片輸出的訊號數量以及種類 的增加，因此，作為訊號傳輸用的引腳(lead)或導線(wire)之 數量也需要大量增加。 然而，由於多數電子產品本身或其零組件的體積或尺寸 有輕薄化或微型化的趨勢，晶片體積也必須隨之縮小，因此 其外接的引腳或導線也必須更細，並且更緊密地排列。目 ® 前，為了確保晶片與引腳或導線的正常導通，並保護晶片以 防止其因輕撞或拉扯等外力造成損傷，常透過封裝的 來達到前述目的。 既有的晶>1封裝型態包含—彻可撓狀基板作為晶片 承載件的捲帶自動接合封裝(Tape Automated B〇nding)技術， 其包含.捲τ承载封裝(Tape Carrier Package, TCP)、薄膜覆晶 封裝(Chip Qn Fikn，①F)#。賴聽型祕將晶片固定= 承載捲帶上，並以晶片的凸塊或銲墊，與承載捲帶的金屬導 電層對位加壓接合，為目前常見的晶片封裝麟之-，特別 4 201032304 是應用於液晶顯示n之鶴晶$之封裝 之金屬物被鳴_方細化形^== 職複數細m墊(㈣pad)，各⑽之—端與^ ^墊電性連接並向外延伸而分別對應連接該些日測試塾中之 片進至承載捲帶後，吾人通常需對該封裝後之晶 目前最常⑽般綠域制試㈣e 來由包含若干騎咖㈣龍針卡(probe card) 測’探針可依序翻職録面，以摘測該 幻忒墊所連接的引腳之電性是否正常。 ^ ’受限於細微加工的製程條件，探針卡的設計存在 較複=點^如il接觸力太小、位移行程不足、製程步驟 卜，探針卡上的探針也可能因為接觸力太小而 二。效刺穿金屬測試墊表面的氧化層，進而降低測試的可 於先m胁巾，為了解決上述的問題，設計者或操作人 ^主會直接加錄針的下_，然而，這獅方式容易造 ^探針的端部歪曲變形’甚至斷裂，減低了探針的使用壽 p並且增加耗材的成本增加。此外，加重探針的下壓力容 易使探針偏移，並且於測試塾表面刮出微粒，微粒可能導致 引腳或測試塾間產生短路現象，進而造成測試絲的誤差。 【發明内容】 因此，本發明之一範疇在於提供一種封裝基板，並且特 201032304 :地用根？ΐ發明之封裝基板上的至少-測試墊具有凹 3 以谷置探針之端部，以解決前述的問題。/、 片，可ίίΓ之封裝基板:用以承裁-晶 層設置於該可撓性3介胃ϋ m ^:導電 ，腳之一端電性連=== 端。特別地，該複數以 夕一、忒墊之表面具有一凹槽，用以容置—接4f 且，^*於實際應財，前述之凹槽可藉由侧而成。並 亥凹槽可視情況貫穿或不貫穿該測試墊。 成 先前題㈣在於提供—種W封裝結構，以解決 板以Ϊ體Ϊ，、’本發明之晶片封裝結構包含封裝基 以及-導^ 封裝基板包含—可驗介電層 等电層邊導電層设置於該可撓性介雷声t， =複數根引腳以及複數個測試整。該些引腳之l端電性連 片’而_測試墊分別對應連接該些引腳之另-端 測一丄 時，丄當探針的端部進人本發明之測試塾上的凹槽 ϊ墊的移動範圍，降低探針於接觸測 弋，本發明之凹槽也可避免探針從測試 而導致引腳或測試墊間產生短路現象，因 +ΐϊΐί的情形發生。另外，探針於測試時的下壓力 術"，太恭ί低’藉此提升該探針的使用壽命。相較於習知技 程的時^以ίίίίί 反以及晶片封襄結構有助於節省測試製 的守間以及金錢成本，並有效提高測試的可信度。 201032304 所附神可以藉由以下的發明詳述及 【實施方式】 穿社^ 種封裝基板以及包含該_基板之晶片封 裝、、、《構。根據本發明之若干具體實施例係揭露如下。[Technical Field] The present invention relates to a package substrate and a chip package structure including the package substrate, and in particular, at least one test pad on the package substrate according to the present invention has a groove Used to accommodate the end of the probe. [Previous Skills] ® As semiconductor technology advances and user needs increase, more and more electronic products require the use of 咼 performance chips as the core of computing. The k-liter of the chip performance usually also represents an increase in the number and type of signals input to or from the chip. Therefore, the number of leads or wires used for signal transmission also needs to be greatly increased. However, due to the trend of thinning or miniaturization of the size or size of most electronic products or their components, the size of the wafer must also shrink, so the external pins or wires must be thinner and more closely arranged. . Before the target, in order to ensure the normal conduction of the wafer and the leads or wires, and to protect the wafer from external damage caused by light impact or pulling, it is often achieved by the package. The existing crystal > 1 package type includes a Tapered Automated B〇nding technology as a wafer carrier, which includes a Tape Carrier Package (TCP). , Chip Qn Fikn (1F)#. The film is fixed on the carrier tape, and is bonded to the metal conductive layer carrying the tape by the bumps or pads of the wafer, which is the common chip package Lin-, especially 4 201032304 It is applied to the liquid crystal display n of the crane crystal of the package of the metal material is _ _ square refinement ^ = = job complex number of m pad ((four) pad), each (10) - end and ^ ^ pad electrically connected and extended After connecting the chips in the test days to the carrying tapes, we usually need to test the crystals of the package (4) in the green zone. (4) e to include several riding machines (four) dragon needle cards (probe) Card) The test probe can be turned over in order to check whether the pins connected to the phantom pad are normal. ^ 'Restricted by the processing conditions of micro-machining, the design of the probe card is more complex = point ^ such as il contact force is too small, the displacement stroke is insufficient, the process steps, the probe on the probe card may also be due to contact force too Small and two. Effectively pierce the oxide layer on the surface of the metal test pad, thereby reducing the risk of the test. In order to solve the above problems, the designer or the operator will directly add the needle to the _, however, the lion is easy. The end of the probe is distorted and deformed, even breaking, reducing the life of the probe and increasing the cost of consumables. In addition, the downforce of the weighted probe easily deflects the probe and scrapes particles off the surface of the test cymbal, which can cause short circuits between the pins or the test leads, which can cause errors in the test wire. SUMMARY OF THE INVENTION Therefore, one aspect of the present invention is to provide a package substrate, and the special 201032304: ground use? At least the test pad on the package substrate of the invention has a recess 3 to valley the end of the probe to solve the aforementioned problems. /, sheet, 封装 Γ 封装 封装 : : : : : : : : : : : : : : 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶In particular, the plurality of surfaces of the mat has a recess for accommodating - 4f, and the recess is formed by the side. And the groove may or may not penetrate through the test pad. In the previous question (4), a W package structure is provided to solve the problem of the board, and the chip package structure of the present invention comprises a package base and the package substrate comprises: a dielectric layer conductive layer Set in the flexible dielectric thunder t, = a plurality of pins and a plurality of test integers. The one end of the pins is electrically connected to the test piece, and the test pads are respectively connected to the other end of the pins, and the end of the probe is inserted into the groove on the test port of the present invention. The movement range of the mattress and the reduction of the probe to the contact test can also prevent the probe from short-circuiting between the lead or the test pad due to the test, which occurs due to the situation of +ΐϊΐί. In addition, the down-pressure of the probe during testing is too low to increase the life of the probe. Compared with the conventional technology, the use of the structure and the chip sealing structure can save the test system's custodial and monetary costs, and effectively improve the credibility of the test. 201032304 The following is a detailed description of the invention and the embodiments of the invention, and the package substrate and the wafer package including the substrate. Several specific embodiments in accordance with the present invention are disclosed below.
f施一至圖三，圖一繪示根據本發明之-具體 實施例的封裝基板I2之上棚；圖二綠示根據本發明之一 1 體實施例的封裝基板12之立體視圖；而圖三翁示根據本^ 明之一具體實施例的晶片封裝結構丨之立體視圖。如圖所 示，本發明之晶片封裝結構1包含該封裝基板12以及設置 於該封裝基板12上之一晶片1〇。 進一步，如圖一及圖二所示，本發明之封裝基板12包含 一可撓性介電層120以及一導電層122(這裡所繪示的導電 層122已藉由蝕刻或其它適當的方式圖案化形成複數根引 腳1220以及複數個測試墊1222)，且該導電層122設置於 該可撓性介電層120上。此外，於本具體實施例中，該可 撓性介電層120上定義有一晶片接合區12〇〇,該晶片10 可藉由覆晶或其它適當的方式貼附至該晶片接合區1200内。 於實際應用中，該可撓性介電層120之材料可為聚醯亞 胺(Polyimide, ΡΙ)、聚酯類化合物(polyethylene terephthalate, PET)或其它適當的材料。此外，該導電層122之材質可為金 屬材料(例如，但不限於，銅）或其它適當的材料。於實務 中，為了增強封裝基板12對晶片10的散熱效果，可撓性介 電層120可選用具有高導熱係數的材料來製作。 進一步，該些引腳1220自該晶片接合區1200向外延 201032304 =，致使當晶片1G接合至該晶片接合區12⑻時，該些 1220之-端電性連接該晶μ 1〇。此外 些引腳122G之另一端(遠離晶^合區: 且该複數個測試墊1222中之至少一測試墊1222之一 =222a具有一凹槽1222b，用以容置—探針3之一端部 1220=1用中，該凹槽臟可藉由蝕刻方式與引腳 的方^而1㈣—餘巾形成，由其它適當 了1之内徑較 如可較容易對準進人該’使該探針3之該端部 τ ^ 之凹槽1222b的外觀、Μ 3 或金錢成本，前述 參見A 寸型悲4可作適當的調整。請 參 試墊肌之第一 l =且=槽_形成於測 該第-表面1222a進人該凹槽12^姐針3之&部30可自 凹槽mu圖四E所示’於實際應用中，該 試墊1222之第二而]面1222&貫穿該測試墊1222至該測 介電層12G的i觸則处（即該_塾1222斯述可撓性 1222。也就是說，該㈣^ 也可不貫穿該測試墊 層，藉此該探針3之^^ 3 依舊保留有部分導電 1222有良好的電性接觸。° 1 _村麵與該測試整 、f圖四A以及圖四B所示，該凹槽1222b可 201032304 ’絲、方柱狀、三肖減或其它多邊形柱 M。如圖四c所示，該凹槽1222b的直徑自該第一表面 1222a往該第二表面12饮漸縮而呈—倒椎形。因此，該凹槽 1通於該測試塾1222之第一表面m2a上的開口較大^ 於圖f ^以及圖四B所示），即使在一可容許的誤差偏移 二hi木針3之該端部％依舊可以輕易地容置於該凹槽 1222b 内。 ❹ 声.步二如圖四D所示’該凹槽1222b的底部可具有弧 又’ 一口圖四E所不’該凹槽m2b可呈傾斜柱狀·，而如圖四 F所示，該凹槽1222b可呈半圓型。F1 to FIG. 3, FIG. 1 is a perspective view of a package substrate 12 according to an embodiment of the present invention; FIG. 2 is a perspective view of a package substrate 12 according to an embodiment of the present invention; A perspective view of a wafer package structure according to one embodiment of the present invention is shown. As shown in the figure, the chip package structure 1 of the present invention comprises the package substrate 12 and a wafer 1 disposed on the package substrate 12. Further, as shown in FIG. 1 and FIG. 2, the package substrate 12 of the present invention comprises a flexible dielectric layer 120 and a conductive layer 122 (the conductive layer 122 illustrated herein has been patterned by etching or other suitable means). A plurality of pins 1220 and a plurality of test pads 1222 are formed, and the conductive layer 122 is disposed on the flexible dielectric layer 120. In addition, in the present embodiment, the flexible dielectric layer 120 defines a die bond region 12, which can be attached to the die bond region 1200 by flip chip or other suitable means. In practical applications, the material of the flexible dielectric layer 120 may be polyimide (polyimide), polyethylene terephthalate (PET) or other suitable materials. In addition, the conductive layer 122 may be made of a metal material such as, but not limited to, copper or other suitable material. In practice, in order to enhance the heat dissipation effect of the package substrate 12 on the wafer 10, the flexible dielectric layer 120 may be fabricated using a material having a high thermal conductivity. Further, the leads 1220 are extended from the wafer bonding region 1200 to the epitaxial 201032304, so that when the wafer 1G is bonded to the wafer bonding region 12 (8), the terminals of the 1220 are electrically connected to the crystal. The other end of the pin 122G (away from the bonding region: and one of the plurality of test pads 1222=222a has a recess 1222b for receiving one end of the probe 3) When 1220=1 is used, the groove can be formed by etching and the side of the pin and 1(4)-the residual towel, and the inner diameter of the other appropriate one is easier to align into the person. The appearance, Μ 3 or monetary cost of the groove 1222b of the end portion τ ^ of the needle 3, as described above, can be appropriately adjusted according to the A-inch type sorrow 4. Please refer to the first l = and = groove _ formed on the muscle of the pad Measuring the first surface 1222a into the groove 12^ the needle 3 of the & portion 30 can be shown from the groove mu Figure 4E 'in practical applications, the test pad 1222 second] face 1222 & The test pad 1222 is at the i-contact of the dielectric layer 12G (ie, the 可 1222 is flexible 1222. That is, the (4) ^ may not penetrate the test pad, whereby the probe 3 ^^ 3 still retains some of the conductive contacts 1222 have good electrical contact. ° 1 _ village surface and the test, f Figure 4A and Figure 4B, the groove 1222b can be 201032304 'silk, square a shape, a three-dimensional subtraction or other polygonal column M. As shown in Fig. 4c, the diameter of the groove 1222b is tapered from the first surface 1222a to the second surface 12 to form an inverted vertex shape. The opening of the groove 1 on the first surface m2a of the test crucible 1222 is larger (as shown in Fig. f^ and Fig. 4B), even if the end of the end of the dihi-wood needle 3 is offset by an allowable error. It can still be easily accommodated in the groove 1222b. ❹ Sound. Step 2 is as shown in Figure 4D. 'The bottom of the groove 1222b can have an arc and a mouth. Figure 4E does not. The groove m2b can be inclined. Columnar·, as shown in FIG. 4F, the groove 1222b may be semicircular.
請注意，前述之凹槽1222b的設計旨在於 的些微偏差而導致探針之端部無法容置於該凹槽f222b S 差，甚至破躺裝基板(如刮傷表面造成斷線 4無法恢復的破壞）。因此，在這樣的目的下，本發明之凹押 =形態可娜況進行合理的輕，並不受限於前面所舉^ 試墊之封裝基板以及晶片封裝結構上的測 封裝其、f槽谷置測試探針的端部。藉此，本發明之 ===== 挪===== 201032304 上錄具財施狀詳述，鱗難更加、、主接 =發明之特徵與精神，而並非以上述所揭露的較：； 體實=例來對本發明之範，加以限制。相反地，其目的是 希望胃b涵盍各種改變及具相等性的安排於本發明所欲申請 之專利範圍的範疇内。 ❹ ❹ 10 201032304 【圖式簡單說明】 圖一係繪示根據本發明之一具體實施例的封裝基板之上 視圖。 、土 圖二係繪示根據本發明之一具體實施例的封裝美 體視圖。 圖三繪示根據本發明之一具體實施例的晶片封裝結構之 ❿ 立體視圖。 圖四A至圖四F分別繪示根據本發明之測試墊之剖面 圖。 【主要元件符號說明】 1 :晶片封裝結構 12 :封裳基板 1200 :晶片接合區 1220:引腳 1222a :第一表面 1222c :第二表面 30 :探針之端部 10 ·晶片 120 :可撓性介電層 122 :導電層 1222 :測試墊 1222b :凹槽 3 :探針Please note that the above-mentioned groove 1222b is designed to be slightly biased so that the end of the probe cannot be accommodated in the groove f222b S, even the broken substrate (such as the scratched surface causes the broken wire 4 to be unrecoverable). damage). Therefore, under such a purpose, the recessed form of the present invention can be reasonably light, and is not limited to the package substrate of the test pad mentioned above and the package package on the chip package structure. Place the end of the test probe. Therefore, the present invention ===== move ===== 201032304 The detailed description of the financial institution is detailed, the scale is more difficult, the main connection = the characteristics and spirit of the invention, and not the above-mentioned disclosure: The actual example is intended to limit the scope of the invention. On the contrary, it is intended that the various changes and equivalence of the stomach be included in the scope of the patent application to which the present invention is intended. ❹ ❹ 10 201032304 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view of a package substrate in accordance with an embodiment of the present invention. Figure 2 is a view of a packaged body in accordance with an embodiment of the present invention. 3 is a perspective view of a wafer package structure in accordance with an embodiment of the present invention. Figures 4A through 4F are cross-sectional views, respectively, of a test pad in accordance with the present invention. [Description of main component symbols] 1 : Chip package structure 12 : sealing substrate 1200 : wafer bonding region 1220 : pin 1222a : first surface 1222c : second surface 30 : probe end portion 10 · wafer 120 : flexible Dielectric layer 122: conductive layer 1222: test pad 1222b: groove 3: probe