[go: up one dir, main page]

TW201029064A - Plasma processing apparatus and plasma processing method - Google Patents

Plasma processing apparatus and plasma processing method Download PDF

Info

Publication number
TW201029064A
TW201029064A TW098105258A TW98105258A TW201029064A TW 201029064 A TW201029064 A TW 201029064A TW 098105258 A TW098105258 A TW 098105258A TW 98105258 A TW98105258 A TW 98105258A TW 201029064 A TW201029064 A TW 201029064A
Authority
TW
Taiwan
Prior art keywords
wafer
film
processing
metal
processing chamber
Prior art date
Application number
TW098105258A
Other languages
Chinese (zh)
Other versions
TWI442468B (en
Inventor
Masahiro Sumiya
Motohiro Tanaka
Kosa Hirota
Original Assignee
Hitachi High Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi High Tech Corp filed Critical Hitachi High Tech Corp
Publication of TW201029064A publication Critical patent/TW201029064A/en
Application granted granted Critical
Publication of TWI442468B publication Critical patent/TWI442468B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32935—Monitoring and controlling tubes by information coming from the object and/or discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32935—Monitoring and controlling tubes by information coming from the object and/or discharge
    • H01J37/32972—Spectral analysis
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Analytical Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A plasma processing apparatus includes a processing chamber arranged in a vacuum vessel. A wafer placed on a sample stage in the processing chamber is processed using a plasma formed in the processing chamber. Before etching the film layers provided on the wafer composed of a metal substance and an underlying oxide film or a material having a high dielectric constant, another wafer, provided on a surface thereof a film composed of a metal of the same kind as the metal substance, is processed and particles of the metal are deposited on an inner wall of said processing chamber.

Description

201029064 六、發明說明： 【發明所屬之技術領域】 本發明關於針對真空容器內之處理室內部配置的半導 體晶圓等之基板狀試料表面被配置的多數膜層，使用處理 室內形成之電漿進行處理的電漿處理裝置或電漿處理方法 ’特別關於使用電漿進行半導體基板等之表面處理的適合 之電漿處理方法。 φ 【先前技術】 隨近年來半導體元件之微細化，使經由微影成像技術 形成之遮罩轉印至下層膜的蝕刻工程，係被要求更高精確 度之尺寸精確度（亦即 CD (Critical Dimension)精確度 )。於量產現場，除CD控制性以外，確保CD之再現性 成爲重要之課題。通常，蝕刻工程中CD變動之主要原因 有，蝕刻腔室內壁附著由被處理材產生之反應生成物、腔 φ 室內構件因爲長期使用而消耗、腔室內構件之溫度等變動 ，自由基對腔室內內壁等之附著機率、對蝕刻性能影響的 電漿狀態產生變動等之主要原因。 ' 於微細化電晶體中，爲控制短通道效應，需要增加閛 ' 極絕緣膜之容量，習知係藉由減少閘極氧化膜之厚度來達 成此目的。但是，閘極氧化膜之薄膜化會導致漏電流增加 ，因此作爲閘極絕緣膜被導入具有更高介電係數之材料（ high-k)。作爲替換氧化膜的high-k材有例如給氧化膜（ Hf〇2 )。但是，習知多晶矽（P〇ly-Si)電極與Hf02間存 -5- 201029064 在材料之不適合性，因此需要具備具有適當工作函數之金 屬膜的構造。金屬材料有各種，如非專利文獻1( Semiconductor International 2008/ 1 號）之揭示被使用 Ti 、N、La 等。 習知上，電漿處理裝置係依晶圓單位或批次單位實施 使用電漿之潔淨處理，以碳（C)、氧化膜、多晶矽（ Poly-Si )、氮化矽等爲對象的製程中，主要爲使用含氟（ F) '氯（C1)、氧（0)之電漿之潔淨處理。另外，蝕刻 腔室內壁構件被消耗而產生之金屬等（例如鋁（A1))之 附著於腔室內構件時，僅靠電漿之潔淨處理難以除去，因 此，事先在製品用晶圓之蝕刻處理前進行陳化（seasoning )等之處理，使腔室內環境保持於一定之技術被檢討。 作爲此種習知技術，如特開2004 - 03 1 308號公報（ 專利文獻1)之揭示。於該習知技術，係於真空容器內之 處理室內部，針對被蝕刻對象之矽晶圓，使用該處理室內 部形成之電漿進行蝕刻時，事先進行陳化處理而於處理室 內使以Si爲組成而被含有的反應生成物附著於處理室內 壁。例如爲形成半導體裝置之閘極而蝕刻處理多晶矽時， 係使用HBr與Cl2、02之單獨或混合之氣體形成電漿，對 矽晶圓進行陳化處理，另外，對處理室實施溼式潔淨後， 針對沈積有A1膜的晶圓，使用SF6氣體與Cl2氣體之混合 氣體形成電漿，對該晶圓進行蝕刻處理，而於處理室內之 石英構件表面形成A1F披膜的處理。 另外，如 J. Vac. Sci. Techno 1. B24, 2 1 9 1 (2006)(非 201029064 專利文獻2 )之揭示，蝕刻金屬材料（例如TiN )時，該金 屬材料附著於腔室內壁，使用上述氣體系列之電漿潔淨處 理時有可能難以充分加以除去。 專利文獻1 :特開2004 - 03 1 3 80號公報 非專利文獻 1 Semiconductor International 日本版 2008.1 pp. 20-27 非專利文獻 2 · Journal of Vacuum Science and Technology ❹ 2191， B 24 (2006) 【發明內容】 (發明所欲解決之課題） 上述習知技術未充分考慮以下之點而產生問題。亦即 ，蝕刻上述高介電係數材料構成之膜層時，因爲含於該材 料的金屬材料之殘留於處理室內，該殘留物導致該處理後 被實施的處理之結果、形狀、CD値等性能，會於處理中 φ 或半隨晶圓片數之增加而變動，進而導致良品率降低之可 能性。 本發明目的在於提供可以抑制性能之變動的電漿處理 裝置或電漿處理方法。 (用以解決課題的手段） 爲達成上述目的，在具備被處理材的晶圓之處理實施 前，該被處理材爲具備：具有金屬之膜及具有high-k材料 之膜的膜層之構造者，針對表面具備和該層構造含有之金 201029064 屬材料爲同種金屬之膜的晶圓，進行處理而達成。如此則 ，可使處理室內之金屬殘留量穩定，可抑制製程之變動。 另外，處理室內之金屬物質之殘留量，藉由監控電漿發光 加以監控，而調節處理條件亦可。 更詳言之爲，爲達成上述目的，本發明之電漿處理裝 置，係具有配置於真空容器內之處理室，使用該處理室內 形成之電漿，對配置於該處理室內的試料台上載置之晶圓 施予處理者；其特徵爲：針對上述晶圓上配置之具有金屬 物質的膜、及其下方配置的氧化膜或具有高介電係數之材 料所構成之膜層，在進行蝕刻處理前，事先進行其他晶圓 之處理，該其他晶圓爲表面具備含有和上述金屬物質爲同 種金屬之膜，沈積該金屬所構成之粒子之後處理上述晶圓 上之上述膜層。 另外，爲達成上述目的，本發明之電漿處理方法，係 針對配置於真空容器內之處理室內的試料台上載置之晶圓 ，於該處理室內形成電漿施予處理者；其特徵爲：針對上 述晶圓上配置之具有金屬物質的膜、及其下方配置的氧化 膜或具有高介電係數之材料所構成之膜層，在進行蝕刻處 理前，事先進行其他晶圓之處理，該其他晶圓爲表面具備 含有和上述金屬物質爲同種金屬之膜，沈積該金屬所構成 之粒子之後處理上述晶圓上之上述膜層。 另外，於上述其他晶圓之處理時，使用上述處理室內 之發光檢測出上述金屬物質之量，依據該檢測結果，來調 節該其他晶圓之處理而達成目的。. -8- 201029064 另外，上述其他晶圓之處理，係由至少2個步驟以上 構成，藉由和蝕刻上述晶圓之膜層時使用之氣體同等的氣 體被進行處理而達成目的。 另外，各個步驟之步驟時間比，係設爲蝕刻上述晶圓 之膜層時之蝕刻時間比的±20%以內而達成目的。 另外，上述事先進行之其他晶圓之處理，係對上述處 理室內實施溼式潔淨之後被進行而達成目的。 另外，上述金屬之物質具有TiN，上述具有高介電係 數之材料爲Hf02，於該蝕刻時至少使用BC13氣體而達成 目的。 【實施方式】 以下依據圖面說明本發明之實施形態。 (實施形態） 以下依據圖1- 7說明本發明之實施形態。圖1爲本 發明之實施形態之使用微波 ECR ( Electron Cyclotron Resonance )形成電漿而處理晶圓的電漿處理裝置之構成 槪略之縱斷面圖。圖中以模式表示真空容器及其內部配置 之處理室及處理室內部配置之試料台、電極，真空容器外 周及上部配置之電場、磁場之供給手段，對彼等供給電力 的電源。彼等以外之機器、裝置，可由具有本實施形態相 關之技術領域之通常知識者，在不嚴重損及本實施形態相 關發明之效果之情況下，依據算出之性能或規格加以配置 -9- 201029064 或刪除。 於圖示之電漿處理裝置，在開放上部之具有圓筒形狀 的真空容器101之上部設置：圓板形狀之噴氣板102 (例 如石英製或釔製，至少於中心部具有氣體流通用的多數貫 穿孔），用於將蝕刻處理用之氣體導入真空容器101內之 具有圓筒形狀的處理室104內部；及介電體窗103 (例如 石英製），密封彼等之內部而構成天井部、構成處理室 104。在噴氣板102與介電體窗103之間的空間，被連通 流通鈾刻氣體用的氣體供給裝置105，而使上述氣體被供 給。 另外，於真空容器101之下部，介由面對處理室104 底面的真空排氣口 106被連接真空排氣裝置，構成可對處 理室104內部排氣、減壓（未圖示）。於處理室104內部 ，爲使產生電漿用之電場傳送至處理室104，於介電體窗 103上方配置電磁波（本實施形態爲微波）傳送用之導波 管107。導波管107之下端部，係面對圓板形狀之介電體 窗103之上面，被連結於具有圓筒形狀之空間。 傳送至導波管1〇7(或天線）的電場，係由電場產生 用電源109振盪形成。被供給至處理室104內部的電波之 頻率，未受本實施形態之作用、效果而特別限定，本實施 形態中使用2.45 G Hz之微波。該微波由電場產生用電源 109形成而傳導至導波管107內部，由介電體窗103上面 透過該構件及下方之噴氣板102，由該下方之處理室104 內部配置之試料台、亦即具備外型模擬其之圓筒形狀的晶 201029064 圓載置用電極111之大略圓形之上面上方，被導入處理室 104內部。 於處理室104之側周圍及上方之外周配置磁場產生線 圈110，可於處理室104內部產生磁場。由電場產生用電 源109振盪被供給至處理室104內部之電場，係和同樣被 供給至處理室104內部之磁場產生相互作用，激發處理用 氣體，而於處理室104內部產生電漿。如上述說明，和噴 氣板102呈對向而於真空容器101內部之處理室104之下 部被配置晶圓載置用電極111，其上部表面被以介電體材 料溶射形成之介電體膜（未圖示）覆蓋，於介電體膜內部 配置之鎢（W)等金屬製導電性膜，係介由高頻濾波器 H5被連接直流電源116。 於晶圓載置用電極111，係於內部被配置鋁（A1)或 Ti等導電性金屬構成之圓板形狀構件，於此介由匹配電路 113被連接高頻電源114。另外，於於晶圓載置用電極111 之金屬製構件內部，被配置螺旋形狀或同心圓狀之多重之 冷媒用流路117，該冷媒用流路係連結於冷媒用配管。冷 媒用配管係連結於調溫器118之同時，亦連結於加熱器 119。加熱器119係連結於加熱控制器120。另外，於晶圓 載置用電極111配置溫度感測器121，其信號被傳送至加 熱控制器120，控制加熱器119之輸出及調溫器118之設 定溫度而控制冷媒之溫度，以使晶圓1 1 2之溫度成爲所要 溫度。藉由該構成，可進行內部冷媒之溫度、換言之，晶 圓載置用電極111之調節。 -11 - 201029064 在構成處理室104之真空容器101外壁，被連接發光 分光器123可以測定處理室104內部之發光，該發光分光 器123被連接於發光資料處理裝置124。伴隨處理而產生 之電漿等之發光，係透過真空容器1〇1側壁配置之石英等 構件之窗，被供給至發光分光器123，經由發光資料處理 裝置124可進行該資料之數値解析。 被搬送至處理室1〇4內部的晶圓112，係被載置於晶 圓載置用電極111上面之介電體膜，藉由直流電源116施 加於內部膜狀電極之直流電壓產生之靜電力被吸附於晶圓 載置用電極U1上。於此狀態被調節溫度，由氣體供給裝 置105介由噴氣板102對處理室104內部供給所要之蝕刻 氣體，而且由真空排氣口 1〇6藉由真空排氣裝置進行處理 室104內部之氣體之排氣，使真空容器101內部被調節成 爲特定壓力。藉由被供給至處理室104內部之電場、磁場 激發氣體，於處理室1〇4內部產生電漿。形成電漿之後， 由連接於晶圓載置用電極111之高頻電源114施加高頻電 力，於晶圓112上面形成偏壓電位，使電漿中之離子被吸 引至晶圓112上面，開始晶圓112之蝕刻處理。 圖2爲圖1之本實施形態進行處理的被處理材之構造 之模式圖。圖中之被處理材，係具有被積層、配置於晶圓 112上面之膜層，圖中表示處理後之膜層之一部分形狀之 模式。 圖中之膜層，係由多數之膜構成，於底層、亦即晶圓 112之矽20 5上面例如由4層構成。彼等爲具有：包含阻 201029064 劑（PR)或硬質遮罩（Si02、SiN、或SiON等）等之遮 罩201及其下方之多晶矽（Poly-Si)膜202、金屬物質構 成之材料的膜（例如TiN，以下稱金屬膜）203，及high-k (例如Hf02 )膜204之積層構造。 此種膜層之構造，係用於形成半導體裝置之閘極構造 者，在蝕刻處理前經由特定處理被形成，藉由微影成像技 術進行遮罩201之不要部分之除去。圖中之彼等之各膜， φ 雖由單一層構成，但亦可由多數層構成。特別是，金屬膜 203可由各爲不同材料之多數層構成。另外，金屬膜203 之材料種類、積層數、厚度可依製造之半導體裝置之規格 對應於NMOS部分、PM0S部分而不同。 各別之積層膜係依據各別之條件、氣體組成、供給量 、壓力、處理時間等之至少之一部分不同的處理程序（ recipe)被處理。遮罩201，僅爲對應於近年之微細加工 的PR時對於膜厚、抗蝕刻性均不充分，因此於PR之下 φ 層配置非晶質碳（ACL)或SiN或SiON及Si02之硬質遮 罩，以彼等爲遮罩再對下層之Poly-Si膜202或金屬膜 203蝕刻亦可。其中省略遮罩201之蝕刻工程之說明。[Technical Field] The present invention relates to a plurality of film layers disposed on a surface of a substrate-like sample such as a semiconductor wafer disposed inside a processing chamber inside a vacuum chamber, using plasma formed in a processing chamber. The treated plasma processing apparatus or plasma processing method is particularly suitable for a plasma processing method for performing surface treatment of a semiconductor substrate or the like using plasma. φ [Prior Art] With the recent miniaturization of semiconductor components, etching of masks formed by lithography imaging techniques to the underlying film is required to be more accurate in dimensional accuracy (ie, CD (Critical) Dimension) accuracy). At the mass production site, in addition to CD control, ensuring the reproducibility of CDs becomes an important issue. In general, the main reason for the CD variation in the etching process is that the reaction product generated by the material to be processed adheres to the inner wall of the etching chamber, the cavity φ is consumed by the indoor component for a long period of time, and the temperature of the component in the chamber changes, and the radical is in the chamber. The main cause of the adhesion rate of the inner wall or the like and the change of the plasma state which affects the etching performance. In the micronized transistor, in order to control the short-channel effect, it is necessary to increase the capacity of the 极'-electrode insulating film, which is conventionally achieved by reducing the thickness of the gate oxide film. However, the thinning of the gate oxide film causes an increase in leakage current, and thus is introduced as a gate insulating film into a material having a higher dielectric constant (high-k). As the high-k material which replaces the oxide film, for example, an oxide film (Hf〇2) is given. However, the conventional polycrystalline germanium (P〇ly-Si) electrode and Hf02 are incompatible with materials, and therefore a structure having a metal film having an appropriate working function is required. There are various kinds of metal materials, and Ti, N, La, etc. are used as disclosed in Non-Patent Document 1 (General International 2008/1). Conventionally, a plasma processing apparatus performs a clean treatment using a plasma in a wafer unit or a batch unit, and is processed in a process of carbon (C), an oxide film, a polycrystalline silicon (Poly-Si), or a tantalum nitride. It is mainly used for the clean treatment of plasma containing fluorine (F) 'chloro (C1) and oxygen (0). In addition, when the metal or the like (for example, aluminum (A1)) which is generated by the inner wall member of the etching chamber is attached to the chamber member, it is difficult to remove only by the clean processing of the plasma, and therefore, the etching of the wafer for the product is performed in advance. The technique of maintaining the internal environment of the chamber was reviewed before the treatment of seasoning and the like. As such a conventional technique, it is disclosed in Japanese Laid-Open Patent Publication No. 2004-0381 (Patent Document 1). According to the prior art, in the inside of the processing chamber in the vacuum container, when the plasma is formed by etching the plasma formed in the processing chamber, the aging wafer is etched in advance and the Si is processed in the processing chamber. The reaction product contained in the composition is attached to the inner wall of the treatment chamber. For example, when a polysilicon is etched to form a gate of a semiconductor device, a plasma is formed by using a gas of HBr and Cl2, 02 alone or in combination, and the germanium wafer is aged, and after the wet cleaning of the processing chamber is performed. For the wafer on which the A1 film is deposited, a plasma is formed by using a mixed gas of SF6 gas and Cl2 gas, and the wafer is etched to form an A1F film on the surface of the quartz member in the processing chamber. Further, as disclosed in J. Vac. Sci. Techno 1. B24, 2 1 9 1 (2006) (non-201029064 Patent Document 2), when a metal material (for example, TiN) is etched, the metal material is attached to the inner wall of the chamber, and is used. When the plasma of the above gas series is cleaned, it may be difficult to remove it sufficiently. Patent Document 1: Japanese Laid-Open Patent Publication No. 2004- 03 1 3 80 Non-Patent Document 1 Semiconductor International Japan Edition 2008.1 pp. 20-27 Non-Patent Document 2 · Journal of Vacuum Science and Technology ❹ 2191, B 24 (2006) [Summary Contents (Problems to be Solved by the Invention) The above-described conventional techniques do not sufficiently take into consideration the following points. That is, when the film layer composed of the high-k material is etched, since the metal material contained in the material remains in the processing chamber, the residue causes the result of the treatment, the shape, and the CD 値 performance after the treatment. It will change during the processing of φ or half with the increase in the number of wafers, which may result in a lower yield. SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma processing apparatus or a plasma processing method which can suppress variations in performance. (Means for Solving the Problem) In order to achieve the above object, the material to be processed is a structure including a film having a metal film and a film having a high-k material before the processing of the wafer including the material to be processed is performed. It is achieved by processing a wafer having a film of the same metal as the gold 201029064 material contained in the layer structure. In this way, the metal residual amount in the processing chamber can be stabilized, and the variation of the process can be suppressed. In addition, the residual amount of the metal substance in the treatment chamber can be monitored by monitoring the plasma luminescence, and the processing conditions can be adjusted. More specifically, in order to achieve the above object, a plasma processing apparatus according to the present invention has a processing chamber disposed in a vacuum chamber, and uses a plasma formed in the processing chamber to mount a sample stage disposed in the processing chamber. The wafer application processor is characterized in that an etching treatment is performed on a film having a metal substance disposed on the wafer, an oxide film disposed therebelow, or a material having a high dielectric constant. Before, the other wafers are processed in advance, and the other wafers have a film containing the same metal as the metal material on the surface, and the particles formed of the metal are deposited, and then the film layer on the wafer is processed. Further, in order to achieve the above object, a plasma processing method according to the present invention is directed to a wafer placed on a sample stage in a processing chamber disposed in a vacuum chamber, and a plasma application processor is formed in the processing chamber; A film layer composed of a film having a metal substance disposed on the wafer, an oxide film disposed therebelow, or a material having a high dielectric constant is subjected to processing of another wafer before performing an etching process. The wafer has a film containing the same metal as the metal material on the surface, and the film formed of the metal is deposited, and then the film layer on the wafer is processed. Further, in the processing of the other wafers described above, the amount of the metal substance is detected by the light emission in the processing chamber, and the processing of the other wafer is adjusted in accordance with the detection result to achieve the object. -8- 201029064 In addition, the processing of the above other wafers is performed by at least two steps or more, and the gas equivalent to the gas used for etching the film layer of the wafer is processed to achieve the object. Further, the step-to-time ratio of each step is set to within ±20% of the etching time ratio when etching the film layer of the wafer. Further, the processing of the other wafers performed in advance is performed after the wet cleaning in the processing chamber is performed. Further, the metal material has TiN, and the material having a high dielectric constant is HfO 2 , and at least BC13 gas is used for the etching to achieve the object. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to Figs. Fig. 1 is a schematic longitudinal sectional view showing the configuration of a plasma processing apparatus for processing a wafer by using a microwave ECR (electron Cyclotron Resonance) according to an embodiment of the present invention. In the drawing, the vacuum chamber and the processing chamber disposed inside the processing chamber and the sample table and the electrode disposed inside the processing chamber, and the means for supplying electric fields and magnetic fields disposed on the outer periphery and the upper portion of the vacuum container, and the power source for supplying electric power thereto are shown. The other machines and devices other than those of the technical field according to the present embodiment can be configured according to the calculated performance or specifications without seriously compromising the effects of the invention related to the embodiment-9-201029064 Or delete. In the plasma processing apparatus shown in the drawing, a disk-shaped air-jet plate 102 (for example, made of quartz or tantalum, having a gas flow-generating majority at least in the center portion) is provided above the open upper vacuum vessel 101 having a cylindrical shape. a through hole) for introducing a gas for etching treatment into a cylindrical processing chamber 104 in a vacuum vessel 101, and a dielectric window 103 (for example, made of quartz), sealing the inside of the chamber to form a patio portion, The processing chamber 104 is constructed. A space between the air jet plate 102 and the dielectric window 103 is connected to a gas supply device 105 for uranium engraving gas, and the gas is supplied. Further, a vacuum evacuation device is connected to the lower portion of the vacuum chamber 101 via a vacuum exhaust port 106 facing the bottom surface of the processing chamber 104, so that the inside of the processing chamber 104 can be exhausted and depressurized (not shown). Inside the processing chamber 104, in order to transfer the electric field for generating plasma to the processing chamber 104, an electromagnetic wave (the present embodiment is a microwave) transmitting waveguide 107 is disposed above the dielectric window 103. The lower end portion of the waveguide 107 is opposed to the upper surface of the disk-shaped dielectric window 103, and is connected to a space having a cylindrical shape. The electric field transmitted to the waveguide 1〇7 (or the antenna) is formed by oscillation of the electric field generating power source 109. The frequency of the electric wave supplied to the inside of the processing chamber 104 is not particularly limited by the action and effect of the present embodiment, and in the present embodiment, a microwave of 2.45 G Hz is used. The microwave is formed by the electric field generating power source 109 and is conducted to the inside of the waveguide 107. The upper surface of the dielectric window 103 passes through the member and the lower air jet plate 102, and the sample stage disposed inside the processing chamber 104 below, that is, The upper surface of the substantially circular shape of the crystal 201029064 circular mounting electrode 111 having a cylindrical shape is introduced into the processing chamber 104. The magnetic field generating coil 110 is disposed around the periphery of the processing chamber 104 and above and outside, and a magnetic field can be generated inside the processing chamber 104. The electric field supplied to the inside of the processing chamber 104 by the electric field generating power source 109 oscillates and interacts with the magnetic field supplied to the inside of the processing chamber 104 to excite the processing gas to generate plasma inside the processing chamber 104. As described above, the wafer mounting electrode 111 is disposed below the processing chamber 104 inside the vacuum chamber 101, and the upper surface thereof is formed by a dielectric film formed by dissolving a dielectric material. As shown in the figure, a metal conductive film such as tungsten (W) disposed inside the dielectric film is connected to the DC power source 116 via the high-frequency filter H5. The wafer mounting electrode 111 is provided with a disk-shaped member made of a conductive metal such as aluminum (A1) or Ti, and the high-frequency power source 114 is connected via the matching circuit 113. In the metal member of the wafer-mounting electrode 111, a plurality of refrigerant flow paths 117 having a spiral shape or a concentric shape are disposed, and the refrigerant flow path is connected to the refrigerant pipe. The refrigerant piping is connected to the temperature controller 118 and is also connected to the heater 119. The heater 119 is coupled to the heating controller 120. Further, the temperature sensor 121 is disposed on the wafer mounting electrode 111, and the signal is transmitted to the heating controller 120, and the output of the heater 119 and the set temperature of the thermostat 118 are controlled to control the temperature of the refrigerant to make the wafer. The temperature of 1 1 2 becomes the desired temperature. With this configuration, the temperature of the internal refrigerant, in other words, the adjustment of the wafer mounting electrode 111 can be performed. -11 - 201029064 The outer wall of the vacuum vessel 101 constituting the processing chamber 104 is connected to the light-emitting beam splitter 123 to measure the light emission inside the processing chamber 104, and the light-emitting beam splitter 123 is connected to the light-emitting data processing device 124. The light emitted by the plasma or the like generated by the processing is supplied to the illuminating spectroscope 123 through a window of a member such as quartz disposed on the side wall of the vacuum chamber 1 ,1, and the data is analyzed by the illuminating data processing device 124. The wafer 112 transferred to the inside of the processing chamber 1〇4 is a dielectric film placed on the upper surface of the wafer mounting electrode 111, and the electrostatic force generated by the DC voltage applied to the internal film electrode is generated by the DC voltage. It is adsorbed on the wafer mounting electrode U1. In this state, the temperature is adjusted, the gas supply device 105 supplies the desired etching gas to the inside of the processing chamber 104 via the air ejection plate 102, and the gas inside the processing chamber 104 is performed by the vacuum exhaust port 1〇6 by the vacuum exhaust device. The exhaust gas is such that the inside of the vacuum vessel 101 is adjusted to a specific pressure. The plasma is generated inside the processing chamber 1〇4 by the electric field and the magnetic field excited by the gas supplied to the inside of the processing chamber 104. After the plasma is formed, high-frequency power is applied from the high-frequency power source 114 connected to the wafer-mounting electrode 111, a bias potential is formed on the wafer 112, and ions in the plasma are attracted to the wafer 112 to start. The etching process of the wafer 112. Fig. 2 is a schematic view showing the structure of a material to be processed which is processed in the embodiment of Fig. 1; The material to be processed in the figure has a film layer which is laminated and disposed on the upper surface of the wafer 112, and shows a pattern of a part of the shape of the film layer after the treatment. The film layer in the figure is composed of a plurality of films, and is formed of, for example, four layers on the bottom layer, that is, on the top surface of the wafer 112. These are films having a mask 201 containing a 201029064 agent (PR) or a hard mask (SiO 2 , SiN, or SiON, etc.) and a polycrystalline silicon (Poly-Si) film 202 and a metal material. (for example, TiN, hereinafter referred to as metal film) 203, and a high-k (for example, HfO 2 ) film 204 laminated structure. The structure of such a film layer is used to form a gate structure of a semiconductor device, which is formed by a specific process before the etching process, and the unnecessary portion of the mask 201 is removed by the lithography technique. In the films of the drawings, φ is composed of a single layer, but may be composed of a plurality of layers. In particular, the metal film 203 may be composed of a plurality of layers each having a different material. Further, the material type, the number of layers, and the thickness of the metal film 203 may differ depending on the NMOS portion and the PMOS portion depending on the specifications of the semiconductor device to be manufactured. The individual buildup films are processed according to at least one of different recipes for individual conditions, gas composition, supply, pressure, processing time, and the like. The mask 201 is only insufficient for film thickness and etching resistance in accordance with the PR of microfabrication in recent years. Therefore, the amorphous layer (ACL) or the hard mask of SiN or SiON and SiO 2 is disposed in the φ layer under the PR. The cover may be etched with the Poly-Si film 202 or the metal film 203 of the lower layer by using them as a mask. The description of the etching process of the mask 201 is omitted.

Poly-Si膜2 02之蝕刻處理氣體可使用Cl2與氟（F) (例如CF4)之混合氣體、或Cl2與HBr之混合氣體。必 要時亦可使用〇2等氣體。 之後，於金屬膜203 (例如TiN )層之蝕刻工程，最 初爲除去金屬膜2 03層之界面（於上下之膜層之間，在作 爲彼等材料之表面彼此之間被形成的面，包含單一或約數 -13- 201029064 原子層之其他構件之膜存在時的界面部分）所形成之自然 氧化膜，設爲相對高之晶圓偏壓之値，增加離子能量。可 使用ΗΒΓ或Ar等作爲處理氣體，亦可使用其他氣體系列 〇 該自然氧化膜之除去工程之後爲蝕刻金屬膜203，主 要使用Cl2氣體或Cl2與HBr之混合氣體作爲處理氣體。 本實施形態中使用之金屬膜203之蝕刻，相對於其他之膜 層，金屬膜2 03之層較薄，因此使成爲較低離子能量而調 整高頻電源114之電力引起之晶圓偏壓之値。 之後，於高介電係數材料、亦即high-k (例如Hf02 )膜之蝕刻使用BCI3或BC13與Cl2之混合氣體。此步驟 中，藉由較低離子能量條件之使用而達成良好的蝕刻特性 (形狀、選擇比）。 習知技術上，蝕刻處理之晶圓片數成爲特定片數時， 係在實施處理室1〇4內部之溼式潔淨等之潔淨厚，爲調節 處理室104內部而實施使用Si、PR或氧化膜晶圓等之非 金屬系列晶圓的蝕刻，而實施處理室1〇4內部之構件表面 之陳化處理後，實施製品晶圓之處理。圖3爲藉由習知技 術，進行表面被配置有處理金屬/ high-k積層構造之被處 理材材的晶圓之多數片之處理時，溼式處理後之多晶矽（ Poly-Si)之蝕刻速率測定結果之分布圖。 於該習知技術，伴隨多數片晶圓之處理片數增加，蝕 刻速率會變化，特別是，在處理開始之極初期蝕刻速率急 速增加，之後呈穩定，因此實施潔淨、開始蝕刻之後之製 -14- 201029064 品晶圓之處理結果，於其後經由特定片數而獲得穩定結果 的晶圓之處理結果之間存在著顯著之形狀差異。 本發明人爲使該原因明確，而於處理室內部設置和處 理室內壁同種夠艦隻測試樣本，針對含金屬膜203之膜層 與不含金屬膜2 03之膜層進行處理時之個別之樣本表面， 使用 XPS( X-ray photo-electron spectroscopy)予以測定 ，解果如圖4所示。如圖4所示，由含金屬膜2 03之膜層 進行處理之樣本檢測出Ti，另外，由含金屬膜203之膜層 進行處理之樣本檢測出氟之增加。 圖5爲以金屬膜203與hi gh-k膜2 04之蝕刻處理之時 間爲參數，連續進行多數片（本實施形態爲約1〇片）之 蝕刻處理後，測定其他晶圓1 12之如圖2所示膜層之 Poly-Si膜202之蝕刻處理速率之結果分布圖。圖中虛線 表示長時間處理晶圓1 12時之穩定之Poly-Si膜202之蝕 刻速率。 如圖所示，high-k膜204之蝕刻處理之時間越少鈾刻 速率越大，時間越多飩刻速率越減少。另外，在一定以上 之high-k膜204之蝕刻處理時間，蝕刻速率呈飽和。本實 施形態中，金屬膜203之材料爲TiN之蝕刻時使用含HBr / Cl2之處理氣體。high-k膜204之蝕刻時使用含BC13/ Cl2之處理氣體。另外，處理該膜層後’將矽晶圓設於電 極上，曝曬於Ar放電，之後藉由TRXF ( Total reflection X-ray Fluorescence)測定砂晶圓表面者。分別將檢測出之 Ti量表示於右軸。 -15- 201029064 本實施形態中，可以推測被檢測出之金屬物質、亦即 Ti，係於處理室104內部作爲粒子殘留之Ti，於處理中經 由Ar之濺鍍被飛散，而沈積於晶圓112上者所引起。因 此，可以考慮爲Poly-Si膜202之蝕刻處理速率與處理室 104內部殘留之Ti量之間具有相關性。 另外，如圖4所示，因爲處理室104內部殘留Ti而 使氟亦同時增加。爲調査該原因，經由詳細觀看XPS之測 定結果（未圖示）發現，於Ti2p峰値除Ti— Ο之鍵結以 外，亦存在Ti— F之峰値。另外，於FIs之峰値出現低束 縛能量方向之能量變動，而使F與任一金屬產生鍵結，本 發明推測此情況下具有Ti 一 F之鍵結。由此亦可說明，因 爲處理室104內部殘留Ti而使構成處理室104內壁表面 之材料物質被氟化，進而電漿中之F增加而使Poly-Si膜 之處理速率增加。 另外，通常，Ti—F、Ti-Ο之鍵結穩定之故，使用 習知技術之電漿之潔淨難以除去。因此，本實施形態中， 在製品用晶圓112之被處理材之處理前，事先針對表面具 備和和該被處理材含有之金屬膜203 (例如TiN)之材料 爲同一物質的晶圓進行處理，進行使同一金屬物質（例如 Ti )附著於處理室1 04內部的陳化處理。如此則，可使處 理室104內部之處理中之氣體組成穩定。如本實施形態之 事前之潔淨處理，係在處理室104內部之構件表面之溼式 潔淨後，處理製品用晶圓1 1 2之前被進行。 本實施形態之陳化處理亦可使用多數片表面配置有 -16- 201029064As the etching treatment gas of the Poly-Si film 202, a mixed gas of Cl2 and fluorine (F) (for example, CF4) or a mixed gas of Cl2 and HBr may be used. Gas such as 〇2 can also be used if necessary. Thereafter, the etching process of the metal film 203 (for example, TiN) layer is initially to remove the interface of the metal film 203 layer (between the upper and lower film layers, the surface formed between the surfaces of the materials, including The natural oxide film formed by a single or about -13-201029064 interface portion in the presence of a film of other members of the atomic layer is set to a relatively high wafer bias voltage to increase the ion energy. It is possible to use ruthenium or Ar or the like as a process gas, and other gas series may be used. After the removal of the natural oxide film, the metal film 203 is etched, and a mixed gas of Cl2 gas or Cl2 and HBr is mainly used as a process gas. In the etching of the metal film 203 used in the present embodiment, the layer of the metal film 203 is thinner than the other film layers, so that the wafer bias voltage caused by the electric power of the high-frequency power source 114 is adjusted to be a lower ion energy. value. Thereafter, BCI3 or a mixed gas of BC13 and Cl2 is used for etching of a high dielectric constant material, that is, a high-k (for example, HfO 2 ) film. In this step, good etching characteristics (shape, selection ratio) are achieved by the use of lower ion energy conditions. In the prior art, when the number of wafers to be etched is a specific number of sheets, it is clean and thick such as wet cleaning inside the processing chamber 1〇4, and Si, PR, or oxidation is performed to adjust the inside of the processing chamber 104. The etching of the non-metal series wafer such as the film wafer is performed, and the surface of the member inside the processing chamber 1〇4 is subjected to the aging treatment, and then the processing of the product wafer is performed. Fig. 3 is a view showing the etching of polycrystalline silicon (Poly-Si) after wet processing when a plurality of wafers having a surface treated with a material for processing a metal/high-k laminated structure are disposed by a conventional technique. Distribution map of rate measurement results. According to the prior art, the etching rate varies with the number of processed wafers of a plurality of wafers. In particular, the etching rate is rapidly increased at the beginning of the processing, and then stabilized, so that the cleaning is performed and the etching is started. 14- 201029064 The processing result of the wafer, there is a significant shape difference between the processing results of the wafer after which the stable result is obtained through a specific number of wafers. In order to clarify the reason, the inventors set up and process the inner wall of the same type of ship-supplied test sample in the interior of the processing chamber, and the individual samples for the film layer containing the metal film 203 and the film layer not containing the metal film 203 are processed. The surface was measured by XPS (X-ray photo-electron spectroscopy), and the result is shown in Fig. 4. As shown in Fig. 4, Ti was detected from the sample treated with the film layer of the metal film 203, and the increase in fluorine was detected from the sample treated with the film layer containing the metal film 203. 5 is a view showing an etching process of a plurality of sheets (about one sheet in this embodiment) by using the etching time of the metal film 203 and the hi gh-k film 204 as a parameter, and then measuring other wafers 1 12 as follows. The resulting distribution of the etching rate of the Poly-Si film 202 of the film layer shown in FIG. The dotted line in the figure indicates the etching rate of the stabilized Poly-Si film 202 when the wafer 1 12 is processed for a long time. As shown, the less the etching time of the high-k film 204, the greater the uranium engraving rate, and the more time the engraving rate decreases. In addition, the etching rate is saturated at a certain etching time of the high-k film 204. In the present embodiment, the material of the metal film 203 is a process gas containing HBr/Cl2 for etching TiN. The processing gas containing BC13/Cl2 is used for etching the high-k film 204. Further, after the film layer was processed, the germanium wafer was placed on the electrode, exposed to Ar discharge, and then the surface of the sand wafer was measured by TRXF (Total Reflection X-ray Fluorescence). The amount of Ti detected is expressed on the right axis. -15- 201029064 In the present embodiment, it is presumed that the detected metal substance, that is, Ti, is contained in the processing chamber 104 as Ti remaining in the processing chamber, and is scattered by sputtering in Ar during processing, and deposited on the wafer. 112 caused by the person. Therefore, it is considered that there is a correlation between the etching treatment rate of the Poly-Si film 202 and the amount of Ti remaining inside the processing chamber 104. Further, as shown in Fig. 4, since Ti remains in the inside of the processing chamber 104, fluorine is also simultaneously increased. In order to investigate the cause, it was found by the detailed observation of the XPS measurement result (not shown) that there is also a peak of Ti-F in addition to the Ti-p bond of the Ti2p peak. Further, in the peak of FIs, there is a change in energy in the direction of low bound energy, and F is bonded to any metal. The present invention presumes that there is a bond of Ti-F in this case. Therefore, it is also explained that the material material constituting the inner wall surface of the processing chamber 104 is fluorinated due to the residual Ti inside the processing chamber 104, and the F in the plasma is increased to increase the processing rate of the Poly-Si film. Further, in general, the bonding of Ti-F and Ti-Ο is stable, and it is difficult to remove the plasma using the conventional technique. Therefore, in the present embodiment, before the processing of the material to be processed of the product wafer 112, the wafer having the same material as the material of the metal film 203 (for example, TiN) contained in the material to be processed is processed in advance. An aging treatment for adhering the same metal substance (for example, Ti) to the inside of the processing chamber 104 is performed. In this way, the composition of the gas in the treatment inside the processing chamber 104 can be stabilized. The pre-cleaning treatment in the present embodiment is performed after the wet cleaning of the surface of the member inside the processing chamber 104, before the wafer 1 1 2 is processed. The aging treatment of this embodiment can also be configured using a plurality of sheets having a surface of -16 - 201029064

TiN的晶圓112’亦即可以重複進行事前之陳化處理。此 時，對各個具有不同膜層之多數片晶圓進行連續之處理亦 可。處理室104內部殘留之金屬物質（Ti)之量，可於陳 化使用之晶圓112上、或無晶圓112狀態下，產生電漿， 使用該電漿之發光予以檢測出。說明使用圖6進行該金屬 物質之檢測。 圖6爲於圖1所示實施形態中，使用含有BC13的處 φ 理氣體產生電漿時Ti引起之發光強度之時間變化圖。本 實施形態中，使用發光資料處理裝置124解析該發光強度 。特別是，藉由其內部配置之運算裝置，讀出同樣配置於 內部之記憶裝置內所記憶之表面配置有上述金屬物質的晶 圓112之蝕刻處理期間被檢測出之發光資料，進行特定金 屬物質對應之波長之發光資料之積分處理，進行包含該積 分處理的特定運算，而算出處理室104內部殘留之Ti量 之表示結果，以此作爲信號予以輸出，而被檢測出Ti量 如上述說明，伴隨著上述晶圓112之處理而沈積於處 理室104內部表面、或殘留於處理室104內部之Ti之量 之增大，其後輩進行之具有被處理材的晶圓112之蝕刻處 理速率會變化，但當Ti之量大於特定値時蝕刻速率漸漸 接近特定値，而成爲飽和狀態。成爲飽和狀態之Ti之量 ，係事先取得在成爲飽和狀態範圍內之長時間，針對表面 含有金屬物質的晶圓112之該膜之蝕刻處理之進行時處理 室1 04內部之發光資料加以解析之中，和進行溼式潔淨後 -17- 201029064 被進行的，表面配置有含金屬物質之膜的晶圓進行 蝕刻處理之差異之發光強度加以比較，檢測出上述 爲飽和狀態之前的陳化之終點。另外，本實施形態 使用含有BC13之氣體系列，但使用Ar等稀有氣體 係類亦可進行同樣之測定。 圖7爲於圖1所示實施形態中，在製品用晶圓 面之被處理材之處理前，未進行上述陳化處理時及 TiN之蝕刻步驟之處理時，進行TiN膜與high-k材 層膜之上述陳化處理、而且藉由電漿發光進行陳化 判斷後，蝕刻處理多晶矽膜203時之蝕刻速率變化 行TiN膜與high-k材料之積層膜之處理，係3例 率之變動最小，被實施穩定之處理。如上述說明 high-k材料之膜的處理，係使用含有BC13的處理 在使用該氣體的處理中，BC13具有除去處理室104 留之Ti之特性。 由此可知，欲調節處理室104內部殘留之Ti 於事前之陳化處理中，針對TiN膜之蝕刻工程與 材料膜之蝕刻工程間的時間比或放電條件，依據電 之檢測所獲得之信號加以調節乃重要者。如此則， 由事前之陳化處理，將處理室104內部殘留或沈積 物質（Ti)之量調節成爲所要之量。 另外，控制處理室104內部殘留之Ti量時， 備具有該膜層構造之被處理材的晶圓112實施蝕刻 由和金屬膜203與high-k膜204之處理所要時間比 事前之 速率成 中，雖 之氣體 1 12表 僅進行 料之積 之終點 圖。進 之中速 ，含有 氣體， 內部殘 量時， high-k 漿發光 可以藉 之金屬 針對具 時，藉 相等或 201029064 20%以內之比，藉由Ti陳化中之TiN膜/ high-k材料構成 之膜之處理時間比，來進行處理，如此則，陳化中沈積之 處理室104內部之Ti之殘留分布，亦成爲和處理實際之 被處理材時同等。此亦可藉由以下之處理進行而獲得：亦 即、將事前之陳化處理中之TiN膜/ high-k材料構成之膜 之構成，和被處理材之構成設爲同等，在TiN膜/high-k 材料所構成之膜之處理中，使處理室104內部之電漿中之 金屬物質之發光強度，和具有被處理材之製品用晶圓112 之處理時、特別是，其之蝕刻速率等之處理條件成爲穩定 狀態下獲得之發光強度成爲相等，而進行事前之陳化處理 中的晶圓112之處理。另外，亦可藉由以下之處理進行而 獲得：使事前之陳化處理之中處理TiN膜/ high-k材料構 成之膜之各個時使用之包含處理氣體之組成等之處理條件 ，設爲和具有被處理材之晶圓112之處理條件相同、或實 質上相同等模擬程度上同等，而加以獲得。 上述之事前之陳化處理係由2個以上之間步驟構成， 藉由進行以上之處理，可以更高精確度調節處理室104內 部殘留之Ti之量或分布，可提升製程之穩定性。 如上述說明，於上述實施形態中，在具有金屬膜203 與high-k膜2 04之積層構造的被處理材之處理實施之前， 針對表面具備和該被處理材含有之金屬膜203之材料爲同 種物質之膜的晶圓，實施處理、對該膜進行蝕刻處理，另 外，藉由監控處理室內之發光，檢測出處理室104內部殘 留之上述金屬物質之量，或者使用檢測結果來調節處理之 -19 - 201029064 條件，依此而使處理室104內部殘留之金屬物質之量穩定 ，如此則，可以抑制處理結果獲得之形狀之變動，進而可 提升加工後之CD値之穩定性，可以提供處理之良品率較 高及隨時間之變化較少的触刻處理之裝置或方法。 處理室104內部殘留之金屬物質之量穩定，因此可以 抑制金屬物質引起之製程之變動，具有抑制CD之變動之 效果。 另外，本實施形態中，雖特別針對ECR電漿裝置之 實施形態說明，但本發明用於其他電漿產生裝置或方法、 例如感應耦合型電漿（ICP)、容量耦合型電漿（CCP ) 亦可獲得同樣效果。 【圖式簡單說明】 圖1爲本發明之一實施形態之微波ECR蝕刻裝置之 縱斷面圖。 圖2爲圖1之本實施形態進行處理的被處理材之構造 之模式之縱斷面圖。 圖3爲藉由習知技術處理金屬/ high-k積層構造之被 處理材材時，晶圓處理後之多晶矽（Poly-Si)之蝕刻速率 測定結果之分布圖。 圖4爲於處理室內部設置和處理室內壁爲同種構件的 測試樣本，處理含有金屬膜203之膜層與不含金屬膜203 之膜層時，使用 XPS ( Xray photo-electron spectroscopy )測定各個樣本表面之結果之分布圖。 -20- 201029064 圖5爲以晶圓上之如圖2所示膜層之金屬膜與high_k 膜之蝕刻處理之時間爲參數，連續進行多數片之蝕刻處理 後，測定其他晶圓之多晶矽之蝕刻處理之速率之結果分布 圖。 圖6爲於圖1所示實施形態中，使用含有BC13的處 理氣體產生電漿時Ti引起之發光強度之時間變化圖。 圖7爲於圖1所示實施形態中，在製品用晶圓丨丨2表 φ 面之被處理材之處理前，未進行上述陳化處理時及僅進行 TiN之餽刻步驟之處理時，進行TiN膜與high-k材料之積 層膜之上述陳化處理、而且藉由電漿發光進行陳化之終點 判斷後，蝕刻處理多晶矽膜203時之蝕刻速率變化圖。 【主要元件符號說明】 101 :真空容器 102 :噴氣板 • :介電體窗 104 :處理室 105 _·氣體供給裝置 106 :真空排氣口 :導波管 108 :空腔共振器 :電場產生用電源 1 1 〇 ·'磁場產生線圈 1 1 1 :晶圓載置用電極 -21 - 201029064 1 1 2 :晶圓 1 1 3 :匹配電路 1 1 4 :高頻電源 1 1 5 :濾波器 1 1 6 :直流電源 1 1 7 :冷媒用流路 1 18 :調溫器 1 1 9 : 1 2 2 :加熱器 1 2 0 :加熱控制器 1 2 1 :溫度感測器 1 2 3 :發光分光器 124:發光資料處理裝置The TiN wafer 112' can be repeatedly subjected to pre-aging treatment. At this time, continuous processing of a plurality of wafers having different film layers is also possible. The amount of the metal substance (Ti) remaining inside the processing chamber 104 can be generated on the wafer 112 used for aging or in the state of no wafer 112, and detected by the luminescence of the plasma. The detection of the metal substance is carried out using Fig. 6. Fig. 6 is a timing chart showing the luminescence intensity caused by Ti when a plasma is generated using a gas containing BC13 in the embodiment shown in Fig. 1. In the present embodiment, the illuminating intensity is analyzed using the illuminating data processing device 124. In particular, the illuminating material detected during the etching process of the wafer 112 on which the metal substance is disposed on the surface of the memory device disposed in the internal memory device is read by the arithmetic device disposed therein, and the specific metal substance is subjected to the specific metal substance. The integration process of the luminescence data of the corresponding wavelength is performed, and the specific calculation including the integration process is performed, and the result of the display of the amount of Ti remaining in the processing chamber 104 is calculated and output as a signal, and the amount of Ti detected is as described above. The amount of Ti deposited on the inner surface of the processing chamber 104 or remaining inside the processing chamber 104 along with the processing of the wafer 112 is changed, and the etching rate of the wafer 112 having the material to be processed by the subsequent generation is changed. However, when the amount of Ti is larger than a certain enthalpy, the etching rate gradually approaches a certain enthalpy and becomes saturated. The amount of Ti which is in a saturated state is obtained in advance for a long period of time in a saturated state, and the luminescence data in the processing chamber 104 is analyzed for the etching process of the film on the wafer 112 containing the metal substance on the surface. In the middle, and after the wet cleaning is performed, the difference in the luminous intensity of the wafer on which the metal-containing film is disposed on the surface is compared, and the end point of the aging before the saturation state is detected. . Further, in the present embodiment, a gas series containing BC13 is used, but the same measurement can be carried out using a rare gas system such as Ar. Fig. 7 is a view showing the TiN film and the high-k material in the embodiment shown in Fig. 1 before the treatment of the material to be processed on the wafer surface of the product, when the aging treatment is not performed and the etching step of TiN is performed. After the aging treatment of the film and the aging of the plasma luminescence, the etching rate of the polycrystalline germanium film 203 is changed by etching, and the treatment of the laminated film of the TiN film and the high-k material is performed in three cases. The smallest, is implemented in a stable process. As described above, the treatment of the film of the high-k material is performed using the treatment containing BC13. In the treatment using the gas, BC13 has the property of removing Ti remaining in the processing chamber 104. Therefore, it is understood that in order to adjust the residual Ti in the processing chamber 104 in the pre-existing aging treatment, the time ratio or the discharge condition between the etching process of the TiN film and the etching process of the material film is determined according to the signal obtained by the electric detection. Adjustment is important. In this case, the amount of residual or deposited substance (Ti) in the processing chamber 104 is adjusted to a desired amount by pre-aging treatment. Further, when the amount of Ti remaining in the processing chamber 104 is controlled, the wafer 112 having the material of the film structure having the film layer structure is etched by the metal film 203 and the high-k film 204 at a higher rate than before. Although the gas 1 12 table only carries out the end point of the product. When entering medium speed, containing gas, and internal residual amount, high-k slurry luminescence can be formed by TiN film/high-k material in Ti aging by means of metal or by ratio of 20% or less in 201029064. The processing time ratio of the film is processed, and thus, the residual distribution of Ti inside the processing chamber 104 deposited in the aging is also equivalent to that when the actual material to be processed is processed. This can also be obtained by the following process: that is, the composition of the film composed of the TiN film/high-k material in the pre-aging treatment, and the composition of the material to be treated are set to be equal, in the TiN film/ In the processing of the film formed of the high-k material, the luminescence intensity of the metal substance in the plasma inside the processing chamber 104, and the processing rate of the wafer 112 for the article having the material to be processed, in particular, the etching rate thereof When the processing conditions are equal, the luminous intensity obtained in the steady state is equal, and the processing of the wafer 112 in the pre-aging processing is performed. In addition, the processing conditions including the composition of the processing gas used when the film of the TiN film/high-k material is processed in the pre-aging treatment can be obtained by the following processing, and The processing conditions of the wafers 112 having the materials to be processed are the same, or substantially the same, and the simulation degrees are equal. The pre-aging aging treatment described above is composed of two or more steps. By performing the above processing, the amount or distribution of Ti remaining in the processing chamber 104 can be adjusted with higher precision, and the stability of the process can be improved. As described above, in the above-described embodiment, before the treatment of the material to be processed having the laminated structure of the metal film 203 and the high-k film 204, the material having the metal film 203 included in the surface and the material to be processed is The wafer of the film of the same substance is subjected to processing, the film is etched, and the amount of the metal substance remaining inside the processing chamber 104 is detected by monitoring the light emission in the processing chamber, or the detection result is used to adjust the processing. -19 - 201029064 The condition is such that the amount of the metal substance remaining inside the processing chamber 104 is stabilized, so that the variation of the shape obtained by the processing result can be suppressed, and the stability of the CD 加工 after processing can be improved, and the treatment can be provided. A device or method of etch processing that has a higher yield and less variation over time. Since the amount of the metal substance remaining inside the processing chamber 104 is stabilized, it is possible to suppress variations in the process caused by the metal substance and to suppress the variation of the CD. Further, in the present embodiment, although the embodiment of the ECR plasma device is specifically described, the present invention is applied to other plasma generating devices or methods, such as inductively coupled plasma (ICP) and capacity coupled plasma (CCP). The same effect can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a longitudinal sectional view showing a microwave ECR etching apparatus according to an embodiment of the present invention. Fig. 2 is a longitudinal sectional view showing the structure of the material to be processed which is processed in the embodiment of Fig. 1; Fig. 3 is a distribution diagram showing the results of measurement of the etching rate of polycrystalline silicon (Poly-Si) after wafer processing when the material to be processed of the metal/high-k laminated structure is processed by a conventional technique. 4 is a test sample in which the inner wall of the processing chamber is disposed and treated as the same member. When the film layer containing the metal film 203 and the film layer containing no metal film 203 are processed, each sample is measured by XPS (Xray photo-electron spectroscopy). The distribution of the results of the surface. -20- 201029064 Figure 5 shows the etching of polysilicon in other wafers after the etching process of a plurality of wafers is continuously performed on the wafer with the etching time of the metal film and high_k film as shown in Fig. 2 as parameters. The resulting distribution of the rate of processing. Fig. 6 is a graph showing temporal changes in luminescence intensity caused by Ti when a plasma is generated using a treatment gas containing BC13 in the embodiment shown in Fig. 1. Fig. 7 is a view showing the process of the embodiment shown in Fig. 1, in which the processing of the material to be processed on the surface of the wafer 丨丨2 of the product is not performed, and when the processing of the TiN is performed only, After the aging treatment of the laminated film of the TiN film and the high-k material and the determination of the end point of the aging by the plasma luminescence, the etch rate change pattern when the polycrystalline germanium film 203 is processed is etched. [Description of main component symbols] 101: Vacuum vessel 102: Air jet plate: : Dielectric window 104: Processing chamber 105 - Gas supply device 106: Vacuum exhaust port: Waveguide 108: Cavity resonator: Electric field generation Power supply 1 1 '·' Magnetic field generating coil 1 1 1 : Wafer mounting electrode-21 - 201029064 1 1 2 : Wafer 1 1 3 : Matching circuit 1 1 4 : High frequency power supply 1 1 5 : Filter 1 1 6 : DC power supply 1 1 7 : Flow path for refrigerant 1 18 : Thermostat 1 1 9 : 1 2 2 : Heater 1 2 0 : Heating controller 1 2 1 : Temperature sensor 1 2 3 : Illumination beam splitter 124 : illuminating data processing device

Claims (1)

201029064 七、申請專利範面： ι· 一種電漿處理裝置，係具有配置於真空容器內之 處理室’使用該處理室內形成之電漿，對配置於該處理室 內的試料台上載置之晶圓施予處理者；其特徵爲： 針對上述晶圓上配置之具有金屬物質的膜、及其下方 配置的氧化膜或具有高介電係數之材料所構成之膜層，在 進行蝕刻處理前，事先進行其他晶圓之處理，該其他晶圓 Φ 爲表面具備有和上述金屬物質爲同種金屬之膜者，沈積該 金屬所構成之粒子之後處理上述晶圓上之上述膜層。 2·如申請專利範圍第1項之電漿處理裝置，其中 於上述其他晶圓之處理時使用上述處理室內之發光檢 測出上述金屬物質之量，依據該檢測結果，來調節該其他 晶圓之處理。 3. 如申請專利範圍第2項之電漿處理裝置，其中 上述其他晶圓之處理，係由至少2個步驟以上構成， φ 藉由和蝕刻上述晶圓之膜層時使用之氣體同等的氣體被進 行處理。 4. 如申請專利範圍第3項之電漿處理裝置，其中 各個步驟之步驟時間比，係設爲蝕刻上述晶圓之膜層 時之蝕刻時間比的±20%以內。 5. 如申請專利範圍第1至4項中任一項之電漿處理 裝置，其中 上述事先進行之其他晶圓之處理，係對上述處理室內 實施溼式潔淨之後被進行。 -23- 201029064 6.如申請專利範圍第1至5項中任一項之電漿處理 裝置，.其中 上述金屬之物質具有TiN，上述具有高介電係數之材 料爲Hf02，於該蝕刻時至少使用BC13氣體。 7· —種電漿處理方法，係針對配置於真空容器內之 處理室內的試料台上載置之晶圓，於該處理室內形成電漿 施予處理者；其特徵爲： 針對上述晶圓上配置之具有金屬物質的膜、及其下方 配置的氧化膜或具有高介電係數之材料所構成之膜層，在 進行蝕刻處理前，事先進行其他晶圓之處理，該其他晶圓 爲表面具備有和上述金屬物質爲同種金屬之膜者，沈積該 金屬所構成之粒子之後處理上述晶圓上之上述膜層。 8. 如申請專利範圍第7項之電漿處理方法，其中 於上述其他晶圓之處理時，使用上述處理室內之發光 檢測出上述金屬物質之量，依據該檢測結果，來調節該其 他晶圓之處理。 9. 如申請專利範圍第8項之電槳處理方法，其中 上述其他晶圓之處理，係由至少2個步驟以上構成， 藉由和蝕刻上述晶圓之膜層時使用之氣體同等的氣體被進 行處理。 10. 如申請專利範圍第9項之電漿處理方法，其中 上述各個步驟之步驟時間比，係設爲蝕刻上述晶圓之 膜層時之蝕刻時間比的±20%以內。 11. 如申請專利範圍第7至10項中任一項之電漿處 -24- 201029064 理方法，其中 上述事先進行之其他晶圓之 實施溼式潔淨之後被進行。 1 2 ·如申請專利範圍第7至 理方法，其中 上述金屬之物質具有TiN， 料爲Hf02，於該蝕刻時至少使用 蠢理，係對上述處理室內 11項中任一項之電漿處 匕述具有高介電係數之材 BC13氣體。201029064 VII. Patent application: ι· A plasma processing device having a processing chamber disposed in a vacuum chamber, using a plasma formed in the processing chamber, and depositing a wafer on a sample stage disposed in the processing chamber a processor for treating a film having a metal substance disposed on the wafer, an oxide film disposed therebelow, or a material having a high dielectric constant, before performing an etching process The other wafer is processed by a film having the same metal as the metal material on the surface, and the film formed of the metal is deposited, and then the film layer on the wafer is processed. 2. The plasma processing apparatus according to claim 1, wherein the amount of the metal substance is detected by using the light emission in the processing chamber during the processing of the other wafer, and the other wafer is adjusted according to the detection result. deal with. 3. The plasma processing apparatus according to claim 2, wherein the processing of the other wafer is performed by at least two steps, and φ is equivalent to a gas used for etching a film layer of the wafer. It is processed. 4. The plasma processing apparatus of claim 3, wherein the step time ratio of each step is within ±20% of the etching time ratio when etching the film layer of the wafer. 5. The plasma processing apparatus according to any one of claims 1 to 4, wherein the processing of the other wafers previously performed is performed after performing wet cleaning in the processing chamber. The plasma processing apparatus according to any one of claims 1 to 5, wherein the metal material has TiN, and the material having a high dielectric constant is Hf02, and at least the etching is performed. Use BC13 gas. 7. A plasma processing method for forming a wafer placed on a sample stage disposed in a processing chamber in a vacuum container, and forming a plasma application processor in the processing chamber; wherein: the wafer is disposed on the wafer a film formed of a film having a metal substance, an oxide film disposed therebelow, or a material having a high dielectric constant, and previously processed by another wafer before being subjected to an etching process, the other wafer having a surface And the metal material is a film of the same metal, and after depositing the particles composed of the metal, the film layer on the wafer is processed. 8. The plasma processing method of claim 7, wherein in the processing of the other wafers, the amount of the metal substance is detected by using the light emission in the processing chamber, and the other wafer is adjusted according to the detection result. Processing. 9. The method of processing an electric paddle according to claim 8, wherein the processing of the other wafer is performed by at least two steps, and a gas equivalent to a gas used for etching the film layer of the wafer is used. Process it. 10. The plasma processing method according to claim 9, wherein the step time ratio of each of the above steps is within ±20% of an etching time ratio when etching the film layer of the wafer. 11. The plasma treatment method of any one of claims 7 to 10, wherein the other wafers previously performed are wet cleaned. 1 2 · The method of claim 7 to claim 7, wherein the metal material has TiN and the material is Hf02, and at least the stupidity is used in the etching, and the plasma is in any one of the above 11 processing chambers. The material BC13 gas having a high dielectric constant is described. -25-25
TW098105258A 2009-01-30 2009-02-19 Plasma processing device and plasma processing method TWI442468B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009018958A JP5377993B2 (en) 2009-01-30 2009-01-30 Plasma processing method

Publications (2)

Publication Number Publication Date
TW201029064A true TW201029064A (en) 2010-08-01
TWI442468B TWI442468B (en) 2014-06-21

Family

ID=42398059

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098105258A TWI442468B (en) 2009-01-30 2009-02-19 Plasma processing device and plasma processing method

Country Status (3)

Country Link
US (2) US8236701B2 (en)
JP (1) JP5377993B2 (en)
TW (1) TWI442468B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI463522B (en) * 2011-07-06 2014-12-01 Tokyo Electron Ltd An antenna, a battery window, a plasma processing device, and a plasma processing method
TWI478204B (en) * 2012-08-24 2015-03-21 Hitachi High Tech Corp Plasma processing device and plasma processing method
TWI492262B (en) * 2013-06-06 2015-07-11 Hitachi High Tech Corp Plasma processing device and plasma processing method

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5377993B2 (en) * 2009-01-30 2013-12-25 株式会社日立ハイテクノロジーズ Plasma processing method
US20130115778A1 (en) * 2011-11-04 2013-05-09 Applied Materials, Inc. Dry Etch Processes
JP6224359B2 (en) * 2013-06-20 2017-11-01 株式会社Ｓｃｒｅｅｎホールディングス Schedule creation method and schedule creation program for substrate processing apparatus
CN105917445B (en) 2014-01-13 2020-05-22 应用材料公司 Self-aligned double patterning with spatial atomic layer deposition
US9405089B2 (en) 2014-05-22 2016-08-02 Texas Instruments Incorporated High-temperature isotropic plasma etching process to prevent electrical shorts
JP6919350B2 (en) * 2017-06-09 2021-08-18 東京エレクトロン株式会社 Substrate processing method and substrate processing equipment
US10636686B2 (en) 2018-02-27 2020-04-28 Lam Research Corporation Method monitoring chamber drift

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6287977B1 (en) * 1998-07-31 2001-09-11 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
US6139702A (en) * 1999-03-05 2000-10-31 United Microelectronics Corp. Seasoning process for etcher
JP2002083974A (en) * 2000-06-19 2002-03-22 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2002025977A (en) * 2000-07-06 2002-01-25 Hitachi Ltd Dry etching method
US20030013314A1 (en) * 2001-07-06 2003-01-16 Chentsau Ying Method of reducing particulates in a plasma etch chamber during a metal etch process
JP4444569B2 (en) 2002-05-01 2010-03-31 ポリマテック株式会社 Key input device
US7094704B2 (en) * 2002-05-09 2006-08-22 Applied Materials, Inc. Method of plasma etching of high-K dielectric materials
JP4365109B2 (en) * 2003-01-29 2009-11-18 株式会社日立ハイテクノロジーズ Plasma processing equipment
JP4504061B2 (en) * 2004-03-29 2010-07-14 東京エレクトロン株式会社 Plasma processing method
US7598167B2 (en) * 2004-08-24 2009-10-06 Micron Technology, Inc. Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures
KR100598051B1 (en) * 2005-02-07 2006-07-10 삼성전자주식회사 Manufacturing method of semiconductor device
JP2007005381A (en) * 2005-06-21 2007-01-11 Matsushita Electric Ind Co Ltd Method and apparatus for plasma etching
JP4849881B2 (en) * 2005-12-08 2012-01-11 株式会社日立ハイテクノロジーズ Plasma etching method
DE102006055038B4 (en) * 2006-11-22 2012-12-27 Siltronic Ag An epitaxated semiconductor wafer and apparatus and method for producing an epitaxied semiconductor wafer
JP2009021584A (en) * 2007-06-27 2009-01-29 Applied Materials Inc High temperature material gate structure high temperature etching method
JP5377993B2 (en) * 2009-01-30 2013-12-25 株式会社日立ハイテクノロジーズ Plasma processing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI463522B (en) * 2011-07-06 2014-12-01 Tokyo Electron Ltd An antenna, a battery window, a plasma processing device, and a plasma processing method
TWI478204B (en) * 2012-08-24 2015-03-21 Hitachi High Tech Corp Plasma processing device and plasma processing method
TWI492262B (en) * 2013-06-06 2015-07-11 Hitachi High Tech Corp Plasma processing device and plasma processing method
US9336999B2 (en) 2013-06-06 2016-05-10 Hitachi High-Technologies Corporation Plasma processing apparatus and plasma processing method
US10192718B2 (en) 2013-06-06 2019-01-29 Hitachi High-Technologies Corporation Plasma processing apparatus and plasma processing method
US11004658B2 (en) 2013-06-06 2021-05-11 Hitachi High-Tech Corporation Plasma processing apparatus and plasma processing method

Also Published As

Publication number Publication date
US20120252200A1 (en) 2012-10-04
JP5377993B2 (en) 2013-12-25
US20100197137A1 (en) 2010-08-05
JP2010177480A (en) 2010-08-12
TWI442468B (en) 2014-06-21
US8236701B2 (en) 2012-08-07

Similar Documents

Publication Publication Date Title
TWI442468B (en) Plasma processing device and plasma processing method
TWI559395B (en) Plasma processing device and plasma processing method
TWI713683B (en) Plasma processing method
WO2005081302A1 (en) Method for cleaning treatment chamber in substrate treating apparatus and method for detecting endpoint of cleaning
JP2004172397A (en) Processing system and processing method for plasma
KR101046357B1 (en) Seasoning method of plasma processing apparatus and determination method of season termination
JP5750496B2 (en) Plasma processing method
US20140299576A1 (en) Plasma processing method and plasma processing apparatus
JP5853087B2 (en) Plasma processing method
US9691618B2 (en) Methods of fabricating semiconductor devices including performing an atomic layer etching process
JP2007324154A (en) Plasma treating apparatus
JP6169666B2 (en) Plasma processing method
JP4381694B2 (en) Sample surface treatment method
CN107710391B (en) Method for etching multilayer film
JP4464631B2 (en) Manufacturing method of semiconductor device
KR101066972B1 (en) Plasma treatment apparatus and plasma treatment method
TW201841089A (en) Method for inspecting flow controller and method for processing processed object for inspecting a flow controller by controlling the delay time of the flow controller in supplying intermittent gas
JPH10308352A (en) Plasma processing method and semiconductor device manufacturing method
JP6713298B2 (en) Plasma processing method and plasma processing apparatus
JP2002208586A (en) Plasma treatment apparatus with dielectric component
JP2004247388A (en) Plasma processing apparatus and processing method

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees