201027214 uoiwv/^xiW 28020twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種薄膜電晶體陣列基板(thin film transistor array substrate) ’且特別是有關於一種具有不共平 面之膜層所串接之資料線的薄膜電晶體陣列基板。 【先前技術】201027214 uoiwv/^xiW 28020twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor array substrate and in particular to A thin film transistor array substrate of a data line in which a planar film layer is connected in series. [Prior Art]
為因應現代產品高速度、高效能、且輕薄短小的要 求，各電子零件皆積極地朝體積小型化發展。各種攜帶式 電子裝置也已漸成主流，例如：筆記型電腦(n〇teb〇〇k)、行 動電話(cell phone)、電子辭典、個人數位助理器(pers〇nalIn response to the demands of modern products for high speed, high efficiency, light weight and shortness, all electronic components are actively moving toward miniaturization. A variety of portable electronic devices have also become mainstream, such as: notebook computers (n〇teb〇〇k), cell phone (cell phone), electronic dictionary, personal digital assistant (pers〇nal
Digital Assistant ’ PDA)、上網機(web pa(j)及平板型電腦 (遞贫PC)等。對於攜帶式電子裝置的影像齡器而言， 為了符合產品趨向小型化之需求，具有空間姻效率佳、 高晝質、低雜功率、無㈣等優越特性之平面顯示哭， 目前已被廣為使用，其中尤以液晶顯示师_町咖 display ; LCD)被廣泛使用。 列的ΪΐίΪ器通t包括掃描線、資料線以及多個陣列排 „.構，而各晝素結構中具有薄膜電 ^一之H素電極綠晶騎11巾社絲示區域， ΐ:重要:1素電極的佈局面積為影響開口 、隹而、食為了增加液晶顯示11的可顯示區域， 進而達到鬲開口率的需求，晝素電- 料線的上方。然而，由於*辛會延伸至相鄰資 易口電壓耗合效應而產生寄生電容 4 201027214 νοιυυυπιι W 28020twf.doc/nDigital Assistant 'PDA', surf machine (web pa(j) and tablet PC (poor PC), etc. For the age of the portable electronic device, in order to meet the demand for miniaturization of the product, it has space efficiency Good, high quality, low noise power, no (four) and other superior characteristics of the flat display crying, has been widely used, especially LCD display _ machica display; LCD) is widely used. The column Ϊΐ Ϊ 通 t 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 包括 t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t The layout area of the 1-electrode electrode is to affect the opening, the sputum, and the food in order to increase the displayable area of the liquid crystal display 11, thereby achieving the 鬲 opening rate requirement, above the halogen electric-feed line. However, since *Xin will extend to the phase Parasitic capacitance generated by the voltage-consumption effect of neighboring resources and easy port 4 201027214 νοιυυυπιι W 28020twf.doc/n
Capadt圆e)，崎生電容正比於晝素電極與資料線之間的 重豐面積，而反比於晝素電極與資料線之間的距離，因而 使得液晶顯示器容易產生串音現象的問題。 =之’圖1A為習知—種薄膜電晶體陣列基板的上 視不思圖，而圖1B為圖mA，剖面線的剖面示意圖。 所不’薄膜電晶體陣列基板100包括掃描 線以及多個陣列排列的晝素結構⑽，其 140^11^ 140 -η 、旦素電極15〇。如圖1A與圖1B所示，書 = 資料線120上方，資料線120與晝素電 極150之間僅具有單_絕緣層16〇，換言之 與晝素電極15〇之_轉僅約 、〇線 度，因，線120與晝素電㈣之間所產生寄生g 大’：：顯不器容易發生串音現象，影響顯示品質。 ❹ ❹Γίΐ"4薄膜電晶體陣列基板中晝素結構的串音 =彳崎雜軸減晝素電極的Φ積，使得金 工=物。然而，降低畫素電二二: =^ 率大幅下降，影響液晶顯示器的可顯示 '二Λ，何絲設計晝*結射畫素電麟資料緩 =度的? 口率，實為目前薄膜電晶體二ί; 路佈局(Layout)上亟待克服的課題。 孜在線 【發明内容】 本發月提供種薄膜電晶體陣列基板，其可以維持顯 5Capadt circle e), the Saki capacitance is proportional to the area of the abundance between the elemental electrode and the data line, and inversely proportional to the distance between the element electrode and the data line, thus making the liquid crystal display susceptible to crosstalk. Fig. 1A is a top view of a conventional thin film transistor array substrate, and Fig. 1B is a cross-sectional view of a cross section taken along line mA. The thin film transistor array substrate 100 includes a scanning line and a plurality of arrays of halogen structures (10) having a 140^11^140-η and a denier electrode 15〇. As shown in FIG. 1A and FIG. 1B, above the book=data line 120, there is only a single-insulating layer 16〇 between the data line 120 and the halogen electrode 150, in other words, only the 昼-turn with the halogen electrode 15 Degree, because, the parasitic g generated between line 120 and halogen electricity (four) is large ':: The display is prone to crosstalk and affects display quality. ❹ ❹Γίΐ"4 The crosstalk of the halogen structure in the thin film transistor array substrate = the Φ product of the 彳 杂 杂 昼 昼 昼 , , , , , , , , , , However, the reduction of pixel power 22: = ^ rate has dropped drastically, affecting the liquid crystal display can display 'two Λ, He silk design 昼 结 结 画 画 画 电 电 电 结 结 结 结 结 结 结 结 口 口 口 口 口 口 口 口 口 口 口 口Crystal ί; Layout on the topic to be overcome.孜 Online 【Abstract】 This month provides a thin film transistor array substrate, which can maintain the display 5
201027214 υ〇1υυυΗ11^ 28020twf.doc/n 示率並有效降低串音現象。 本發明提出一種薄膜電晶體陣 二置=%:=多條資料線與多個= 排列且相一導線與第二導線彼此平行 列，筮·道弟—蜍線與第二導線是彼此交替地排 f，d:越掃描線，第一導線位於兩相鄰掃描線之 二導線與第二導線分職第—導電層與第二導電層 斤'、且成’且第-導電層與基板之_距離小於第二導電層 :、基板=間的距離。各晝素結構包括薄膜電晶體以及畫素 電極。㈣電晶體麟應之掃Lx及職之各第二導線 電性連接。晝素電極與薄膜電晶體電性連接，晝素電極的 至少部分延伸至相鄰之第一導線上方。 々在本發明之一實施例中，薄膜電晶體陣列基板更包括 第一絕緣層以及第二絕緣層，其中第一絕緣層覆蓋第一導 ，層，且第二絕緣層覆蓋第二導電層以及薄膜電晶體。此 時，在晝素電極與對應之第一導線之間具有第一絕緣層以 及第二絕緣層所構成的疊層。 在本發明之一實施例中，薄膜電晶體陣列基板更包括 跳線層，且位於第一導線上方的第—絕緣層與第二絕緣層 具有多個第一接觸窗，以分別暴露出各第一導線的兩端， 而位於第二導線上方的第二絕緣層具有多個第二接觸窗’ 以分別暴露出各第二導線的兩端’跳線層藉由各第一接觸 έι以及各苐二接觸窗而電性連接於各第一導線與各第二導 201027214 …v一ilW 28020twf.doc/j 線之間’其中第—導線與第二導線在投影面積上不重爲， 而跳線層的組成與畫素電極的組成相同。 " 在本發明之一實施例中，上述之第—導線 在投影方向上至少部分重疊，且位於各第—導線與各第1 導線重疊區域内的第—絕緣層具有—開口 : 由開口與各第-導線連接》 弟-導線猎 在本發明之一實施例中，上述之各薄膜電晶體具有間201027214 υ〇1υυυΗ11^ 28020twf.doc/n rate and effectively reduce crosstalk. The invention provides a thin film transistor array two-set=%:=multiple data lines and a plurality of=arranged and the one-phase wire and the second wire are parallel to each other, and the 道·Dao-蜍 line and the second wire are alternately arranged with each other. Row f, d: the scan line, the first wire is located on the two adjacent scan lines, the second wire and the second wire are divided into the first conductive layer and the second conductive layer, and the first conductive layer and the substrate The distance is less than the distance between the second conductive layer: and the substrate. Each of the halogen structures includes a thin film transistor and a pixel electrode. (4) The electric crystal Lin should sweep the Lx and the second wire of the job to be electrically connected. The halogen electrode is electrically connected to the thin film transistor, and at least a portion of the halogen electrode extends over the adjacent first wire. In one embodiment of the present invention, the thin film transistor array substrate further includes a first insulating layer and a second insulating layer, wherein the first insulating layer covers the first conductive layer, and the second insulating layer covers the second conductive layer and Thin film transistor. At this time, a laminate of a first insulating layer and a second insulating layer is provided between the halogen electrode and the corresponding first wire. In an embodiment of the invention, the thin film transistor array substrate further includes a jumper layer, and the first insulating layer and the second insulating layer above the first conductive layer have a plurality of first contact windows to respectively expose the first a second insulating layer above the second wire has a plurality of second contact windows ′ to expose two ends of each of the second wires respectively. The jumper layer is provided by each of the first contacts and each of the wires Two contact windows are electrically connected between each of the first wires and each of the second leads 201027214 ...v-ilW 28020twf.doc/j line, wherein the first wire and the second wire are not heavy on the projected area, and the jumper The composition of the layer is the same as that of the pixel electrode. In an embodiment of the invention, the first conductive wires at least partially overlap in a projection direction, and the first insulating layer located in an overlapping region of each of the first conductive wires and each of the first conductive wires has an opening: Each of the first-wire connection is in the embodiment of the present invention, wherein each of the above-mentioned thin film transistors has an interval
極、通道層、源極以及汲極，各閉極與對應之掃描線連接， 各源極與對應之第二導線連接，各祕與各晝素電極連 接。此時’其中閘極是由第一導電層所組成，源極、汲極 以及第二導線是由第二導電層所組成，通道層之材質為非 晶矽。 ' ^ 在本發明之一實施例中，上述之各薄膜電晶體具有半 導體層，且半導體層具有一與第二導線電性連接之源極區 以及一與晝素電極電性連接之汲極區。 在本發明之一實施例中，上述之第一導線與第二導線 不共平面，且第一導線的寬度實質上等於第二導線的寬度。 由於本發明之薄膜電晶體陣列基板中，將資料線劃分 為相互串接且不共平面的第一導線以及第二導線，藉由增 加第一導線與晝素電極之間的距離，有效被降低資料線與 晝素電極之間的寄生電容，並維持一定程度的可顯示區域。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 201027214 VO IV/、/、/**··!· x'W 28020twf.doc/n 【實施方式】 第一實施例 圖2為本發明一實施例之薄膜電晶體陣列基板的示意 圖，而圖3A與3B分別緣示為圖2中對應於A-A’以及B-B， 剖面線之剖面示意圖。請參照圖2、圖3A與圖3B，薄膜 電晶體陣列基板200是由多個晝素結構陣列排列於基板上 所組成，為方便說明，在圖中僅繪示兩個晝素結構作代表。The pole, the channel layer, the source and the drain are connected to the corresponding scan lines, and the sources are connected to the corresponding second wires, and the secrets are connected to the respective pixel electrodes. At this time, the gate is composed of a first conductive layer, and the source, the drain and the second wire are composed of a second conductive layer, and the channel layer is made of a non-crystal. In one embodiment of the present invention, each of the thin film transistors has a semiconductor layer, and the semiconductor layer has a source region electrically connected to the second wire and a drain region electrically connected to the halogen electrode. . In an embodiment of the invention, the first wire and the second wire are not coplanar, and the width of the first wire is substantially equal to the width of the second wire. In the thin film transistor array substrate of the present invention, the data line is divided into the first wire and the second wire which are connected in series and are not coplanar, and the distance between the first wire and the halogen electrode is effectively reduced. The parasitic capacitance between the data line and the halogen electrode maintains a certain degree of displayable area. The above and other objects, features, and advantages of the present invention will become more apparent <RTIgt; 201027214 VO IV/, /, /**···· x'W 28020twf.doc/n [Embodiment] FIG. 2 is a schematic diagram of a thin film transistor array substrate according to an embodiment of the present invention, and FIG. 3A The relationship with 3B is shown as a cross-sectional view of the hatching corresponding to A-A' and BB in Fig. 2, respectively. Referring to FIG. 2, FIG. 3A and FIG. 3B, the thin film transistor array substrate 200 is composed of a plurality of halogen structure arrays arranged on a substrate. For convenience of description, only two halogen structures are represented in the figure.
請參照圖2、圖3A與圖3B ’薄膜電晶體陣列基板2〇〇 主要是由一基板210、多條掃描線220、多條資料線230 與多個畫素結構240所構成’且多條掃描線22〇、多條資 料線230與多個晝素結構240配置在基板21〇上。掃描線 220由第一導電層Ml所組成。各資料線23〇主要是由多 條彼此串接且交錯排列的第一導線232以及第二導線234 所組成，其中第一導線232與第二導線234分別由第一導 電層Ml與第二導電層M2所組成，且第一導電層Μι與 第二導電層M2分屬不同膜層，換言之，第一導電層 與第二導電層M2不共平面。在本實施例中，第-導線232 的寬度實質上等於第二導線234的寬度。此外，第一導電 f Ml與第二導電層M2可以選用相同或不同組成的導體 材料，例如H鈦、上述氮化物或上述任—組合本 如圖2所7F ’第二導線234跨越掃描線22G，而第- 則位於兩相鄰掃描線22〇 包括薄膜電晶體25〇 ~ 乂及晝素電極260，其中薄膜電晶體 201027214 --------iW 28020twfd〇c/n 參 250與對應之掃氣線22〇以及對應之各第二導線说電性 連接，晝素電極260與薄膜電晶體250電性連接，且書 電極260部分延伸至相鄰之第一導線232上方。…、 q繼續參照圖2、圖3A與圖3B，值得一提的是，不同 於習知，在本發明之薄膜電晶體陣列基板2〇〇中令妗 掃描線220的資料線23〇區域為第二導線234，且其^ ，位於第-導電層M1上方的第二導電層M2，用以傳 料線23G的訊號。並且，本發明令位於_鄰掃描線挪 之間且與晝素電極細主要重疊的資料線細區域為第一 232 ’且第-導線232纟要是由與晝素電極細相距 較㈣第一導電層M1所構成’使得晝素電極260盥資料 =30之間具有由第-絕緣層270以及第二絕緣層28= 、的疊層’換吕之’畫素電極26〇與資料線細之間的 距離為第-絕緣層27()以及第二職層挪之厚度的總 此純於f知，本發明之薄膜電基板· 猎由拉長晝素電極26〇與資料線23〇之間的距離使 ，電極260與資料線23〇之間的寄生電容降低，進^ 減少串音現象的發生。 负 值侍-提的是’在本實施例中，薄膜電晶體25〇屬於 :種底閘極型薄膜電晶體，如圖2所示。具體而言，薄膜 '晶體250具有閘極252、通道層254、源極256以及没極 Π處各閑極252與對應之掃描線220連接，各源極256 :鱼/之第二導線234連接’各没極258與各畫素電極260 連接。此時’其中閘極议是由第一導電層奶所組成， 28020twf.doc/n 201027214 源極256、汲極258以及第二導線234是由第二導電層M2 所組成，通道層254之材質為非晶矽。並且，如圖3ΘΒ所 示，第一絕緣層270覆蓋第一導電層M1，且第二絕緣層 280覆蓋第二導電層]y[2以及薄膜電晶體250。 為清楚說明各構件在基板上的相對位置，以下將以圖 2、圖3A以及圖3B之薄膜電晶體陣列基板2〇〇為例，簡 單說明薄膜電晶體陣列基板2〇〇的製作流程。請同時參照 圖2、圖3A以及圖3B。首先，於基板21〇上沈積一第一 導電層Ml，接著進行第一導電層M1的圖案化製程，以於 基板210上形成多條掃描線22〇、多個閘極252以及位於 兩相鄰掃描線220之間的第一導線232。接著，形成第一 絕緣層270以覆蓋該些掃描線22〇、該些閘極252 些第一導線232。之後，於基板21〇上進行第二導電層 的圖案化製程’錄第-職層，上形❹二導線 234、多個源極256以及多個汲極258。接著，形成第二絕 緣層28G以覆盍多條第一導線234、多個源極Μ6以及多 ，沒極258，並接著進行該些接觸窗的圖案化製程，以於 第-絕緣層27G中形成第—接觸窗m以暴露各一導 2*32的部分’並且第二絕緣層，中形成對應各第一接觸 齒H1的開口以暴露各第一導線232的部分，且 層具有第二接觸窗H2以暴露各第二導線234的部分。 之後’與第二絕緣層28G上形成多個晝素電極以及多 個跳線層29G ’其中各跳線層，分別經㈣—接觸窗m 以及第二接觸窗H2與第-導線232以及第 10 201027214 voiv/uunifW 28020twf.doc/n 性連接。 承上述，如圖3A所示，對於上層的晝素電極26〇而 言，由於第一導線232相較於圖3B之第二導線234屬於 較下層的第一導體層M1 ’依據寄生電容值與二電極之間 的距離成反比之關係’本發明將資料線230區域中主要與 晝素電極260重疊的區域，規劃為畫素結構組成臈層中屬 雜下層的第-導線232，如此一來，可以使得晝素電極 ❹ 260與資料、線230之間的重疊面積在不縮減下，降低晝素 260與資料線230之間的寄生電容，進而有效減^串 音現象的發生。 基於實際的製程良率考量，如圖3B所示，在本實施 =中’第-導線232與第二導線234在投影方向上並不重 且而疋利用跳線層290電性連接於第一導線232與第二 ，線234之間。詳言之，請同時參照圖2與圖3B，位於第 導線232上方的第一絕緣層27〇與第二絕緣層28〇具有 ^個第一接觸窗H1 ’以分別暴露出各第-導線232的兩 巧’而位於第二導線M4上方的第二絕緣層2S〇具有多個 第二接觸+窗H2 ’以分別暴露出各第二導線234的兩端，跳 線層290藉由各第一接觸窗m以及各第二接觸窗H2而電 性連接於各第一導線232與各第二導線234之間。實務上， 跳線層290可選用與晝素電極260組成相同的材質，換言 之，跳線層290與晝素電極260可利用同一道光罩製程製 作完成。 圖3C為本發明第一實施例中沿圖2 BB，剖面線另一種 11 201027214 28020twf.d〇c/nReferring to FIG. 2, FIG. 3A and FIG. 3B, the thin film transistor array substrate 2 is mainly composed of a substrate 210, a plurality of scanning lines 220, a plurality of data lines 230, and a plurality of pixel structures 240. The scan line 22A, the plurality of data lines 230, and the plurality of pixel structures 240 are disposed on the substrate 21A. The scanning line 220 is composed of a first conductive layer M1. Each of the data lines 23 〇 is mainly composed of a plurality of first wires 232 and second wires 234 which are serially connected and staggered, wherein the first wires 232 and the second wires 234 are respectively formed by the first conductive layer M1 and the second conductive layer. The layer M2 is composed, and the first conductive layer 与1 and the second conductive layer M2 belong to different film layers. In other words, the first conductive layer and the second conductive layer M2 are not coplanar. In the present embodiment, the width of the first wire 232 is substantially equal to the width of the second wire 234. In addition, the first conductive f M1 and the second conductive layer M2 may be selected from the same or different composition of the conductor material, such as H titanium, the above nitride or any of the above-mentioned combinations, as shown in FIG. 2, the second wire 234 spans the scan line 22G. And the first-position is located on two adjacent scan lines 22A including a thin film transistor 25〇~乂 and a halogen electrode 260, wherein the thin film transistor 201027214 --------iW 28020twfd〇c/n 参250 corresponds to The scavenging wire 22〇 and the corresponding second wires are electrically connected, the halogen electrode 260 is electrically connected to the thin film transistor 250, and the book electrode 260 portion extends over the adjacent first wire 232. Referring to FIG. 2, FIG. 3A and FIG. 3B, it is worth mentioning that, unlike the conventional method, in the thin film transistor array substrate 2 of the present invention, the data line 23〇 region of the scan line 220 is The second wire 234, and the second conductive layer M2 located above the first conductive layer M1, is used to transmit the signal of the line 23G. Moreover, the present invention causes the data line fine area located between the adjacent scan lines and mainly overlapping with the halogen element to be the first 232 ′ and the first conductive line 232 is finely spaced from the halogen element (four) first conductive The layer M1 is formed such that the pixel electrode 260 盥 data=30 has a layer of the first insulating layer 270 and the second insulating layer 28=, and the 'electrode element 26' The distance between the first insulating layer 27 () and the thickness of the second layer is generally pure, and the thin film electrical substrate of the present invention is between the elongated halogen electrode 26 and the data line 23 The distance between the electrode 260 and the data line 23A is reduced, and the occurrence of crosstalk is reduced. The negative value is that in the present embodiment, the thin film transistor 25 〇 belongs to a seed gate type thin film transistor, as shown in FIG. Specifically, the thin film 'crystal 250 has a gate 252, a channel layer 254, a source 256, and each of the idle electrodes 252 connected to the corresponding scan line 220, and each source 256: fish/second wire 234 is connected. 'The respective poles 258 are connected to the respective pixel electrodes 260. At this time, 'the gate is composed of the first conductive layer of milk, 28020twf.doc/n 201027214 source 256, the drain 258 and the second wire 234 are composed of the second conductive layer M2, the material of the channel layer 254 It is amorphous. Also, as shown in FIG. 3A, the first insulating layer 270 covers the first conductive layer M1, and the second insulating layer 280 covers the second conductive layer]y[2 and the thin film transistor 250. In order to clearly explain the relative positions of the members on the substrate, the fabrication process of the thin film transistor array substrate 2 will be briefly described below by taking the thin film transistor array substrate 2 of Figs. 2, 3A and 3B as an example. Please refer to FIG. 2, FIG. 3A and FIG. 3B at the same time. First, a first conductive layer M1 is deposited on the substrate 21, and then a patterning process of the first conductive layer M1 is performed to form a plurality of scan lines 22, a plurality of gates 252, and two adjacent layers on the substrate 210. The first wire 232 between the scan lines 220. Next, a first insulating layer 270 is formed to cover the scan lines 22 and the gates 252 of the first wires 232. Thereafter, a patterning process of the second conductive layer is performed on the substrate 21A, and the second layer 234, the plurality of sources 256, and the plurality of drain electrodes 258 are formed. Next, a second insulating layer 28G is formed to cover the plurality of first conductive lines 234, the plurality of source electrodes 6 and the plurality of gates 258, and then the patterning process of the contact windows is performed to be in the first insulating layer 27G. Forming a first contact window m to expose portions of each of the leads 2*32 and a second insulating layer in which openings corresponding to the respective first contact teeth H1 are formed to expose portions of the respective first wires 232, and the layer has a second contact Window H2 exposes portions of each of the second wires 234. Then, a plurality of halogen electrodes and a plurality of jumper layers 29G are formed on the second insulating layer 28G, wherein each of the jumper layers passes through the (four)-contact window m and the second contact window H2 and the first-wire 232 and the tenth 201027214 voiv/uunifW 28020twf.doc/n Sexual connection. As described above, as shown in FIG. 3A, for the upper layer of the halogen electrode 26, since the first wire 232 is lower than the second wire 234 of FIG. 3B, the first conductor layer M1' of the lower layer is based on the parasitic capacitance value. The relationship between the two electrodes is inversely proportional to the relationship. The present invention divides the region of the data line 230 that mainly overlaps the halogen electrode 260, and is planned to be a pixel-structure constituting the first-wire 232 of the eucalyptus layer. The overlapping area between the pixel electrode 260 and the data and the line 230 can be reduced without reducing the parasitic capacitance between the pixel 260 and the data line 230, thereby effectively reducing the occurrence of crosstalk. Based on the actual process yield considerations, as shown in FIG. 3B, in the present embodiment, the 'first-wire 232 and the second wire 234 are not heavy in the projection direction and are electrically connected to the first by the jumper layer 290. Wire 232 is between the second and line 234. In detail, referring to FIG. 2 and FIG. 3B simultaneously, the first insulating layer 27A and the second insulating layer 28's above the second conductive layer 232 have a first contact window H1' to expose the respective first wires 232, respectively. The second insulating layer 2S located above the second wire M4 has a plurality of second contacts + windows H2' to expose both ends of the second wires 234, respectively, and the jumper layer 290 is first The contact window m and each of the second contact windows H2 are electrically connected between each of the first wires 232 and each of the second wires 234. In practice, the jumper layer 290 can be made of the same material as the halogen electrode 260. In other words, the jumper layer 290 and the halogen electrode 260 can be fabricated by the same mask process. 3C is another cross section of FIG. 2B in the first embodiment of the present invention. 11 201027214 28020twf.d〇c/n
UOU/Ul/^lI W 實施型態的剖面示意圖。請參照圖2與圖3C，設計者亦可 ，於降低資料線230之阻容遲滯現象(RC delay)的考量，將 第—導線232的部分區域與第二導線234重疊，並在重疊 2直接相接。詳言之，第一導線232與第二導線234在投 二方白上八有至少部分重豐區域，且位於此重疊區域内的 第一絕緣層270具有一開口 272,第二導線234藉由開口 272與第一導線232直接連接。因此，UOU/Ul/^lI W Schematic diagram of the implementation. Referring to FIG. 2 and FIG. 3C, the designer can also reduce the RC delay of the data line 230 by overlapping the partial area of the first wire 232 with the second wire 234 and directly overlap the 2 wires. Docked. In detail, the first wire 232 and the second wire 234 have at least partially overlapping regions on the white square, and the first insulating layer 270 located in the overlapping region has an opening 272, and the second wire 234 is The opening 272 is directly connected to the first wire 232. therefore,
-導線说與第二導線234電性連接的方式。不阳疋弟 第二實施例 圖4為本發明一實施例之薄膜電晶體陣列基板的示意 ，而圖5A與5B分別緣示為圖4中對應於A_A，以及B b， 剖面線之剖®示意圖。為了簡化刻，在此不再對該些與 圖2、圖3A與圖3B所示之構件類似的部份加以說明。與 =2、圖3A與圖3B相較’本實施例之薄膜電晶體陣列基 板_中的薄膜電晶體350屬於頂閘型薄膜電晶體，頂閘 型薄膜電晶體包含單閘極多晶⑦薄膜電晶體、制極多晶 Π膜電晶體或其它電晶體。在本實施例中，薄膜電晶體 50是以多晶矽薄膜電晶體為範例，但並不限於此。 圖6為圖4中之薄膜電晶體沿cc,剖面線的局部剖面 I道請參照圖6,薄膜電晶體35〇具有一半導縣36〇，且 體層360具有一與第二導線234電性連接之源極區 以及-與晝素電極電性連接之汲極區364， 半導體層360之組成為多晶石夕，當然，薄膜^曰 體350尚具有閘極252。為清楚說明各構件之間的關係， 12 201027214 U8iuuu4ifW 28020twf.doc/n 以下將以圖4、圖5A以及圖5B之薄膜電晶體陣列基板300 為例，簡單說明薄膜電晶體陣列基板300的製作流程。 請同時參照圖4、圖5A、圖5B以及圖6。首先，於 基板210上進行半導體層360的圖案化製程’並且於半導 體層360上覆蓋閘絕緣層370。之後，於閘絕緣層370上 進行第一導電層Ml的圖案化製程，以於基板21〇上形成 多條掃描線220、多個閘極252以及位於兩相鄰掃描線220 ⑩ 之間的第一導線232。並且’於半導體層36〇上進行離子 摻雜製程，使得半導體層360中經摻雜後的部分區域形成 非本徵半導體（Extrinsic Semiconductor)而分別構成源極 ，362以及汲極區364。接著，形成第一絕緣層27〇以覆 盍該些掃描線220、該些閘極252以及該些第一導線232， 其中第一絕緣層270,如圖5B所示，具有第一接觸窗Ηι 以暴露各第一導線232的部分，且第一絕緣層27〇具有分 別暴露出源極區362以及汲極區364的源極接觸窗/'Hs以 及汲極接觸窗Hd。 β 之後.，於基板210上進行第二導電層Μ:的圖案化製 程’以於第一絕緣層27〇上形成多條第二導線Μ4、多個 ，極祝以及多個没極258，其中_ 256透過源極 固Hs而與源極區3½連接’没極攻透過沒極接觸窗 而，汲極區364連接，且第二導線234與源極256連接。 接著’形成第二絕緣層280以覆蓋多條第二導線234 個源極256以及多個没極258，其中第二絕緣層㈣ 對應各第-接觸窗H1的開口以暴露各第一導線攻^ 13 201027214 υ» iuuu4ifW 28020twf.doc/n 分，第二絕緣層280具有第二接觸窗H2以暴露各第二導 線234的部分，並且第二絕緣層280具有第三接觸窗jj3 以暴露出沒極258。之後，於第二絕緣層28〇上形成多個 畫素電極260以及多個跳線層290，其中各跳線層29〇分 別經由第一接觸窗H1以及第二接觸窗H2與第一導線232 以及第二導線234電性連接，而晝素電極260經由第三接 觸窗H3而與汲極258連接。 ❹ 承上述，在本實施例中，對於上層的晝素電極260而 5，其與> 料線230重疊區域的第—導線232之間，同樣 具有兩層絕緣層加總的間距，如第—絕緣層27〇以及第二 絕緣層270 ’同樣也可以使得在不縮減晝素電極面& 的情況下，降低畫素電極260與資料線230之間的寄生電 容，進而有效減少串音現象的發生。 綜上所述，本發明之薄膜電晶體陣列基板因應資料 線所在位置，而將資料線適當劃分為 串 «及第二導線，並拉長畫素電極與第一導線之=距:線 罾 猎此’晝素電極與資料線間的寄生電容可以有效降低，因 此熟悉此技術領域之技術者在晝素結構的設計上，可以軚 不受寄生電容的限制，將晝素電極延伸至資料線上方，以 增加晝素之開口率’進而提升液晶顯示器的顯示亮度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 14 201027214 uoiuuuhiiW 28020twf.doc/n 為準。 【圖式簡單說明】 圖1A為習知—種薄膜電晶體陣列基板的上視示意 圖。 圖1B為圖1A沿AA’剖面線的剖面示意圖。 圖2為本發明一實施例之薄膜電晶體陣列基板的示意 圖。 參 圖3A與3B分別續示為圖2中對應於a_a，以及b_b， 剖面線之剖面示意圖。 圖3C為圖2沿BB’剖面線的另一種剖面示意圖。 圖4為本發明一實施例之薄膜電晶體陣列基板的示意 圖。 圖5A與5B分別繪示為圖4中對應於A-A，以及B七， 剖面線之剖面示意圖。 圖6為圖4中之薄膜電晶體沿CC，剖面線的局部剖面 圖。 〇 【主要元件符號說明】 100、200、300 :薄膜電晶體陣列基板 110、220 :掃描線 120、230 :資料線 130、240:畫素結構 140、350 :薄膜電晶體 150、260 :畫素電極 160 :絕緣層 201027214 u〇 i uv/uhi rw 28020twf.doc/n 210 :基板 232 :第一導線 234 :第二導線 250 :薄膜電晶體 252 :閘極 254 :通道層 256 :源極 258 :汲極 ® 270 :第-絕緣層 272 :開口 280 :第二絕緣層 290 ··跳線層 360 :半導體層 362 :源極區 364 · >及極區 370 :閘絕緣層 θ H1 :第一接觸窗 H2 :第二接觸窗 H3 :第三接觸窗 Hs :源極接觸窗 Hd :汲極接觸窗 Ml :第一導電層 M2 :第二導電層The way the wire is electrically connected to the second wire 234. Second Embodiment FIG. 4 is a schematic view of a thin film transistor array substrate according to an embodiment of the present invention, and FIGS. 5A and 5B are respectively shown in FIG. 4 corresponding to A_A and B b, and a section line of the cross section schematic diagram. In order to simplify the engraving, portions similar to those shown in Figs. 2, 3A and 3B will not be described here. Compared with =2, FIG. 3A and FIG. 3B, the thin film transistor 350 in the thin film transistor array substrate of the present embodiment belongs to a top gate type thin film transistor, and the top gate type thin film transistor includes a single gate polycrystalline 7 film. A transistor, a polycrystalline germanium film transistor or other transistor. In the present embodiment, the thin film transistor 50 is exemplified by a polycrystalline germanium thin film transistor, but is not limited thereto. 6 is a partial cross-sectional view of the thin film transistor of FIG. 4 along the line cc. Referring to FIG. 6, the thin film transistor 35 has a half lead 36 〇, and the bulk layer 360 has a second connection to the second lead 234. The source region and the drain region 364 electrically connected to the halogen electrode, the semiconductor layer 360 is composed of polycrystalline spine. Of course, the thin film body 350 further has a gate 252. In order to clearly explain the relationship between the members, 12 201027214 U8iuuu4ifW 28020twf.doc/n The film transistor array substrate 300 of FIGS. 4, 5A, and 5B will be taken as an example to briefly describe the fabrication process of the thin film transistor array substrate 300. . Please refer to FIG. 4, FIG. 5A, FIG. 5B and FIG. First, the patterning process of the semiconductor layer 360 is performed on the substrate 210 and the gate insulating layer 370 is covered on the semiconductor layer 360. Then, a patterning process of the first conductive layer M1 is performed on the gate insulating layer 370 to form a plurality of scan lines 220, a plurality of gates 252, and a portion between the adjacent scan lines 220 10 on the substrate 21A. A wire 232. And performing an ion doping process on the semiconductor layer 36, such that the doped regions of the semiconductor layer 360 are formed as extrinsic semiconductors to form the source, 362 and drain regions 364, respectively. Next, a first insulating layer 27 is formed to cover the scan lines 220, the gates 252, and the first wires 232, wherein the first insulating layer 270, as shown in FIG. 5B, has a first contact window The portions of the respective first wires 232 are exposed, and the first insulating layer 27 has source contact windows/'Hs and drain contact windows Hd exposing the source regions 362 and the drain regions 364, respectively. After β, a patterning process of the second conductive layer Μ is performed on the substrate 210 to form a plurality of second wires 4, a plurality of electrodes, and a plurality of gates 258 on the first insulating layer 27 _ 256 is connected to the source region 31⁄2 through the source solid Hs. The gate region 364 is connected, and the second wire 234 is connected to the source 256. Then forming a second insulating layer 280 to cover the plurality of second wires 234 source 256 and the plurality of gates 258, wherein the second insulating layer (4) corresponds to the opening of each of the first contact windows H1 to expose the first wires. 13 201027214 υ»iuuu4ifW 28020twf.doc/n, the second insulating layer 280 has a second contact window H2 to expose portions of the respective second wires 234, and the second insulating layer 280 has a third contact window jj3 to expose the gates 258 . Thereafter, a plurality of pixel electrodes 260 and a plurality of jumper layers 290 are formed on the second insulating layer 28, wherein each jumper layer 29 is respectively connected to the first wires 232 via the first contact window H1 and the second contact window H2. The second wire 234 is electrically connected, and the halogen electrode 260 is connected to the drain 258 via the third contact window H3. In the present embodiment, for the upper layer of the halogen electrode 260, and between the first wire 232 of the region overlapping with the > the material line 230, there is also a total spacing of two insulating layers, such as The insulating layer 27A and the second insulating layer 270' can also reduce the parasitic capacitance between the pixel electrode 260 and the data line 230 without reducing the surface of the pixel electrode, thereby effectively reducing crosstalk. happened. In summary, the thin film transistor array substrate of the present invention appropriately divides the data line into a string «and a second wire according to the position of the data line, and lengthens the distance between the pixel electrode and the first wire: The parasitic capacitance between the 'negative electrode and the data line can be effectively reduced. Therefore, those skilled in the art can extend the halogen element to the data line without being limited by the parasitic capacitance in the design of the pixel structure. In order to increase the aperture ratio of the sputum, thereby increasing the display brightness of the liquid crystal display. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope defined in the appended patent application, which is incorporated herein by reference. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a top plan view of a conventional thin film transistor array substrate. Fig. 1B is a schematic cross-sectional view taken along line AA' of Fig. 1A. Fig. 2 is a schematic view showing a thin film transistor array substrate according to an embodiment of the present invention. 3A and 3B are respectively shown as cross-sectional views corresponding to a_a and b_b in Fig. 2, and hatching. Fig. 3C is another schematic cross-sectional view taken along line BB' of Fig. 2. Fig. 4 is a schematic view showing a thin film transistor array substrate according to an embodiment of the present invention. 5A and 5B are respectively schematic cross-sectional views of the hatching corresponding to A-A and B7 in Fig. 4. Figure 6 is a partial cross-sectional view of the thin film transistor of Figure 4 taken along line CC. 〇 [Main component symbol description] 100, 200, 300: thin film transistor array substrate 110, 220: scan line 120, 230: data line 130, 240: pixel structure 140, 350: thin film transistor 150, 260: pixel Electrode 160: Insulation layer 201027214 u〇i uv/uhi rw 28020twf.doc/n 210: Substrate 232: First wire 234: Second wire 250: Thin film transistor 252: Gate 254: Channel layer 256: Source 258: Bungee® 270: first insulating layer 272: opening 280: second insulating layer 290 · jumper layer 360: semiconductor layer 362: source region 364 · > and polar region 370: gate insulating layer θ H1 : first Contact window H2: second contact window H3: third contact window Hs: source contact window Hd: drain contact window M1: first conductive layer M2: second conductive layer