TW201023299A - Method of forming stacked dies - Google Patents

Abstract

The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wafer substrate. The method generally reduces the risks of overly-thinning a wafer substrate in a wafer back-side grinding process typically used to expose and make electrical contacts to the TSVs. By providing deeper TSVs and bonding pads, individual wafers and dies may be bonded directly between the TSVs and bonding pads on an additional wafer.

Description

201023299 ' VI. EMBODIMENT OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method of fabricating an integrated circuit, and more particularly to a method of forming a stacked die having one or more through-via vias . [Prior Art] In general, the operating speed of an integrated circuit is affected by the distance between the components on the wafer that are most distant and can communicate with each other. The three-dimensional structure of the layout circuit has been confirmed to be effective in lowering the on-wafer component-communication path length, which provides a vertical distance between layers that is much smaller than the width of each layer of the wafer. Thus, by vertically stacking circuit layers, the overall wafer idle speed is typically increased. Such stacking has been carried out by means of wafer bonding. Wafer bonding is the joining of two or more semiconductor wafers on which integrated circuits have been formed. The wafer is usually bonded by means of direct bonding of the outer oxide layer or by adding a layer of electricity to the layer. The result of the bonding results in a three-dimensional wafer stack that is subsequently cut into individual stacked dies, (4) a stacked granule having a multi-layer integrated circuit. In addition to the advantages of increased speed typically found in three-dimensional structural circuitry, wafer stacking has other potential benefits, including improved form factors, low cost, and through system-on-system (soc) solutions. Larger degree of integration. In order to allow various components to be integrated into each of the stacked dies, an electrical connection is provided to provide a conductor between the vertical layers. Typically, when a through-hole window is fabricated, a via window that fills the conductor material is provided, and the vias are completely passed through the 201023299 • layer to contact and connect the TSVs and conductors of other bonding layers. In an existing TSV formation process, TSVs are formed after forming a complementary metal oxide semiconductor (CMOS) device on a wafer substrate, or even after an upper metallization process. A disadvantage of TSVs after CMOS or metallization processes is that the density of the vias is typically low due to etching and design constraints. Etching through the metallization layer typically does not create a recess and provides a particularly dense TSV. In addition, again because of the process etching through metallization and contact area, the design of the via is limited by the existing structure of the metallization layer and the contact area. Therefore, designers will usually have to design the TSV Network ® system around the existing metal layers and contact lines. These limited designs and densities can cause problems with connectivity, contact, and reliability. Another limitation of the existing TSV formation process is the limited depth of TSVs that can be formed in the wafer substrate. Due to the existing structure of the metallization layer, the conventional process for forming TSV openings in the wafer substrate is carried out to a limited depth in the wafer substrate, wherein the finite depth is much less than the thickness of the substrate. For example, a plasma machining process can generally be used to form a TSV opening having a depth ranging from substantially 25 micrometers to substantially 50 micrometers. The thickness of the substrate is substantially 700 micrometers compared to the thickness of a typical secondary crystal substrate. Back-grinding is typically used to thin the thickness of the wafer substrate to less than 1 μm and expose TSVs to connect the stacked dies. However, such an embodiment may reduce the mechanical strength of the wafer substrate, which is the solid foundation of the integrated circuit formed thereon. In addition, the excessively thinned wafer substrate is often damaged, thus seriously affecting the yield of the overall 1C product. SUMMARY OF THE INVENTION 201023299 The preferred embodiment of the present invention forms TSVs prior to metallization, and thus the suspension can solve or avoid the occurrence of these or other problems, and a technical advantage can be obtained. TSVs with larger aspect ratios and deeper into the wafer substrate can be fabricated. This approach substantially reduces the risk of wafer substrates being over-thinned during wafer back-grinding processes, where wafer back-grinding processes are typically used to expose and make electrical contacts to TSVs. By providing deeper TSVs and bonding, each wafer and die can be bonded directly between the TSVs and the bond pads on the other wafer. In accordance with a preferred embodiment of the present invention, a method of forming a stacked integrated circuit semiconductor die is provided, comprising the following steps. One or more recesses are formed in the first semiconductor wafer, and the recesses are filled with a conductor material to form one or a plurality of through vias in the first semiconductor wafer. Forming one or more bonding contacts on a front surface of the first semiconductor wafer, attaching a front surface of the first semiconductor wafer to a wafer carrier, and exposing the first semiconductor crystal The back of the circle. The back side of the first semiconductor wafer is thinned until the through via window is exposed and slightly protrudes from the back side. The through-via vias are aligned and bonded to one or more bonding contacts on the plurality of bonding surfaces on the second semiconductor die. In accordance with another preferred embodiment of the present invention, a method of forming a stacked semiconductor circuit die is provided, comprising the steps of: providing a first semiconductor wafer, wherein the semiconductor wafer has one or a plurality of via vias Formed in the substrate. A front surface of the first semiconductor wafer is attached to the wafer carrier and a back surface of the first semiconductor wafer is exposed. The first semiconductor crystal is thinned, and the straight (four) through-layer window is exposed and slightly protruded from 201023299. Forming a thinned back surface of the wafer = the first bonding contact is in the first semiconductor contact electrical coupling, 丨% i metallized insulating layer. The first and second bonding vias are described. Provided with - or a plurality of second semiconductor wafer members 111, the second bonding contact substrate wafer 叼镬 σ surface thereof. Aligning and engaging the first joint contact of the first joint on the first semiconductor circle. σ depends on the corresponding on the +-conductor workpiece. [Embodiment] The application and implementation of the preferred embodiment will be disclosed in detail below. However, it will be appreciated that the present invention provides many innovative concepts that are applicable, which can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Referring now to Figure 1, a cross-sectional view of the wafer 1 。 is shown. The wafer 1 〇 includes a substrate 1 〇〇 and devices 101 Α , 1 〇 1 Β and i 〇 lc fabricated on the substrate 100 , wherein the substrate 100 is generally made of bismuth (Si), but may also be gallium arsenide (GaAs). , zirconia (GaAsP), indium (InP), GaAlAs, InGaP, and the like. In Fig. 1B, an insulating layer (sometimes referred to as an interlayer dielectric layer or ILD layer) 102 is deposited on the substrate 1 of the wafer 10. The above insulating material contains, for example, oxidized hair and ph〇sphosilicate glass (PSG). As shown in Fig. 1C, etching is performed on the wafer 10 to fabricate the via via trenches 103 and 104 and the contact openings 111A, 111B and U1C in the interlayer dielectric layer 1〇2. In order to prevent any conductor material from being dissolved into the active portion of the circuit system of the wafer, the dielectric liner 105 is deposited in a conformal layer, such as silicon Nitride. On the circle 10, there are vias 103 and 104. In a preferred embodiment, the dimensions (e.g., diameter) of the via recesses 103 and 104 range from substantially 5 microns to substantially 50 microns and the aspect ratio ranges from substantially 12:1 to substantially 3: 1. As shown in Fig. 1D, a layer of conductor material, i.e., conductor 〇6, is formed over wafer 10. The conductor material may comprise various materials such as copper, crane, aluminum, gold, silver, and the like. The conductor 106 fills the TSV via recesses 1 〇 3 φ and 104, and the contact openings 111A, 111B and 111C. After the excess portion of the conductor 1〇6 is removed by rice etching, chemical mechanical polishing (CMP), and the like, the wafer 10 includes the contacts 118A, 118B, and 118C in the interlayer dielectric layer 1〇2 and the through-holes. The vias (tsvs) i 〇 7 and ι 08, wherein TSVs 107 and 108 are simultaneously formed in the substrate 1 〇〇 and the interlayer dielectric layer 1 〇 2, as shown in FIG. 1E. In another embodiment, contacts 118A, 118B, and 118C can be formed prior to fabrication of TSVs 107 and 108. In another and/or alternative embodiment, the contacts 118A, 118B, and 118C may be formed after the TSVs ι 7 and 1〇8 are formed. Next, referring to FIG. 1F, a first interconnect layer (M1 layer) is deposited and patterned on the wafer 1 by applying a general post-production process in the integrated circuit manufacturing process to form a first interconnect. Lines 12A, 12B, and 12〇c, and contact pads 124 and 125, wherein first interconnects 12A to 12〇c are coupled to devices 1〇1A to 1〇lc through contacts 118A to 118C, respectively. And the contact pads 124 and 125 are respectively coupled to the through-via windows 1〇7, 1〇8. The first intermetal dielectric layer 200 is deposited onto the wafer 1 . Next, using the existing technique 201023299, such as a dual damascene (eg, al damascene) process, the second interconnect layer is patterned (the M2 layer is deposited on the sundial 10 and a similar method is formed to form the upper 4=210. The class covers the interconnect line in the second interconnect layer = layer (= layer), and the interconnect line is interconnected by the second intermetal dielectric layer 3'0=connected on the line circle 10 The process of the structure can be separated by layer 300. The crystal row is formed until the various devices in the wafer 1G are connected in layers to be used for the required interaction between the features. _Material = mutual η: :: Conductive material may include that the 'via window is usually used to pass through: J touch 1...5, and lightly connect to the upper interconnect layer (10) layer and = != line. For example 'contact pad 124 And the interconnecting line 210 is performed by a direct connection method by using a via window Vlala, wherein the via vmla is formed on the through via window 1〇7 and aligned with the via via 1〇7. For example, the contact pad 125 extends through a redistribution Mi feature 138, wherein the redistribution M1 feature 138 is coupled to the interconnect line 210 through the via vial. In this example, The window 4 & is not formed on the through via window ι 8 and is not aligned with the via via 108. Various embodiments of the present invention are not limited to the via via contact pad and the upper interconnect The interconnections in the layers are only directly connected. It is also worth noting that the vias are used to connect the interconnects in the interconnect layers, but are not shown in order to simplify the drawing. In Fig. 1F, a spacer layer 345 (also sometimes referred to as a passivation layer) is deposited over the wafer 10, wherein the spacer layer 345 provides mechanical or chemical protection of the devices and interconnects in the wafer 10. As shown in FIG. 1G, bonding contacts 410, 411, and 412 are formed via deposition of dielectric layer 339, which can be used to place interconnects and interconnects with wafers. Any of any of the wafers is insulated from any of its circuitry or devices. A recess is formed in the dielectric layer 339, and conductor material is deposited in the recesses to form the joint contacts 410, 411 and 4 Π. The money engraves the insulating material of the dielectric layer 339 until the bonding contacts 410, 411, and 412 are exposed. The bonding contacts, 411 and 412 are still higher than the top end of the dielectric layer 339. The bonding contacts 410, 411 and 412 can be electrically connected to the conductor line 310 through the via 347 in the insulating layer 345. As shown in FIG. 1G, the positions of the bonding contacts 410, 411, and 412 with respect to the conductor lines 31 () in the lower top interconnect layer are not limited. However, the bonding contacts 41, 411, and 412 and the conductors are not limited. There should be other ways of connecting the 310, such as the redistribution layer 35G (Fig. 2), Kirin Road or similar structure. The various aspects of the present invention do not limit the direct connection between the bond contacts and the interconnect lines in the top interconnect layer. As shown in Fig. 1H, an adhesive 450 is applied to the wafer 1 to bond the wafer 1 to the wafer carrier 500. The carrier 500 is typically used to provide mechanical support during subsequent thinning of the back of the 10 panel 100. In a preferred embodiment: the carrier 5〇0 can be a glass substrate or a bare wafer having a gray scale ranging from substantially fine to substantially 1000 microns. Figure 11 is a cross-sectional view of wafer 10 not according to an embodiment of the present invention. In order to provide the vias 107 and 108 to thin the substrate 100 on the back side, and remove a portion ' of the substrate 100 to expose the vias 107 and 108 by, for example, a dice tape or the like. Contact point. In the above steps, the carrier 500 is fixed to the wafer thinning handle type jig (wtfer 201023299 round thinning handle jig), and the wafer thinning handle type jig is then mounted on the intergranular thinning mechanism. In these portions of the substrate 100, the vias and 108 are slightly protruded from the substrate 100β after the substrate thinning process, and the thickness of the wafer 10 is reduced to a range of substantially 25 micrometers to substantially 25 micrometers. The first J-picture shows that the SI 10 is stacked and bonded to the wafer u (four) plane. The wafer 11 includes a substrate 600, a dielectric layer 624, and an insulating layer 626. The substrate _ may comprise - or a plurality of pre-formed semiconductor components, the dielectric layer 624 may be used to isolate interconnects formed in different interconnect layers, and the insulating layer 626 ❹ may be used to limit various components on any of the wafers The dry 1 is aligned with and bonded to the vias 107 and the bonding pads 607, and the vias 108 and bonding pads 608 to form stacked wafers. The medium of the mouth, such as steel, crane, copper-tin alloy, gold-tin alloy, steel galvanic, staggered tin alloy or the like, can be applied between the mating contacts of the pre-bonded wafer and 11. In a preferred embodiment, after the thinning process of the substrate lion is performed 450. If the carrier 500 is removed from the H/曰® 10 and the adhesive is removed, the metallized insulating layer 127 is deposited on the back side of the substrate 100 on the protruding edge of the upper layer 8 of the via 〇7 on. The metallization insulating layer 127 has a plurality of layers of insulating material of a layer of lining material, wherein any metal deposited in the metallization process by the Pf in the liner material penetrates into the wafer 10 and is etched in the metallization insulating layer 127. Grooves 130 and 131 are formed. The metallization process shown in the figure forms bond pads 132 and 133. Sinking μ, such as steel, tantalum, aluminum or the like, in the metallized insulating layer 127, by grinding the wire (4) or removing the metal by _ method or chemical mechanical

II 201023299 The remainder to form bond pads 132 and 133. The wafer subjected to the above process is indicated as wafer 10' in the first L-picture. FIG. 1M is a cross-sectional view showing the wafer 11 stacked and bonded to the wafer 10'. The wafer 11 includes a substrate 600, a dielectric layer 624, and an insulating layer 626. The substrate 600 can include one or more pre-formed semiconductor components, the dielectric layer 624 can be used to isolate interconnects formed in different interconnect layers, and the insulating layer 626 can be used to limit interference between various components on the two wafers. . At the bonding pads 607 and 132 and the bonding pads 608 and 133, the wafers 10 and 11 are aligned and bonded together to form a stacked wafer 13. Bonding media, such as copper, tungsten, copper-tin alloy, gold-tin alloy, indium gold alloy, lead-tin alloy or the like, are applied between the bonding contacts on the pre-bonded wafers 10' and 11. It should be noted that while wafers 10, 10', and 11 are illustrated in a manner that forms a stacked wafer structure, the particular wafers used herein are not intended to limit embodiments of the invention in any way. In practical applications, the structures of the wafers 10, 10' and 11 may be wafers or dies, so the stacked structure may have a structure of die-bonded grains, a structure of die-bonded wafers or a wafer-bonded crystal. Round structure. It should also be noted that any number of different devices, components, connectors or similar structures may be integrated into the wafers 10, 10' and 11. The particular elements or elements that may be exemplified herein are not intended to limit the embodiments of the invention in any way. It should be further noted that only a certain number of active components, such as devices 101A through 101C, and vias, such as vias 107 and 108, are shown for clarity of illustration. However, in the practical application of this technology in the field of 12 201023299, the integrated circuit system related to the integrated circuit and the stacked die may contain millions or even tens of millions or more of active components. And these interconnect structures may contain dozens or even hundreds of conductors in the uppermost dielectric layer t. Similarly, it will be understood by those of ordinary skill in the art that, in practical applications, each stacked die contains tens or more of the backside connections of the conductive vias or wires. Moreover, the stacked die structure in the preferred embodiment may include tens or even hundreds of bonding contacts for electrical connection to the integrated circuit package, for example, although only three bonding contacts 410 are shown. 412. 3 is a cross-sectional view of the integrated circuit package 20 in a flip chip ball grid array structure. The integrated circuit package 2 includes stacked dies of the preferred embodiment, such as stacked wafers 12 (Fig. ij) Or a stacked die in 13 (Fig. 1M). After the stacked dies in the stacked wafers 12, 13 are formed, a plurality of bonding contacts, such as bonding contacts 41 〇 412, are typically arranged in an array on the bonding surface 75. The bonding surface 75 is adhered to the package substrate 50 through a solder bump (e.g., solder ball) 55, and is further electrically connected to the printed circuit board (not shown) through the package wiring 65. It should be noted that in the preferred embodiment, other integrated circuit packages can also be used to package the stacked die. In another example, the stacked dies can be soldered directly to the printed circuit board. Particular elements or missing elements that may be illustrated herein are not intended to limit the embodiments of the invention in any way. It should be noted that the wafers and grains described or illustrated in the above parent example are intended to provide alternative embodiments of the vias, contact pads and bond pads that may be employed in various embodiments of the present invention. In other or alternative embodiments of the invention, any combination of the exemplified options may be utilized. These descriptions 13 201023299 are not intended to limit the various other and/or alternative embodiments of the present invention. It should be noted that the various layers of process A or process required for the different layers described in the embodiments are described as including various material. The metal of the gold bond pad can be any suitable metal or alloy, such as the copper crane, Lu Minggang and the like. Furthermore, any dielectric material may be used depending on the desired use and function of the different dielectric layers or insulating layers, such as oxidizing dreams, nitriding stones, carbon carbide, nitrogen oxidizing seconds, and the like. The invention is not limited to the use of any particular range of compounds and materials. It should be further noted that the different layers and grooves in the illustrated embodiment may be deposited or formed using the I process of the basin. For example, the formation of various layers such as oxides, dielectrics or germanium layers can be achieved by chemical vapor deposition (sCVD), atomic layer deposition (ALD) or the like. Further, the removal of material from the wafer can be accomplished via dry or wet etching, chemical mechanical polishing (CMP), or the like. The invention is not limited to any single method. Figure 4 is a flow diagram showing exemplary steps for practicing an embodiment of the present invention. In step 400, one or more recesses are formed in the first wafer before the semiconductor component is formed in the wafer. The recess extends from the front surface of the wafer to a predetermined distance from the back surface of the wafer. In step 410, a conductor material such as copper, tungsten, aluminum or the like is deposited into the above-mentioned recesses, wherein the conductor material forms a plurality of vias. In a preferred embodiment, the size (e.g., diameter) of the via is between substantially 15 microns and substantially 35 microseconds and the aspect ratio ranges from substantially 2:1 to substantially 3.3:1. In step 420, a semiconductor element (for example, a complementary metal oxide 201023299 semiconductor, or a bipolar device or the like) is formed on the wafer, and an interlayer dielectric layer is deposited on the semiconductor device and the via 30. 'The interlayer dielectric layer is composed of - material, . . . , positive surface germanium, tantalum nitride, tantalum carbide, niobium oxynitride, or its::: 224 t ' or two or two contacts Selecting a contact between the layers to electrically connect to a plurality of selected transmissive layers

: an oxygen semiconductor semiconductor device on the front side of the first semiconductor wafer: a dielectric layer deposited from the interlayer dielectric to the wafer on the semiconductor tree: the intermediate dielectric layer is composed of - material, such as = Fossil eve, acid acid glass (ρ_-fine; psG), ^ 520, sputum hair, nitrogen oxide dream or its similar materials. In the step, one or more recesses are formed into the semiconductor wafer. These recesses: the inter-layer dielectric layer and the front surface of the wafer to the back surface of the wafer: at a distance from the front. At step 530+, a conductor material, such as steel, or the like, is deposited into the recess to form a via window in the wafer. In a preferred embodiment, the size of the through-cut window (eg, direct intrusion) ranges from substantially 15 microns to substantially 35 microns, and the aspect ratio ranges from substantially 2:1 to substantially 3.3: Between 1. In step 54(), $- or a plurality of contacts are in the interlayer dielectric layer, wherein a plurality of selected contacts are electrically connected to the plurality of selected through-via windows. Figure 6 is a diagram showing an exemplary flow of steps for implementing an embodiment of the present invention. In step 600, before forming the semiconductor device in the wafer (for example, FIG. 4) or after forming the semiconductor device on the wafer, but forming the complex 15 201023299, the number = interconnection is formed on the wafer to form a connection. Semi-conducting in the wafer:: (from Figure 5), forming - or complex ===: extension in the first wafer: to be separated from the back surface of the wafer - pre-copper, crane, trench deposition conductor Materials such as windows. In this case, the conductor material forms a plurality of layers of the dream layer _ between the dimensions of the 3 via window (for example, the diameter). Between 35 microns, and the aspect ratio is between 3.3:1. In order to hit the enthusiasm, in the layer-------------------------------------------------------------- In step _ +, Shi Xijie layer: electrical layer and contact. Forming a complex number to the layer: == conductor element and through-via window. In step 64 ", two: bonding is in contact with one or a plurality of dielectric layers, : two: two:: electrically connected to a plurality of selected wear:: layer quotient. In step 650 t, the foregoing: "through the stacked die to the wafer structure or wafer alignment σ σ contact alignment = soil:; or two contact surfaces on the surface; complex: = or two . Then, the stacked die-to-wafer bonding structure can be cut or packaged by electrically connecting to the printing by solder bumps, one or more bonding contacts bonded to the integrated circuit package. Circuit board. Through packaged conductors 16 201023299 Figure 7 is a flow chart showing an exemplary step of implementing an embodiment of the present invention. In step 700, the front surface of the first wafer is attached to the carrier with an adhesive, wherein the first wafer has one or a plurality of through-via windows. In step 710, a portion of the substrate material on the back side of the first wafer is removed to expose the backside connection of the via via. In step 720, one or more back bond contacts are made that are electrically connected to the backside connections exposed by the connection vias. In step 730, the back side of the first wafer is bonded and contacted with a material that is electrically compatible with the bonding contact, such as copper, crane, gold, copper-tin alloy, indium gold alloy, lead-tin alloy, or the like. The bond contacts of a wafer are aligned and joined. Although the present invention and its advantages have been described in detail above, it should be understood that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the invention. In addition, the scope of the present application is not limited to the specific embodiments of the processes, machinery, manufacture, compositions, methods, methods and steps described in the specification. Anyone having ordinary skill in the art will readily appreciate from the disclosure of the present invention that existing or future embodiments can perform substantially the same function or substantially the same as the above-described embodiments. The resulting process, machine, manufacture, material composition, means, method or procedure can be applied in accordance with the present invention. Therefore, the scope of the appended claims is intended to cover such modifications, such BRIEF DESCRIPTION OF THE DRAWINGS In order to provide a more complete understanding of the present invention and its advantages, reference is made to the above description in conjunction with the accompanying drawings in which: FIGS. 1A to 1M are shown in accordance with an embodiment of the present invention. A cross-sectional view of a wafer having a through-stone window. 2 is a cross-sectional view showing a wafer having a via via formed in a substrate and a dielectric layer in accordance with an embodiment of the present invention. 3 is a cross-sectional view showing a wafer having a via via formed in a substrate and a dielectric layer in accordance with an embodiment of the present invention. • Figure 4 shows a cross-sectional view of a stacked wafer structure. Figure 5 is a flow chart showing an exemplary step of implementing an embodiment of the present invention. Figure 6 is a flow chart showing an exemplary step of implementing an embodiment of the present invention. Figure 7 is a flow chart showing an exemplary step of implementing an embodiment of the present invention. [Main component symbol description] 10, 10', 11, 12, 13: wafer 100: substrate 101A, 101B, 101C: device 102: interlayer dielectric layer 103, 104: through the via window recess 105: Electrical lining 106: conductors 107, 108: through-through vias 118A, 118B, 118C: contacts 120A, 120B, 120C: first mutual 127: metallized insulating layer connections 130, 131: recesses 124, 125: contact Pad 201023299 '200: first inter-metal dielectric layer 132, 133: bond pad 210: interconnect 300: second inter-metal dielectric layer 310: interconnect line viaa, vialb: via 339: dielectric layer 345 : spacer layer 347 : via window 350 : redistribution layer 410 , 411 , 412 : bonding contact 450 : adhesive 500 : carrier 600 : substrate 607 , 608 : bonding pad 624 : dielectric layer 626 : insulating layer 20 : integrated body Circuit package 19

Claims (1)

201023299 VII. Patent Application Range: 1. A method for forming a semiconductor chip of a stacked integrated circuit, comprising: forming one or more recesses in a first semiconductor wafer; filling the recesses with a conductive material a trench to form one or more via vias in the first semiconductor wafer; forming one or more bonding contacts on a front side of the first semiconductor wafer; attaching the first semiconductor wafer The front side is to a carrier and exposes a back side of the first semiconductor wafer; the thin back of the first semiconductor wafer is thinned until the or the through via window is exposed and slightly protrudes from the first The back side of the semiconductor wafer; and aligning and bonding the one or more bonding contacts on the one or more bonding surfaces of the or the via vias and a second semiconductor die or wafer. The method of claim 1, wherein the or the grooves have a diameter ranging from substantially 5 micrometers to substantially 50 micrometers, and an aspect ratio ranging from substantially 12:1 to substantially 3:1. 3. The method of claim 1, further comprising: forming one or more semiconductor components in the first semiconductor wafer; forming an interlevel dielectric layer on the first semiconductor wafer; forming one or more Contact pads on the interlayer dielectric layer and electrically contacting the or through vias; 20 201023299 • forming a plurality of interconnected greedy circuits in the dielectric layer on the interlayer dielectric layer, Electrical connection of some 彡远金广线:: metal body element and the layer or the contact &> semi-conductive forming surface or (4) bonding lying-upper dielectric layer, the bonding Contact bonding electrical coupling refers to the interconnection of two metal lines: 4. The method of claim 3, wherein the or the contacts are coupled by a heavy conductor layer or the gums. Via window. 5. The method of claim 3, wherein the step of forming or the recesses is prior to the step of forming the or the germanium semiconductor device. 6. The method of claim 3, wherein the step of forming the or the recesses is prior to the step of forming the erected metal lines. 7. The method of claim 1, wherein the conductor material used to form the or the through-via window is selected from the group consisting of copper, tungsten, aluminum, gold, silver, and combinations thereof. One of the groups. 8. The method of claim 1 , wherein after the thinning step, the first semiconductor wafer has a thickness ranging from substantially 25 micrometers to substantially 250 micrometers. 21 201023299 9. The method of claim 1 The method further includes: after the thinning step, forming a metallization insulating layer on the back surface of the first semiconductor wafer; and forming one or more second bonding pads in the metallization insulating layer, wherein the Or the second bonding pads are electrically connected to the or the through vias and protrude slightly from the metalized insulating layer. 10. The method of claim 9, wherein the or the second bond pads are electrically coupled to the or through vias via a repeating conductor layer. 11. A method of forming a semiconductor die of a stacked integrated circuit, comprising: providing a first semiconductor wafer having one or a plurality of via vias formed in a substrate; attaching the first a front surface of a semiconductor wafer to a carrier and exposing a back surface of the first semiconductor wafer; thinning the back surface of the first semiconductor wafer until the or the through via window is exposed and slightly And protruding from the back surface of the first semiconductor wafer; forming one or more first bonding contacts in a metallization insulating layer on the back surface of the first semiconductor wafer after thinning, the first bonding Contacting electrically coupled to the or the through vias; providing a second semiconductor workpiece having one or more second bond contacts on a bonding surface of the second semiconductor workpiece; Aligning and bonding the one or more first bonding contacts on the first semiconductor wafer to the corresponding one or more bonding interfaces 22 on the second semiconductor workpiece 201023299 12. As described in claim 11 The method, wherein the second semiconductor workpiece comprises a semiconductor wafer, and wherein the step of joining the wafer to produce a bonded pair of round grain structure. 13. The method of claim 11, wherein the second semiconductor workpiece comprises a semiconductor die, and wherein the bonding step produces a die-to-wafer bonding structure. 14. The method of claim 11, wherein the or the through-via window has a diameter ranging from substantially 5 micrometers to substantially 50 micrometers, and an aspect ratio ranging from substantially 12:1 to substantially 3 : 1. 15. The method of claim 11, wherein after the thinning step, the first semiconductor wafer has a thickness ranging from substantially 25 microns to substantially 250 microns. 16. The method of claim 11, wherein the conductor material used to form the one or more through-via windows is selected from the group consisting of copper, tungsten, aluminum, gold, silver, and combinations thereof. One. 17. The method of claim 11, further comprising: forming one or more semiconductor components in the first semiconductor wafer; and forming one or more second bonding contacts to the front surface of the first semiconductor wafer The second bonding contact is electrically coupled to the or the semiconductor component via one or a plurality of interconnecting metal lines of an inter-metal dielectric layer 23 201023299* on the first semiconductor wafer. And the or through through window. 18. The method of claim 17, wherein the forming the or the semiconductor elements in the first semiconductor wafer is performed after forming the or the via vias. 19. The method of claim 17, wherein the step of forming the or the semiconductor elements in the first semiconductor wafer is prior to the step of forming the semiconductor elements or the interconnect metal lines. 20. The method of claim 17, further comprising: bonding the second or the second on the stacked semiconductor circuit die by a plurality of bumps in a flip chip circuit package structure The bonding contact is bonded to an integrated circuit package substrate. twenty four