201021171 •凡、贫明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板與封裝結構，尤指一種基 板具有導電柱之封裝基板與封裝結構。 土 【先前技術】 料導體封裝製程中，m(Flip Chip)係為一種 因應南密度線路之需求所發展出的半導體晶片封裝 術’其係於具有半導體積體電路（ic)之晶片的表面上配置 有電極墊，並於該電極墊上形成有焊料凸塊，且在有 =板上形成有相對應之電性連接塾與焊接材料，俾提供 =導體晶月以電性接觸面朝下的方式設置於該封裝基 月 > 閱第1A及1B圖’係為習知之重 意圖，係提供一基板本體日 封裝之不 體具有電性接導體晶片13’該基板本 焊I f 且該餘本體10上形成有防 知層12，該防焊層12 φ ^ ❹出出成有複數開孔120，以對應露 材料塾11 ’該電性接觸墊11上形成有焊接 雷朽執，而該半導體晶片13具有複數電極墊13〇,於兮 =墊uo上形成有禪料凸塊131 、:； 應電性連接該焊接材料11〇，如第 4凸上:31對 行廻焊（reflow)製程 · τ接者’進 π〇融合成焊料16，/於广科…鬼131與該焊接材料 並於该防焊層12與半導體晶片13 =二底充材们5,以加強該基板本 日日片U之間的結合強度’如第^所示。牛導體 111004 5 201021171 1:翏1第2'及託圖’係為習知之另-種覆晶封裝之 供—基板本體1G及半導體以13’該基板 本體10具有毛性接觸墊u，且該基板本體1〇上形成有 ==广該防焊層12中形成有複數開孔12G， 路出出各該電性接觸仙’於該電性接觸 有 短銅柱14，於該麵钿缸H , 丄❿风有 •丰暮雜曰K 形成有焊接材料110，·而該 +導體曰曰片13具有複數電極墊13〇，於該電極塾⑽上 • St:料:| 131 ’令該焊料凸塊131對應連接該焊接 ·: = = :=:進行賴程，令該 防焊層12與半導體曰=融合成焊料16，並於該 託圖所示。、牛導體-片Μ之間的結合強度’如第 然而，習知覆晶式封裝結構係於半 =:便於結合至該基板本體之電性接觸塾上之= 鲁:阳該半導體晶片之線寬和線距遠小於該基板本 度較高而二電?墊上形成焊料凸塊的製程難 m接μ &學用品與設備成本亦高於該基板本 2成知接材料。此外’另一種習知之覆晶式封裝結構係 接： = 成短銅柱及焊接材料，再以焊接材料連 接=體：片的電極墊上的焊料凸塊；惟習知受 力’、電鑛形成的短銅柱之高度有限，最大約為15微 焊料H ^此+導體晶片之電極塾上仍須有適當量的 干科凸塊，令该晶片及基板本體之間維持足夠之距離，俾 111004 6 201021171 刊於廻焊後，該底充材料易於填入晶片及其 隙’所以封I结構仍須於該半導體晶片的電極塾上 焊料凸塊及焊接材_焊會融_成輝料201021171 • Description of the invention: [Technical Field] The present invention relates to a package substrate and a package structure, and more particularly to a package substrate and package structure in which a substrate has conductive pillars. [Previous Technology] In the material conductor packaging process, m (Flip Chip) is a semiconductor wafer package developed in response to the demand of the south density line, which is attached to the surface of a wafer having a semiconductor integrated circuit (ic). An electrode pad is disposed, and a solder bump is formed on the electrode pad, and a corresponding electrical connection and a solder material are formed on the y= board, and the 导体 supply=the conductor crystal is electrically contacted downward. The first base and the first embodiment of the present invention are provided with a substrate body package, and the substrate is provided with an electrical conductor wafer 13'. A protective layer 12 is formed on the 10, and the solder resist layer 12 φ ^ ❹ is formed into a plurality of openings 120 to correspond to the exposed material 塾 11 '. The electrical contact pad 11 is formed with a solder bump, and the semiconductor The wafer 13 has a plurality of electrode pads 13A, and zen bumps 131 are formed on the 兮=pad uo, and the solder material 11〇 is electrically connected, such as the fourth bump: 31 pairs of reflow processes. · τ connector 'into π 〇 fusion into solder 16, / Yu Guangke... Ghost 13 1 and the solder material are applied to the solder resist layer 12 and the semiconductor wafer 13 = two bottom filling members 5 to enhance the bonding strength between the substrate sheets U as shown in the figure. Cattle conductor 111004 5 201021171 1: 翏1 2' and 托图' is another conventional flip-chip package supply - substrate body 1G and semiconductor 13', the substrate body 10 has a brittle contact pad u, and The substrate body 1 is formed with a plurality of openings 12G formed in the solder resist layer 12, and each of the electrical contacts is electrically connected to the short copper pillars 14 in the electrical contact. , the hurricane has a rich enthalpy K formed with a solder material 110, and the + conductor cymbal 13 has a plurality of electrode pads 13 〇 on the electrode 塾 (10) • St: material: | 131 'make the solder The bump 131 is connected to the solder:: = = :=: to carry out the process, and the solder resist layer 12 and the semiconductor germanium= are fused into the solder 16, and are shown in the bracket. The bonding strength between the bobbin and the sheet is the same as that of the semiconductor wafer. The width and the line spacing are much smaller than the high degree of the substrate, and the process of forming the solder bump on the second electric pad is difficult to connect with the μ & the cost of the article and equipment is higher than that of the substrate. In addition, 'the other conventional flip-chip package structure is connected: = short copper pillar and solder material, and then connected with solder material = body: solder bump on the electrode pad of the chip; but the well-known force', electric ore formation The height of the short copper column is limited, and the maximum is about 15 micro solder H ^. The electrode of the conductor wafer must still have an appropriate amount of dry bumps to maintain a sufficient distance between the wafer and the substrate body, 俾111004 6 201021171 Published after soldering, the underfill material is easy to fill the wafer and its gap' so the I structure still needs to be solder bumps and solder materials on the electrode pads of the semiconductor wafer.
: ’若焊料之用量過多’將使該輝料與J 4產生橋接，而需加大焊料與焊料之間距， j 間距封裝結構之發展。 丈不利於細 因此’鑒於上述之問題’如何避免習知技術中之 ❿ 須於半導體晶片的電極墊上形成焊料凸塊： 距：裝‘構的製程難度增加與成本上升及限制細間 :封裝結構之發展等問題’實已成為目前 【發明内容】 ㈣上述f知技術之缺失，本發明之目的係提供一種 =基：與封裝結構，藉由形成於基板之導電柱上的焊接 ’以電性連接至半導體晶片之電極墊，而 ❹：=塾上形成焊料凸塊，因此製程簡易、：構簡單1 乂-且有利於形成細間距之封裝結構。 美板目的’本發明提供一種封裝基板，係包括: f本體、，係具有相對之第—表面與第二表面，於該第- 、有複數電性接觸塾，該第—表面及該些電性接觸塾 第防焊層，且该第一防焊層具有複數對應外露出 :书n接觸塾之第—開孔；複數導電柱，係對應設於各 ::丰露之電眭接觸墊上’該導電柱之高度係為20至60 r ;; ( M m)，以及複數焊接材料，係對應設於各該導電 111004 7 201021171 狂上0 依上述之封裝基板，該導電柱之高度係最佳為4〇微 米（// m)。 依上述之結構，該導電柱係可為銅，而該焊接材料係 '可為焊錫。 依上所述’復包括有機保焊層（〇rganic s〇lderabimy preservatives，OSP)，係設於該導電柱之外露表面上。 又依上述之結構，復包括複數谭球塾，係、設於該第二 ❿表面上’並於該第二表面上設有第二防焊層，且該第二防 焊層具有複數對應外露出各該谭球藝之第二開孔；復包括 複數焊料球，係對應設於各該焊球墊上；或者，該谭球塾 供作與墊閘陣列結構（Land grid array，⑽之電性連 接。 且有==提供一種封裝結構，係包括:基板本體，係 表面及第二表面，於該第-表面具有複數 m m 々弟表面及該些電性接觸墊上設有第一防 墊之第一開孔 有複數對應外冑出各該電性接觸 並於，第1複數焊球墊，係設於該第二表面， 上設有第二防辉層，且該第二防谭層且有 ==該焊球塾之第二開孔;複數導電柱:係 20至60微米（路^電性接觸墊上，該導電柱之高度係為 柱上；以及半導體Ύ複數谭料，係對應設於各該導電 曰片且古於 日片，係接置於該些焊料上，該半導體 日日片具有作用面，於 /千导胧 、'^乍用面具有複數電極墊，並於該電 111004 8 201021171 蚀上f艾有表面處理層，該表面處理層係可為化鎳浸金 (Electroless Ni & Immersion Gold，ENIG)、化鎳！巴浸金 (Electroless Nickel/Electro less Pal lad ium/1 miners ion Gold, ENEPIG) 或焊塊底部金屬化（Under bump metallurgy, UBM)結構層，該些電極塾對應接合至各該導 電柱上之焊料5令該半導體晶片電性連接至該基板本體。 依上述之封裝結構，復包括底充材料，係設於該基板 ' 本體之第一防焊層表面與半導體晶片之間；該導電柱之 _高度係最佳為40微米（// m );該導電柱係可為銅，而該 焊料係可為焊錫。 又依上述之封裝結構，復包括複數焊料球，係對應設 於各該焊球墊上；或者，該焊球墊供作與墊閘陣列結構 (Land grid array, LGA)之電性連接。 本發明之封裝結構，係藉由在基板本體上之電性接觸 墊上形成有導電柱，且在該導電柱上形成有焊接材料，並 藉由形成於該導電柱上之焊接材料以電性連接至該半導 ❹體晶片之電極墊，無需在該半導體晶片之電極墊上形成焊 料凸塊，而僅需於該導電柱上形成少量之焊接材料，因此 製程簡易、結構簡單、成本較低且迴焊後不易產生焊料橋 接，而有利於形成細間距封裝結構，又該導電柱之高度約 在20至60微米（/zm)，仍可使該底充材料易於填入該 半導體晶片與基板本體之間隙。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 9 111004 201021171 八’热恐此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 [第一實施例] 一請參閱第3A至3E圖，係為本發明之封裝基板之製法 不意圖。 ❹: 'If the amount of solder is too much' will bridge the J 4 , and increase the distance between the solder and the solder, the development of the j-pitch package structure. It is not conducive to fineness. Therefore, in view of the above problems, how to avoid the need to avoid solder bumps on the electrode pads of semiconductor wafers: Distance: Increased manufacturing difficulty and cost increase and limited thinness: package structure The development of the problem has become the present invention [invention] (4) the lack of the above-mentioned technology, the object of the present invention is to provide a = base: and the package structure, by the solder formed on the conductive posts of the substrate 'electricity The electrode pad is connected to the semiconductor wafer, and the solder bump is formed on the ❹:= ,, so the process is simple, the structure is simple, and the package structure with fine pitch is formed. The present invention provides a package substrate comprising: a body having opposite first and second surfaces, wherein the first, plurality of electrical contacts, the first surface and the electricity Sexual contact with the first solder mask layer, and the first solder resist layer has a plurality of corresponding external exposures: the first n-opening of the book n contact ;; the plurality of conductive pillars are correspondingly disposed on each of the electric contact pads of the: The height of the conductive column is 20 to 60 r;; (M m), and the plurality of solder materials are correspondingly disposed on each of the conductive electrodes 111004 7 201021171. According to the above package substrate, the height of the conductive column is optimal. It is 4 〇 micron (// m). According to the above structure, the conductive pillar can be copper, and the solder material can be solder. According to the above, the 包括rganic s〇lderabimy preservatives (OSP) are disposed on the exposed surface of the conductive pillar. According to the above structure, the complex includes a plurality of tanballs, which are disposed on the surface of the second crucible, and a second solder resist layer is disposed on the second surface, and the second solder resist layer has a plurality of corresponding Exposing the second opening of each of the Tan ball art; the complex includes a plurality of solder balls, correspondingly disposed on each of the solder ball pads; or, the Tan ball is provided for electrical connection with the gate array structure (Land grid array, (10) And having a package structure comprising: a substrate body, a surface and a second surface, wherein the first surface has a plurality of mm surfaces and the first contact pads are provided on the electrical contact pads The opening has a plurality of corresponding electrical contacts, and the first plurality of solder ball pads are disposed on the second surface, and the second anti-glare layer is provided, and the second anti-tan layer has = the second opening of the solder ball ;; a plurality of conductive columns: 20 to 60 micrometers (on the electrical contact pad, the height of the conductive column is on the column; and the semiconductor Ύ plural tan materials, corresponding to each The conductive cymbal and the ancient film are attached to the solder, and the semiconductor Japanese film has The surface has a plurality of electrode pads on the surface of the surface, and the surface of the surface layer is etched with a surface treatment layer, and the surface treatment layer can be nickel immersion gold (Electroless Ni & ; Immersion Gold, ENIG), Electroless Nickel/Electro less Pal lad ium/1 miners ion Gold (ENEPIG) or Under bump metallurgy (UBM) structural layer, these electrodes Corresponding to the solder 5 bonded to each of the conductive pillars, the semiconductor wafer is electrically connected to the substrate body. According to the package structure, the bottom filling material is disposed on the surface of the first solder resist layer of the substrate Between the semiconductor wafers; the height of the conductive pillars is preferably 40 micrometers (//m); the conductive pillars may be copper, and the solder may be solder. According to the above package structure, the plurality of solders are included. The ball is correspondingly disposed on each of the solder ball pads; or the solder ball pad is electrically connected to a land grid array (LGA). The package structure of the present invention is on the substrate body Electrically formed on the electrical contact pads a pillar, and a solder material is formed on the conductive pillar, and is electrically connected to the electrode pad of the semiconductor wafer by a solder material formed on the conductive pillar, without forming solder on the electrode pad of the semiconductor wafer The bumps only need to form a small amount of solder material on the conductive pillars, so the process is simple, the structure is simple, the cost is low, and solder bridging is not easy after reflow, which is favorable for forming a fine pitch package structure, and the conductive pillars The height is about 20 to 60 micrometers (/zm), and the underfill material can still be easily filled into the gap between the semiconductor wafer and the substrate body. [Embodiment] The following is a description of the embodiments of the present invention by way of specific specific examples. 9 111004 201021171 A person skilled in the art can easily understand other advantages and effects of the present invention from the disclosure of the present specification. [First Embodiment] Referring to Figures 3A to 3E, the method of manufacturing the package substrate of the present invention is not intended. ❹
如第3A圖所示，提供一具有相對之第一表面2〇a盘 弟二表面20b之基板本體20,於該第一表面2〇a盥 表面2〇b分別具有複數電性接觸塾2〇 〇、IAs shown in FIG. 3A, a substrate body 20 having a surface 20b opposite to the first surface 2A is provided, and the surface 2〇b of the first surface 2a has a plurality of electrical contacts respectively. 〇, I
Sr::之第一表面_與第二表面二 ^成弟一防焊層21a與第二防焊層训，且該第一 2第1&-=二：谭層_分別形成有複數第-開孔2心 以對應分別露―觸塾= 如第3B圖所示，於該些電性接㈣ 層21 a及該第一龆力0, Λ 弟防焊 該導電層2?卜 〇&之孔壁上形成導電層22,且於 電層22上形成阻層23，該 、 ❹區230，並對；s | + & + θ 23形成有禝數開口 立對應露出各該電性接觸墊2〇1上 第3C圖所示，於各 上形成係可為銅之導電⑽m中之導電層22 該電性接觸連接至 如第3D图所示，於 2、 :：d。 之焊接材料25。 电狂上形成係可為銲錫 如f 3E圖所示，移除該阻層 22’以外露出該^覆i之導電層 防&層21a、各該導電枉 111004 10 201021171 ㈣料25’·藉由製程能力的提 而可使用較厚的光阻，*姐曰s 4竿义於白知技術 幵光及退洗光阻的能力，且 .i鍍技術亦有所進步，而可使各該導 :…微米（㈣），較佳可為40微米（二= 外’移除該阻層23及導電声22之制々在厘3 )此 此不再為文贅述。係屬習知者’故於 ，有機：=:圖所示，於如第犯圖所示之結構上施加 有機料層（0rganic s〇lderabimy ⑽ ❹㈣sp)28，該有機保焊層28係形成於該 = 球之外露表面上，以保護該導電柱24與焊球塾= 不會爻到外界的影響而氧化。 r本發明提供—種縣基板，係包括：基板本體20， 係具有相對之第-表面2〇a與第二表面咖，於該第一表 面20a具有複數電性接觸墊2〇1，該第一表面.及該些 電性接觸墊2〇1上設有第一防焊層21a，且該第一防㈣ 21具有複數對應外露出各該電性接觸墊2qi之第一開孔 ❿⑽；㈣導電柱24，係對應設於各該外露之電性接觸 墊201上，該導電柱24之高度係為20至60微米（㈣）； 以及複數焊接材料25，係對應設於各該導電柱24上。 依上述之封裝基板，該導電柱24之高度係最佳為4〇 微米（// in)。The first surface _ of the Sr:: and the second surface are formed by a solder resist layer 21a and a second solder mask layer, and the first 2 first & -= 2: tan layer _ respectively form a plurality of - The opening 2 is corresponding to the respective touch-touch 塾 = as shown in FIG. 3B, in the electrical connection (four) layer 21 a and the first 龆 force 0, the 防子 solder-proof the conductive layer 2 〇 〇 & A conductive layer 22 is formed on the wall of the hole, and a resist layer 23 is formed on the electrode layer 22, and the germanium region 230 is formed with a number of openings corresponding to the s | + & + θ 23 to expose each of the electrical contacts. As shown in Fig. 3C of pad 2, a conductive layer 22 in a conductive (10) m layer of copper may be formed on each of the pads. The electrical contact is connected as shown in Fig. 3D at 2, ::d. Welding material 25. The electric mad formation system may be solder as shown in the figure of f 3E, and the conductive layer prevention layer 21a exposed outside the resist layer 22' is removed, and each of the conductive layers 111004 10 201021171 (four) material 25' Thicker photoresist can be used by the process capability. *Sister 曰 4 竿 于 于 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白 白Lead: ... micron ((4)), preferably 40 microns (two = outer 'removal of the resistive layer 23 and the conductive sound 22 of the crucible 3) This is no longer a description. As a result, the organic layer (0rganic s〇lderabimy (10) ❹(4) sp) 28 is applied to the structure as shown in the figure, and the organic solder layer 28 is formed on the structure shown in the figure. The ball is exposed on the exposed surface to protect the conductive post 24 from the solder ball 塾 = not oxidizing due to external influences. The present invention provides a seed substrate, comprising: a substrate body 20 having a first surface 2a and a second surface, the first surface 20a having a plurality of electrical contact pads 2〇1, the first a first solder resist layer 21a is disposed on a surface of the electrical contact pads 2, and the first anti-four (21) 21 has a plurality of first opening holes (10) corresponding to the respective electrical contact pads 2qi; (4) The conductive pillars 24 are correspondingly disposed on the exposed electrical contact pads 201. The height of the conductive pillars 24 is 20 to 60 micrometers ((4)); and the plurality of soldering materials 25 are correspondingly disposed on the conductive pillars 24 on. According to the package substrate described above, the height of the conductive pillars 24 is preferably 4 微米 micrometers (//in).
II
I 依上述之結構，該導電柱24係可為銅，而該焊接材， 料25係可為焊錫。 依上所述，復包括有機保焊層（〇rganics〇lderabiiHy 111004 11 201021171 preservatives, 0SP)28，係設於該導電柱24之外露表面 上0 又依上述之結構，復包括複數焊球墊202，係設於該 第二表面20b上，並於該第二表面20b上設有第二防焊層 21b，且該第二防焊層21b具有複數對應外露出各該焊球 墊202之第二開孔210b ;復可包括複數焊料球29，係對 ‘並設於各該焊球墊202上；或者，該焊球墊202可供作與 塾閘陣列結構（Land grid array, LGA)之電性連接。 ❹[第二實施例] 請參閱第4圖，係為本發明之封裝基板應用於封裝結 構之示意圖。 如第4圖所示，提供一具有作用面26a之半導體晶片 26，於該作用面26a具有複數電極墊261，並於該電極墊 261上形成表面處理層262，使該些電極墊261對應各該 導電柱24上之焊接材料25，並於廻焊後形成焊料25’， 令該半導體晶片26電性連接至該基板本體20;其中，該 ⑩表面處理層262係可為化鎳浸金（Electroless Ni & Immersion Gold, ENIG)、化鎳 le 浸金（Electroless Nickel/Electroless Pal ladium/Immersion Gold, ENEPIG) 或焊塊底部金屬化（Under bump metallurgy，UBM)結構 層；且於該焊球墊202上形成有焊料球2丨9，藉以電#連 接至外部電子裝置，或者該焊球墊202供作與墊閘陣列結 構（Land grid array, LGA)之電性連接；並於該基板本體 20之第一防焊層21a表面與半導體晶片26之間注入底充 12 111004 201021171 狗·科“，以加強該基板本體2 結合強度。 ” + V體晶片26之間的 =發明提供-種封襞結構’係包括：基 係具有相對之第一表面20a及第— 而目士、电* 弟一表面2〇b’於該第一表 面咖具有複數電性接觸墊2〇1，該第一表面施及該此 1性接觸墊2G1上設有第—防焊層^ 焊層 …具有複數對應外露出各該電性接觸塾2〇1::層 數焊她2,係對應設於各該第二表面 ❹並於㈣二表面伽上設有第二防烊層仙，且該 弟二防焊層21b具有複數對應外露出各該焊球塾2〇2之第 一開孔鳩；複數導電柱24，係、對應設於各該外露之電 上導電柱24之尚度係為20至60微米 (^m);複數焊料25，，係對應設於各該導電柱“上； 以及半導體晶片26,係具有作用面—，於該作用面服 具有複數電極墊26卜並於該電極整261上設有表面處理 層262,該表面處理層262係可為化錄浸金⑻咖〇1_ ❹W & ί麵rsionGold，刪）、化鎳把浸金⑻咖〇1咖According to the above structure, the conductive pillar 24 can be copper, and the solder material 25 can be solder. According to the above, the organic solder resist layer (〇rganics〇lderabiiHy 111004 11 201021171 preservatives, 0SP) 28 is disposed on the exposed surface of the conductive pillar 24 and further comprises a plurality of solder ball pads 202 according to the above structure. Is disposed on the second surface 20b, and is provided with a second solder resist layer 21b on the second surface 20b, and the second solder resist layer 21b has a plurality of corresponding portions to expose the second solder ball pads 202. The opening 210b; the composite may include a plurality of solder balls 29, which are disposed on each of the solder ball pads 202; or the solder ball pads 202 may be used as a power grid array (LGA) Sexual connection.第二 [Second Embodiment] Referring to Fig. 4, there is shown a schematic view of a package substrate of the present invention applied to a package structure. As shown in FIG. 4, a semiconductor wafer 26 having an active surface 26a is provided. The active surface 26a has a plurality of electrode pads 261, and a surface treatment layer 262 is formed on the electrode pads 261, so that the electrode pads 261 are corresponding to each other. The soldering material 25 on the conductive pillars 24, and after soldering, forms a solder 25', so that the semiconductor wafer 26 is electrically connected to the substrate body 20; wherein the 10 surface treatment layer 262 can be nickel immersion gold ( Electroless Ni & Immersion Gold, ENIG), Electroless Nickel/Electroless Pal ladium/Immersion Gold (ENEPIG) or Under bump metallurgy (UBM) structural layer; and the solder ball pad A solder ball 2丨9 is formed on the 202, and is electrically connected to the external electronic device, or the solder ball pad 202 is electrically connected to the land grid array (LGA); and the substrate body 20 is Between the surface of the first solder resist layer 21a and the semiconductor wafer 26, a bottom charge 12 111004 201021171 is added to enhance the bonding strength of the substrate body 2. "Between the V body wafers 26" Structure's include The base has a first surface 20a and a first surface, and the surface of the first surface 20bb has a plurality of electrical contact pads 2〇1, and the first surface applies the The first contact pad 2G1 is provided with a first solder mask layer. The solder layer has a plurality of corresponding external exposed portions. The electrical contact layer 2:1: the number of layers is soldered to her 2, and is correspondingly disposed on each of the second surfaces. a second anti-corrugated layer is provided on the (four) two surface gamma, and the second solder resist layer 21b has a plurality of first opening holes corresponding to the respective solder balls 塾2〇2; the plurality of conductive columns 24, Corresponding to each of the exposed electrical upper conductive pillars 24 is 20 to 60 micrometers (^m); a plurality of solders 25 are correspondingly disposed on each of the conductive pillars; and the semiconductor wafer 26 has a function The surface has a plurality of electrode pads 26 and a surface treatment layer 262 is disposed on the electrode 261. The surface treatment layer 262 can be a chemical immersion gold (8) curry 1_ ❹W & 面 face rsionGold , delete), nickel, immersion gold (8) curry 1 coffee
Nickel/Electroless Pal ladium/Immersion Gold, ENEPIG) 或焊塊底部金屬化（Under bump metallurgy，UM)結構 層4些電極墊261係對應接合至各該導電柱μ上之焊 料25，令該半導體晶片26電性連接異該基板本缉2〇。 依上述之封裝結構，復包括底充材料27，係設於該 基板本體20之第一防焊層21a表面與半導體晶片26之 間；該導電柱24之高度係最佳為4〇微米（# m);該導 111004 13 201021171 ’€枉㈣可為銅’而該焊料25，係可為焊錫。 依上述之封裝結構，復包括焊料球29，传雙於令 焊球墊202上，戎去—阳丄 你口又於各亥 (Land grid s array，lga)之電性連接。 體之i=執本發明之封裝結構’主要係藉由在基板本 .接材料，料莫ί形成導電才主，且在該導電柱上形成有焊 -恭勒 ^電柱之焊料25,電性連接該半導體晶片之 電極墊，又該導雷奴 卞守體日日月之 梭佔外 电柱之尚度約在20至60微米（）， 俾使该底充材料易於填 β ； 隙，日太恭ηΒ 、、 +導姐日曰片與基板本體之間 形成煩料t封襄結構無需在該半導體晶片之電極墊上 形成;fcf·料凸塊，而僅需於導 此製程簡易、結構簡；形成少量焊接材料，因 橋接，=利於形成細間距封裝結構。胃產生㈣ 上述貫施例僅例示性說明本 ;r限制本發明。任何熟習此項技藝之人士=不： ❿變。：：之::’及範疇下’對上述實施例進行修飾與改 範圍所列。 權利保魏圍’應如後述之申請專利 【圖式簡單說明】 圓；第UWB圖係為習知之一種覆晶封裝結構之示意 ί 第2A與2B圖係為習知之另一藉考曰丄 圖； < 为種覆日日封裝結構之示意 示意圖；其 第3A至3E圖係為本發明之封裝基板之 111004 14 意圖 琢第 3E’圖為第3E圖之另 一實施例； 第4 〇 圖係為本發明之封裝基板應用: 要元件符號說明】 2〇 基板本體 11 、 201 焊球墊 110 、 25 防焊層 120 26 半導體晶片 130 、 261 焊料凸塊 14 27 底充材料 16、25， 第一表面 20b 第一防焊層 21b 第—開孔 210b 等電層 23 開口區 24 作用面 262 有機保焊層 高度 29 以及 於封裝結構之示 第二表面 第二防垾 弟一開孔 P且層 導電杈 201021171 202 * 12 13、 % ]3l 15 > 2〇a 2la 21 〇a 22 230 26a ©28 d 15 ^1004Nickel/Electroless Pal ladium/Immersion Gold, ENEPIG) or under bump metallurgy (UM) structural layer 4 electrode pads 261 are correspondingly bonded to the solder 25 on each of the conductive pillars μ, so that the semiconductor wafer 26 The electrical connection is different from the substrate. According to the above package structure, the underfill material 27 is disposed between the surface of the first solder resist layer 21a of the substrate body 20 and the semiconductor wafer 26; the height of the conductive pillar 24 is preferably 4 〇 micron (# m); the guide 111004 13 201021171 '€(4) may be copper' and the solder 25 may be solder. According to the above package structure, the solder ball 29 is further included, and the solder ball is placed on the solder ball pad 202, and the mouth is connected to the anode. The mouth is connected to the ground grid s array (lga). The body i=execution of the package structure of the present invention is mainly formed by forming a conductive material on the substrate, and forming a solder on the conductive pillar with a solder-gongler^electric column 25, electrical The electrode pad of the semiconductor wafer is connected, and the outer portion of the wire rod of the sun and the moon is about 20 to 60 micrometers (), so that the bottom filling material is easy to fill β; , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The solder material, due to bridging, = facilitates the formation of fine pitch package structures. Stomach Production (4) The above examples are merely illustrative of the present invention; r limits the invention. Anyone who is familiar with this skill = no: change. The following examples are modified and modified in the following examples. The right to protect Weiwei' should be patented as described later [simple description of the figure] circle; the UWB diagram is a schematic diagram of a conventional flip-chip package structure. Figures 2A and 2B are another example of the conventional study. < is a schematic diagram of the package structure of the day; the 3A to 3E diagrams are 111004 of the package substrate of the present invention. 14 FIG. 3E' is another embodiment of FIG. 3E; FIG. For the package substrate application of the present invention: Description of the components: 2 〇 substrate body 11 , 201 solder ball pads 110 , 25 solder mask 120 26 semiconductor wafer 130 , 261 solder bumps 14 27 bottom filling materials 16, 25 , a surface 20b first solder mask layer 21b first opening 210b isoelectric layer 23 open region 24 active surface 262 organic solder layer height 29 and second surface of the package structure Conductive 杈201021171 202 * 12 13 , % ]3l 15 > 2〇a 2la 21 〇a 22 230 26a ©28 d 15 ^1004