201015716 九、發明說明： 【發明所屬之技術領域】 本發明係㈣-種半導趙元件，特別是指-種閘極角落呈現拋物線狀 的半導體元件》 【先前技術】 半導體元件係由許多金屬氧化物場效應電晶體（M〇SFET)組構、趨動 而成，而在CMOS製程中NM0S與PM0S中閘極形狀則因製程與功能上的需求 ❹-般連成長條狀的’㈣率半導趙元件閘極結構的形狀職本上可以為任 何形狀，例如三邊形、四邊形、八邊形等。 當啟動半導體元件時’眾多廳-旦同時趨動，所有單位所貢獻之電 流將加成構成所設計的功率或電流。但是，傳統的金屬氧化物場效應電晶 體（M0SFET)為避免聰結構產生尖端放電，因此角落會形弧形，但 這樣圓弧形角落在電晶體運作時會使得電流的被趨財向產生魏，在互 相干擾的情況下，將導致不僅減低半導體元件反應切換速率。再者，造成 ❹加持其歐姆熱的產生’徒然浪費資源，導致降低半導體元件壽命與可靠度。 有鑑於此’本發明遂針對上述習知技術之缺失，提出一種勒新的半導 體元件’以有效克服上述之該等問題。 【發明内容】 本個之主要目的在提供—種⑽s半導體元件，其陳結構的角落為 拋物線狀，以利用拋物線所具有的聚焦光學性質，來達到訊號間彼此不會 互相干擾’藉此使所趨動之電流順暢不亂，以加快電晶體開關的切換速率， 並達到降低元件運作時的溫度，增加元件整體的可靠度。 5 201015716 本發明之另-目的在提供_種神半導體元件，制極結構的角落為 拋物線狀，以利用拋物線所具有的聚焦光學性質，來達到訊號間彼此不會 互相干擾，藉此使所趨動之電流順暢不亂，以加快電晶體開關的切換速率， 並達到降低元件運作時的溫度，增加元件整體的可靠度β 本發明之又-目的在提供-種功料導體元件，其基底或/與護環的角 落為抛物線狀。 為達上述之目的，本發明提供一種CM0S半導體元件，其包含有至少一 〇 電晶體賴，其概在於電晶體結構之閘極結構的祕馳物線狀或此角 落的若干點（一般為五點或超過五點）即符合拋物線曲線。 本發明尚提供一種功率半導體元件，其包含有一基底；至少一護環， 其係位於該基底的周緣；以及至少一閘極結構，其係位於該基底上；其特 徵在於該閘極結構之角落為拋物線狀或此角落的若干點（一般為五點或超 過五點）即符合拋物線曲線。 底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術内 Θ 容、特點及其所達成之功效》 【實施方式】 本發明鑑於習知半導體元件之金屬氧化物場效應電晶體之閘極結構在 角落形成圓形狀結構後會產生電流趨動方向紊亂、歐姆熱增加、元件壽命 減少與可靠度降低等缺失，提出—齡意雜閘極結構之肖落為拋物線狀 的嶄新的半導體元件，來圓其角落頂點，以利用拋物線所具有的光學性質， 整頓電流的趨動方向’減少互相干擾現象，來增加半導體元件的切換速率。 201015716 ❹ 請-併參閱第i圖與第2圖，其係為本發明之⑽s半導體树的立體 不意圖與俯棚。如圖所示’電晶想結構1G包含有_ p型半導體基底（或 N-welm2;兩各位於P型半舰底（或N_weu) 12上的隔離結構14、 14，其_以定義出-主動师6;—位於主動區域16上的_結㈣， 此閘極結構18之四⑽落24為拋物雜，且符合方程式(^χ2)，a〇為 任意數；-源極摻雜區26與一閘極摻雜區28，其係位於閉極結構^兩側 之P型半導體基底（或N-well) 12内，源極摻_6朗極摻雜區现係 利用對p型半導體基底丨2 (或N_wel i)進行N+ (或p+)離子摻雜所形成。 上述之拋物線狀角落24係可以用蝕刻、雷射或其它方式製得。 再者’請參閱第3圖，閘極結構18上可更包含有一金屬層3〇，且此金 顧30與閘極結構18之接點處（咖㈣b，是位於閘極結構圓弧狀角 落之拋物線的焦點’鑑此’可增加開關速率以及減少自發性的雜訊干擾。 請參閱第4圖，其係本發明之功率半導體元件的—具體實施例示意圖。 如圖所示，本發明之功率半導體元件包含有一基底4〇，其外圍利用雷射、 ©微祕刻或其它方式形成數铜以提㈣高壓雜喊環（卩娜職） 42 ;以及數個位於基底4〇上的閘極結構44。其中，基底4〇的角落利用雷 射、微影蝕刻或其它方式形成皆為拋物線狀，且符合方程式& = 〇〆），Μ 為任意數’而位絲底3G _之護環也同樣具有肖料她物線狀且符合 方程式〇-«〆），沾為任意數之特性。 再者，功率半導體元件之閘極結構44，如同先前之CMOS元件，角落呈 現拋物線狀’且符合方程式(v，2)，a3離意數。舉例來說，當閉極結 201015716 構44為四邊形時’則如第5圖所示，閉極結構44角落符合方程式(㈣㈣， 且角落之中心點係位於0-〇.5χ2)拋物線之頂點。 此外’因為功率半導體元件上之閘極結構44為了使基底單位面積 上能具備有衫數量_極結構44，歧生出衫不同形__結構 44。但所有多邊形綠也皆符合方程式(户岣（其中a為任意數〉鑑此， 當閘極結構44為五邊形時，則如第6圖所示，閘極結構& _落符合方 蠡程式且角落之中心點係位於拋物線户^之頂點。當開極結㈣ ©為六邊形時，如第7圖所示，閘極結構44的角落符合方程式㈣且角落 之中心點係位於抛物線少=lx2之頂點。 β再者，功率半導體元件上更具有一金屬層此金屬層可分為兩類：一 是Dmin (汲極）上的金屬直接與功率半導體上問極上的金屬連接（即 short) 蚁Drain(祕)上金屬sepame，其健於_結構上形 成金屬層ifj此金屬層與閘極結構之接觸點位置係位於閑極結構角落之抛 物線·點上，僅需符合設計準則即可。藉由這樣的結構設計，可增加開 © 關速率以及減少自發性的雜訊干擾。 舉例來說’當閘極結構44與金屬層46結構如第8圓所示之四邊形時， 金屬層46與閘極結構44之接點處（c〇ntact) b，是位於閘極結構圓弧狀 角落之拋物線的焦點上。 本發明藉由利用拋物線的光學特性，產生聚焦功能，來達到使半導體 讀之所有電晶體運作咐會產生職互奸擾，使所趨_電流順暢不 201015716 鑑此’在電晶體元件内被趨動的電流不會互相干擾之前提下，將可以 使電晶體元件整體的切換速率增加，再者可有效避免習知僅使用圓弧狀角 落設計時，會產生歐姆熱，造成資源浪費等問題，並且本發明之具有拋物 線角落之半導體元件的整體壽命能較為延長且可靠度可大幅度提升。 綜上所述，本發明係提出一種嶄新的半導體元件，其電晶體結構之閘 極結構的角落係成拋物線狀，以利用拋物線所具有的聚焦光學性質，來達 到訊號不互相干擾，以使所趨動之電流順暢不亂，而增加電晶體開關的切 換速率並達到降低元件運作時的溫度，增加半導體元件整體的可靠度。 再者，閘極結構上之金屬石夕化物與閘極結構之接點處，是位於閉極結構之 圓弧狀角落之拋物線的焦點，以增加開關速率以及減少自發性的雜訊干擾。 唯以上所崎，縣本發明之較佳實細，並_來蚊本發明 實施之範®。故即凡依本伽㈣範_狀特徵構_為之均等變化 或修飾，均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 第1 ®係本發明之CMOS半導體結構的立體示意圖。 第2圖係本發明之⑽S半導體結構的俯視示意圖。 S 3關本發明之具有_結構上金屬層之⑽s半導觀構的立體示音 圖。 〜 第4圖係轉明之功轉導體元件的—具體實施例示意圖。 ^ 5圖係轉社轉半導體树之祕結縣四邊辦狀體實 惹圖。 201015716 第6圖係本發明之功率半導體元件之閘極結構呈現五邊形時的具體實施例 示意圖。 第7圖係本發明之功率半導體元件之閘極結構呈現六邊形時的具體實施例 示意圖。 第8圖係本發明之具有閘極結構上金屬層之功率半導體元件結構的立體示 意圖。 【主要元件符號說明】 10電晶體結構 12P型半導體基底 14、14’隔離結構 16主動區域 18閘極結構 24角落 26源極摻雜區 Q 28閘極摻雜區 30金屬層 40基底 42護環 44閘極結構 46金屬層 b接點處201015716 IX. Description of the Invention: [Technical Field] The present invention is a (four)-a semi-conductive semiconductor element, particularly a semiconductor element having a parabolic shape at a gate corner. [Prior Art] A semiconductor element is oxidized by many metals. The field effect transistor (M〇SFET) is constructed and oscillated. In the CMOS process, the gate shape of NM0S and PM0S is increased by the process and function requirements. The shape of the gate structure of the guide element can be any shape, such as a trigon, a quadrangle, an octagon, and the like. When a semiconductor component is activated, the numerous cells are simultaneously driven, and the current contributed by all the cells will add up to constitute the designed power or current. However, the traditional metal oxide field effect transistor (M0SFET) is used to avoid the tip discharge of the Cong structure, so the corners will be curved, but such a circular arc will cause the current to be generated when the transistor is operated. In the case of mutual interference, it will result in not only reducing the switching rate of the semiconductor element reaction. Furthermore, causing ❹ to increase the production of ohmic heat is a waste of resources, resulting in reduced lifetime and reliability of semiconductor components. In view of the above-described drawbacks of the present invention, a new semiconductor element is proposed to effectively overcome the above problems. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a (10) s semiconductor device in which the corners of the structure are parabolic, in order to utilize the focusing optical properties of the parabola to achieve that the signals do not interfere with each other. The current of the driving is smooth and unobtrusive, so as to speed up the switching speed of the transistor switch, and reduce the temperature when the component operates, and increase the overall reliability of the component. 5 201015716 Another object of the present invention is to provide a semiconductor element in which the corners of the pole structure are parabolic in order to utilize the focusing optical properties of the parabola to achieve mutual interference between the signals, thereby making the trend The current is smooth and uninterrupted, so as to speed up the switching rate of the transistor switch, and reduce the temperature at the time of operation of the component, and increase the reliability of the overall component of the component. The present invention is further intended to provide a conductor element, a substrate or / The corner of the guard ring is parabolic. In order to achieve the above object, the present invention provides a CMOS semiconductor device comprising at least one germanium transistor, which is substantially in the form of a secret structure of a gate structure of a transistor structure or a plurality of points in the corner (generally five Point or more than five points) is in line with the parabolic curve. The present invention further provides a power semiconductor device comprising a substrate; at least one guard ring on a periphery of the substrate; and at least one gate structure on the substrate; characterized by a corner of the gate structure It is a parabolic curve or a number of points in this corner (generally five or more than five points). The details of the present invention, the contents of the technology, the features, and the effects achieved by the present invention will be more readily understood by the following detailed description. [Embodiment] The present invention is directed to the metal oxide field effect of conventional semiconductor devices. When the gate structure of the crystal forms a circular structure at the corner, there will be a turbulence in the direction of current escaping, an increase in ohmic heat, a decrease in the life of the device, and a decrease in reliability. It is proposed that the new structure of the gate-like gate is parabolic. The semiconductor component is rounded to its corner vertices to take advantage of the optical properties of the parabola and to rectify the direction of current flow to reduce mutual interference to increase the switching rate of the semiconductor component. 201015716 ❹ Please - and refer to Figures i and 2, which are the three-dimensional not intended and the shed of the (10)s semiconductor tree of the present invention. As shown in the figure, the electro-optical structure 1G includes a _ p-type semiconductor substrate (or N-welm 2; two isolation structures 14 and 14 each located on a P-type half-ship (or N_weu) 12, which are defined by - The active member 6; the _ junction (4) located on the active region 16, the fourth (10) of the gate structure 18 is 24 parabolic, and conforms to the equation (^χ2), a 〇 is an arbitrary number; - the source doping region 26 And a gate doped region 28, which is located in a P-type semiconductor substrate (or N-well) 12 on both sides of the closed-pole structure, and the source-doped -6-doped region is utilized by the p-type semiconductor substrate丨2 (or N_wel i) is formed by N+ (or p+) ion doping. The above parabolic corner 24 can be made by etching, laser or other means. See also Figure 3, gate structure 18 may further include a metal layer 3〇, and the contact point between the gold matrix 30 and the gate structure 18 (Cai (4) b, is the focus of the parabola at the arc-shaped corner of the gate structure, which can increase the switching rate. And reducing the spurious interference of spurious. Please refer to Fig. 4, which is a schematic diagram of a specific embodiment of the power semiconductor device of the present invention. The power semiconductor device of the present invention comprises a substrate 4〇, the periphery of which is formed by laser, © micro-secret or other means to form a plurality of copper (IV) high-voltage shunt ring (卩娜职) 42; and several are located on the substrate 4 The gate structure 44. wherein the corners of the substrate 4 are formed by laser, lithography or other means are parabolic, and conform to the equation & = 〇〆), Μ is any number ' and the bottom of the wire 3G _ The retaining ring is also similar to her linear shape and conforms to the equation 〇-«〆, which is characterized by any number. Furthermore, the gate structure 44 of the power semiconductor component, like the previous CMOS component, has a parabola angle and conforms to equation (v, 2), a3 being deliberate. For example, when the closed pole junction 201015716 is a quadrilateral, then as shown in Fig. 5, the corner of the closed pole structure 44 conforms to the equation ((4) (4), and the center point of the corner is at the apex of the parabola of 0-〇.5χ2). In addition, the gate structure 44 on the power semiconductor element has a different shape __ structure 44 in order to provide the number of shirts _ pole structure 44 per unit area of the substrate. However, all polygon greens also conform to the equation (household (where a is an arbitrary number). When the gate structure 44 is a pentagon, as shown in Fig. 6, the gate structure & _ falls in accordance with the square The center point of the program and the corner is at the apex of the parabola. When the open junction (4) © is hexagonal, as shown in Fig. 7, the corner of the gate structure 44 conforms to the equation (4) and the center point of the corner is at the parabola. Less = the apex of lx2. β further, there is a metal layer on the power semiconductor component. The metal layer can be divided into two types: one is that the metal on the Dmin is directly connected to the metal on the power semiconductor (ie, Short) ant Drain (secret) on the metal sepame, which is formed on the _ structure to form a metal layer ifj. The contact point position of the metal layer and the gate structure is located at the parabola point of the corner of the idle pole structure, only need to meet the design criteria With such a structural design, the turn-on rate can be increased and the spurious noise can be reduced. For example, when the gate structure 44 and the metal layer 46 have a quadrangle as shown in the eighth circle, the metal layer 46 and the junction of the gate structure 44 C〇ntact) b is the focus of the parabola at the arcuate corner of the gate structure. The present invention utilizes the optical properties of the parabola to produce a focusing function to achieve the operation of all the transistors of the semiconductor read. Rape, make the trend _ current smooth without 201015716 This is to say that the current that is driven in the transistor element will not be interfered with each other, it will increase the switching rate of the whole crystal element, and can effectively avoid It is known that when only the arc-shaped corner design is used, ohmic heat is generated, which causes waste of resources, and the like, and the overall life of the semiconductor element having the parabolic corner of the present invention can be extended and the reliability can be greatly improved. The present invention provides a novel semiconductor device in which the corners of the gate structure of the transistor structure are parabolically shaped to utilize the focusing optical properties of the parabola to achieve that the signals do not interfere with each other, so that the current flowing is smooth. Do not mess, but increase the switching rate of the transistor switch and reduce the temperature when the component operates, increase the semiconductor component Reliability. Furthermore, the junction of the metal-lithium compound and the gate structure on the gate structure is the focus of the parabola at the arc-shaped corner of the closed-pole structure to increase the switching rate and reduce the spontaneity. The interference is only the above, the county is better than the invention, and the mosquito is the implementation of the invention. Therefore, the equivalent variation or modification of the genus It is included in the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A first schematic diagram of a CMOS semiconductor structure of the present invention is shown in Fig. 2. Fig. 2 is a schematic plan view of a (10)S semiconductor structure of the present invention. A stereophonic diagram of a (10)s semi-conducting structure with a metal layer on the structure. ~ Figure 4 is a schematic diagram of a specific embodiment of a transposed conductor element. ^ 5 The picture is transferred to the semiconductor tree of the secret county of the four sides of the county. 201015716 Fig. 6 is a schematic view showing a specific embodiment when the gate structure of the power semiconductor device of the present invention exhibits a pentagon shape. Fig. 7 is a view showing a specific embodiment of the gate structure of the power semiconductor device of the present invention in the form of a hexagon. Fig. 8 is a perspective view showing the structure of a power semiconductor element having a metal layer on a gate structure of the present invention. [Main component symbol description] 10 transistor structure 12P type semiconductor substrate 14, 14' isolation structure 16 active region 18 gate structure 24 corner 26 source doping region Q 28 gate doping region 30 metal layer 40 substrate 42 guard ring 44 gate structure 46 metal layer b junction