201015178. \j r 26299twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種陣列基板與顯示面板，且特別是 有關於一種主動元件陣列基板（Active device array substrate)與液晶顯示面板（Liquid Crystal Display panel， LCD panel)。 ❹ 【先刖技術】 為了配合現代之生活模式，視訊或影像裝置之體積曰 漸趨於輕薄。隨著光電技術與半導體製造技術的發展，平 面型顯示器（Flat Panel Display, FPD)，例如液晶顯示器， 已逐漸成為顯示器產品之主流。 一般而言，液晶顯示器是由液晶顯示面板與背光模組 (Backlight Module)所組成，而液晶顯示面板又是由主動 =件陣列基板、彩色濾光基板、以及液晶層所組成。在液 晶顯示面板的設計中，需衡量主動元件陣列基板的周邊電 路（Periphery circuits )的電阻值與驅動晶片的匹配性。特 別疋’隨著液晶顯示器的高解析度與周邊電路區狹小化的 發展’在周邊電路區中的引線電阻（leadlineresistance) 將成為影響顯示品質的關鍵因素之一。 圖1為習知的主動元件陣列基板的示意圖。請參照圖 夕此主動元件陣列基板100包括：基板110、畫素陣列120、 多數條引線130與多數個接墊14〇。基板11()具有顯示區 Π2、引線區114與接墊區Π6。晝素陣列12〇是由多條掃 5 26299twf.doc/n 201015178 描線122、多條資料線124、多個主動元件126與多個奎素 電極128所構成。引線130設置在引線區1 μ中，日胞: 晶片（未緣不）疋接合在接塾區116中的接塾上140。值 得注意的是，由於引線130長度的差異，使得引線區114 中間部分的引線電阻值R2遠小於引線區114兩側部分的 引線電阻值Rl、R3。由於引線電阻值R1、R2、R3彼此 之間的差異，使得驅動晶片所輸出的電壓信號在經弓丨線 130傳遞後’在顯示區Π2中產生不同程度的壓降。因此， ® 若是引線電阻值R卜R2、R3的差異程度過大，具有此主 動元件陣列基板100的液晶顯示面板（未繪示）則會發生 顯示晝面不均的異常現象。 對於上述的顯示異常，美國專利US 6,879,367與美國 專利公開公報US 2004/0239863已提出相關的解決方法。 在美國專利US 6,879,367中，將原先引線電阻較小的引線 彎曲化，亦即，以增加引線長度的方式來增加引線電阻值， 進而達到使引線電阻值均化的效果。然而，利用引線的彎 φ 曲配置需要額外的引線配置面積，因此，不利於周邊電路 區狹小化的發展。再者，彎曲的引線也不易計算其電阻值， 而在電路設計上產生困難。 另外’在美國專利公開公報US 2004/0239863中，將 原先引線電阻較大的配線向外擴展，且配合變化引線寬度 的方式來調整引線電阻值’進而達到使引線電阻值均化的 蛛果。然而’變化引線寬度的方式也需要額外的引線配置 面積，而不利於周邊電路區的狹小化發展。承上述，習知 6 ^ * W 26299twf.doc/n 201015178 的主動7L件㈣基板並紐同時兼顧提供良好的驅動電 壓、以及周邊電路區的狹小化的需求。 【發明内容】 有鑑於此，本發明提供—種主動元件陣列基板，能夠 在周邊電路區有限的面積内使引線的電阻值均化，進而使 驅動晶片能提供相同大小的驅動電壓。 本發明還提供-種液晶顯示面板，具有上述的主動元 件陣列基板，而具有良好的顯示品質。 基於上述，本發明提出一種主動元件陣列基板，包括 一基板、一晝素陣列、多數條引線以及多數個接墊。基板 t有-顯示區、-引線區與—接墊區，引線區位於顯示區 /、接塾區之間。晝素陣列設置於顯示區中。引線設置於引 f區中’引線電性連接到晝素陣列，且位在引線區中間部 /刀的引線的電阻值小於位在引線區兩侧部分的引線的電阻 ❿ 值。接墊設置於接塾區中，接墊電性連接到對應的引線， 且位在接麵巾間部分的接墊的電阻值讀位在接塾區兩 側部分的接墊的電阻值。 基於上述，本發明又提出—種液晶顯示面板，包括·· 動元件陣列基板、彩色濾光基板以及液晶層。彩 色=基板對向於线元件陣板。液晶層設置於主動 兀件陣列基板與彩色濾光基板之間。 ，本發明的—實施例中，上述的每—接塾包括··電性 接、病、晶片輪出端以及延伸部，而延伸部位於電性接續 201015178 …一tw 26299twfd〇c/n 端與晶片輪出端之間，其中，位在接墊區中間部分的接墊 的延伸部的長度大於位在接墊區兩侧部分的接塾的延伸部 的長度。 在本發明的一實施例中，上述的每一接墊包括：一第 一導電層、一絕緣層與一透明導電層。第一導電層設置於 基板上。絕緣層設置於第一導電層上，此絕緣層具有至少 一接觸窗開口。透明導電層設置於絕緣層上且透過接觸窗 ❹ 開口電性連接第一導電層。 在本發明的一實施例中’上述位在接墊區中間部分的 接塾的透明導電層的寬度小於位在接墊區兩側部分的接塾 的透明導電層的寬度。 在本發明的一實施例中，上述位在接墊區中間部分的 接墊的接觸窗開口的面積小於位在接墊區兩侧部分的接墊 的接觸窗開口的面積。 在本發明的一實施例中，上述的位在接墊區中間部分 的接墊的接觸窗開口的數量少於位在接墊區兩侧部分的接 © 墊的接觸窗開口的數量。 在本發明的一實施例中，上述的每一接塾更包括至少 一弟二導電層，電性連接到第一導電層及透明導電層，且 多個導電路徑位於第二導電層、第一導電層與透明導電層 之間。 曰 在本發明的一實施例中，上述的透明導電層的材質包 括銦錫氧化物或銦鋅氧化物。 在本發明的一實施例中，上述的晝素陣列包括：多數 201015178 υ / * υ! rw 26299twf.doc/n =描線與錄歸鱗1触主動元件 ^。主動元件麟應的掃描線以及 :極與對應的主動元件電性連接。主動元件包$膜ί 本發二月因採用具有第_導電層與透明導電層的 盘二i猎t調整接墊的長度、寬度、接觸窗開口的面積 八數1等；或利用跳層方式在第—導電層、第201015178. \jr 26299twf.doc/n IX. Description of the Invention: The present invention relates to an array substrate and a display panel, and more particularly to an active device array substrate and Liquid crystal display panel (LCD panel). ❹ 【Advanced Technology】 In order to cope with the modern lifestyle, the size of video or video devices has become thinner and lighter. With the development of optoelectronic technology and semiconductor manufacturing technology, Flat Panel Display (FPD), such as liquid crystal display, has gradually become the mainstream of display products. Generally, a liquid crystal display is composed of a liquid crystal display panel and a backlight module, and the liquid crystal display panel is composed of an active array substrate, a color filter substrate, and a liquid crystal layer. In the design of the liquid crystal display panel, it is necessary to measure the matching between the resistance value of the peripheral circuit of the active device array substrate and the driving wafer. In particular, as the high resolution of the liquid crystal display and the narrowing of the peripheral circuit area have progressed, the lead line resistance in the peripheral circuit area has become one of the key factors affecting the display quality. 1 is a schematic view of a conventional active device array substrate. Referring to the figure, the active device array substrate 100 includes a substrate 110, a pixel array 120, a plurality of leads 130, and a plurality of pads 14A. The substrate 11 () has a display area Π2, a lead area 114, and a pad area Π6. The halogen array 12 is composed of a plurality of sweeps 26 26299 twf.doc/n 201015178 traces 122, a plurality of data lines 124, a plurality of active elements 126, and a plurality of quetia electrodes 128. The lead 130 is disposed in the lead region 1 μ, and the wafer: wafer (not edge) is bonded to the tab 140 in the interface 116. It is to be noted that the lead resistance value R2 of the intermediate portion of the lead portion 114 is much smaller than the lead resistance values R1, R3 of the both portions of the lead portion 114 due to the difference in the length of the lead 130. Due to the difference between the lead resistance values R1, R2, R3, the voltage signal outputted by the drive wafer is caused to have different degrees of pressure drop in the display area Π2 after being transmitted through the bow line 130. Therefore, if the degree of difference between the lead resistance values R, R2, and R3 is too large, an abnormal phenomenon in which the surface unevenness is displayed occurs on the liquid crystal display panel (not shown) of the active element array substrate 100. For the display anomalies described above, a solution has been proposed in U.S. Patent No. 6,879,367 and U.S. Patent Publication No. US 2004/0239863. In U.S. Patent No. 6,879,367, the lead having a small lead resistance is bent, that is, the lead resistance is increased by increasing the length of the lead, thereby achieving the effect of equalizing the resistance of the lead. However, the use of the bent φ curve configuration of the leads requires an additional lead arrangement area and, therefore, is disadvantageous for the development of the narrowness of the peripheral circuit area. Moreover, the bent leads are also difficult to calculate the resistance value, which causes difficulty in circuit design. Further, in the U.S. Patent Publication No. 2004/0239863, the wiring having a large lead resistance is expanded outward, and the lead resistance value is adjusted in accordance with the variation of the lead width to further achieve the effect of equalizing the lead resistance value. However, the manner in which the lead width is varied also requires an additional lead configuration area, which is disadvantageous for the narrow development of the peripheral circuit area. In view of the above, the active 7L (4) substrate of the conventional 6 ^ * W 26299twf.doc/n 201015178 also meets the need to provide good driving voltage and narrowing of the peripheral circuit area. SUMMARY OF THE INVENTION In view of the above, the present invention provides an active device array substrate capable of homogenizing the resistance of a lead within a limited area of a peripheral circuit region, thereby enabling the drive wafer to provide the same magnitude of drive voltage. The present invention also provides a liquid crystal display panel having the above-described active element array substrate and having good display quality. Based on the above, the present invention provides an active device array substrate comprising a substrate, a halogen array, a plurality of leads, and a plurality of pads. The substrate t has a display area, a lead area and a pad area, and the lead area is located between the display area / the junction area. The pixel array is disposed in the display area. The leads are disposed in the lead-f region. The leads are electrically connected to the pixel array, and the resistance of the leads located at the middle portion of the lead portion/knife is smaller than the resistance ❿ of the leads located at both sides of the lead portion. The pads are disposed in the interface region, the pads are electrically connected to the corresponding leads, and the resistance values of the pads located in the portion between the pads are read at the resistance values of the pads on both sides of the interface. Based on the above, the present invention further provides a liquid crystal display panel including a dynamic element array substrate, a color filter substrate, and a liquid crystal layer. Color = Substrate is opposite to the line component board. The liquid crystal layer is disposed between the active element array substrate and the color filter substrate. In the embodiment of the present invention, each of the above-mentioned interfaces includes an electrical connection, a disease, a wafer wheel end and an extension, and the extension portion is located at the electrical connection 201015178 ... a tw 26299twfd 〇 c / n end and Between the wafer wheel ends, wherein the length of the extension of the pad located in the middle portion of the pad region is greater than the length of the extension of the interface at the sides of the pad region. In an embodiment of the invention, each of the pads includes a first conductive layer, an insulating layer and a transparent conductive layer. The first conductive layer is disposed on the substrate. The insulating layer is disposed on the first conductive layer, the insulating layer having at least one contact opening. The transparent conductive layer is disposed on the insulating layer and electrically connected to the first conductive layer through the contact opening. In an embodiment of the invention, the width of the transparent conductive layer of the interface at the intermediate portion of the pad region is smaller than the width of the transparent conductive layer of the interface at both sides of the pad region. In an embodiment of the invention, the area of the contact opening of the pad located in the middle portion of the pad region is smaller than the area of the contact opening of the pad located on both sides of the pad region. In an embodiment of the invention, the number of contact openings of the pads in the middle portion of the pad region is less than the number of contact openings in the pads of the pads on both sides of the pad region. In an embodiment of the invention, each of the interfaces further includes at least one second conductive layer electrically connected to the first conductive layer and the transparent conductive layer, and the plurality of conductive paths are located in the second conductive layer, first Between the conductive layer and the transparent conductive layer. In an embodiment of the invention, the material of the transparent conductive layer comprises indium tin oxide or indium zinc oxide. In an embodiment of the invention, the above-described pixel array includes: a plurality of 201015178 υ / * υ! rw 26299twf.doc / n = line and record scale 1 touch active element ^. The scanning line of the active component and the pole are electrically connected to the corresponding active component. Active component package $film ί In February, the length and width of the pad, the area of the contact window opening, and the like were adjusted by using the disk with the first conductive layer and the transparent conductive layer. In the first conductive layer, the first
^明導電層之間設置多轉電路徑，朗可使位在接^區 中間部分的接墊的電阻值大於位在接墊區& 的電阻值。因此，可對於不同區_引_阻值軸^匕塾 而減少因引_電阻值差異所造成的顯示異常。利用接塾 區的内部空間進行電阻值的調整，無需增加引線配置面 積，而能夠使引線的設計更有彈性。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實施例，並配合所附圖式，作詳細說明如下。、 【實施方式】 主動元件陣列基板 第一實施例 圖2為本發明第一實施例的主動元件陣列基板的示意 圖。圖3為本發明第一實施例的主動元件陣列基板的接墊 區的放大示意圖。圖4為沿著圖3的A_A，線的剖面示意 圖。請共同參照圖2、圖3與圖4，此主動元件陣列基板 200包括一基板210、一晝素陣列220、多數條引線23〇以 9 26299twf.doc/n 201015178 及多數個接墊240。基板210具有一顯示區212、一引線區 214與一接墊區216,引線區214位於顯示區212與接塾區 216之間。晝素陣列220設置於顯示區212中。引線230 5又置於引線£ 214中’引線230電性連接到晝素陣歹j 220， 且位在引線區214中間部分的引線230的電阻值R2小於 位在引線區214兩側部分的引線230的電阻值ri、R3。 接墊240設置於接墊區216中’接墊240電性連接到對應 的引線230 ’且位在接塾區216中間部分的接墊240的電 阻值R5大於位在接塾區216兩側部分的接墊240的電阻 值 R4、R6 〇 請再參照圖2，晝素陣列220可以包括：多數條掃描 線222與多數條資料線224、多數個主動元件226及多數 個晝素電極228。主動元件226與對應的掃描線222以及 資料線224電性連接。晝素電極228與對應的主動元件226 電性連接。主動元件226包括薄膜電晶體或其他適合的元 件’如二極體。 ❹ 在此實施例中’每一接墊240包括:電性接續端240a、 晶片輸出端240b以及延伸部240c，而延伸部240c位於零 性接續端240a與晶片輸出端240b之間，其中，位在接墊 區216中間部分的接墊240的延伸部240c的長度大於位在 接墊區216兩側部分的接墊240的延伸部240c的長度。藉 此，可使位在接墊區216中間部分的接墊240的電阻值R5 大於位在接墊區216兩側部分的接墊240的電阻值R4、 R6 ’而對於引線230的電阻值幻、R2、R3進行補償。 201015178w 26299twf.doc/n 特別是’此接墊240可為兩層結構。在此實施例中， 每一接墊240包括：一第一導電層242、一絕緣層244與 一透明導電層246。第一導電層242設置於基板21〇上。 絕緣層244設置於第一導電層242上，此絕緣層244具有 至少一接觸窗開口 244a。透明導電層246設置於絕緣層244 上且透過接觸窗開口 244a電性連接第一導電層242。亦 即，在接墊區216的内部空間中，對於具有第一導電層242 與透明導電層246之雙層結構的接塾24Ό進行長度、寬度 等的調整’藉此可以降低引線230電阻值Ri、R2、R3的 差異里，而達到引線230電阻值均化的設計需求，也無需 增加引線區214的配置面積。另外，透明導電層246的材 質包括錮錫氧化物或銦辞氧化物。再者，圖4中還繪示驅 動晶片（未繪示）的凸塊B與晶片輸出端24〇b電性連接 的情形。 圖5為圖4的接墊的等效電路示意圖。請參照圖4與 圖5，由於此接墊240具有第一導電層242與透明導電^ © 246 ’.所以可藉由調整第一導電層242或透明導電層24曰6 的長度與寬度，以調整接墊240的電阻值。如圖5戶^示， R242為第一導電層242的電阻值，其為可調整的數值；Rch 為第一導電層242與透明導電層246之間的接觸電阻，g 為固疋的數值；R246為透明導電層246的電阻值，其為可 調整的數值。藉由調整R242與R246的數值’可以得^具有 不同電阻值R4、R5、R6的接墊240,如圖2所示。/、 更詳細而言，可使位於中間部分的接墊24〇的電阻值 201015178 υ /1 υ 1 ο^,ι ι W 26299twf.doc/n R5大於位在触區216 _部分的接墊24()的電阻 R4、R6以進行接墊240的電阻值的調整，即可對於 230的電阻值R1、R2、R3進行補償。如此—來，如此二 來，可使驅動晶片（未緣示）提供相同大小的驅動電魔。 以下說明調整接墊240電阻值的方法。 圖6A〜圖6D為本發明較佳實施例的位於接塾區中的 數種接墊的示意圖。請先參照圖6A與圖6B，可利用透明 導電層246對於接墊240的電阻值進行調整。—般而言， 第一導電層242使用金屬材料（例如鋁、鉻），而透明導 電層246大多使用銦錫氧化物，由於銦錫氧化物的電阻值 比金屬材料高10〜40倍’若是再考慮膜厚的差異性，其差 異更可高達60〜1〇〇倍。所以，如圖6A所示，使透明導 電層246的寬度較小，則接墊24〇的電阻值上昇；如圖6b 所示，使透明導電層246的寬度較大，則接墊24〇的電阻 值下降。亦即，可控制透明導電層246的寬度來調整接墊 240的電阻值。更詳細而言，請參照圖2、圖與圖， ® 可使位在接墊區216中間部分的接墊240.的透明導電層 246的寬度大於位在接墊區216兩側部分的接墊24〇的透 明導電層246的寬度。如此，可對於引線23〇的電阻值尺卜 R2、R3進行補償。 另外’圖6C與圖6D則是透過調整接墊的延伸部24〇c 的長度，來調整接墊240的電阻值，亦即，如圖sc所示， 使延伸部240c較短，則接墊24〇的電阻值下降；如圖 所不，使延伸部240c較長，則接墊240的電阻值上昇。此 12 201015178 0710182ITW 26299twf.doc/n 部分的内容已經於圖3所述，在此不予以重述。 承上述’此接墊240包含雙層結構的設計，此設計是 利用第一導電層242與透明導電層246的電阻值不同，並 配合長短窄寬的設計調整，以達到均化引線230電阻值的 效果。結果疋’可使驅動晶片（未纟會示）提供相同大小的 驅動電壓，進而可減少引線230的電阻值差異所造成的顯 示異常。由於是利用接墊區216的内部空間，所以無需增 加引線230的配置面積，也可以對於引線23〇的電阻值進 行均化。再者，相較於習知彎曲引線的方式而言，在本實 施例中計算引線230、接墊240的電阻值較為容易。 第一實施例 圖7為本發明第二實施例的主動元件陣列基板的接墊 區的放大示思圖。請參照圖7，此第二實施例的接塾240 與第一實施例的接墊240類似，以相同的符號標示相同的 ❺ 構件。其差別是，在第二實施财，乃是利用調整接觸窗 開口 244a的面積、數量等’來對此接墊24〇的 R5、R0進行調整。 圖8為沿著圖7的B-B，線的剖面示意圖。圖9為圖8 的接塾的等效電路示意圖。請參照囷7、圖圖9，可夢 由調整第-導電層242與透明導電層246之間的接觸^ 積，以調整接墊240的電阻值’如圖9所示，其中，r 為第-導電層242的電阻值’其為固定的數值 = -導電層2公與透明導電層2杯之間的接觸電阻，其為可 13 201015178 v # » v 1 x'W 26299twf.doc/n 凋整的數值；R_246為透明導電層246的電阻值，其為固6 的數值。 ’、”、、疋 更詳細而言，若第一導電層242與透明導電層246之 間的接觸面積越大，則接墊240的電阻值下降；若第—導 電層242與透明導電層246之間的接觸面積越小，則接墊 240的電阻值上昇。藉此，可以使位在接墊區216中間部 分的接墊240的電阻值R5大於位在接墊區216兩側部^ ❻的接墊240的電阻值則、R6。再者，圖8中猶示驅動 晶片（未繪示）的凸塊B與晶片輸出端24%電性連接 情形。 圖10A〜圖1〇Ε為本發明較佳實施例的接墊區中數種 接墊的示意圖。請先參照圖10A與圖1〇B，可利用接觸窗 開口 244a的面積大小來調整接墊24〇的電阻值，亦即，如 圖10A所示，使接觸窗開口 244a的面積較小，則接墊24〇 的電阻值上昇；如圖l〇B所示，使接觸窗開口 2他的面 積較大，則接墊240的電阻值下降。更詳細而言，請參照 ❹ ® 7、® 10A與圖励，可使位在接塾區216中間部分的 接墊240的接觸窗開口 244a的面積小於位在接墊區216 兩側部分的接墊240的接觸窗開口 244a的面積^如此，可 對於引線230的電阻值幻、R2、R3進行補償。 另外，明再參照圖10C與圖1〇d，可利用接觸窗開口 244a的數量多寡來調整接墊24〇的電阻值，亦即，如圖i〇c 所示，接觸窗開口 244a的數量較多，則接墊24〇的電阻值 下降；如圖10D所示，接觸窗開口 24乜的數量較少，則 14 201015178^ 26299tw£doc/n 接塾240的電阻值上昇。更詳細而言，請參照圖7、圖 與圖10D，可使位在接墊區2]6尹間部分的接墊24〇的接 觸窗開口 244a的數量少於位在接墊區216兩側部分的接墊 240的接觸固開口 244a的數量。如此，可對於引線230的 電阻值Rl、R2、R3進行補償。^The multi-turn path is set between the conductive layers, so that the resistance value of the pads in the middle portion of the connection region is greater than the resistance value at the pad region & Therefore, the display abnormality caused by the difference in the value of the lead-in resistance can be reduced for different regions. By adjusting the resistance value by using the internal space of the interface, it is possible to make the design of the lead more flexible without increasing the lead layout area. The above described features and advantages of the present invention will become more apparent from the following description. [Embodiment] Active device array substrate First Embodiment Fig. 2 is a schematic view of an active device array substrate according to a first embodiment of the present invention. Fig. 3 is an enlarged schematic view showing a pad region of an active device array substrate according to a first embodiment of the present invention. Fig. 4 is a schematic cross-sectional view taken along line A-A of Fig. 3; Referring to FIG. 2, FIG. 3 and FIG. 4 together, the active device array substrate 200 includes a substrate 210, a halogen array 220, a plurality of leads 23 9 9 26299 twf.doc/n 201015178 and a plurality of pads 240. The substrate 210 has a display area 212, a lead area 214 and a pad area 216, and the lead area 214 is located between the display area 212 and the interface area 216. The halogen array 220 is disposed in the display area 212. The lead 230 5 is again placed in the lead 214. The lead 230 is electrically connected to the pixel array j 220, and the resistance value R2 of the lead 230 located in the middle portion of the lead portion 214 is smaller than the lead located on both sides of the lead portion 214. The resistance values of 230 are ri, R3. The pad 240 is disposed in the pad region 216. The pad 240 is electrically connected to the corresponding lead 230 ′. The resistance value R5 of the pad 240 located at the middle portion of the interface region 216 is greater than the position on both sides of the interface region 216 . The resistance values R4 and R6 of the pads 240. Referring to FIG. 2 again, the pixel array 220 may include a plurality of scanning lines 222 and a plurality of data lines 224, a plurality of active elements 226, and a plurality of halogen electrodes 228. The active component 226 is electrically coupled to the corresponding scan line 222 and data line 224. The halogen electrode 228 is electrically connected to the corresponding active component 226. Active component 226 includes a thin film transistor or other suitable component such as a diode.每一 In this embodiment, each of the pads 240 includes: an electrical connection end 240a, a wafer output end 240b, and an extension portion 240c, and the extension portion 240c is located between the zero-effect connection end 240a and the wafer output end 240b. The length of the extension 240c of the pad 240 in the middle portion of the pad region 216 is greater than the length of the extension 240c of the pad 240 located at the sides of the pad region 216. Thereby, the resistance value R5 of the pad 240 located in the middle portion of the pad region 216 can be made larger than the resistance values R4, R6' of the pads 240 located at the two sides of the pad region 216, and the resistance value of the lead 230 is illusory. , R2, R3 compensate. 201015178w 26299twf.doc/n In particular, this pad 240 can be a two-layer structure. In this embodiment, each of the pads 240 includes a first conductive layer 242, an insulating layer 244 and a transparent conductive layer 246. The first conductive layer 242 is disposed on the substrate 21A. The insulating layer 244 is disposed on the first conductive layer 242, and the insulating layer 244 has at least one contact opening 244a. The transparent conductive layer 246 is disposed on the insulating layer 244 and electrically connected to the first conductive layer 242 through the contact opening 244a. That is, in the inner space of the pad region 216, the length, width, and the like of the interface 24B having the two-layer structure of the first conductive layer 242 and the transparent conductive layer 246 are adjusted, thereby reducing the resistance value Ri of the lead 230. In the difference between R2 and R3, the design requirement of achieving uniformization of the resistance of the lead 230 does not require an increase in the arrangement area of the lead region 214. In addition, the material of the transparent conductive layer 246 includes antimony tin oxide or indium oxide. Furthermore, FIG. 4 also shows a case where the bump B of the driving wafer (not shown) is electrically connected to the wafer output terminal 24〇b. FIG. 5 is an equivalent circuit diagram of the pad of FIG. 4. FIG. Referring to FIG. 4 and FIG. 5 , since the pad 240 has the first conductive layer 242 and the transparent conductive layer 246 ′′, the length and width of the first conductive layer 242 or the transparent conductive layer 24 曰 6 can be adjusted by Adjust the resistance value of the pad 240. As shown in FIG. 5, R242 is a resistance value of the first conductive layer 242, which is an adjustable value; Rch is a contact resistance between the first conductive layer 242 and the transparent conductive layer 246, and g is a solid value; R246 is the resistance value of the transparent conductive layer 246, which is an adjustable value. The pad 240 having different resistance values R4, R5, R6 can be obtained by adjusting the values of R242 and R246, as shown in Fig. 2. /, In more detail, the resistance value 201015178 υ /1 υ 1 ο^, ι ι W 26299 twf.doc/n R5 of the pad 24 位于 located in the middle portion is larger than the pad 24 of the contact portion 216 _ portion The resistors R4 and R6 of () adjust the resistance values of the pads 240, and can compensate for the resistance values R1, R2, and R3 of 230. In this way, in this way, the driver chip (not shown) can be provided with the same size of driving magic. The method of adjusting the resistance value of the pad 240 will be described below. 6A-6D are schematic views of a plurality of pads in an interface area in accordance with a preferred embodiment of the present invention. Referring first to Figures 6A and 6B, the resistance of the pad 240 can be adjusted using the transparent conductive layer 246. Generally, the first conductive layer 242 uses a metal material (for example, aluminum or chromium), and the transparent conductive layer 246 mostly uses indium tin oxide, since the resistance value of the indium tin oxide is 10 to 40 times higher than that of the metal material. Considering the difference in film thickness, the difference can be as high as 60 to 1 times. Therefore, as shown in FIG. 6A, when the width of the transparent conductive layer 246 is made smaller, the resistance value of the pad 24 is increased; as shown in FIG. 6b, the width of the transparent conductive layer 246 is made larger, and the pad 24 is The resistance value drops. That is, the width of the transparent conductive layer 246 can be controlled to adjust the resistance value of the pad 240. In more detail, referring to FIG. 2 and FIG. 2, the width of the transparent conductive layer 246 of the pad 240. which is located in the middle portion of the pad region 216 is greater than the pads located on both sides of the pad region 216. The width of the 24 inch transparent conductive layer 246. Thus, the resistance values R2 and R3 of the lead wires 23 can be compensated. In addition, FIG. 6C and FIG. 6D adjust the resistance value of the pad 240 by adjusting the length of the extension portion 24〇c of the pad, that is, as shown in FIG. The resistance value of 24 下降 decreases; if the extension portion 240c is made longer, the resistance value of the pad 240 rises. The content of this 12 201015178 0710182ITW 26299twf.doc / n part has been described in Figure 3, and will not be repeated here. According to the above description, the pad 240 includes a double-layer structure, which is designed to utilize the resistance values of the first conductive layer 242 and the transparent conductive layer 246, and is adjusted in accordance with the design of the length, width, and width to achieve the resistance of the homogenizing lead 230. Effect. As a result, 驱动' can drive the driving wafer (not shown) to provide the driving voltage of the same magnitude, thereby reducing the display abnormality caused by the difference in the resistance value of the lead 230. Since the internal space of the pad region 216 is utilized, it is not necessary to increase the arrangement area of the leads 230, and the resistance value of the leads 23A can be equalized. Furthermore, it is easier to calculate the resistance values of the lead wires 230 and the pads 240 in the present embodiment as compared with the conventional method of bending the leads. [First Embodiment] Fig. 7 is an enlarged schematic view showing a pad region of an active device array substrate according to a second embodiment of the present invention. Referring to Figure 7, the interface 240 of this second embodiment is similar to the pad 240 of the first embodiment, with the same reference numerals designating the same 构件 member. The difference is that in the second implementation, R5 and R0 of the pad 24A are adjusted by adjusting the area, the number, etc. of the contact opening 244a. Figure 8 is a cross-sectional view taken along line B-B of Figure 7 . Figure 9 is a schematic diagram of an equivalent circuit of the connector of Figure 8. Referring to FIG. 7, FIG. 9 , it is possible to adjust the contact between the first conductive layer 242 and the transparent conductive layer 246 to adjust the resistance value of the pad 240 as shown in FIG. 9 , where r is the first - the resistance value of the conductive layer 242 'is a fixed value = - the contact resistance between the conductive layer 2 and the transparent conductive layer 2 cup, which is 13 201015178 v # » v 1 x'W 26299twf.doc/n The integer value; R_246 is the resistance value of the transparent conductive layer 246, which is a value of solid 6. In more detail, if the contact area between the first conductive layer 242 and the transparent conductive layer 246 is larger, the resistance value of the pad 240 is decreased; if the first conductive layer 242 and the transparent conductive layer 246 The smaller the contact area is, the higher the resistance value of the pad 240 is. Thereby, the resistance value R5 of the pad 240 located in the middle portion of the pad region 216 can be made larger than the two sides of the pad region 216. The resistance value of the pad 240 is R6. Further, in Fig. 8, the bump B of the driving chip (not shown) is electrically connected to the output terminal of the wafer 24%. Fig. 10A to Fig. 1 A schematic diagram of several types of pads in the pad region of the preferred embodiment of the present invention. Referring first to FIG. 10A and FIG. 1B, the resistance of the pad 24 〇 can be adjusted by the size of the contact opening 244a, that is, As shown in FIG. 10A, when the area of the contact opening 244a is made smaller, the resistance value of the pad 24 is increased; as shown in FIG. 1B, the contact opening 2 is made larger in area, and the pad 240 is The resistance value drops. In more detail, please refer to ❹ ® 7, 10A and the diagram excitation, which can be located in the middle of the junction area 216. The area of the contact opening 244a of the pad 240 is smaller than the area of the contact opening 244a of the pad 240 located on both sides of the pad region 216. Thus, the resistance value of the lead 230, R2, R3 can be compensated. Referring again to FIG. 10C and FIG. 1D, the resistance value of the pad 24 〇 can be adjusted by the number of contact opening 244a, that is, as shown in FIG. Then, the resistance value of the pad 24 下降 decreases; as shown in FIG. 10D, the number of contact opening 24 较少 is small, and the resistance value of the junction 14 240 is increased. For more details, please refer to 7, FIG. 10D, FIG. 10D, the number of contact opening 244a of the pad 24 位 in the pad portion 2] 6 can be made less than the contact of the pad 240 at the two sides of the pad region 216. The number of solid openings 244a is such that the resistance values R1, R2, R3 of the leads 230 can be compensated.
利用調整接觸窗開口 244a的面積、數量，使得原先 電阻值，小的引線23〇可以藉由加上電阻值較大的接塾 240’或疋使得原先電阻值較大的引線23〇可以藉由加上電 阻值較小的接墊240，而達到均化電阻值的效果。By adjusting the area and the number of the contact opening 244a, the original resistance value, the small lead 23〇 can be made by adding the contact 240' or the 电阻 with a larger resistance value, so that the lead 23 with a larger resistance value can be used. The pad 240 having a small resistance value is added to achieve the effect of equalizing the resistance value.
请參照圖10E，每一接墊240可以更包括至少一第二 導電層248，經由透明導電層m與第一導電層242電& 連接。亦即，多連接一層第二導電層248可使接墊的 電阻值變大’另外，也利用跳層連接的方式，在第一導電 層242、第二導電層248與透明導電層246之間設置多個 =電路未緣不）。當導電路徑越多接墊的電阻 同樣地’可使位在接墊區训中間部分的接墊240 Ι 的數量多於位在接塾區216兩側部分的接塾 w2電路㈣數量。如此’可對於引線23G的電阻值 、R3進行補償，而達到電阻均化效果。 夕變第一導電層242與透明導電層246 #方气，、開口 24知的面積或數量，或是利用跳層連接 如ti-Ι*以到均化引線230電阻值R：l、R2、R3的效果。 Λ ’可使轉晶片（树示）提供相同大小的驅動 15 201015178 υ/ιυιοζι iW 26299twf.doc/n 液晶顯示面板 圖11為本發明較佳實施例之一種液晶顯示面板的示 意圖。請參照圖11，此液晶顯示面板300包括：主動元件 陣列基板310、彩色遽光基板320以及液晶層330。主動元 件陣列基板310可以是上述第一實施例或第二實施例的主 動元件陣列基板200。彩色濾光基板320對向於主動元件 陣列基板310。液晶層330設置於主動元件陣列基板31〇 φ 與彩色濾光基板320之間。 此液晶顯示面板300使用了上述的主動元件陣列基板 200，所以，即使引線23〇的電阻不同，藉由接墊區216 的接墊240的補償設計，其驅動晶片（未繪示）仍然能夠 提供相同大小的驅動電壓，進而使液晶顯示面板3〇〇具有 良好的顯示品質。 綵上所述，本發明的主動元件陣列基板與液晶顯示面 板至少具有以下優點： 利用具有第一導電層與透明導電層的接墊，且葬由碉 ❹整接整的長度、寬度、接觸窗開口的面積與數量、 跳層方式在第-導電層、第二導電層、透明導電層之間設 置多個導電路徑’可使位在接塾區中間部分的接墊的電阻 值大於位在接塾區兩侧部分的接墊的電阻值。因此，可對 於不同區域的引線電阻值進行均化，驅動晶片能夠提供大 小相同的驅動電壓，進而減少因引線的電阻值差異所造成 的顯不異常。另外’利用接塾區的内部空間進行接墊的電 阻值調整’無需增加引線配置面積，而能夠使引線的設計 16 201015178 26299twf.d〇c/n 基板有利於周邊電路的 面板能夠顯示;=匕主動元件陣列基板的液晶顯示 ^…、:本&明已以較佳實施例揭露如上，然其並 限^本發明，任何所屬技卿域巾具有通常知識者，在不 明之精神和範圍内，當可作些許之更動與潤飾，Referring to FIG. 10E, each of the pads 240 may further include at least one second conductive layer 248 electrically and electrically connected to the first conductive layer 242 via the transparent conductive layer m. That is, multiple layers of the second conductive layer 248 may be used to increase the resistance of the pads. Additionally, a jump layer connection is also used between the first conductive layer 242, the second conductive layer 248, and the transparent conductive layer 246. Set multiple = circuit not to be). The more conductive paths the resistance of the pads are, the more the number of pads 240 位 in the middle portion of the pad region is greater than the number of pads w2 in the portions of the junction region 216. Thus, the resistance value of the lead 23G and R3 can be compensated to achieve the resistance equalization effect. Evening the first conductive layer 242 and the transparent conductive layer 246 #方气, the area or the number of the openings 24, or using a jump layer connection such as ti-Ι* to the homogenization lead 230 resistance values R: l, R2 The effect of R3. Λ ' can make the transfer wafer (tree) provide the same size of the drive 15 201015178 υ/ιυιοζι iW 26299twf.doc/n Liquid crystal display panel FIG. 11 is a schematic view of a liquid crystal display panel according to a preferred embodiment of the present invention. Referring to FIG. 11, the liquid crystal display panel 300 includes an active device array substrate 310, a color light-emitting substrate 320, and a liquid crystal layer 330. The active element array substrate 310 may be the active element array substrate 200 of the first embodiment or the second embodiment described above. The color filter substrate 320 is opposed to the active device array substrate 310. The liquid crystal layer 330 is disposed between the active device array substrate 31 φ φ and the color filter substrate 320. The liquid crystal display panel 300 uses the active device array substrate 200 described above, so that even if the resistance of the leads 23 is different, the driving chip (not shown) can still be provided by the compensation design of the pads 240 of the pad region 216. The driving voltage of the same size further makes the liquid crystal display panel 3〇〇 have good display quality. As described above, the active device array substrate and the liquid crystal display panel of the present invention have at least the following advantages: using a pad having a first conductive layer and a transparent conductive layer, and burying the length, width, and contact window The area and the number of openings, and the layered manner of placing a plurality of conductive paths between the first conductive layer, the second conductive layer and the transparent conductive layer can make the resistance value of the pads located in the middle portion of the joint region larger than the bit gap The resistance value of the pads on both sides of the crotch area. Therefore, the lead resistance values of different regions can be equalized, and the driving wafer can provide the same driving voltage as the size, thereby reducing the abnormality caused by the difference in the resistance value of the leads. In addition, 'the resistance value adjustment of the pad using the internal space of the interface area' does not require an increase in the lead arrangement area, but enables the design of the lead 16 201015178 26299 twf.d〇c/n substrate to facilitate display of the panel of the peripheral circuit; The liquid crystal display of the active device array substrate has been disclosed above in the preferred embodiment, but it is not limited to the present invention, and any parent domain towel has the usual knowledge, within the spirit and scope of the unknown. When you can make some changes and retouch,
彳H護翻當視伽之㈣專觀圍所界 為準。 巧 【圖式簡單說明】 圖1為習知的主動元件陣列基板的示意圖。 圖2為本發明第一實施例的主動元件陣列基板的示奄 圖。 圖3為本發明第一實施例的主動元件陣列基板的接墊 區的放大示意圖。 圖4為沿著圖3的Α-Α，線的剖面示意圖。 圖5為圖4的接墊的等效電路示意圖。 圖6Α〜圖6D為本發明較佳實施例的接墊區中數種接 塾的示意圖。 圖7為本發明苐二實施例的主動元件陣列基板的接整 區的放大示意圖。 圖8為沿著圖7的Β-Β’線的剖面示意圖。 圖9為圖8的接墊的等效電路示意圖。 圖10Α〜圖10Ε為本發明較佳實施例的位於接墊區中 17 201015178 υ /1 υ 1 δ2ΐ Γ W 26299twf.doc/n 的數種接墊的示意圖。 圖11為本發明較佳實施例之一種液晶顯示面板的示 意圖。 【主要元件符號說明】 100、200、310 :主動元件陣列基板 110、210 :基板 112、212 ··顯示區 ^ 114、214 :引線區 116、216:接墊區 120、220 :晝素陣列 122、222 :掃描線 124、224 :資料線 126、226 :主動元件 128、228 :畫素電極 130、230 :引線 G 140、240 :接墊 240a:電性接續端 240b :晶片輸出端 240c :延伸部 242 :第一導電層 244 :絕緣層 244a :接觸窗開口 246 :透明導電層 18 l W 26299twf.doc/n 248 :第二導電層 300 .液晶顯不面板 320 :彩色濾光基板 330 :液晶層 B ·驅動晶片的凸塊 電阻值 R1~R6 ' Rch ' R242 ' R244 ' R246 *彳H Guarding is regarded as the quaint gamma (4). BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a conventional active device array substrate. Fig. 2 is a schematic view showing an active device array substrate according to a first embodiment of the present invention. Fig. 3 is an enlarged schematic view showing a pad region of an active device array substrate according to a first embodiment of the present invention. Figure 4 is a cross-sectional view along line Α-Α of Figure 3; FIG. 5 is an equivalent circuit diagram of the pad of FIG. 4. FIG. 6A-6D are schematic views of several types of contacts in a pad region in accordance with a preferred embodiment of the present invention. Fig. 7 is an enlarged schematic view showing a finishing area of an active device array substrate according to a second embodiment of the present invention. Figure 8 is a schematic cross-sectional view along the line Β-Β' of Figure 7. FIG. 9 is an equivalent circuit diagram of the pad of FIG. 8. FIG. 10A to 10B are schematic views of several pads in the pad region 17 201015178 υ /1 υ 1 δ2ΐ Γ W 26299twf.doc/n according to a preferred embodiment of the present invention. Figure 11 is a schematic illustration of a liquid crystal display panel in accordance with a preferred embodiment of the present invention. [Main component symbol description] 100, 200, 310: active device array substrate 110, 210: substrate 112, 212 · display area ^ 114, 214: lead region 116, 216: pad region 120, 220: pixel array 122 222: scan lines 124, 224: data lines 126, 226: active elements 128, 228: pixel electrodes 130, 230: leads G 140, 240: pads 240a: electrical connection ends 240b: wafer output ends 240c: extension Portion 242: first conductive layer 244: insulating layer 244a: contact window opening 246: transparent conductive layer 18 l W 26299twf.doc / n 248: second conductive layer 300. liquid crystal display panel 320: color filter substrate 330: liquid crystal Layer B · Bump resistance value of the driver wafer R1~R6 ' Rch ' R242 ' R244 ' R246 *
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