201010515 ‘ 九、發明說明： 【發明所屬之技術領域】 本發明係指一種用於一積體電路中提升靜電放電保護的方法 及其相關靜電放電保護裝置及積體電路，尤指一種利用輸出緩衝 單元導通靜電電流之靜電放電保護方法及其相關靜電放電保護裝 置及積體電路。 ❹ 【先前技術】 靜電放電（Electrostatic Discharge ’ ESD)保護是為了防止積 體電路在生產、測試或使用的過程中，遭到靜電放電對積體電路 造成永久性的破壞。一般而言，積體電路對於靜電放電之防護能 力係隨著其尺寸之縮小而減弱。隨著積體電路製程技術之不斷改 進，積體電路之電晶體尺寸已從次微米進步到深次微米。因此， 如何提升靜電放電保護也就變得更加重要。 〇 請參考第1圖，第1圖為習知具有靜電放電保護功能之一積體 電路10的示意圖。積體電路10包含有一偵測單元1〇〇、一核心電 路102、-:P型金氧半（PMOS)電晶體p2、一_金氧半（NM〇s) 電晶體N2及一電流開關106。偵測單元1〇〇係由一 PM0S電晶體 P1、一 NMOS電晶體N卜一電阻幻及一電容〇所組成，用以 偵測靜電放電的電壓脈衝訊號，以適時開啟電流開關1〇6使靜電 -電流得以導通。換句話說，靜電電流由積體電路ι〇外部進入接腳 *處’透過m順向偏壓到電源’偵測單元1〇〇可於靜電放電發生時 201010515 控制1G6的開啟動作，將靜電電流導通到地端，以避免 靜電電流影響其它元件的運作。PM〇s電晶體p2及丽〇3電晶 體N2係為輸出緩衝單元，用以提供輸出訊號緩衝功能，以避免負 載影響核心電路1〇2之運作。此外，積體電路1〇的輸出端另連接 有-極體D1及D2，提供箝制電壓脈衝的功能，以使靜電電壓被 掛制在-固疋範圍内。值得注意的是，二極體D1及〇2可用二極 體連結方式(伽⑽咖娜之PM〇s電晶體及觀⑽電晶體分 © 別構成。 因此’積體電路10係透過侧單元1〇〇，適時開啟電流開關 106 ’使靜電電流得以導通，並透過二極體及，使靜電電壓 被籍制在固定範圍内。然而，若積體電路1〇未接通正常電源，則 NM〇S 1：晶體N2或PM0S電晶體P2係處於不確定的半開啟狀 L換句話說’NM〇s電晶體N2或腹〇8電晶體p2有可能處於 ❹可以導通電流的情形。在此情形下，若NMOS電晶體N2或PMOS 電晶體P2的晶體寬度較小，當發生靜電放 靜電電料通卿_减喊㈣。 為了避免上述情形發生，一般而言，除了 電晶體 及PM0S電晶體p2必須根據相關靜電放電保護佈局規範（咖 触）加以佈局（Layout)，二極體D1及m也必須以較大面積 佈局。然而，這樣—來，不但晶片面積必須增加，而且也未必能 對導通靜電電触供助益。此外，在_s f晶體N2、蘭s 201010515 電晶體P2與二極體D卜D2之間，習知技術可另外加一電阻rS 以減少流經NMOS電晶體N2及PMOS電晶體P2的靜電電流， 但是當NMOS電晶體Ν2及PMOS電晶體Ρ2處於不確定的半開 啟狀態時，靜電電流依然可能流經NMOS電晶體Ν2及PMOS電 晶體Ρ2。換句話說’即使加了電阻RS，靜電電流還是有機會破壞 NMOS電晶體Ν2或PMOS電晶體Ρ2。 【發明内容】 因此’本發明之主要目的即在於提供用於一積體電路中提升 靜電放電保護的方法及其相關靜電放電保護裝置及積體電路。 本發明揭露一種用於積體電路中提升靜電放電保護的方法， 包含有偵測該積體電路之一電源通道的電源訊號，以產生一债測 結果；以及於該偵測結果顯示該電源通道的電源訊號包含有一脈 衝訊號時，分別控制該積體電路之複數個輸出緩衝單元之輸出情 形’以將該脈衝訊號所引起之電流導通至一地端。 本發明另揭露-種用於，積體電路中提升靜電放電保護的褒 置，包含有一開關，包含有一第一端耦接於該電源通道，一第二 端耗接於該地端’-第三端’及-第四端耦接於該分派單元，用 來根據該第-端至該紅端的電壓差，控她第—端至該第四端 之訊號連結，職生該侧結果，-電阻，触於制關之該第 -端與該第二端之間；以及-電容’她於該開關之該第三端與 201010515 該第二端之間。 .本發明另揭露一種可提升靜電放電保護的積體電路，包括有 一電源通道，用來提供電源訊號；一核心電路 ^ 叫肖來產生複數個 訊號處理結果；複數個輸出緩衝單元，耦接於該 ^ ^ 電，用來 輸出該複數個訊號處理結果；以及一靜電放電保護装置勺 一偵測單元，耦接於該電源通道，用來偵測該電源通、首的=源吕 號，以產生一娜果，·以及一分派單元’耦接於讀 該複數個輸出緩衝單元，用來於該偵測結果顯示該電源通道的電 源訊號包含有一脈衝訊號時’分別控制該複數個輪出緩衝單元之 輸出情形，以將該脈衝訊號所引起之電流導通至—地端 【實施方式】 請參考第2圖’第2圖為本發明實施例一積體電路2〇的示音 圖。積體電路20可提升靜電放電保護，其包括有—電源通^ PWR_CH、一核心電路200、輸出緩衝單元〇Bj〜〇Β η及一靜 電放電保護裝£ 202。電源通道Pwr〜ch用來提供電源訊號，以 驅動核心電路200正常運作，從而透過輸出緩衝單元〇bj〜 〇B_n，輸出訊號處理、结果。靜電放電保護褒置2〇2包含有一侧 單元204及-分派單S 2G6，用來提供靜電放電保護。偵測單元 204耦接於電源通道PWR—CH，用來偵測電源通道pWR—CH的電 源訊號’以產生-偵測結果DCT。分派單元2〇6耦接於摘測單元 204，用來於彳貞測結果DCT顯示電源通道pWR_CH的電源訊號包 201010515 ^ 含有一脈衝訊號時，分別控制輸出緩衝單元ΟΒ_1〜〇B_n，以使 脈衝訊號所引起之電流導通至一地端GND_CH。 簡單來說’透過靜電放電保護裝置202，當靜電放電於電源通 道PWR_CH引發一電壓脈衝時，偵測單元204可偵測到有靜電放 電發生，則分派單元206係分別控制每一輸出緩衝單元OBJ〜 OB_n，使脈衝訊號所引起之電流導通至地端GND_CH，以避免靜 〇 電放電造成電路永久性損壞。關於靜電放電保護裝置202之運作 方式，可歸納為一靜電放電保護流程3〇，如第3圖所示。靜電放 電保護流程30包含以下步驟： 步驟300 :開始。 步驟302:偵測單元204偵測電源通道PWR_CH的電源訊號， 以產生偵測結果DCT。 步驟304 :於偵測結果DCT顯示電源通道PWR_CH的電源訊 ❹ 號包含有脈衝訊號時，分派單元206分別控制輸出緩 衝單元OB—1〜〇B_n之輸出情形，以將脈衝訊號所引 起之電流導通至地端GND_CH。 步驟306 :結束。 特別/主意的是，當偵測結果DCT顯示電源通道的電 源訊號包含有脈衝訊號時，分派單元m係'「分別」控制輸出緩 衝單元OB—1〜〇B_n之輸出情形。換言之，分派單元挪並非同 時啟動輸出緩衝單元〇Bj〜〇B_n或同時關閉輸出緩衝單元 201010515 * 〇B」〜0B-n，而是根據每一輸出緩衝單元之特性，進行控制，以 將脈衝訊號所引起之電流導通至地端GND—CH，或阻絕脈衝訊號 所引起之電流流過而產生破壞。 在習知技術中’輸出緩衝單元的功能較為單純，主要是提供緩 衝功能，以避免負載影響核心電路之運作。相較之下，在本發明 令，輸出緩衝單it除了在正常操作時擔任輸出訊號的緩衝器外， ❹並且在靜電放電發生時，執行分擔功率籍制damp)電晶體 導通靜電電流的功能。 、另S面’第2圖所不之積體電路2〇係用以說明本發明之精 神’本領域具通常知識者當可據以做不同之修飾^例來說，如 第4圖所示’偵測單元204之架構可以仿照第i圖中偵測單元100 之架構’亦即，由PM〇st晶體卩卜⑽⑽電晶體犯、電阻幻 ❿及電备C1所組成。其中，PM〇s電晶體及丽電晶體犯 之組合係實現-關，肋根據電阻R1之跨壓（即電源通道 败一CHJL _點如之電壓差），控制電源通道顺⑶至分 派單元206之訊號連結，以產生偵測結果dct。 ~ 詳細說明偵測單元204的運作方式如下。首先，因電容α與 =幻串聯’電源通道PWR—CH對電容α充電能產生時間延 • P1因此，當靜電放電所狀之脈衝輸彳達腳S電晶體 ，、原極丨相對於脈衝電壓而言’節點耶在靜電脈衝發生的 201010515 瞬間係處於—較低賴。騎，電謂之顧已足明啟PM0S 電晶體P1，使PMOS電晶體P1的酿也在瞬間達到高電壓位準， 以產生偵測結果DCT。換言之，以第4圖為例， 為一高龍位料，即絲顏棘2㈣麵财pw果CH發 出一電壓脈衝訊號，代表有靜電放電發生。 ^述，在本發日种，分派單心6係根據每—輸出緩衝 ❾単几之特性，如電流負載能力，控制其導通或關閉，以將脈衝訊 號所引起之電料輸_ GND_CH。_纽，·電流負載 =1=的輸出緩衝單元，如具有大通道電晶體之輸 緩衝单凡’刀派皁元206可於靜電放電發生時予以開啟，以擔 任導通靜電頓的任務；相反地，對於電流負201010515 ' IX, invention description: [Technical field of invention] The present invention relates to a method for improving electrostatic discharge protection in an integrated circuit and related electrostatic discharge protection device and integrated circuit, especially an output buffer The electrostatic discharge protection method for the unit to conduct the electrostatic current and the related electrostatic discharge protection device and the integrated circuit. ❹ [Prior Art] Electrostatic Discharge (ESD) protection is to prevent permanent damage to the integrated circuit caused by electrostatic discharge during the production, testing or use of the integrated circuit. In general, the protection capability of an integrated circuit for electrostatic discharge is reduced as its size shrinks. As the integrated circuit process technology continues to improve, the transistor size of the integrated circuit has progressed from submicron to deep micron. Therefore, how to improve the protection of electrostatic discharge becomes more important. 〇 Refer to Figure 1, which is a schematic diagram of a conventional integrated circuit 10 having an electrostatic discharge protection function. The integrated circuit 10 includes a detecting unit 1 , a core circuit 102 , a - P type MOS transistor p2 , a NMOS transistor (NM 〇 s) transistor N2, and a current switch 106. . The detecting unit 1 is composed of a PM0S transistor P1, an NMOS transistor N, a resistor phantom and a capacitor ,, for detecting the voltage pulse signal of the electrostatic discharge, so as to turn on the current switch 1〇6 in time. Static electricity - current is turned on. In other words, the electrostatic current is controlled by the external circuit of the integrated circuit ι ' ' ' ' 顺 顺 顺 顺 顺 顺 顺 顺 顺 ' ' ' ' ' ' ' 2010 2010 2010 2010 2010 2010 2010 2010 2010 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制Conducted to the ground to prevent static currents from affecting the operation of other components. The PM〇s transistor p2 and the Radisson 3 transistor N2 are output buffer units that provide an output signal buffering function to prevent the load from affecting the operation of the core circuit 1〇2. Further, the output terminals of the integrated circuit 1A are further connected to the - pole bodies D1 and D2 to provide a function of clamping a voltage pulse so that the electrostatic voltage is suspended in the -solid range. It is worth noting that the diodes D1 and 〇2 can be formed by a diode connection method (G (10) Gana's PM〇s transistor and (10) transistor. Therefore, the 'integrated circuit 10 is transmitted through the side unit 1 〇〇, the current switch 106' is turned on in time to enable the electrostatic current to be turned on, and the electrostatic voltage is made to pass through the diode and the electrostatic voltage is made within a fixed range. However, if the integrated circuit 1 is not turned on, the NM〇 S 1: crystal N2 or PMOS transistor P2 is in an indeterminate half-open state. In other words, 'NM〇s transistor N2 or 〇8 transistor p2 may be in a state where ❹ can conduct current. In this case If the crystal width of the NMOS transistor N2 or the PMOS transistor P2 is small, when an electrostatic discharge occurs, the electrostatic charge is turned off (4). In order to avoid the above situation, in general, in addition to the transistor and the PMOS transistor p2 must According to the layout of the relevant electrostatic discharge protection layout (cookie), the diodes D1 and m must also be arranged in a large area. However, in this way, not only the area of the chip must be increased, but also the static electricity may not be turned on. Electric contact In addition, between the _sf crystal N2, the blue s 201010515 transistor P2 and the diode D Bu D2, the conventional technique may additionally add a resistor rS to reduce the static electricity flowing through the NMOS transistor N2 and the PMOS transistor P2. Current, but when the NMOS transistor 及2 and the PMOS transistor Ρ2 are in an indeterminate half-on state, the electrostatic current may still flow through the NMOS transistor Ν2 and the PMOS transistor Ρ2. In other words, even if the resistor RS is applied, the electrostatic current There is still a chance to destroy the NMOS transistor Ν2 or the PMOS transistor Ρ2. [Invention] Therefore, the main object of the present invention is to provide a method for improving electrostatic discharge protection in an integrated circuit and related electrostatic discharge protection device and product. The present invention discloses a method for improving electrostatic discharge protection in an integrated circuit, comprising detecting a power signal of a power supply channel of the integrated circuit to generate a debt measurement result; and displaying the detection result When the power signal of the power channel includes a pulse signal, respectively controlling the output situation of the plurality of output buffer units of the integrated circuit to be cited by the pulse signal The current is conducted to a ground end. The present invention further discloses a device for improving electrostatic discharge protection in an integrated circuit, comprising a switch including a first end coupled to the power channel and a second end The fourth end of the ground and the fourth end are coupled to the dispatching unit for controlling the signal from the first end to the fourth end according to the voltage difference between the first end and the red end Linking, the result of the student's side, - resistance, between the first end and the second end of the switch; and - capacitance 'here between the third end of the switch and the second end of 201010515. The invention further discloses an integrated circuit capable of improving electrostatic discharge protection, comprising a power channel for providing a power signal; a core circuit for generating a plurality of signal processing results; and a plurality of output buffer units coupled to The ^ ^ electricity is used to output the plurality of signal processing results; and an electrostatic discharge protection device spoon detecting unit is coupled to the power channel for detecting the power source and the first source source Produce a nagna, and a dispatch unit' And reading the plurality of output buffer units for displaying, when the detection result indicates that the power signal of the power channel includes a pulse signal, respectively controlling the output of the plurality of wheel buffer units to cause the pulse signal to be caused The current is conducted to the ground end. [Embodiment] Please refer to FIG. 2, FIG. 2 is a sound diagram of the integrated circuit 2A according to the embodiment of the present invention. The integrated circuit 20 can enhance electrostatic discharge protection, including - power supply PWR_CH, a core circuit 200, output buffer units 〇Bj 〇Β η, and an electrostatic discharge protection package 202. The power channels Pwr~ch are used to provide power signals to drive the core circuit 200 to operate normally, thereby outputting signal processing and results through the output buffer units 〇bj~ 〇B_n. The ESD protection device 2〇2 includes a side unit 204 and a dispatching single S 2G6 for providing electrostatic discharge protection. The detecting unit 204 is coupled to the power channel PWR-CH for detecting the power signal ' of the power channel pWR_CH to generate a detection result DCT. The dispatching unit 2〇6 is coupled to the extracting unit 204 for controlling the output buffer unit ΟΒ_1~〇B_n to be pulsed when the power signal packet 201010515 of the power supply channel pWR_CH is displayed in the DCT test result. The current caused by the signal is turned on to a ground terminal GND_CH. Briefly, 'through the electrostatic discharge protection device 202, when the electrostatic discharge causes a voltage pulse in the power supply channel PWR_CH, the detecting unit 204 can detect the occurrence of electrostatic discharge, and the dispatching unit 206 controls each output buffer unit OBJ. ~ OB_n, the current caused by the pulse signal is turned on to the ground GND_CH to avoid permanent damage to the circuit caused by static electric discharge. The operation mode of the electrostatic discharge protection device 202 can be summarized as an electrostatic discharge protection process, as shown in Fig. 3. The electrostatic discharge protection process 30 includes the following steps: Step 300: Start. Step 302: The detecting unit 204 detects the power signal of the power channel PWR_CH to generate a detection result DCT. Step 304: When the detection result DCT shows that the power signal of the power channel PWR_CH includes the pulse signal, the dispatching unit 206 controls the output of the output buffer units OB-1 to 〇B_n to turn on the current caused by the pulse signal. To ground GND_CH. Step 306: End. In particular, when the detection result DCT shows that the power signal of the power channel contains a pulse signal, the dispatch unit m controls the output of the output buffer units OB-1 to _B_n separately. In other words, the dispatch unit does not simultaneously start the output buffer unit 〇Bj~〇B_n or simultaneously close the output buffer unit 201010515 * 〇B"~0B-n, but controls according to the characteristics of each output buffer unit to transmit the pulse signal. The induced current is conducted to the ground GND-CH, or the current caused by the pulse signal is blocked to cause damage. In the prior art, the function of the output buffer unit is relatively simple, mainly to provide a buffer function to prevent the load from affecting the operation of the core circuit. In contrast, in the present invention, the output buffer unit it performs a function of sharing the electrostatic current of the transistor in addition to the buffer serving as the output signal during normal operation and when the electrostatic discharge occurs. The other side of the S-Plane 2 is not intended to illustrate the spirit of the present invention. Those skilled in the art can make different modifications as shown in FIG. The structure of the detecting unit 204 can be modeled on the structure of the detecting unit 100 in the figure i, that is, the PM 〇st crystal ( (10) (10) transistor ray, the resistor illusion and the power reserve C1. Among them, the combination of PM〇s transistor and Lidian crystal is realized-off, and the rib is controlled according to the voltage across the resistor R1 (ie, the power channel loses a CHJL_point voltage difference), and the power supply channel is controlled (3) to the dispatch unit 206. The signal is linked to generate the detection result dct. ~ Detailed description of the operation of the detecting unit 204 is as follows. First, due to the capacitance α and = phantom series 'power channel PWR-CH charging capacitor α can produce a time delay • P1 Therefore, when the electrostatic discharge is shaped like a pulse, the pin is connected to the transistor S, the original pole 丨 relative to the pulse voltage In fact, 'node yeah is at a low level in 201010515 when the electrostatic pulse occurs. Riding, the electric premise has fully opened the PM0S transistor P1, so that the PMOS transistor P1 is also brought to a high voltage level in an instant to generate the detection result DCT. In other words, taking Figure 4 as an example, a voltage pulse signal is generated for a high-long material, that is, the silky prickly 2 (four) face pw fruit CH, which represents the occurrence of electrostatic discharge. As mentioned in the present issue, the single-core 6 system is controlled according to the characteristics of each-output buffer, such as the current load capacity, to control its turn-on or turn-off, so that the electric energy caused by the pulse signal is transmitted to _ GND_CH. _ New, · Current load = 1 = output buffer unit, such as the transmission buffer with a large channel transistor, the 'knife soap element 206 can be turned on when the electrostatic discharge occurs, to serve as a task to conduct static electricity; For negative current
件的輸出緩鮮元，如具有顿道電晶體讀出緩衝單元，分I =二靜電放電發生時予以關，_免受着電電流之 ❹：釘，當靜電放電發生時，靜電電流係由高電流負 載能力之輸出緩衝單元導通至地，而不會造成 輸出緩衝科關壞。 ^ :】注意的是，分派單元206係分別控制每一輸出糊 =，其實現方式舰竭統絲喊聰t 考第5圖至第8圖，第5圖至箆 第圖顯示本發明實施例積體電鲜 50、60、70、80之示意圖。積體 视瓶哥路50、60、70、80皆由第’ 圖之積體電路20變化而得，僅句冬 ▲ 匕3兩輪出電晶體（ΡΙ1、Nil、ΡΙ2， 201010515 - NI2、PI3、NI3、PI4、NI4)作為輸出緩衝單元。此外，積體電路 50'60、70、80之靜電放電保護裝置皆是由第4圖所示之偵測單 元204與一 NMOS電晶體N3所組成。廟〇8電晶體N3係實現 第2圖中分派單元206，且根據輸出電晶體之電流負載能力的不 同’與輸出電晶體間的連結方式亦不同，以實現一反相器或一傳 輸器，請見以下說明。 ^ 在第5圖中’PMOS電晶體PI1之通道寬度較大，因此，靡〇3 電曰曰體N3之没極輛接於PMOS電晶體ριι之閘極。如此^一來，當 靜電放電發生時，NMOS電晶體N3會打開，使pm〇s電晶體PI1 之閘極導通至地，以開啟PMOS電晶體PI1，從而輔助導通靜電 電流。在此情形下，NMOS電晶體N3係為一反相器。 在第ό圖中，NMOS電晶體NI2之通道寬度較大，因此,nmos Ο 電晶體Ν3之閘極耦接於NMOS電晶體ΝΙ2之閘極。如此一來， 當靜電放電發生時，NMOS電晶體NI2之閘極會接通至高電壓位 準，以開啟NMOS電晶體NI2，從而輔助導通靜電電流。在此情 形下，NMOS電晶體N3可視為一傳輸器，用來輸出偵測結果DCT 至NMOS電晶體NI2之閘極。 在第7圖中’PMOS電晶體PI3之通道寬度較小，因此，_〇；5 電晶體N3之閘極耦接於PM0S電晶體PB之閘極。如此一來，當 靜電放電發生時，PMOS電晶體PI3之間極會接通至高電壓位準， 12 201010515The output of the piece of gradual fresh element, such as with a Donor transistor readout buffer unit, is turned off when I = two electrostatic discharge occurs, _ is protected from electric current: nail, when electrostatic discharge occurs, the electrostatic current is The output buffer unit of high current load capability is turned on to ground without causing the output buffer to be shut down. ^ :] Note that the dispatch unit 206 controls each output paste = respectively, and its implementation mode is the same as the embodiment of the present invention. FIG. 5 to FIG. Schematic diagram of the integrated electric fresh 50, 60, 70, 80. The integrated body bottle roads 50, 60, 70, 80 are all changed from the integrated circuit 20 of the figure, only the winter ▲ 匕 3 two-wheel output transistors (ΡΙ1, Nil, ΡΙ2, 201010515 - NI2, PI3 , NI3, PI4, NI4) as an output buffer unit. In addition, the electrostatic discharge protection devices of the integrated circuits 50'60, 70, and 80 are composed of the detecting unit 204 and an NMOS transistor N3 shown in FIG. The Temple 8 transistor N3 system realizes the dispatch unit 206 in FIG. 2, and the connection between the output transistor and the output transistor is different according to the current load capacity of the output transistor to realize an inverter or a transmitter. Please see the instructions below. ^ In the fifth figure, the channel width of the PMOS transistor PI1 is large. Therefore, the pole of the 靡〇3 battery body N3 is connected to the gate of the PMOS transistor ρι. In this way, when the electrostatic discharge occurs, the NMOS transistor N3 is turned on, and the gate of the pm〇s transistor PI1 is turned to the ground to turn on the PMOS transistor PI1, thereby assisting the conduction of the electrostatic current. In this case, the NMOS transistor N3 is an inverter. In the second figure, the channel width of the NMOS transistor NI2 is large. Therefore, the gate of the nmos Ο transistor Ν3 is coupled to the gate of the NMOS transistor ΝΙ2. As a result, when an electrostatic discharge occurs, the gate of the NMOS transistor NI2 is turned on to a high voltage level to turn on the NMOS transistor NI2, thereby assisting in turning on the electrostatic current. In this case, the NMOS transistor N3 can be regarded as a transmitter for outputting the detection result DCT to the gate of the NMOS transistor NI2. In Fig. 7, the channel width of the PMOS transistor PI3 is small, and therefore, the gate of the transistor N3 is coupled to the gate of the PMOS transistor PB. As a result, when an electrostatic discharge occurs, the pole between the PMOS transistors PI3 is turned to a high voltage level, 12 201010515
以關閉PMOS電晶體PI3，從而阻絕靜電電流。在此情形下，NMOS 電晶體N3可視為一傳輸器，用來輸出偵測結果DCT至PMOS電 晶體PI3。 在第8圖中’ NMOS電晶體NI4之通道寬度較大，因此，NMOS 電晶體N3之汲極耦接於NMOS電晶體NI4之閘極。如此一來， 當靜電放電發生時，NMOS電晶體N3會打開，使NMOS電晶體 ❹ NI4之閘極導通至地，以關閉NMOS電晶體NI4,從而避免NMOS 電晶體NI4因流過靜電電流而被破壞。在此情形下，NMOS電晶 體N3可視為一反相器。 综合第5圖至第8圖可知，根據輪出電晶體電流負載能力， 電晶體N3可為一傳輸器或一反相器，以於靜電放電發生 時將通道寬度較大的PMOS電晶體及丽os電晶體開啟，並將 通道寬度較小的PMOS電晶體或nmOS電晶體關閉。如此一來， 靜電電流可有效導通至地，且可保護電晶體受到破壞。 在習知技術中’當積體電路處於未接通正常電源的情況下， 輪出緩衝單元㈣NMOS電晶體〇M〇S電晶體倾於不確定的 狀態’因而可能導通電流而發生永久性的損壞。相較之下，本發 明可根據輪出緩衝單元的魏負餘力，於靜電放電發生時，控 ，特定電晶體_啟或賴，以達到疏導靜電放電電流或保料 曰曰體的目的0 201010515 ❹ 削/试⑤的疋’由於本發明料對每-輸出緩衝單元之特性， ^或關閉每一輸出緩衝單元。當輸出緩衝單元係屬於大通道電 =並伽Wtw，&晴纟刪晶體接腳處 # _ 一極體(damp di〇de)或二極體連結方式_麵咖机 可用較小的面積佈局，以減少晶片面積。此外，因為輸出 、·單it可〜擔功轉制(pQwei>啦晶體導通靜電電流， 所以靜電保護能力較好。輸出緩衝單元通道較小的時候，則關閉 輸出緩衝單元。·，本發啊在增加靜電賴的时，減少所 需要的晶片面積。 综上所述’本發明係於靜電放電發生時，分別控制每一輸出 緩衝單it，以透過電流導通能力較麵輸出緩衝單元，將脈衝訊 號所引起之電流導通至地端，並關閉電流導通能力較弱的輸出緩 衝單元，避免靜電放電造成電路永久性損壞。因此，本發明可有 效將靜電電流導通至地，避免造成其它元件的損壞。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知具有靜電放電保護功能之一積體電路之示意 圖。 第2圖為本發明實施例一積體電路之示意圖。 201010515 第3圖為用於第2圖之積體電路之一靜電放電保護流程之示 意圖。 第4圖為用於第2圖之積體電路之一偵測單元之示意圖。 第5圖為本發明實施例一積體電路之示意圖。 第6圖為本發明實施例一積體電路之示意圖。 第7圖為本發明實施例一積體電路之示意圖。 第8圖為本發明實施例一積體電路之示意圖。To turn off the PMOS transistor PI3, thereby blocking the electrostatic current. In this case, the NMOS transistor N3 can be regarded as a transmitter for outputting the detection result DCT to the PMOS transistor PI3. In Fig. 8, the channel width of the NMOS transistor NI4 is large. Therefore, the drain of the NMOS transistor N3 is coupled to the gate of the NMOS transistor NI4. In this way, when the electrostatic discharge occurs, the NMOS transistor N3 is turned on, and the gate of the NMOS transistor ❹NI4 is turned to the ground to turn off the NMOS transistor NI4, thereby preventing the NMOS transistor NI4 from being flown by the electrostatic current. damage. In this case, the NMOS transistor N3 can be regarded as an inverter. It can be seen from Fig. 5 to Fig. 8 that the transistor N3 can be a transmitter or an inverter according to the current carrying capacity of the transistor, so that the PMOS transistor with a large channel width can be generated when the electrostatic discharge occurs. The os transistor is turned on and the PMOS transistor or nmOS transistor with a small channel width is turned off. In this way, the electrostatic current can be effectively conducted to the ground and the transistor can be protected from damage. In the prior art, 'when the integrated circuit is not turned on the normal power supply, the buffering unit (4) NMOS transistor 〇M〇S transistor is tilted in an indeterminate state' and thus may cause current to be permanently damaged. . In contrast, the present invention can control the specific transistor _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ❹ / / test 5 疋 'Because of the characteristics of the per-output buffer unit of the present invention, ^ or each output buffer unit is turned off. When the output buffer unit belongs to the large channel electric = gamma Wtw, & clearing the crystal pin at the end of the # _ one dipole (damp di〇de) or diode connection method _ coffee machine can be used for smaller area layout To reduce the wafer area. In addition, because the output, · single it can be converted to work (pQwei> crystal conduction static current, so the electrostatic protection ability is better. When the output buffer unit channel is small, the output buffer unit is turned off. When the electrostatic discharge is increased, the required wafer area is reduced. In summary, the present invention controls each output buffer unit it when the electrostatic discharge occurs, so as to transmit the pulse conduction signal through the current conduction capability. The induced current is conducted to the ground end, and the output buffer unit with weak current conduction capability is turned off to avoid permanent damage of the circuit caused by electrostatic discharge. Therefore, the present invention can effectively conduct the electrostatic current to the ground and avoid damage of other components. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be covered by the present invention. [Simplified Description] FIG. 1 is a conventional A schematic diagram of an integrated circuit of an electrostatic discharge protection function. Fig. 2 is a schematic diagram of an integrated circuit according to an embodiment of the present invention. Figure 3 is a schematic diagram of an electrostatic discharge protection process for an integrated circuit of Figure 2. Figure 4 is a schematic diagram of one of the detection units for the integrated circuit of Figure 2. Figure 5 is an implementation of the present invention. 1 is a schematic diagram of an integrated circuit according to an embodiment of the present invention. FIG. 7 is a schematic diagram of an integrated circuit according to an embodiment of the present invention. FIG. 8 is a schematic diagram of an integrated circuit according to an embodiment of the present invention. Schematic diagram.
Ο 【主要元件符號說明】 10、20、50、60、70、80 100、204 102、200 106 202 206 Ρ 卜 Ρ2、PU、ΡΙ2、ΡΙ3、ΡΙ4 Ν1 > Ν2 ' Ν3 ' Nil ' ΝΙ2 > Ν1 R1 'RS Cl D1 > D2 GND_CH PWR_CH OB 1 〜OB n 積體電路 偵測單元 核心電路 電流開關 靜電放電保護裝置 分派單元 PMOS電晶體 NI4 NMOS電晶體 電阻 電容 二極體 地端 電源通道 輸出緩衝單元 201010515 偵測結果 流程 步驟Ο [Description of main component symbols] 10, 20, 50, 60, 70, 80 100, 204 102, 200 106 202 206 Ρ Ρ 2, PU, ΡΙ 2, ΡΙ 3, ΡΙ 4 Ν 1 > Ν 2 ' Ν 3 ' Nil ' ΝΙ 2 > Ν1 R1 'RS Cl D1 > D2 GND_CH PWR_CH OB 1 ~ OB n Integrated circuit detection unit core circuit current switch electrostatic discharge protection device dispatch unit PMOS transistor NI4 NMOS transistor resistor and capacitor diode ground power channel output buffer Unit 201010515 Detection result flow step
DCT 30 300、302、304、306 ❹DCT 30 300, 302, 304, 306 ❹
1616