201005947 WZ1TW 24864twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電子裝置、薄膜電晶體、顯示裝. 置及導體接觸製程’且特別是有關於一種具有多層金屬、结 構之電子裝置、薄膜電晶體、顯示裝置及導體接觸製程。 【先前技術】 在一般的半導體製程或液晶顯示器的金屬化製程 ❹ 中，一般是選用鋁(A1)、鉬(Mo)、组(Ta)、鉻(Cr)、鎢(W) 等金屬或其合金做為金屬層之材料，其中又以鋁為最常 用。鋁是地球上含量最豐富的金屬，其價格便宜且具有多 項特點，如電阻係數低、對基板的附著性（adhesi〇n)佳、 且蝕刻特性（etching characteristics)好。以常見的開關元 件薄膜電晶體為例，就常以鋁作為閘極與源/汲極金屬層之 材質。 然而，若以單層鋁作為閘極時，則鋁接觸大氣之後會 φ 產生氧化物。當使用蝕刻液進行蝕刻時，所產生的鋁氧化 物將無法有效地被蝕刻液蝕刻。此外，若以單層鋁作為源/ 及極，在鋁層之上形成銦錫氧化物等氧化物導電層時，鋁 的表面^會被腐姓而使銘與氧化物導電層之接觸阻抗過 ^為了避免產生鋁氧化物或是避免鋁被腐蝕的問題，通 :會在銘層之上形成另—層金屬層而形成多層金屬的結 構。 :般來說，多層金屬的結構多以鋁與鉬(Mo)或是鉬合 、而形成。以鋁與鉬或其合金所構成的多層金屬結構雖有 iZITW 24864twf.doc/n 201005947 ❿ 助於蝕刻製程的進行，也可降低金屬層與氧化物導電層間 =阻抗。然而，銦是貴金屬材料，其靶材成本比其他金屬 $出許多。此外，製造薄膜電晶體時，必須進行乾式蝕刻 製程形成接觸窗，以使氧化物導電層與多層金屬結構的汲 極接觸。此時，鉬會受到六氟化硫(SF6)等蝕刻氣體的腐蝕 =使氧化物導電層與鉬之間僅在所蝕刻出的開口周圍形成 晨狀接觸。整體而& ,銘與錮或其合金所構成的多層金屬 結構應祕半導體元件或是侧電子裝置時，仍有成本無 法降低且製程良率不高的情形。 、 【發明内容】 本發明提供一種電子裝置，以解決習知之電子裝置中 多層金屬結構的高成本問題。 本發明另提供一種薄膜電晶體，以提升薄膜電晶 製程良率。 本發明又提供—種顯示裝置，其具有 咼製程良率。 又 良率本發明更提供—種導體接觸製程，可提高導體接觸的 ^發明提丨—觀子I置以及—麵示裝置。此電子 此顯示裝置皆至少具有配置於基材上之導體圖案。 實質純銘層以及_爛合金層。實質純紹 曰 ；土材上。鋁鎳鑭合金層則配置於實質純鋁層上。 链链棚之實〜例之電子裝置及顯示裝置中，上述之 錄爛合金層中，制含量介於(U wt%〜6wt%。 201005947 * “TZ1TW 24864twf.doc/n 本發明之一實施例之電子裝置及顯示裝置中，上述之 銘鎳鑭合金層中，鑭的含量介於0 i wt%〜2wt%。 本發明之一實施例之電子裝置及顯示裝置中，更包括 氧化物導電層，配置於鋁鎳鑭合金層上，且氧化物導電層 與紹鎳鑭合金層直接接觸。此外，氧化物導電層之材質包 括銦錫氧化物或銦鋅氧化物。 本發明之一實施例之電子装置及顯示裝置中，上述之 ❹ 電子裝置更包括配置於實質純銘層之下之導電層，以使實 質純鋁層夾於導電層以及鋁鎳鑭合金層之間。其中，導電 層之材質包括氮化鉬或鉬。 本發明之一實施例之電子裝置及顯示裝置中，上述之 實質純鋁層之中銘的含量大於等於99.0 wt〇/。。 本發明之一實施例之電子裝置及顯示裝置中，上述之 銘鎳鑭合金之阻抗為3 μΩ-cm〜5 μΏ-cm。 本發明之一實施例之電子裝置及顯示裝置中，上述之 ❹ 純鋁層之厚度與鋁鎳鑭合金層之厚度之間的比例為 本發明之一實施例之電子裝置及顯示裝置中，上述之 銘鎳鑭合金層之厚度為200 A〜500 A。 本發明更k出一種薄膜電晶體，其適於配置於基板 上。此薄膜電晶體包括閘極、閘絕緣層、半導體層以及源 極與汲極。閘極配置於基板上，且閘極包括第一實質純鋁 層以及第一鋁鎳鑭合金層，其中第一實質純鋁層位於第一 鋁鎳鑭合金層以及基板之間。閘絕緣層配置於基板上並覆 7 -1Z1TW 24864twf.doc/n 201005947 蓋閘極。半導體層配置於閘極上方之閘絕緣層上。源極與 没極配置於半導體層上，源極與汲極分別對應於閘極之兩 側。 ' 本發明再提出一種薄膜電晶體，其適於配置於基板 上。此薄膜電晶體包括閘極、閘絕緣層、半導體層以及源 極與汲極。閘極配置於基板上。閘絕緣層配置於基板上並 覆蓋閘極。半導體層配置於閘極上方之閘絕緣層上。源極 φ 與汲極配置於半導體層上，源極與汲極分別對應於閘極之 兩側。源極與汲極由導電層、第二實質純鋁層以及第二鋁 鎳鑭合金層依序疊置所組成，且導電層與半導體層接觸。 本發明之一實施例之薄膜電晶體中，上述之第一鋁鎳 鋼合金層中，鎳的含量介於0.1 wt%〜6 wt%。 本發明之一實施例之薄膜電晶體中，上述之第一鋁鎳 爛合金層中’鑭的含量介於O.i wt%〜2 wt%。 、 本發明之一實施例之薄膜電晶體中，上述之導電層之 材質包括氮化鉬或是鉬。 參本發明之-實施例之薄膜電晶體中，上述之 純鋁層之厚度與第二鋁鎳鑭合金層之厚度之間的比例 為 10:1。 本發明之-實施例之薄膜電晶體中，上述之第二紹錄 鑭合金層之厚度例如為200 A〜500 A。 ’、 本發明之一實施例之薄膜電晶體中，上述之第一鋁鎳 鋼°金層與第二銘鎳鑭合金層之阻抗實質上為3 μΩ-c 5 μΩπιη。 〜 8 lZlTW24864twf.doc/n 201005947 本發明之一實施例之薄膜電晶體中，上述之第二鋁鎳 鑭合金層中’鎳的含量例如介於〇丨wt%〜6 wt〇/〇。 本發明之一實施例之薄膜電晶體中，上述之第二鋁鎳 鑭合金層中，鑭的含量大致介於0.1 wt%〜2 wt%。 、 本發明之一實施例之薄膜電晶體中，上述之第一實質 純鋁層與第二實質純鋁層之中鋁的含量大於等於99.0 wt%。 φ 本發明之一實施例之薄膜電晶體中，更包括配置於基 板上之保護層，且保護層覆蓋源極與汲極。保護層例如具 有一開口，其中開口暴露汲極之部分區域。此外。薄膜電 晶體更包括氧化物導電層，配置於保護層上，且氧化物導 電層藉由開口與汲極之第二鋁鎳鑭合金層直接接觸。氧化 物導電層之材質例如為銦錫氧化物或銦鋅氧化物。 本發明之一實施例之薄膜電晶體中，上述之第一實質 純鋁層之厚度與第一鋁鎳鑭合金層之厚度之間的比 10:卜 ® 本發明之一實施例之薄膜電晶體中，上述之第一鋁鎳 鑭合金層之厚度為200 A〜500 A。 ' 本發明又提出一種導體接觸製程，其包括下列步驟。 在一基板上形成第一圖案化金屬層。在基板上形成覆蓋第 一圖案化金屬層的第一絕緣層。在第一絕緣層上形成第二 圖案化金屬層，其中第一圖案化金屬層與第二圖案化金^ 層至少其中之一包括實質純鋁層以及配置於實質純鋁芦 的銘錄鋼合金層。在第—絕緣層上形成覆蓋第二圖案^金 9 201005947 rv/v/jj^^rZlTW 24864twf.doc/n 屬層的第二絕緣層。在第二絕緣層上形成圖案化遮罩層， 其中圖案化遮罩層具有開口與薄化區。開口位於第一圖案 化金屬層上方，而薄化區位於第二圖案化金屬層上方，且 圖案化遮罩層在薄傾之部分的厚度小於在其他部分的厚 度。以圖案化遮罩層為罩幕而進行一蝕刻製程，以移除第 一絕緣層與二絕緣層位於該開口下方之部分而暴露第一圖 案化金屬層的部分區域，並移除圖案化鮮層之薄化區與 第二絕緣層位於薄化區下方之部分而暴露第二圖案化金屬 層的部分區域。移除_化鮮層。在第二絕緣層上形成 -圖案化導體層’其巾圖案料體層直接麵第—圖案化 金屬層與第二圖案化金屬層被暴露的部分區域。 在本發明之-實施例之導體接觸製程中，形成圖案化 遮罩層的方法包括於基板上形成-光阻材料層以及進行一 微影製程。絲材料層覆蓋第二絕緣層，峨影製程中使 用半透光罩’以將光阻材料層圖案化成圖案化遮罩層。 在本發明之-實施例之導體接觸製程中，形成第一圖 案化金屬層的方法包括於基板上依序形成實質_材料層 賴合金材料層，並圖案化實質純_料層以及銘 錄鋼合金材料層。 發明之一實施例之導體接觸製程中’形成第二圖 =金屬層的方法包括於基板上依序形成—導電層、一實 層以及鑭合金材料層，並圖案化導電 曰 μ質純崎料層以及第―㉝錄鑭合金材料層。 在本發明之-實施例之導體接觸製程中，上述之触刻 2010〇5947—一 製程包括一非等向性蝕刻製程。 ίίΓ於^純㈣上形成_鑭合金層以構成多 層金屬結構，作Α雷早驻番σ巫，耳从傅風爹 導俨η 薄骐電晶體或是顯示裝置的 由於齡金不易氧化，具有抗·氣體六 穿置^=屬層躺於電子裝置、薄膜電晶體與顯示 =置有助於&升其電性品質’且製作良率也相對較高。此 卜，紹、鎳、鑭等金屬相較於銦或銦合金而言，是較 的金屬材質，因而本發明的材料成本低廉。 2硫的特性，__合金層與氧化物導電層或盆他導 =之間的接觸阻抗較低。因此，將實質輪層血201005947 WZ1TW 24864twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to an electronic device, a thin film transistor, a display device and a conductor contact process, and in particular to a multilayer metal , structural electronic devices, thin film transistors, display devices and conductor contact processes. [Prior Art] In general semiconductor processes or metallization processes of liquid crystal displays, metals such as aluminum (A1), molybdenum (Mo), group (Ta), chromium (Cr), tungsten (W) or the like or The alloy is used as the material of the metal layer, and aluminum is most commonly used. Aluminum is the most abundant metal on earth, and it is inexpensive and has many characteristics, such as low resistivity, good adhesion to substrates, and good etching characteristics. Taking a common switching element thin film transistor as an example, aluminum is often used as a material for the gate and source/drain metal layers. However, when a single layer of aluminum is used as the gate, the aluminum will generate an oxide after it contacts the atmosphere. When etching is performed using an etching solution, the generated aluminum oxide will not be effectively etched by the etching liquid. In addition, when a single layer of aluminum is used as a source/pole, an oxide conductive layer such as indium tin oxide is formed on the aluminum layer, and the surface of the aluminum is eroded to cause contact resistance between the electrode and the oxide conductive layer. ^ In order to avoid the problem of aluminum oxide or to avoid corrosion of aluminum, pass: a layer of metal is formed on the layer to form a multilayer metal structure. In general, the structure of a multilayer metal is mostly formed by combining aluminum with molybdenum (Mo) or molybdenum. The multilayer metal structure composed of aluminum and molybdenum or an alloy thereof can be reduced by the iZITW 24864twf.doc/n 201005947 助 to facilitate the etching process, and also to reduce the impedance between the metal layer and the oxide conductive layer. However, indium is a precious metal material, and its target cost is much higher than other metals. In addition, when manufacturing a thin film transistor, a dry etching process must be performed to form a contact window to bring the oxide conductive layer into contact with the anode of the multilayer metal structure. At this time, molybdenum is corroded by an etching gas such as sulfur hexafluoride (SF6) = a morning contact is formed between the oxide conductive layer and the molybdenum only around the etched opening. When the multilayer metal structure composed of the whole and the amps and the alloys or their alloys is a secret semiconductor element or a side electronic device, there is still a case where the cost cannot be lowered and the process yield is not high. SUMMARY OF THE INVENTION The present invention provides an electronic device to solve the high cost problem of a multilayer metal structure in a conventional electronic device. The present invention further provides a thin film transistor for improving the film crystal process yield. The present invention further provides a display device having a process yield. Moreover, the present invention further provides a kind of conductor contact process, which can improve the contact of the conductor, the invention, the view, and the surface display device. The electronic display device has at least a conductor pattern disposed on the substrate. Substantially pure layer and _ rotten alloy layer. The essence is pure 曰 曰; on the soil. The aluminum-nickel-niobium alloy layer is disposed on the substantially pure aluminum layer. In the electronic device and the display device of the example of the chain shed, the content of the above-mentioned recorded alloy layer is between (U wt% and 6 wt%. 201005947 * "TZ1TW 24864twf.doc/n" one embodiment of the present invention In the electronic device and the display device, the content of germanium in the above-mentioned nickel-niobium alloy layer is between 0% by weight and 2% by weight. In the electronic device and the display device according to an embodiment of the present invention, an oxide conductive layer is further included. And disposed on the aluminum-nickel-niobium alloy layer, and the oxide conductive layer is in direct contact with the Shao-Ni-Al alloy layer. Further, the material of the oxide conductive layer includes indium tin oxide or indium zinc oxide. In the electronic device and the display device, the electronic device further includes a conductive layer disposed under the substantially pure layer to sandwich the substantially pure aluminum layer between the conductive layer and the aluminum-nickel-niobium alloy layer. The material of the present invention is an electronic device and a display device. And display device The impedance of the above-mentioned nickel-niobium alloy is 3 μΩ-cm to 5 μΏ-cm. In the electronic device and the display device according to an embodiment of the present invention, the thickness of the above-mentioned pure aluminum layer and the thickness of the aluminum-niobium alloy layer In the electronic device and the display device according to an embodiment of the present invention, the thickness of the above-mentioned nickel-niobium alloy layer is 200 A to 500 A. The present invention further provides a thin film transistor which is suitable for being disposed in On the substrate, the thin film transistor comprises a gate, a gate insulating layer, a semiconductor layer, and a source and a drain. The gate is disposed on the substrate, and the gate comprises a first substantially pure aluminum layer and a first aluminum-nickel-niobium alloy layer. The first substantially pure aluminum layer is located between the first aluminum-nickel-niobium alloy layer and the substrate. The gate insulating layer is disposed on the substrate and covered with a gate electrode. The semiconductor layer is disposed above the gate electrode. On the gate insulating layer, the source and the drain are disposed on the semiconductor layer, and the source and the drain respectively correspond to the two sides of the gate. The present invention further provides a thin film transistor suitable for being disposed on a substrate. The transistor includes a gate and a gate a gate layer, a semiconductor layer, and a source and a drain. The gate is disposed on the substrate. The gate insulating layer is disposed on the substrate and covers the gate. The semiconductor layer is disposed on the gate insulating layer above the gate. The source φ and the drain Disposed on the semiconductor layer, the source and the drain respectively correspond to the two sides of the gate, and the source and the drain are composed of a conductive layer, a second substantially pure aluminum layer and a second aluminum-nickel alloy layer. And the conductive layer is in contact with the semiconductor layer. In the thin film transistor of one embodiment of the invention, the content of nickel in the first aluminum-nickel steel alloy layer is between 0.1 wt% and 6 wt%. In the thin film transistor, the content of '镧 in the first aluminum-nickel alloy layer described above is between 0% by weight and 2% by weight. In the thin film transistor according to an embodiment of the invention, the material of the conductive layer comprises molybdenum nitride or molybdenum. In the thin film transistor according to the embodiment of the invention, the ratio between the thickness of the above-mentioned pure aluminum layer and the thickness of the second aluminum-niobium alloy layer is 10:1. In the thin film transistor of the embodiment of the invention, the thickness of the second alloy layer described above is, for example, 200 A to 500 A. In the thin film transistor according to an embodiment of the present invention, the impedance of the first aluminum-nickel steel layer and the second layer of the nickel-niobium alloy layer is substantially 3 μΩ-c 5 μΩπηη. 〜 8 lZlTW24864twf.doc/n 201005947 In the thin film transistor according to one embodiment of the present invention, the content of nickel in the second aluminum-niobium alloy layer is, for example, 〇丨wt% to 6 wt〇/〇. In the thin film transistor according to an embodiment of the present invention, in the second aluminum-nickel-niobium alloy layer, the content of niobium is approximately 0.1 wt% to 2 wt%. In the thin film transistor according to an embodiment of the present invention, the content of aluminum in the first substantially pure aluminum layer and the second substantially pure aluminum layer is greater than or equal to 99.0 wt%. φ In the thin film transistor according to an embodiment of the invention, the protective layer is further disposed on the substrate, and the protective layer covers the source and the drain. The protective layer has, for example, an opening in which the opening exposes a portion of the drain. Also. The thin film transistor further includes an oxide conductive layer disposed on the protective layer, and the oxide conductive layer is in direct contact with the second aluminum-niobium alloy layer of the drain by the opening. The material of the oxide conductive layer is, for example, indium tin oxide or indium zinc oxide. In a thin film transistor according to an embodiment of the present invention, a ratio between a thickness of the first substantially pure aluminum layer and a thickness of the first aluminum-niobium alloy layer is 10: a thin film transistor according to an embodiment of the present invention The first aluminum-nickel-niobium alloy layer has a thickness of 200 A to 500 A. The invention further proposes a conductor contact process comprising the following steps. A first patterned metal layer is formed on a substrate. A first insulating layer covering the first patterned metal layer is formed on the substrate. Forming a second patterned metal layer on the first insulating layer, wherein at least one of the first patterned metal layer and the second patterned gold layer comprises a substantially pure aluminum layer and an etched steel alloy disposed on the substantially pure aluminum ruth Floor. A second insulating layer covering the second pattern is formed on the first insulating layer 9 201005947 rv/v/jj^^rZlTW 24864twf.doc/n. A patterned mask layer is formed on the second insulating layer, wherein the patterned mask layer has an opening and a thinned region. The opening is above the first patterned metal layer and the thinned region is above the second patterned metal layer, and the thickness of the patterned mask layer in the thinly inclined portion is less than the thickness in other portions. An etching process is performed by patterning the mask layer as a mask to remove a portion of the first insulating layer and the second insulating layer under the opening to expose a portion of the first patterned metal layer, and removing the patterned fresh The thinned region of the layer and the second insulating layer are located at a portion below the thinned region to expose a portion of the second patterned metal layer. Remove _ fresh layer. A patterning conductor layer is formed on the second insulating layer, the surface of which is directly exposed to a portion of the patterned metal layer and the second patterned metal layer. In the conductor contact process of the present invention, the method of forming a patterned mask layer includes forming a photoresist layer on the substrate and performing a lithography process. The layer of silk material covers the second insulating layer, and a translucent cover is used in the shadowing process to pattern the layer of photoresist into a patterned mask layer. In the conductor contact process of the embodiment of the present invention, the method of forming the first patterned metal layer comprises sequentially forming a layer of a substantial material layer on the substrate, and patterning the substantially pure layer and the inscription steel Alloy material layer. In the conductor contact process of one embodiment of the invention, the method of forming the second pattern=metal layer comprises sequentially forming a conductive layer, a solid layer and a layer of tantalum alloy material on the substrate, and patterning the conductive germanium pure raw material The layer and the 133th layer of alloy material layer. In the conductor contact process of the embodiment of the present invention, the above-described etched 2010〇5947-process includes an anisotropic etch process. ίίΓ on the pure (four) to form a _ 镧 alloy layer to form a multi-layer metal structure, as the Α 早 驻 驻 σ , , , , , , , , , 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅 傅Anti-gas six-through ^= genus lying on the electronic device, thin film transistor and display = set to help & upgrade its electrical quality' and the production yield is relatively high. Therefore, the metal such as lanthanum, nickel, and lanthanum is a relatively metal material compared to indium or indium alloy, and thus the material of the present invention is low in cost. 2 The characteristics of sulfur, the contact resistance between the __ alloy layer and the oxide conductive layer or the pot electrode = lower. Therefore, the essence of the round of blood
為讓本發明之上述和其他目的、特徵和伽能更明顯 易懂’下文特舉較佳實關，並配合所 明如下。 丨F汁、、，田況 【實施方式】 圖1繪示為本發明之一實施例之顯示裝置。請參昭圖 1 ’顯示裝置100包括第一基板110、第二基板12〇以及位 於第一基板110與第二基板120之間的顯示介質13〇。舉 例而言，當顯示裝置100為一液晶顯示裝置時，第一基板 11〇例如是主動元件陣列基板，第二基板120例如是&色 濾光片，而顯示介質130例如是液晶層。當然，顯示裝置 1〇〇也可以是電漿顯示裝置、有機電激發光顯示裝置^其 他種類的顯示裝置。當顯示裝置100為有機電激發光顯^ 裝置時，也可僅具有一第一基板110及配置於第—基板11〇 上並作為顯示介質130的有機發光層。本實施例在此將第 11 ^lZlTW 24864twf.doc/n 201005947 -基板110視為液晶絲裝置之絲元件_基板以進行 說明。第-基板11G上具有多個可傳輸電子訊號的導體圖 案’以傳輸電子訊號使顯示裝置賴晝面顯示的功 能。這些導體随例如是資料線、掃描線、電容電極 電接墊以及4膜電晶體之閘極、源極與沒極等。 ❹ 由先前技術可知，若以低電阻係數的銘製作第一基板 110上的導體®案’射提供良好的訊號傳輸品質，且也 可降低顯示裝置1GG之製作成本。然而，單層銘金屬會受 到其他侧製程或是薄膜沉積製程影響而被雜或氧化， 進而與其他導财料間產生大的接_抗。·，有許多 ^用^金制油金屬層結合❹層金屬結構的概念相 繼被k出’例如以銦層或齡金層與齡屬層結合。然而， 金屬，所需成本太高’域會受到氣體六氟化 j賴，㈣響半導體元件之餘良率。因此，本實施 二、f提出利用域鑭合金層與實質純1呂層的多層金屬結 以解決習知之導翻餘法兼顧高電性品質與低成本花 =的問題。當然、’本發明並不限定將_鑭合金層與實質 、/呂層的多層金屬結構應用於顯示裝置中。在其他實施例 錄鑭合金層與實質純銘層的多層金屬結構也可以應 ；種電子裝置或其他電子產品的導體圖案當中。 本實施例以鋁鎳鑭合金層與實質純鋁層的多層金屬 、.，°構作為顯示裝置100的局部區域140之導體圖宰來進行 繪示為圖丨之顯示裝置的局部 "，L百先’請參照圖2A ’於一基材21〇上形成導體圖案 12 _._1Z1TW 24864twf.doc/n 220。形成導體圖案22㈣方法例如是在基板2i()上依序全 自沉積實質馳材料（未繪示）及域鑭合金材料（未繪 不）’亚進行圖案化製程以形成導體圖案22〇。導體圖案22〇 疋由第〃紹錄鑭合金層222與第—實質純铭層224所構 成，且第-實質純紹層224失於第一紹錄鋼合金層M2與 基板2io之間。在本實施例中，導體圖案mo包括閑極22〇a 與電容電極220B，而在其他實施例中，導體圖案22〇還可 ❹ 以包括掃描線、資料線等其他金屬導線。 進行圖案化製程形成導體圖案DO時，第一實質純紹 層224未直接暴露於空氣中，而使導體圖案22〇不致因銘 與空氣間反應而產生氧化層。因此’導體圖案22()具有高 製程良率。另外’第-銘錄鑭合金層222中，鎳的含量介 於0.1 wt%〜6 Wt%，而鑭的含量介於〇」树％〜2加％。由如 此的組成成分所構成的銘鎳鑭合金之阻抗大致為3叫僅 〜5μΩ^ιη。此外，第一實質純鋁層224之中鋁的含量大於 等於99.0 wt% ’且第-實質純銘層似之厚度與第一銘錄 « 鑭合金層瓜之厚度之間的比例為1〇:1。在此實施例卜 第一鋁鎳鑭合金層2D之厚度為2〇〇 A〜5〇〇 A。 接著，請參照圖2B，在導體圖案22〇上形成閘絕緣 層230。形成閘絕緣層230的方式例如是進行化學氣相沉 積(Chemical Vapor Deposition，CVD)製程，將氧化石夕、氮 化矽或是氮氧化矽等絕緣材質形成於基板21〇上，並覆蓋 住導體圖案220。第一鋁鎳鑭合金層222不會與空氣或是 其他氣體反應而氧化，因此導體圖案22〇的表面可以保有 13 -1Z1TW 24864twf.doc/n 201005947 良好的導電性。若欲以導體圖案220與其他導線接觸時， 不容易發生接觸不良的問題。 ' 再來，請參照圖2C，在閘極220A上方形成半導體層 240。半導體層240的形成方式例如是先進行一化學氣相沉 積製程，將非晶矽沉積於閘絕緣層23〇上，接著進行一捧 雜製程及圖案化製程’以形成在閘極220A上方的半導體 層240。其中，摻雜製程可使半導體層24〇中含有摻質之 部伤具有較低的接觸阻抗。然而，在其他實施例中，半導 體層240的形成方式也可以不需進行摻雜製程而僅以本徵 非晶矽構成半導體層240。 然後，請參照圖2D，在半導體層24〇上形成另一導 體圖案’其包括源極250A與没極250B。形成源極肩 與沒極2·的方法例如是進行—沉積製程以將導電相 料、實質純鋁材料以及鋁鎳鑭合金材料依序形成於基相 210上。之後，藉由圖案化製程將這些金屬材料圖案化， 以形成位於閘極22GA兩側的源極25GA與沒極25犯。此 時，源極250A與汲極250B例如是由導電層256、 質純鋁層254及第二鋁鎳鑭合金層252 ，構成。閘極繼、源極250a:== 體260。另外，形成源極25〇a與没極2· 的同時也可以形成龍線、掃描線或其他導體圖案。 源二 =之時==’因此在製作 成第二實質_i 254 m▲層256後，再形 尽貫施例而言，導電層256的 --1Z1TW 24864twf.doc/n 201005947 材質例如是氮化錮或銦。導電層256之配置有助於降低源 極25〇A/;及極2观和半導體層24〇之間的接觸阻抗。另The above and other objects, features and gamma of the present invention are more apparent and understood.丨F汁,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Referring to FIG. 1 ', the display device 100 includes a first substrate 110, a second substrate 12A, and a display medium 13A located between the first substrate 110 and the second substrate 120. For example, when the display device 100 is a liquid crystal display device, the first substrate 11 is, for example, an active device array substrate, the second substrate 120 is, for example, a & color filter, and the display medium 130 is, for example, a liquid crystal layer. Of course, the display device 1 may be a plasma display device, an organic electroluminescence display device, or other types of display devices. When the display device 100 is an organic electroluminescence device, it may have only a first substrate 110 and an organic light-emitting layer disposed on the first substrate 11A as the display medium 130. In this embodiment, the 11th 1st illuminator is considered to be the wire element_substrate of the liquid crystal wire device. The first substrate 11G has a plurality of conductor patterns capable of transmitting electronic signals to transmit electronic signals to cause the display device to display the functions. These conductors are, for example, data lines, scan lines, capacitor electrode pads, and gates, sources, and gates of the 4-membrane transistor. ❹ It is known from the prior art that the conductors on the first substrate 110 are made with a low resistivity to provide good signal transmission quality, and the manufacturing cost of the display device 1GG can also be reduced. However, a single layer of metal may be contaminated or oxidized by other side processes or thin film deposition processes, which in turn creates a large resistance to other materials. There are many concepts in which a metal layer of a ruthenium metal layer is bonded to a metal layer of a ruthenium layer, for example, in combination with an indium layer or an ageing layer and an age layer. However, the metal, the cost is too high, the domain will be subject to gas hexafluoride, and (4) the remaining yield of the semiconductor component. Therefore, in the second embodiment, a multi-layer metal junction using a domain-germanium alloy layer and a substantially pure one-layer layer is proposed to solve the problem of high-electricity quality and low-cost flowering. Of course, the present invention does not limit the application of a multi-layered metal structure of a yttrium alloy layer and a substantial layer of ruthenium to a display device. In other embodiments, the multilayer metal structure of the alloy layer and the substantially pure layer may also be used in the conductor pattern of an electronic device or other electronic product. In this embodiment, the multilayer metal of the aluminum-niobium alloy layer and the substantially pure aluminum layer is used as the conductor pattern of the partial region 140 of the display device 100, and is shown as a part of the display device of the figure.百先'Please refer to FIG. 2A' to form a conductor pattern 12_._1Z1TW 24864twf.doc/n 220 on a substrate 21A. The method of forming the conductor pattern 22 (4) is, for example, performing a patterning process on the substrate 2i() by sequentially depositing a substantial material (not shown) and a domain alloy material (not shown) to form the conductor pattern 22A. The conductor pattern 22 is formed by the second layer of the alloy layer 222 and the first substantially pure layer 224, and the first substantially pure layer 224 is lost between the first layer of the alloy layer M2 and the substrate 2io. In the present embodiment, the conductor pattern mo includes the dummy pole 22〇a and the capacitor electrode 220B, and in other embodiments, the conductor pattern 22〇 may also include other metal wires such as scan lines, data lines, and the like. When the patterning process is performed to form the conductor pattern DO, the first substantially pure layer 224 is not directly exposed to the air, so that the conductor pattern 22 does not cause an oxide layer to react with the air. Therefore, the conductor pattern 22() has a high process yield. Further, in the "first-inscription" alloy layer 222, the content of nickel is from 0.1 wt% to 6 Wt%, and the content of niobium is between % and 2% by weight. The impedance of the nickel-niobium alloy composed of such a composition is approximately 3 〜5 μΩ^ιη. In addition, the content of aluminum in the first substantially pure aluminum layer 224 is greater than or equal to 99.0 wt% ' and the ratio of the thickness of the first-substantially pure layer to the thickness of the first inscription «the thickness of the alloy layer is 1〇: 1. In this embodiment, the thickness of the first aluminum-niobium alloy layer 2D is 2 〇〇 A 〜 5 〇〇 A. Next, referring to Fig. 2B, a gate insulating layer 230 is formed on the conductor pattern 22A. The method of forming the gate insulating layer 230 is, for example, a chemical vapor deposition (CVD) process, in which an insulating material such as oxidized oxide, tantalum nitride or hafnium oxynitride is formed on the substrate 21 and covered with a conductor. Pattern 220. The first aluminum-nickel-niobium alloy layer 222 does not react with air or other gases to oxidize, so that the surface of the conductor pattern 22 can maintain a good electrical conductivity of 13 -1Z1TW 24864twf.doc/n 201005947. If the conductor pattern 220 is to be in contact with other wires, the problem of poor contact is less likely to occur. Further, referring to FIG. 2C, a semiconductor layer 240 is formed over the gate 220A. The semiconductor layer 240 is formed by, for example, performing a chemical vapor deposition process on which the amorphous germanium is deposited on the gate insulating layer 23, followed by a heterogeneous process and a patterning process to form a semiconductor over the gate 220A. Layer 240. Wherein, the doping process can have a low contact resistance in the semiconductor layer 24 含有 containing the dopant. However, in other embodiments, the semiconductor layer 240 may be formed in such a manner that the semiconductor layer 240 is formed only of intrinsic amorphous germanium without performing a doping process. Then, referring to Fig. 2D, another conductor pattern ' is formed on the semiconductor layer 24', which includes the source 250A and the gate 250B. The method of forming the source shoulder and the gate electrode is, for example, a deposition-deposition process for sequentially forming a conductive material, a substantially pure aluminum material, and an aluminum-niobium alloy material on the base phase 210. Thereafter, the metal materials are patterned by a patterning process to form source 25GA and immersed 25 on both sides of the gate 22GA. At this time, the source electrode 250A and the drain electrode 250B are composed of, for example, a conductive layer 256, a pure aluminum layer 254, and a second aluminum nickel-niobium alloy layer 252. Gate succeeds, source 250a: == body 260. Further, a long line, a scanning line or another conductor pattern may be formed while forming the source 25 〇 a and the immersion 2·. When the source 2 = = = ' Therefore, after making the second substantial _i 254 m ▲ layer 256, the -1Z1TW 24864twf.doc/n 201005947 material of the conductive layer 256 is, for example, nitrogen. Pupation or indium. The configuration of the conductive layer 256 helps to reduce the contact resistance between the source 25A/; and the pole 2 and the semiconductor layer 24A. another
外’第二鋁鎳鑭合金層252中，鎳的含量介於（U • wt%〜6Wt%，而鑭的含量介於〇1加％〜2^%。如此的组成 成分所構成的_鑭合金之阻抗大致為3〜5吣 -cm。第—實質純紹層254之中㈣含量大於等於 wt% ’且第二實質純料之厚度與第二雜鑭合金層 ❿252之厚度之間的比例為10:卜此外’第二銘錄斕合金層 252之厚度為200 A〜500 Λ。 4參照圖2Ε，完成薄膜電晶體26〇的製作之後，可在 基板^10上形成保護層27〇以將薄膜電晶體覆蓋。形 成保護層fG的方法包括以化學氣相沉積法形成氧化石夕、 氮匕夕鼠氧化梦專絕緣材質於基板210上，以覆蓋整個 薄膜電晶體260。當然，為了使後續各元件的製程更加方 便，可以在保護層270上形成一平坦層272。平坦層272 之材®可以是祕亞胺（pQlyimide)、壓克力樹脂(acrylic resin)、酚醛樹脂(n〇v〇lac resin)或其他有機材料。平坦層 272之材質也可以氧化矽、氮化矽或氮氧化矽等無^ 料。此外，為了使薄膜電晶體260與外部電極層連接，必 須進行非等向性蝕刻製程以在保護層270與平坦層272中 形成一開口 274，以暴露出汲極250Β的部份區域^ 接著’請參照圖2F ’於基板210上形成一外部電極 280，且外部電極28〇藉由開口 274與汲極25〇β接^。外 邛電極280的形成方法例如是以物理氣相沉積法將氧化物 15 201005947 u Zl TW 24864twf-doc/n 導電材料形成於平坦層272上，其中氧介鉍道+ 疋銦錫氧化物、銦鋅氧化物或其他材質。此時 1〇〇的局部區域丨4〇已大致製作完成。 、 詳細來說，形成開口 274時所進行之非等向性侧 ^列如是電漿侧製程，其使用的電漿氣體為六氣化硫。In the outer 'second aluminum-nickel-niobium alloy layer 252, the content of nickel is between (U • wt% and 6 wt%, and the content of niobium is between 加1 plus % and 2% by weight. _镧 constituted by such a composition The impedance of the alloy is approximately 3 to 5 吣-cm. The ratio of the thickness of the second substantially pure material to the thickness of the second hybrid alloy layer 252 is greater than or equal to the weight % of the first substantially pure layer 254. Further, the thickness of the second alloy layer 252 is 200 A to 500 Å. 4 Referring to FIG. 2, after the fabrication of the thin film transistor 26 is completed, a protective layer 27 can be formed on the substrate . The thin film transistor is covered. The method of forming the protective layer fG includes forming a oxidized stone by a chemical vapor deposition method, and oxidizing the insulating material on the substrate 210 to cover the entire thin film transistor 260. Of course, in order to The process of subsequent components is more convenient, and a flat layer 272 can be formed on the protective layer 270. The material of the flat layer 272 can be pQlyimide, acrylic resin, phenolic resin (n〇v) 〇lac resin) or other organic materials. The material of the flat layer 272 can also be oxygen In addition, in order to connect the thin film transistor 260 to the external electrode layer, an anisotropic etching process must be performed to form an opening 274 in the protective layer 270 and the flat layer 272. To expose a portion of the drain 250 ^ ^ Next, please refer to FIG. 2F ' to form an external electrode 280 on the substrate 210, and the external electrode 28 is connected to the drain 25 〇 β through the opening 274. The formation method of 280 is, for example, forming an oxide 15 201005947 u Zl TW 24864 twf-doc/n conductive material on the flat layer 272 by physical vapor deposition, wherein the oxygen channel + yttrium indium tin oxide, indium zinc oxide Or other materials. At this time, the partial area 〇〇4〇 of 1〇〇 has been roughly completed. In detail, the anisotropic side column formed when the opening 274 is formed is a plasma side process, and the plasma used therein is used. The gas is six gasified sulfur.
ΓΐίΓ0B的材質是由鉬或其合金與實質純鋁層構成的 夕=金屬結構，則進行非等向性蝕刻製程時，開口 274所 暴露出來的鉬會被電漿氣體侵蝕。如此一來，接觸阻抗較 低的鉬可能在開口 274的部分會被爛掉，而僅能藉由位 於開口 274側壁的銦與外部電極28〇接觸，而大幅減少鉬 金屬與外部電極280的接觸面積。同時，開口 274所暴露 之鋁在被腐蝕後與外部電極28〇的接觸阻抗也很大。換言 之，以鉬或其合金與實質純鋁層構成的多層金屬結構作為 /及極250B時’主要只靠開口 274侧壁的钥與外部電極“ο 之間的環狀接觸，而導致整體接觸阻抗極大，甚至可能發 生接觸不良之情形。 相較之下，本實施例將第二鋁鎳鑭合金層252形成於 第二實質純鋁層254上，第二鋁鎳鑭合金層252不會在非 等向性蝕刻製程中被電漿氣體侵蝕。因此，開口 274暴露 的是第二鋁鎳鑭合金層252，第二鋁鎳鑭合金層252與外 部電極280之間是呈現整面地接觸，使得薄膜電晶體26〇 與外部電極280之間的電性接合相當良好。另外，在形成 氧化物導電材料時’金屬鋁的表面容易受到腐蝕，因此本 實施例之第二銘鎳鑭合金層252可保護第二實質純鋁層 16 201005947r/1TW24864twfH ; ________ .1Z1TW 24864twf.doc/n 254 ’以避免金屬抑職細影響外部電極·與沒極 250B之間的電性接觸。 ” . 實務上’外部電極可說是-畫素電極，而圖1之 ' 顯示裝置1〇0的局部區域140可說是一由薄膜電晶體260 與外部電極280組成之晝素結構。當然，第二紹錄鋼合金 層252、第二實質純紹層254與導電層256所構成的多層 金屬結構或第一鋁鎳鑭合金層222與第一實質純鋁層224 ⑩ 所構成的多層金屬結構不僅限於應用在薄膜電晶體2曰60的 導體圖案中。在其他實施例中，上述之多層金屬層結構也 可以應用於各式導線及各種導體圖案中。 除此之外，在電子裝置以及顯示裝置中，不同層之金 屬圖案常需相互電性連接或是分別與最上層之導體層電性 連接。因此，圖3A〜圖3H將提出本發明之一實施方式之 多層金屬結構之接觸製程。 凊先參照圖3A，在一基板310上形成一第一圖案化 金屬層320。形成此第一圖案化金屬層32〇的方法包括在 ❿紐310上依序形成m純轉料層(树示)以及 一第一鋁錄鑭合金材料層（未繪示），並將其圖案化以形成 依序堆疊的第一實質純鋁層322以及第一鋁鎳鑭合金層 324。換言之，第一圖案化金屬層32〇包括第一實質純鋁層 322以及第一铭鎳鑭合金層324。當然，在其他實施例中， 第一圖案化金屬層32〇也可以是由其他金屬材質以一層或 是多層疊層結構所組成。 接著’請參照圖3B，在基板310上形成覆蓋第一圖案 17 201005947 ---------1Z1TW 24864twf.doc/n 化金屬層320的一第一絕緣層33(^第一絕緣層33〇例如 是氧化矽、氮化矽、氮氧化矽或是其他絕緣材質。在此， • 第一絕緣層330完整地將第一圖案化金屬層32〇覆蓋。 然後’請參照圖3C，在第一絕緣層330上形成第二 圖案化金屬層340。形成此第二圖案化金屬層34〇的方法 包括在基板310上依序形成一導電材料層、一第二實質純 鋁材料層（未繪示）以及一第二鋁鎳鑭合金材料層（未繪 φ 不）’並將其圖案化以形成依序堆疊的導電層342、第二實 質純鋁層344以及第二鋁鎳鑭合金層346。導電層342例 如疋由氮化鉬或是鉬等金屬材質所組成。換言之，第二圖 案化金屬層340包括導電層342、第二實質純銘層344以 及第一鋁鎳鑭合金層346。當然，在其他實施例中，第二 圖案化金屬層34G也可以是由其他金屬材質以-層或是多 層疊層結構所組成。 a ^後，請參照圖3D，在第一絕緣層330上形成一層 $蓋第一金屬層340之第二絕緣層35G。第二絕緣層35〇 ^成方式例如是則b學氣相沉積法或是物理氣相沉積法 將絕緣材料形成於第一絕緣層33〇上。在本實施例中，第 料、邑緣層350之材質可以是有機絕緣材料或是無機絕緣材 接下來，晴參照圖3E與圖3F，在第二絕緣層3刈上 案:化遮罩層362。實務上，此步驟是先在第二絕 並一，2成光阻材料層360。接著，使用一半透光罩 ’仃一微影製程，以將光阻材料層360圖案化成圖案化 18 201005947 ▲…〜一 i *rZlTW 24864twf.doc/n 遮罩層362。由於半透光罩可區分為不同 ”利用半透光罩進行曝光製程可使對應不同== 光阻材㈣360姆絲度。讀 $ 阻材料層遍進行顯影即可形成圖案化遮罩層362 ^ ，，圖案化遮罩層362可具有一開口 3 64與—薄化區3的。 坪細來說，圖案化遮罩層362中，開口 364位於第一圖案 =金屬層320上方，而薄化區施位於第二圖案化金屬層The material of ΓΐίΓ0B is a metal structure composed of molybdenum or its alloy and a substantially pure aluminum layer. When an anisotropic etching process is performed, the molybdenum exposed by the opening 274 is eroded by the plasma gas. As a result, the molybdenum having a lower contact resistance may be rotted in the portion of the opening 274, and the contact between the molybdenum metal and the external electrode 280 can be greatly reduced only by the indium of the sidewall of the opening 274 being in contact with the external electrode 28?. area. At the same time, the contact resistance of the aluminum exposed by the opening 274 to the external electrode 28A after being etched is also large. In other words, when a multi-layered metal structure composed of molybdenum or an alloy thereof and a substantially pure aluminum layer is used as the / and the pole 250B, the annular contact between the key of the side wall of the opening 274 and the external electrode "o" is dominant, resulting in an overall contact resistance. In the first embodiment, the second aluminum-nickel-niobium alloy layer 252 is formed on the second substantially pure aluminum layer 254, and the second aluminum-nickel-niobium alloy layer 252 is not in the non-defective manner. The isotropic etching process is eroded by the plasma gas. Therefore, the opening 274 is exposed to the second aluminum-niobium alloy layer 252, and the second aluminum-niobium alloy layer 252 and the external electrode 280 are in full-surface contact, so that The electrical connection between the thin film transistor 26A and the external electrode 280 is quite good. In addition, the surface of the metal aluminum is susceptible to corrosion when the oxide conductive material is formed, so the second indium nickel alloy layer 252 of the embodiment can be Protecting the second substantially pure aluminum layer 16 201005947r/1TW24864twfH ; ________ .1Z1TW 24864twf.doc/n 254 'To avoid the metal restraint affecting the electrical contact between the external electrode and the pole 250B." . Electrode can be said - pixel electrode, and FIG. 1 of the 'display device 1〇0 local region 140 can be said to be a day of the pixel structure 260 and the thin film transistor 280 of the external electrode composition. Of course, the second layer of the steel alloy layer 252, the second substantially pure layer 254 and the conductive layer 256, or the first aluminum-aluminum-niobium alloy layer 222 and the first substantially pure aluminum layer 224 10 The metal structure is not limited to being applied to the conductor pattern of the thin film transistor 2曰60. In other embodiments, the multilayer metal layer structure described above can also be applied to various types of wires and various conductor patterns. In addition, in electronic devices and display devices, metal patterns of different layers are often electrically connected to each other or electrically connected to the uppermost conductive layer. Therefore, Figs. 3A to 3H will propose a contact process of a multilayered metal structure according to an embodiment of the present invention. Referring first to Figure 3A, a first patterned metal layer 320 is formed on a substrate 310. The method for forming the first patterned metal layer 32A includes sequentially forming a m pure transfer layer (tree) and a first aluminum aluminum alloy material layer (not shown) on the button 310, and patterning the pattern The first substantially pure aluminum layer 322 and the first aluminum nickel bismuth alloy layer 324 stacked in sequence are formed. In other words, the first patterned metal layer 32A includes a first substantially pure aluminum layer 322 and a first inscribed nickel-niobium alloy layer 324. Of course, in other embodiments, the first patterned metal layer 32 can also be composed of other metal materials in a one-layer or multi-layer laminated structure. Next, referring to FIG. 3B, a first insulating layer 33 covering the first pattern 17 201005947 ---------1Z1TW 24864 twf.doc/n metal layer 320 is formed on the substrate 310 (the first insulating layer) 33〇 is, for example, tantalum oxide, tantalum nitride, tantalum oxynitride or other insulating material. Here, the first insulating layer 330 completely covers the first patterned metal layer 32. Then, please refer to FIG. 3C, A second patterned metal layer 340 is formed on the first insulating layer 330. The method for forming the second patterned metal layer 34 includes sequentially forming a conductive material layer and a second substantially pure aluminum material layer on the substrate 310 (not And a second aluminum-nickel-niobium alloy material layer (not drawn φ not) and patterned to form a sequentially stacked conductive layer 342, a second substantially pure aluminum layer 344, and a second aluminum-nickel-niobium alloy layer 346. The conductive layer 342 is made of, for example, a metal material such as molybdenum nitride or molybdenum. In other words, the second patterned metal layer 340 includes a conductive layer 342, a second substantially pure layer 344, and a first aluminum nickel-niobium alloy layer 346. Of course, in other embodiments, the second patterned metal layer 34G can also It is composed of other metal materials in a layer or a multilayer laminated structure. After a, referring to FIG. 3D, a second insulating layer 35G covering the first metal layer 340 is formed on the first insulating layer 330. The second insulating layer 35 is formed on the first insulating layer 33 by, for example, a b-vapor deposition method or a physical vapor deposition method. In the embodiment, the first material and the edge layer 350 are formed. The material may be an organic insulating material or an inorganic insulating material. Next, referring to FIG. 3E and FIG. 3F, on the second insulating layer 3, the mask layer 362 is formed. In practice, this step is first in the second And one, 20% of the photoresist material layer 360. Then, using a half transmissive cover 仃 a lithography process to pattern the photoresist material layer 360 into a pattern 18 201005947 ▲...~i i *rZlTW 24864twf.doc/n Mask layer 362. Since the translucent cover can be distinguished as different, the exposure process using the translucent cover can make the corresponding difference == photo resist material (four) 360 m filament. Read the resist material layer to develop the pattern to form the pattern. The mask layer 362 ^ , the patterned mask layer 362 can have an opening 3 64 and a thin . Ping thin region 3, the patterned mask layer 362, the opening 364 is located above the first patterned metal layer = 320, and the thinned region is applied in the second patterned metal layer
〇上方。此外’圖案化遮罩層362在薄化區364之部分 的厚度小於在其他部分的厚度。 然後，請參照圖3F以及圖3G，以圖案化遮罩層362 為罩幕而進行一银刻製程，並移除圖案化遮罩層362。钱 ^製程例如是乾式_製程’也可以是非等向性姓刻製 程二，例來說’乾式餘刻製程例如是電裝侧製程，且使 氟化硫為㈣氣體。在此步驟中，第一絕緣層33〇與 第二絕緣層350位於開口 364下方之部分會被移除，且第 一圖案化金屬層320的部分區域被暴露出來。此外，圖案 化遮罩層362之薄化區366與位於薄化區366下方之部分 第二絕緣層350也會被移除，並且第二圖案化金屬層34〇 的部分區域也會被暴露。 在本實施例中，第一圖案化金屬層320以及第二圖案 化金屬層340上方的絕緣層必須被移除，以使此兩金屬層 ，露出來，以便於與上層的導體層電性連接。然而，位於 第一圖案化金屬層320上方的絕緣層有兩層，而第二圖案 化金屬層340上方的絕緣層僅有一層。若以第一圖案化金 201005947 AW/ ^TZITW 24864twf.doc/n 屬層320表面作為蝕刻製程的終點’則須將第一絕緣層33〇 與弟一絕緣層350移除。此時，第二圖案化金屬層340上 方若僅有第二絕緣層350，則第二圖案化金屬層34〇會有 ' 部份被移除。也就是說，受限於絕緣膜層的層數不一致， 第一圖案化金屬層320以及第二圖案化金屬層340不易在 相同的餘刻終點同時被暴露出來。 因此，本實施例在第二圖案化金屬層34〇上方形成厚 φ 度較薄的圖案化遮罩層362,以使蝕刻製程所達到的蝕刻 深度恰可暴露出第二圖案化金屬層34〇表面。換言之，第 一圖案化金屬層320以及第二圖案化金屬層34〇的表面恰 可於相同的蚀刻終點被暴露出來。進一步來說，第一圖案 化金屬層320以及第二圖案化金屬層34〇被暴露出來的區 域例如都是由鋁鎳鑭金屬材質所構成，不容易受到電漿氣 體六氟化硫腐敍。因此，第一圖案化金屬層32〇以及第一 圖案化金屬層340的表面可保有良好的導電性，而有助於 提升其相關應用產品的電性特性。 、 • 之後，請參照圖3H，在第二絕緣層35〇上形成一圖 案化導體層370，其中圖案化導體層370直接接觸第一圖 案化金屬層320與第二圖案化金屬層34〇被暴露的部分區 域。圖案化導體層370之材質例如是金屬導電材質、氧化 物導電材質或其他導電材質。圖案化導體層370使得第一 圖案化金屬層320與第二圖案化金屬層340電性連接。由 於，第一圖案化金屬層320以及第二圖案化金屬層34〇被 暴露出來的區域不易受到電漿氣體的腐蝕，因而與圖案化 ；FZ1TW 24864twf.doc/n 201005947〇 Above. Further, the thickness of the patterned mask layer 362 in the portion of the thinned region 364 is smaller than the thickness in other portions. Then, referring to FIG. 3F and FIG. 3G, a silver engraving process is performed by patterning the mask layer 362 as a mask, and the patterned mask layer 362 is removed. The process may be, for example, a dry process or an anisotropic process, for example, the dry process may be, for example, an electrical side process, and the sulfur fluoride is a (four) gas. In this step, the portion of the first insulating layer 33 and the second insulating layer 350 under the opening 364 is removed, and a portion of the first patterned metal layer 320 is exposed. In addition, the thinned region 366 of the patterned mask layer 362 and a portion of the second insulating layer 350 underlying the thinned region 366 are also removed, and a portion of the second patterned metal layer 34 is also exposed. In this embodiment, the insulating layer above the first patterned metal layer 320 and the second patterned metal layer 340 must be removed, so that the two metal layers are exposed to be electrically connected to the upper conductor layer. . However, the insulating layer above the first patterned metal layer 320 has two layers, and the insulating layer above the second patterned metal layer 340 has only one layer. If the first patterned gold 201005947 AW/^TZITW 24864twf.doc/n layer 320 surface is used as the end point of the etching process, the first insulating layer 33 and the first insulating layer 350 must be removed. At this time, if there is only the second insulating layer 350 above the second patterned metal layer 340, the second patterned metal layer 34 has a portion removed. That is, the number of layers limited by the insulating film layer is inconsistent, and the first patterned metal layer 320 and the second patterned metal layer 340 are not easily exposed at the same end point of the same. Therefore, in this embodiment, a patterned mask layer 362 having a thin thickness of φ is formed over the second patterned metal layer 34〇 so that the etching depth achieved by the etching process can directly expose the second patterned metal layer 34〇. surface. In other words, the surfaces of the first patterned metal layer 320 and the second patterned metal layer 34 are exposed to the same etching end point. Further, the exposed regions of the first patterned metal layer 320 and the second patterned metal layer 34 are, for example, made of an aluminum-niobium metal material, and are not easily rusted by the plasma gas sulphur hexafluoride. Therefore, the surfaces of the first patterned metal layer 32 and the first patterned metal layer 340 can maintain good electrical conductivity and help to enhance the electrical properties of their related applications. Then, referring to FIG. 3H, a patterned conductor layer 370 is formed on the second insulating layer 35, wherein the patterned conductor layer 370 directly contacts the first patterned metal layer 320 and the second patterned metal layer 34. Part of the area exposed. The material of the patterned conductor layer 370 is, for example, a metal conductive material, an oxide conductive material or other conductive material. The patterned conductor layer 370 electrically connects the first patterned metal layer 320 to the second patterned metal layer 340. Because the exposed regions of the first patterned metal layer 320 and the second patterned metal layer 34 are less susceptible to corrosion by the plasma gas, and thus patterned; FZ1TW 24864twf.doc/n 201005947
導體層370接觸的接觸面可全面地導電。此外，第一圖案 化金屬層320以及第二圖案化金屬層340被暴露出來的區 域是由低阻抗的鋁鎳鑭金屬材質所構成，所以第一圖案化 金屬層320以及第二圖案化金屬層340之間可保持良好的 電性連接。在此，雖以第一圖案化金屬層320與第二圖案 化金屬層340經由圖案化導體層370而互相電性連接為 例’但圖案化導體層370也可以包括彼此獨立的多個部分 而分別與第一圖案化金屬層320及第二圖案化金屬層34〇 電性連接。整體來說，本實施例之導體接觸製程係藉由_ 次的蝕刻製程就使不同層的金屬層具有良好的電性連接， 而有助於提升相關應用產品的電性品質。 綜上所述，本發明之電子裝置、薄膜電晶體與顯示裴 置及導體接觸製程至少具有以下所述之優點。本發明之電 子裝置、薄膜電晶體與顯示裝置利用鋁鎳鑭合金層與實質 純鋁層之多層金屬層的結構作為導體圖案，可以避免實質 純紹層受到氧化或是腐㈣影響導體圖案的導電性。如 此’本發明之電子裝置、賴電晶體與齡裝置中的導體 圖案可以具有較低的接觸阻抗與良好的電性。再者，銘、 格比鉬便宜，以鋁鎳鑭合金作為多層金屬結構 卢拉，有助於降低製造成本。另外，鋁鎳鑭合金有 曰】力’有助於提高本發明之電子裝置、薄膜電 曰曰體與顯不裝置的製程 ==增加製程複雜度的前二= 曰此與同一個上層導體層間具有良好的電性連 21 201005947 lZlTW24864twf.d〇c/n 接。 雖然本發明已以較佳實施例揭露如上，然其並非 限定本發明’任何所屬技觸域巾具有通常知 乂 脫離本發明之精神和範_，#可作些許之更動與不 因此本發明之保魏圍當視後社㈣專利_所界定者 為準。 【圖式簡單說明】The contact surface that the conductor layer 370 contacts can be fully electrically conductive. In addition, the exposed regions of the first patterned metal layer 320 and the second patterned metal layer 340 are formed of a low-resistance aluminum-niobium metal material, so the first patterned metal layer 320 and the second patterned metal layer A good electrical connection can be maintained between 340. Here, although the first patterned metal layer 320 and the second patterned metal layer 340 are electrically connected to each other via the patterned conductive layer 370 as an example, the patterned conductive layer 370 may also include a plurality of portions that are independent of each other. The first patterned metal layer 320 and the second patterned metal layer 34 are electrically connected to each other. In general, the conductor contact process of the present embodiment has a good electrical connection between the metal layers of different layers by the etching process of _ times, which helps to improve the electrical quality of related applications. In summary, the electronic device, the thin film transistor and the display device and the conductor contact process of the present invention have at least the advantages described below. The electronic device, the thin film transistor and the display device of the invention use the structure of the multi-layer metal layer of the aluminum-niobium alloy layer and the substantially pure aluminum layer as the conductor pattern, so as to avoid the oxidation of the substantially pure layer or the corrosion of the conductive pattern. Sex. The conductor pattern in the electronic device, the galvanic crystal and the aged device of the present invention can have a low contact resistance and good electrical properties. Furthermore, Ming and Ge are cheaper than molybdenum, and aluminum-niobium-niobium alloy is used as a multilayer metal structure Lula to help reduce manufacturing costs. In addition, the aluminum-niobium-niobium alloy has the advantage that the process of the electronic device, the thin-film electric body and the display device of the present invention is improved == the first two steps of increasing the complexity of the process are 曰 between this and the same upper conductor layer Has a good electrical connection 21 201005947 lZlTW24864twf.d〇c/n connection. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention. Any of the embodiments of the present invention have the general knowledge and scope of the invention, and may be modified and not protected by the present invention. Weiwei is regarded as the back of the company (4) Patent _ as defined. [Simple description of the map]
圖1缘示為本發明之一實施例之顯示裝置。 140的製 圖2A〜2b會示為圖1之顯示裝置的局部區域 作流程。 。圖3A〜圖犯繪示為本發明之—實施例之導體接觸製 【主要元件符號說明】 100 :顯示裝置 110 :第一基板 120 :第二基板 130 :顯示介質 140 =局部區域 210、310 :基板 220 :導體圖案 220A :閘極 220B :電容電極 222、324 :第一铭錄爛合金層 224、322 :第一實質純鋁層 22 二」」'Z1TW 24864twf.doc/n 201005947 230 :閘絕緣層 240 :半導體層 250A :源極 250B :汲極 252、346 :第二鋁鎳鑭合金層 254、344 :第二實質純鋁層 256、342 :導電層 260 :薄膜電晶體 ® 270 :保護層 272 :平坦層 274、364 :開口 280 :外部電極 320 :第一圖案化金屬層 330 :第一絕緣層 340 :第二圖案化金屬層 350 :第二絕緣層 參 36〇 :光阻材料層 362:圖案化遮罩層. 366 :薄化區 370 :圖案化導體層 23Fig. 1 is a view showing a display device according to an embodiment of the present invention. The drawings of Figs. 2A to 2b are shown as a partial flow of the display device of Fig. 1. . FIG. 3A is a diagram showing a conductor contact system according to an embodiment of the present invention. [Main component symbol description] 100: display device 110: first substrate 120: second substrate 130: display medium 140 = partial regions 210, 310: Substrate 220: Conductor pattern 220A: Gate 220B: Capacitance electrodes 222, 324: First inscribed rotten alloy layer 224, 322: First substantially pure aluminum layer 22""" Z1TW 24864twf.doc/n 201005947 230: Brake insulation Layer 240: semiconductor layer 250A: source 250B: drain 252, 346: second aluminum-niobium alloy layer 254, 344: second substantially pure aluminum layer 256, 342: conductive layer 260: thin film transistor® 270: protective layer 272: flat layer 274, 364: opening 280: external electrode 320: first patterned metal layer 330: first insulating layer 340: second patterned metal layer 350: second insulating layer 〇 36: photoresist material layer 362 : patterned mask layer. 366: thinned region 370: patterned conductor layer 23