201005832 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種半導體裝置，制是關於製作應變 矽電晶體的方:法。 【先前技術】 隨著半導體朝向微細化尺寸之發展，電晶體的閘極、 源極、汲㈣尺寸也隨著特徵尺寸的減小而跟著不斷地縮 小。但由於材料先天物理性質的限制，閘極、源極、汲極 的尺寸減小會造成電晶體元件中決定電流大小的載子量減 少’進而影響電晶體的效能。因此，提升載子遷移率以增 加MOS電晶體之速度已成為目前半導體技術領域中之— 大課題。 在目河已知的技術中，係有利用在通道中製造機械應 力，以提升載子遷移率的方法。例如，在矽基底上磊晶生 成一鍺化矽（silicon germanium ; SiGe)通道層，以形成一壓 細應變通道（compressive strained channel)，可以明顯地增 加電洞遷移率。或者在鍺化矽層上磊晶生成一矽通道 (silicon channel) ’ 以形成一伸張應變通道（tensUestrained channel)，則可以明顯地增加電子遷移率。 201005832 另外，亦有使用選擇性磊晶成長方法，於閘極形成之 後，在源極/汲極區域中嵌入摻雜鍺，形成受壓擠的應變矽 結構，以增進PMOS的電子遷移率。或在NMOS製程中進 行摻雜碳的矽選擇性磊晶嵌入源極/汲極區域中，形成拉伸 的應變矽結構，以增進電子遷移率。 ' 又或者另有使用在接觸洞餘刻停止層（contact etch stop layer，CESL)施加應力，使半導體基底上各電晶體的 通道產生伸張或壓縮的應變，而改進載子的遷移率。 然而，隨著金氧MOS電晶體之尺寸不斷朝向微型化發 展，對於MOS電晶體之速度需求亦不斷地增加，利用上述 習知技術所形成之壓縮應力或伸張應力，已難以達成所需 的程度。 【發明内容】 有鑑於此，申請人提出一種製作應變矽電晶體之方 法，以改善上述習知技術的缺點，進而提升M0S電晶體之 效能。 本發明提供一種製作應變矽電晶體之方法，首先，提 供一基底包含一第一電晶體區、一第二電晶體區以及一絕 6 201005832 緣物位於該第一電晶體區和該第二電晶體區之間，接著， 於該第一電晶體區之該基底内形成一第一應變矽層，然 後，於該第二電晶體區之該基底内形成一第二應變矽層， 之後，於該第一電晶體區形成一第一導電型態的電晶體， 最後於S亥第二電晶體區形成一第二導電型態的電晶體。 本發明另提供一種製作應變矽電晶體之方法，首先， 0 長1 (、基底包含一電晶體區以及一絕緣物位於該電晶體區 之外圍，然後，於該電晶體區之該基底内形成一應變矽層， 之後於該電晶體區形成一第一導電型態的電晶體。 本發明又提供一種製作應變矽電晶體之方法，首先提 供一基底包含一電晶體區以及一絕緣物位於該電晶體區之 外圍’其次於該電晶體區内進行一非晶矽化製程，接著， 0 於該電晶體區内形成一摻雜井，然後形成一應力層覆蓋該 電晶體區，之後進行一回火製程，以在該電晶體區之該基 底内形成一應變矽層並且活化該摻雜井内之摻質，最後移 除該應力層以及於該電晶體區形成一第一導電型態的電晶 本發明之應變石夕電晶體製程其特徵在於利用應力記憶 技術(SMT)所形成在電晶體區内的應變矽層之形成時點，係 在隔離結構，例如淺溝渠隔離結構，完成之後，而電晶體 7 201005832 還未形成之前。此外，利用本發明之製程，在進行摻雜井 離子佈植製程和非晶矽化製程時，可以使用同一個遮罩。 再者，本發明之應變矽電晶體製程中，可以在一次回火步 驟中同時趨入及活化摻雜井内之摻質並且在基底内形成應 變夺7層。 【實施方式】 請參考第1圖至第5圖，第1圖至第5圖為本發明第 一較佳實施例之製作應變矽電晶體之製程示意圖。 如第1圖所示，首先提供一基底10，例如一矽基底或 一絕緣層上覆石夕（SOI)基底等，而基底10表面定義有一第 一電晶體區12與一第二電晶體區14，接著進行淺溝隔離 結構(STI)等之隔離製程，例如利用蝕刻步驟先在基底10 ❹蝕刻出溝渠，再利用化學沉積製程，沉積一層氧化物填滿 溝渠以及覆蓋基底表面，接著再用化學機械研磨將前述的 氧化物磨平，以於基底10中形成淺溝隔離結構16等之絕 緣物加以隔離電晶體區12、14，其中第一電晶體區12係 為用來形成第一導電型悲之電晶體的主動區域’也就是 說，設置在第一電晶體區12内的電晶體為第一導電型態， 例如N型M0S電晶體；第二電晶體區14係為用來形成第 二導電型態的電晶體的主動區域，也就是說，設置在第二 8 201005832 電晶體區14内的電晶體為第二導電型態，例如P型MOS 電晶體。以下之實施例將以第一電晶體區12上的電晶體為 N型，第二電晶體區14上的電晶體為P型來舉例說明。 接著進行一非晶石夕化製程，例如以一全面性（blanket) 單一離子佈植製程，使用氣(xenon ; Xe)、氬（argon ; Ar)或 鍺(germanium ; Ge)等離子，全面性地同時佈植第一電晶體 Λ 區12與第二電晶體區14。其中，進行此單一離子的佈植 製程時，所使用之氙離子、氬離子或鍺離子之濃度為大於 1Ε14，其能量為大於lOkev。 然後，如第2圖所示，於基底10之第一電晶體區12 與第二電晶體區14上分別形成一第一應力層18和一第二 應力層20。第一應力層18包含一第一石夕氧廣22和一第一 氮化矽層24，其中第一氮化矽層24具有一伸張應力，且 參位於第一矽氧層22上，而第一矽氧層22之功用在於作為 I虫刻停止層或緩衝層，避免第一氮化石夕層24中的應力過 大，造成基底10的結構損壞。根據不同的產品要求，第一 矽氧層22可選擇性的形成。也就是說，第一應力層18亦 可以只包含第一氮化矽層24。同樣的，第二應力層20包 含一第四矽氧層26和一第二氮化矽層28，其中第二氮化 矽層28具有一壓縮應力。第四矽氧層26之功用亦在於避 免第二氮化矽層28中的應力過大，造成基底10的結構損 9 201005832 壞或作為第二氮化矽層28的蝕刻停止層，再者，如同第一 矽氧層22，第四矽氧層26也可以選擇性的形成。此外， 第一氮化矽層24和第二氮化矽層28的形成方式可以為例 如，先在基底10上形成一碎氧層，然後全面形成一具有一 伸張應力的第一氮化矽層24，再經由微影、蝕刻步驟，將 在第二電晶體區14上的第一氮化矽層24加以去除，由於 在去除第一氮化矽層24的過程中會利用前述矽氧層作為 φ 蝕刻停止層而蝕刻了第二電晶體區14上的部分矽氧層，因 此便形成了第一電晶體區12上的未受蝕刻的第一矽氧層 22及第二電晶體區14上受過蝕刻的第二矽氧層。接著， 在第一氮化矽層24和第二矽氧層上全面形成一第三矽氧 層作為另一蝕刻停止層，然後，形成具有壓縮應力的第二 氮化矽層28全面覆蓋在第一氮化矽層24和第二矽氧層上 的第三矽氧層，之後，利用微影、蝕刻步驟將在第一氮化 矽層24上的第二氮化矽層28移除，而餘留在第二電晶體 φ 區14上的第二矽氧層和第三矽氧層，由於皆為相同材料， 因此在第2圖上將第二矽氧層和第三矽氧層視做一第四矽 氧層26。補充說明的是：在第一氮化矽層24上的第二氮 化矽層28也可以不移除，也就是說，不用形成在前述步驟 中所述的第三矽氧層，直接在第一氮化矽層24和第二矽氧 層上形成第二氮化矽層28即可，而第二氮化矽層28會同 時覆蓋第一氮化矽層24和第二矽氧層。再者，第一氮化矽 層24的厚度應加以設計使得第一電晶體區12所受到的總 10 201005832 應力為第一氮化石夕層24所提供的應力。 此外，第一矽氧層22和第一氮化矽層24可以在同一 個腔室中形成；而第四矽氧層26和第二氮化矽層28可以 在同一個腔室中形成，也就是說，可以避免基底由於變換 腔室需要離開真空狀態的情形。此外，應力的調整可藉由 沉積製程參數的匹配或施以離子佈植、回火、紫外光(UV) ^ 等表面處理達成，此皆為熟習該項技藝者與通常知識者所 熟知，故不多加以贅述。 如第3圖所示，進行一回火製程，同時使基底10表層 之矽原子依照第一應力層18和第二應力層20所提供的伸 張/壓縮方向重新排列，以於第一電晶體區12與第二電晶 體區14下方之基底10中，分別形成一第一應變矽層30和 一第二應變石夕層32。至此完成利用應力記憶技術(stress ❿ memorization technique; SMT)在基底10内分別形成一具有 伸張應力第一應變矽層30和一具有壓縮應力的第二應變 矽層32。接著，移除第一應力層18和第二應力層20並形 成圖案化(patterned)之光阻34，曝露出第一電晶體區12和 部分的淺溝渠絶緣結構16，接著進行摻雜井離子佈植製 程，利用P型摻質在第一電晶體區12内的基底10中形成 一 P型掺雜井36。 11 201005832 设有，如弟 移除光阻34後，另形成 化之先阻38以曝露出 战圖案 離結構16，接著進行二-=體區14和部分的漫溝渠隔 第二電晶體區14内的;:離子佈植製程利用換質在 内的基底10中形成一 N型摻雜井4〇。 如5圖所不’進行—高溫熱製程如 以趨入及活化人I程， ❹ 生松雜井36和Ν型摻雜井40内之換哲 妾著，分別在？型_井3〜Ν型摻雜井4Q上形朗極 、44和相對應之N型源極/㈣摻雜區46與P型源二/ 汲極摻雜區48。$ μ· . - ηη '、 至此，本發明之具有應變矽層的CM〇 晶體，如雷日獅电 生電日日體50和p型電晶體52業已完成。 〜請參考第6圖至第9圖，第6圖至第9圖為本發明第 -^佳實施例之製作電晶體之製程示意圖。其中具有相同 ❹力月b的凡件仍沿用與第-較佳實施例相同的符號來表示。 “如第6圖所示，首先提供一基底1〇，其上具有一第一 =曰曰體區12與一第二電晶體區14，接著於基底1〇中形成 戋溝％離結構（STI) 16等之絕緣物加以隔離電晶體區η、 其中淺溝隔離結構16之製程方式在第一實施例中已有 描述，在此不再贅述。此外，第一電晶體區12係為用來形 成第導電型態之電晶體的主動區域，也就是說，設置在 第— "'電晶體區12内的電晶體為第一導電型態，例如 12 201005832 MOS電晶體；第二電晶體區14係為用來形成第二導電型 態的電晶體，例如P型MOS電晶體。 接著形成圖案化之光阻34，曝露出第一電晶體區12 和部分的淺溝渠隔離結構16，接著進行一第一非晶矽化製 程，以離子佈植製程佈植第一電晶體區12，其中離子佈植 所使用的離子包含氙離子、氬離子和鍺離子等，然後，繼 @ 續以光阻34作為遮罩，進行一第一摻雜井離子佈植製程， 例如利用P型摻質以在第一電晶體區12内的基底10中形 成一 P型摻雜井36。根據本發明之另一較佳實施例，前述 之第一非晶矽化製程和第一摻雜井離子佈植製程之製程順 序可以交換，例如，先進行第一摻雜井離子佈植製程以形 成P型摻雜井36，再進行第一非晶矽化製程，但都以圖案 化之光阻34當作遮罩。 ® 如第7圖所示，移除光阻34，另形成一圖案化之光阻 38以曝露出第二電晶體區14和部分的淺溝渠隔離結構 16，然後進行第二非晶矽化製程，以離子佈植製程佈植第 二電晶體區14。同樣的，離子佈植所使用的離子包含氙離 子、氬離子和鍺離子等，而此兩次的非晶矽化製程所使用 之氙離子、氬離子或鍺之濃度分別為大於1E14，其能量為 大於lOKev。然後，繼續以圖案化之光阻38作為遮罩，進 行一第二摻雜井離子佈植製程，例如利用N型摻質在第二 13 201005832 電晶體區…的基底”形成… 發明之另一較接 成Ν聖摻雜井4〇。根據太 車又佳實施例，同樣的 根據本 私和第二接進井離子佈植 之第二非晶石夕化製 皆以圖索化之光阻38當作遮罩。、王順序可以交換，但仍 本电明之第二較佳眚 ^ 稍加改變，即 e 1 1 6 @至第7圖之步驟若 ❹ 形成之前，先^ : 佳實施例··首先在光幻4未 面性進行非曰矽電晶體區12和第二電晶體區14内全 订非日日矽化製程， ^王 34以在第—電晶㈣形成光阻 程，成。型摻雜井36,接;第如第摻7^^ 34，另形成光阻38,在第二移除光阻 井離子佈植势浐m ”日日區14内進行第二摻雜 、私，以形成N型摻雜井4〇。而第三 例的後續步驟則與第二較佳實施例補。—d貫施 φ :第8圖所示，於基底1〇之第一電 電晶體區14上分別彬士、性 2興第一 20。第P應力層18和—第二應力層 μ力層18包含-第-矽氧層22和—第一氮化 m其2中第—氮化石夕層24具有一伸張應力，且位於第 擇性=2上。根據不同的產品要求，第一石夕氧層22選 =的:成：同樣的，第二應力層20包含一第四秒氧層 — 切層28，其巾第4切層28具有一壓 細應力。再者，如同第一石夕氧層22，第四石夕氧層％也可 14 201005832 以選擇性的形成。此外，第一矽氧層22、第四矽氧層26、 第一氮化矽層24和第二氮化矽層28之形成方式如同第一 較佳實施例中所描述，在此不再贅述。 如9圖所示，進行一高溫熱製程，例如一回火製程， 以趨入及活化P型摻雜井36和N型摻雜井40内之摻質， 並且同時在弟一電晶體區12與弟二電晶體區14下方之基 @ 底10中，分別形成一第一應變矽層30和一第二應變矽層 32。然後，移除第一應力層18與第二應力層20之後，再 分別於P型摻雜井36和N型摻雜井40上形成閘極42、44 和N型源極/汲極摻雜區46、P型源極/汲極摻雜區48。至 此，本發明之具有應變矽層的CMOS電晶體，如N型電晶 體50和P型電晶體52已經完成。 第10a圖繪示的是本發明第一較佳實施例之步驟的流 ® 程圖，第10b圖繪示的是本發明第二較佳實施例之步驟流 程圖。第10c圖繪示的是本發明第三較佳實施例之步驟流 程圖。 綜合上述說明，以及第l〇a、10b和10c圖中顯示，本 發明之第一實施例、第二實施例和第三實施例的特徵在於 非晶矽製程係實施於淺溝渠隔離結構完成之後，及開始製 作電晶體之前進行，如此一來，可以在電晶體區的基底上 15 201005832 全面形成應變矽層。 晶:二r 明之第二實施例的優點在於在進行第-非 案化光「高濃度離子佈植製程時係使用同-個圖 植製程時得使用：第製程和第二高濃度離子佈 化_丼==圖;化光阻。再者，趨入及活 係使用π = 應變㈣和—第二應變梦層 個回火製程’並且可在同— 空狀態。再者，如第I0b圖所示，若將於第 換：:進行非晶妙製程和接雜井佈植製程之順序交 井佈植h *—電晶雜β㈣行非晶㈣程和騎的摻雜 之順序交換’即可變化成本發明之另 电日日體之製程步驟。 "第 區ut，第^圖所示，f先提供一基底110包含有一電晶體 ^ έ接著於基底η〇中形成如淺溝隔離結構(STI) 116 邑緣物環繞電晶體區112，淺溝隔離結構(STI) 116之 式如第一較佳實施例中所描述，在此不再贅述。其 主勒Γ體區112可以用來形成—特定導電型態之電晶體的 區域，也就是說，設置在電晶體區η]内的電晶體可 ' 導電型態，例如：ρ型或Ν型。 16 201005832 接著，進行一非晶矽化製程，例如以一全面性單一離 子佈植製程，使用氙、氬或鍺離子等，全面性地佈植電晶 體區112。其中，進行此單一離子的佈植製程時，所使用 之氙離子、氬離子或鍺離子之濃度分別為大於1E14，其能 量為大於lOKev。 如第12圖所示，於基底110之電晶體區112上形成一 應力層118,應力層118可包含一矽氧層122和一氮化矽層 124。若第一導電型態為N型，則將氮化矽層124調整為具 有伸張應力，若第二導電型態為P型，則將氮化矽層124 調整為具有壓縮應力，其中應力的調整可藉由沉積製程參 數的匹配或施以離子佈植、回火、紫外光(UV)等表面處理 達成，此皆為熟習該項技藝者與通常知識者所熟知，故不 多加以贅述。根據本發明之另一較佳實施例，應力層118 ® 亦可以只包含氮化矽層124，而矽氧層122可以選擇性的 形成。再者，石夕氧層122和說化石夕層124可以利用同一個 腔室中依續沉積形成。 如第13圖所示，進行一回火製程，同時使石夕原子依照 應力層118所提供的伸張/壓縮方向重新排列，以於電晶體 區112下方之基底110中，形成一應變矽層130。至此完成 利用應力記憶技術（SMT)在基底110内形成一應變矽層 17 201005832 130 需 要說明的是：若第—導電型態為則應變石夕層 A㉟應變；若第二導電型‘態為P型則應變㈣13〇 為壓縮應變。 制二’於電晶體區112 β ’接著進行摻進井離子佈植 ,、】用Ν型或ρ型摻質在電晶體區112内的基底 广1 —摻雜井136。隨後，進行一高溫熱製程，例如一 〇回火製程，以趨入及活化摻雜井136中之摻質。 1 ^ ^ 上形成一閘極142和一源極/汲極摻雜區146。 ^本發明之具有應變矽層的MOS電晶體15Θ業已完成。 曰★請參考第14圖至第16圖，第14圖至第16圖為本發 明^五較佳實施例之製作電晶體之製程示意圖。其中具有 一同力此的元件仍沿用與第四較佳實施例相同的符號來表 示。 ❿ ^ 第14圖所示，首先提供一基底110包含有一電晶體 區U2，接著於基底110中形成如淺溝隔離結構(STI) 116 等之、、邑緣物環繞電晶體區112，其中電晶體區112可以用來 形成-特定導電型態之電晶體的主動區域，也就是說，設 置在電晶體區m内的電晶體為第一導電型態電晶體，例 如：PM〇S 或 NMOS。 201005832 然後，形成圖案化之光阻134，於電晶體區112内，接 著進行一非晶矽化製程，以離子佈植製程佈植電晶體區 112，其中離子佈植所使用的離子包含氙離子、氬離子和鍺 離子等，所使用之氙離子、氬離子或鍺離子之濃度分別為 大於1E14，其能量為大於lOKev。隨後，繼續以光阻134 作為遮罩，進行一摻雜井離子佈植製程，利用摻質在電晶 體區112内的基底110中形成一摻雜井136，值得注意的 φ 是：若第一導電型態電晶體為NMOS，則高濃度離子佈植 所植入的離子為P型；若第二導電型態電晶體為PMOS， 則高濃度離子佈植所植入的離子為N型。根據本發明之另 一較佳實施例，前述之非晶矽化製程和高濃度離子佈植製 程之製程順序可以交換，例如，先進行摻雜井離子佈植製 程以形成摻雜井136，再進行非晶矽化製程，但都以圖案 化之光阻134當作遮罩。 本發明之第五較佳實施例的第14圖之步驟若稍加改 變，即可變為一第六較佳實施例：首先，在光阻134未形 成之前，先於電晶體區112内全面性進行非晶矽化製程， 之後’再形成光阻134，以在電晶體區112内進行推雜井 離子佈植製程，以形成摻雜井136。而第六較佳實施例的 後續步驟則與第五較佳實施例相同。 如第15圖所示，於基底110之電晶體區112上形成一 19 201005832 f24力層二Τ、應力層118包含-矽氧層122和-氮化矽層 ㈣It 1電型態為N3^j將氮化石夕層124調整為具有 為具型態為p型則將氣化㈣124調整 m亦可以只包人/據本發明之另-較佳實施例，應力層 的形成。再者=夕124 ’而石夕氧詹122可以選擇性 個腔室連續沉糾成θ 22和氣切層124可以利用同一 ❹201005832 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device which is a method for producing a strained germanium transistor. [Prior Art] As the size of the semiconductor toward the miniaturization has progressed, the size of the gate, the source, and the NMOS of the transistor has been continuously reduced as the feature size is reduced. However, due to the inherent physical properties of the material, the reduction in the size of the gate, source, and drain causes a reduction in the amount of carriers that determine the magnitude of the current in the transistor element, which in turn affects the performance of the transistor. Therefore, increasing the carrier mobility to increase the speed of MOS transistors has become a major issue in the field of semiconductor technology. Among the techniques known to Meguro, there is a method of using mechanical stress in a channel to increase the mobility of a carrier. For example, epitaxial deposition of a germanium germanium (SiGe) channel layer on a germanium substrate to form a compressive strained channel can significantly increase hole mobility. Alternatively, epitaxial formation of a silicon channel on the germanium telluride layer to form a tensile strain channel (tensUestrained channel) can significantly increase the electron mobility. 201005832 In addition, a selective epitaxial growth method is used to embed doping enthalpy in the source/drain region after the gate is formed to form a squeezed strain 矽 structure to enhance the electron mobility of the PMOS. Or doped carbon doped in the NMOS process is selectively epitaxially embedded in the source/drain region to form a tensile strain 矽 structure to enhance electron mobility. Alternatively, or in addition, a contact etch stop layer (CESL) is used to apply stress to cause tensile or compressive strain of the channels of the transistors on the semiconductor substrate to improve the mobility of the carrier. However, as the size of the gold-oxygen MOS transistor continues to be toward miniaturization, the speed demand for the MOS transistor is also increasing, and it is difficult to achieve the required degree by using the compressive stress or the tensile stress formed by the above-mentioned conventional techniques. . SUMMARY OF THE INVENTION In view of the above, the applicant proposes a method of fabricating a strained germanium crystal to improve the disadvantages of the above-mentioned prior art, thereby improving the performance of the MOS transistor. The present invention provides a method for fabricating a strained germanium crystal. First, a substrate is provided with a first transistor region, a second transistor region, and a substrate 6 201005832 edge is located in the first transistor region and the second electrode Between the crystal regions, a first strain 矽 layer is formed in the substrate of the first transistor region, and then a second strain 矽 layer is formed in the substrate of the second transistor region, and then The first transistor region forms a first conductivity type of transistor, and finally a second conductivity type transistor is formed in the second transistor region. The present invention further provides a method for fabricating a strained germanium crystal. First, 0 is 1 (the substrate comprises a transistor region and an insulator is located at the periphery of the transistor region, and then formed in the substrate of the transistor region a strained germanium layer, and then forming a first conductivity type of transistor in the transistor region. The invention further provides a method for fabricating a strained germanium transistor, first providing a substrate comprising a transistor region and an insulator located thereon The periphery of the transistor region is followed by an amorphous deuteration process in the transistor region. Then, a doping well is formed in the transistor region, and then a stress layer is formed to cover the transistor region, and then one time is performed. a fire process for forming a strained germanium layer in the substrate of the transistor region and activating the dopant in the doped well, finally removing the stress layer and forming a first conductivity type of crystal in the transistor region The strained magnet crystal process of the present invention is characterized in that the point of formation of the strain enthalpy layer formed in the transistor region by the stress memory technique (SMT) is in an isolation structure such as a shallow trench. The trench isolation structure is completed, and before the transistor 7 201005832 has not been formed. In addition, with the process of the present invention, the same mask can be used for the doping well ion implantation process and the amorphous germanium process. In the strain 矽 transistor process of the present invention, the dopant in the doping well can be simultaneously induced and activated in a single tempering step and a strain is formed in the substrate. [Embodiment] Please refer to FIG. 1 to 5, FIG. 1 to FIG. 5 are schematic views showing a process for fabricating a strained germanium crystal according to a first preferred embodiment of the present invention. As shown in FIG. 1, a substrate 10 such as a germanium substrate or an insulating layer is first provided. An overlying stone (SOI) substrate or the like, and a surface of the substrate 10 defines a first transistor region 12 and a second transistor region 14, followed by an isolation process such as a shallow trench isolation structure (STI), for example, using an etching step. Etching the trenches on the substrate 10, using a chemical deposition process, depositing a layer of oxide to fill the trenches and covering the surface of the substrate, and then smoothing the oxides by chemical mechanical polishing to the substrate 10. The insulators of the shallow trench isolation structure 16 and the like are used to isolate the transistor regions 12, 14, wherein the first transistor region 12 is used to form an active region of the first conductivity type sinusoidal crystal. The transistor in the transistor region 12 is in a first conductivity type, such as an N-type MOS transistor; the second transistor region 14 is an active region of a transistor used to form a second conductivity type, that is, The transistor disposed in the transistor region 14 of the second 8 201005832 is of a second conductivity type, such as a P-type MOS transistor. The following embodiment will use the transistor on the first transistor region 12 as an N-type, second. The transistor on the transistor region 14 is exemplified by a P-type. Next, an amorphous austenitic process is performed, for example, a blanket single ion implantation process, using gas (xenon; Xe), argon (argon). ; Ar) or 锗 (germanium; Ge) plasma, the first transistor 12 region 12 and the second transistor region 14 are simultaneously implanted in a comprehensive manner. Among them, when the single ion implantation process is performed, the concentration of cesium ions, argon ions or cesium ions used is greater than 1 Ε 14 and the energy thereof is greater than 10 keV. Then, as shown in Fig. 2, a first stressor layer 18 and a second stressor layer 20 are formed on the first transistor region 12 and the second transistor region 14 of the substrate 10, respectively. The first stressor layer 18 includes a first yttrium oxide layer 22 and a first tantalum nitride layer 24, wherein the first layer of tantalum nitride layer 24 has a tensile stress and is located on the first layer of silicon oxide layer 22, and The function of an oxygen layer 22 is to act as an I-stop layer or buffer layer to prevent excessive stress in the first layer of nitride layer 24, resulting in structural damage of the substrate 10. The first oxygen layer 22 can be selectively formed according to different product requirements. That is, the first stressor layer 18 may also include only the first tantalum nitride layer 24. Similarly, the second stressor layer 20 includes a fourth silicon oxide layer 26 and a second tantalum nitride layer 28, wherein the second tantalum nitride layer 28 has a compressive stress. The function of the fourth silicon oxide layer 26 is also to avoid excessive stress in the second tantalum nitride layer 28, resulting in structural damage of the substrate 10 9 201005832 or as an etch stop layer of the second tantalum nitride layer 28, again, as The first silicon oxide layer 22 and the fourth silicon oxide layer 26 may also be selectively formed. In addition, the first tantalum nitride layer 24 and the second tantalum nitride layer 28 may be formed by, for example, forming a grounded oxygen layer on the substrate 10 and then integrally forming a first tantalum nitride layer having a tensile stress. 24, further removing the first tantalum nitride layer 24 on the second transistor region 14 via a lithography and etching step, since the foregoing silicon oxide layer is utilized as a process for removing the first tantalum nitride layer 24 φ etching the stop layer to etch a portion of the germanium oxide layer on the second transistor region 14, thereby forming an unetched first germanium oxide layer 22 and a second transistor region 14 on the first transistor region 12. An etched second silicon oxide layer. Next, a third silicon oxide layer is formed on the first tantalum nitride layer 24 and the second tantalum layer as another etching stop layer, and then the second tantalum nitride layer 28 having compressive stress is formed to be completely covered. a tantalum nitride layer 24 and a third tantalum oxide layer on the second tantalum oxide layer, after which the second tantalum nitride layer 28 on the first tantalum nitride layer 24 is removed by a lithography, etching step, and The second silicon oxide layer and the third silicon oxide layer remaining on the second transistor φ region 14 are both of the same material, so the second silicon oxide layer and the third silicon oxide layer are regarded as the second layer. A fourth silicon oxide layer 26. It is added that the second tantalum nitride layer 28 on the first tantalum nitride layer 24 may not be removed, that is, the third silicon oxide layer described in the foregoing step is not formed, directly in the first The second tantalum nitride layer 28 may be formed on the tantalum nitride layer 24 and the second tantalum oxide layer, and the second tantalum nitride layer 28 covers the first tantalum nitride layer 24 and the second tantalum oxide layer simultaneously. Furthermore, the thickness of the first tantalum nitride layer 24 should be designed such that the total 10 201005832 stress experienced by the first transistor region 12 is the stress provided by the first nitride layer 24. In addition, the first silicon oxide layer 22 and the first tantalum nitride layer 24 may be formed in the same chamber; and the fourth silicon oxide layer 26 and the second tantalum nitride layer 28 may be formed in the same chamber, That is, it is possible to avoid the situation in which the substrate needs to leave the vacuum state due to the transformation chamber. In addition, the adjustment of the stress can be achieved by matching the deposition process parameters or by surface treatment such as ion implantation, tempering, ultraviolet light (UV) ^, etc., which are familiar to those skilled in the art and those skilled in the art. Do not repeat them. As shown in FIG. 3, a tempering process is performed while the germanium atoms in the surface layer of the substrate 10 are rearranged according to the stretching/compression directions provided by the first stress layer 18 and the second stress layer 20 to form the first transistor region. A first strained layer 30 and a second strained layer 32 are formed in the substrate 10 below the second transistor region 14, respectively. Thus, a stress ❿ memorization technique (SMT) is used to form a first strain enthalpy layer 30 having a tensile stress and a second strain enthalpy layer 32 having a compressive stress, respectively, in the substrate 10. Next, the first stressor layer 18 and the second stressor layer 20 are removed and a patterned photoresist 34 is formed, exposing the first transistor region 12 and a portion of the shallow trench isolation structure 16, followed by doping well ions The implantation process utilizes a P-type dopant to form a P-type doping well 36 in the substrate 10 within the first transistor region 12. 11 201005832 is provided, after the removal of the photoresist 34, the formation of the first resistance 38 to expose the war pattern from the structure 16, followed by the two-= body region 14 and part of the diffuser trench in the second transistor region 14 The ion implantation process forms an N-type doping well 4 in the substrate 10 including the mass change. As shown in Figure 5, the high-temperature thermal process, such as the trending and activation of the human I process, the 松生松井36 and the Ν-type doping well 40, are in the same place, respectively? The type_well 3~Ν type doping well 4Q is formed on the upper side, 44 and the corresponding N type source/(tetra) doped region 46 and the P type source di/dot doped region 48. $ μ· . - ηη ', so far, the CM 晶体 crystal of the present invention having a strained ruthenium layer, such as the Lei Ri Shi electro-electricity solar body 50 and p-type transistor 52, has been completed. ~ Please refer to FIG. 6 to FIG. 9 , and FIG. 6 to FIG. 9 are schematic diagrams showing the process of fabricating the transistor according to the first embodiment of the present invention. The parts having the same force month b are still represented by the same symbols as those of the first preferred embodiment. "As shown in Fig. 6, first, a substrate 1 is provided, which has a first = germanium region 12 and a second transistor region 14, and then a trench % structure is formed in the substrate 1 (STI). The insulation of the 16th isolating the transistor region η, wherein the process of the shallow trench isolation structure 16 has been described in the first embodiment, and will not be described herein. In addition, the first transistor region 12 is used for Forming an active region of the first conductivity type of transistor, that is, the transistor disposed in the first "' transistor region 12 is a first conductivity type, such as 12 201005832 MOS transistor; second transistor region 14 is a transistor for forming a second conductivity type, such as a P-type MOS transistor. Next, a patterned photoresist 34 is formed to expose the first transistor region 12 and a portion of the shallow trench isolation structure 16, followed by In a first amorphous deuteration process, the first transistor region 12 is implanted by an ion implantation process, wherein ions used in the ion implantation include barium ions, argon ions, and strontium ions, and then, followed by a photoresist 34 As a mask, performing a first doping well ion implantation process For example, a P-type dopant is utilized to form a P-type doping well 36 in the substrate 10 within the first transistor region 12. According to another preferred embodiment of the present invention, the first amorphous deuteration process and the first The process sequence of the doping well ion implantation process can be exchanged. For example, the first doping well ion implantation process is first performed to form the P-type doping well 36, and then the first amorphous deuteration process is performed, but both are patterned. The photoresist 34 acts as a mask. As shown in Fig. 7, the photoresist 34 is removed, and a patterned photoresist 38 is formed to expose the second transistor region 14 and a portion of the shallow trench isolation structure 16, and then Performing a second amorphous deuteration process, implanting the second transistor region 14 by an ion implantation process. Similarly, ions used in ion implantation include helium ions, argon ions, and erbium ions, and the two amorphous portions The concentration of helium ions, argon ions or helium used in the deuteration process is greater than 1E14, respectively, and the energy is greater than lOKev. Then, using the patterned photoresist 38 as a mask, a second doping well ion implantation process is performed. , for example, using N-type dopants in the second 13 201005832 The base of the crystal region... is formed... The other of the inventions is connected to the crucible. According to a preferred embodiment of the trolley, the same amorphous austenitic system based on both the private and the second implanted ion implants uses the patterned photoresist 38 as a mask. The order of the king can be exchanged, but the second best 眚^ of the present electric power is slightly changed, that is, the steps of e 1 1 6 @ to the seventh figure are formed before the first ^: the best embodiment·· first in the light 4 The non-planarity is carried out in the non-tantalum crystal region 12 and the second transistor region 14 in a full-time non-daily deuteration process, and the king 34 forms a photoresist process in the first electron crystal (four). The doping well 36 is connected to the first doping 7^^ 34, and another photoresist 38 is formed, and the second doping and private are performed in the second removing photoresist well ion implantation potential 浐m ” day zone 14 To form an N-type doping well 4〇, and the subsequent step of the third example is complemented by the second preferred embodiment. - d is applied φ: Figure 8 shows the first electro-optic crystal region on the substrate 1〇 14 respectively, Bing Shi, Sex 2 Xing 20. The P-stress layer 18 and the second stress layer μ-force layer 18 comprise a - 矽-oxygen layer 22 and - a first nitriding m 2 of the first - nitrite The layer 24 has a tensile stress and is located at the selectivity = 2. According to different product requirements, the first layer of the oxidized layer 22 is selected: the same, the second layer of stress 20 contains a fourth second oxygen Layer - the layer 28, the fourth layer 28 of the towel has a crushing stress. Further, like the first layer of the oleic oxygen layer 22, the fourth layer of the oxylate layer can also be selectively formed by 14 201005832. The first oxygen layer 22, the fourth silicon oxide layer 26, the first tantalum nitride layer 24, and the second tantalum nitride layer 28 are formed in the same manner as in the first preferred embodiment, and will not be described herein. Figure 9 shows a high A thermal process, such as a tempering process, to entangle and activate dopants in the P-type well 36 and the N-type well 40, and simultaneously under the transistor region 12 and the second transistor region 14 In the base @ the bottom 10, a first strained layer 30 and a second strained layer 32 are respectively formed. Then, after removing the first stress layer 18 and the second stress layer 20, respectively, respectively, the P-type doping well 36 The gates 42 and 44 and the N-type source/drain doping region 46 and the P-type source/drain doping region 48 are formed on the N-type doping well 40. Thus, the CMOS having the strained germanium layer of the present invention A transistor such as an N-type transistor 50 and a P-type transistor 52 has been completed. Fig. 10a is a flow chart of the steps of the first preferred embodiment of the present invention, and Fig. 10b is a view of the present invention. A flow chart of the steps of the second preferred embodiment. Figure 10c is a flow chart showing the steps of the third preferred embodiment of the present invention. The foregoing description, as well as the drawings of Figures 10a, 10b and 10c, show the present invention. The first embodiment, the second embodiment and the third embodiment are characterized in that the amorphous germanium process is implemented after the shallow trench isolation structure is completed, and Before the fabrication of the transistor, the strain enthalpy layer can be fully formed on the substrate of the transistor region 15 201005832. The second embodiment of the crystal is advantageous in that the first-non-case light is "high concentration ion". The planting process is used when the same process is used: the first process and the second high-concentration ionization _丼==Fig.; the photoresist is used. Furthermore, the penetration and the activity use π = strain (4) and - The second strain of the dream layer tempering process 'and can be in the same - empty state. Again, as shown in Figure I0b, if it will be replaced:: the order of the amorphous process and the integration process The well-distributed h*-electro-crystal hybrid β (four) row amorphous (four) process and the riding doping sequence exchange 'can change the cost of the invention of the electric circuit. "Different area ut, as shown in the figure, f first provides a substrate 110 comprising a transistor ^ and then forming a shallow trench isolation structure (STI) 116 in the substrate η〇, the edge surrounding the transistor region 112, shallow The trench isolation structure (STI) 116 is as described in the first preferred embodiment and will not be described herein. The main body region 112 can be used to form a region of a specific conductivity type of transistor, that is, a transistor disposed in the transistor region η] can be 'conductive type, for example: p-type or Ν-type . 16 201005832 Next, an amorphous deuteration process is performed, for example, in a comprehensive single ion implantation process, using a helium, argon or helium ion, etc., to fully implant the electromorphic region 112. Wherein, when the single ion implantation process is performed, the concentrations of cesium ions, argon ions or cesium ions used are respectively greater than 1E14, and the energy thereof is greater than lOKev. As shown in FIG. 12, a stressor layer 118 is formed on the transistor region 112 of the substrate 110. The stressor layer 118 may include a germanium oxide layer 122 and a tantalum nitride layer 124. If the first conductivity type is N-type, the tantalum nitride layer 124 is adjusted to have a tensile stress, and if the second conductivity type is a P-type, the tantalum nitride layer 124 is adjusted to have a compressive stress, wherein the stress is adjusted. It can be achieved by matching the deposition process parameters or by surface treatment such as ion implantation, tempering, ultraviolet light (UV), etc., which are well known to those skilled in the art and those of ordinary knowledge, and therefore will not be described in detail. According to another preferred embodiment of the present invention, the stress layer 118 ® may also include only the tantalum nitride layer 124, and the silicon oxide layer 122 may be selectively formed. Furthermore, the stone oxide layer 122 and the fossil layer 124 can be formed by successive deposition in the same chamber. As shown in FIG. 13, a tempering process is performed, and at the same time, the Shixia atoms are rearranged according to the stretching/compression direction provided by the stress layer 118 to form a strained layer 130 in the substrate 110 below the transistor region 112. . So far, a strain enthalpy layer 17 is formed in the substrate 110 by using the stress memory technology (SMT). 201005832 130 It should be noted that if the first conductivity type is strain strain A35 strain; if the second conductivity type state is P The type is strain (four) 13 〇 is the compressive strain. The second layer is implanted in the transistor region 112β' followed by doping ion implantation, and the doped well 136 is doped with a germanium or p-type dopant in the crystal region 112. Subsequently, a high temperature thermal process, such as a tempering process, is performed to effect and activate the dopant in the doped well 136. A gate 142 and a source/drain doping region 146 are formed on 1^^. The MOS transistor 15 having the strained germanium layer of the present invention has been completed.曰 ★ Please refer to Figs. 14 to 16 , and Figs. 14 to 16 are schematic views showing the process of fabricating a transistor according to a preferred embodiment of the present invention. Elements having the same force are still indicated by the same reference numerals as the fourth preferred embodiment. ❿ ^ As shown in Fig. 14, first, a substrate 110 is provided with a transistor region U2, and then a shallow trench isolation structure (STI) 116 is formed in the substrate 110, and a germanium edge surrounds the transistor region 112, wherein the substrate The crystal region 112 can be used to form an active region of a transistor of a particular conductivity type, that is, the transistor disposed within the transistor region m is a first conductivity type transistor, such as PM〇S or NMOS. 201005832 Then, a patterned photoresist 134 is formed in the transistor region 112, followed by an amorphous deuteration process to implant the transistor region 112 in an ion implantation process, wherein the ions used in the ion implantation comprise strontium ions, For argon ions, strontium ions, etc., the concentrations of cesium ions, argon ions or cesium ions used are greater than 1E14, respectively, and the energy is greater than lOKev. Subsequently, the doping well ion implantation process is continued with the photoresist 134 as a mask, and a doping well 136 is formed in the substrate 110 in the transistor region 112 by using the dopant. The notable φ is: if the first The conductive type transistor is an NMOS, and the ion implanted by the high concentration ion implantation is P type; if the second conductivity type transistor is a PMOS, the ion implanted by the high concentration ion implantation is N type. According to another preferred embodiment of the present invention, the process sequence of the amorphous dimination process and the high concentration ion implantation process may be exchanged, for example, the doping well ion implantation process is first performed to form the doping well 136, and then The amorphous deuteration process, but with the patterned photoresist 134 as a mask. The step of Fig. 14 of the fifth preferred embodiment of the present invention can be changed to a sixth preferred embodiment if it is slightly changed. First, before the photoresist 134 is formed, it is comprehensive before the transistor region 112. The amorphous deuteration process is performed, and then the photoresist 134 is formed to perform a well-well ion implantation process in the transistor region 112 to form the doping well 136. The subsequent steps of the sixth preferred embodiment are the same as those of the fifth preferred embodiment. As shown in FIG. 15, a 19 201005832 f24 force layer is formed on the transistor region 112 of the substrate 110, and the stress layer 118 includes a germanium oxide layer 122 and a tantalum nitride layer (4). The It 1 electrical type is N3^j. The formation of the stressor layer can be carried out by adjusting the nitride layer 124 to have a p-type of the shape of the vaporization (four) 124. Furthermore, = 夕124 ’, and Shixi Oxygen 122 can selectively continually sink into θ 22 and the gas cut layer 124 can utilize the same ❹
帛6圖所不，進行—回火製程，㈣原子依照應力 ^所提ί、的伸張’壓縮方向重新排列，以於電晶體區⑴ 、 τ 元成—應變矽層130，並同時趨入及帛6Fig. No, the tempering process is carried out, and (4) the atoms are rearranged according to the stretching direction of the stress, so that the transistor region (1) and the τ element become the strained layer 130, and at the same time
〉舌化摻雜井136内之换@ E , ^ L 1之掺質。至此完成利用應力記憶技術在 土 f U〇内形成—應變石夕層130,然後移除應力層118。需 兒明的疋若第—導電型態為\型則應變石夕層13〇為伸 ^應變，若第二導電型態為P型則應變矽層130為壓縮應 I接著，在摻雜井130上形成一閘極142和一源極/汲極 接雜區146。至此’本發明之具有應變石夕層的MOS電晶體 150已經完成。 第17a圖繪不的是本發明第四較佳實施例之步驟的流 圖’第17b圖綠示的是本發明第五較佳實施例之步驟流 &圖’第17e ®♦示的是本發明第六較佳實施例之步驟流 程圖。 201005832 由第17a圖、第17b、第17c圖以及上述說明可知，本 發明之第四實施例、第五實施例和第六實施例的特徵在於 非晶矽製程實施於淺溝渠隔離結構完成之後，及開始製作 電晶體之前進行，如此一來，可以在電晶體區的基底上全 面形成應變矽層。 此外，本發明之第五實施例的優點在於在進行非晶石夕 化製程和高濃度離子佈植製程時係使用同一個圖案化光 阻。再者’趨入及活化摻雜井之摻質以及形成應變矽層係 使用同一個回火製程，並且可在同一個腔室進行，因此不 需要離開真空狀態。並且，如第17b圖所示，若將其中的 #晶矽製程和摻雜井佈植製程之順序交換’即可變化成本 發明之另一應變矽電晶體之製程步驟。 φ 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 園所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第5圖為本發明第一較佳實施例之製作電晶體之 製程示意圖。 第ό圖至第9圖為本發明第二較佳實施例之製作電晶體之 201005832 製程示意圖。 第10a圖繪示的是本發明第一較佳實施例之步驟的流程 圖。 第10b圖繪示的是本發明第二較佳實施例之步驟流程圖。 第10c圖繪示的是本發明第三較佳實施例之步驟流程圖。 第11圖至第13圖為本發明第四較佳實施例之製作電晶體 之製程示意圖。 q 第14圖至第16圖為本發明第五較佳實施例之製作電晶體 之製程示意圖。 第17a圖繪示的是本發明第四較佳實施例之步驟的流程 圖。 第17b圖繪示的是本發明第五較佳實施例之步驟流程圖。 第17c圖繪示的是本發明第六較佳實施例之步驟流程圖。 【主要元件符號說明 ] 10 基底 12 第一電晶體區 14 第二電晶體區 16 淺溝渠隔離結構 18 第一應力層 20 第二應力層 22 第一矽氧層 24 第一氮化矽層 26 第四矽氧層 28 第二氮化矽層 30 第一應變矽層 32 第二應變矽層 34 光阻 36 P型摻雜井 22 201005832 38 光阻 40 Ν型摻雜井 42 閘.極 44 閘極 46 N型源極/汲極摻雜48 Ρ型源極/汲極摻雜區 區 50 N型電晶體 52 Ρ型電晶體 110 基底 112 電晶體區 16 淺溝渠隔離結構 118 第一應力層 〇 122 第一矽氧層 124 第一氮化矽層 130 第一應變ί夕層 134 光阻 136 摻雜井 142 閘極 146 源極/汲極摻雜區 150 電晶體 參 23〉The doping of @E , ^ L 1 in the doped well 136. Thus, the stress-memory technique is used to form the strained layer 130 in the soil f U〇, and then the stress layer 118 is removed. If the first conductivity type is \ type, then the strained stone layer 13〇 is the extension strain. If the second conductivity type is P type, the strained layer 130 is compressed and then followed by the doping well. A gate 142 and a source/drain junction region 146 are formed on 130. Up to this point, the MOS transistor 150 having the strained layer of the present invention has been completed. Figure 17a is a flow chart showing the steps of the fourth preferred embodiment of the present invention. Figure 17b is a flow chart showing the flow of the fifth preferred embodiment of the present invention. Figure 17e A flow chart of the steps of the sixth preferred embodiment of the present invention. 201005832 It can be seen from the 17th, 17b, 17c and the above description that the fourth embodiment, the fifth embodiment and the sixth embodiment of the present invention are characterized in that the amorphous germanium process is implemented after the shallow trench isolation structure is completed. And before the fabrication of the transistor is started, so that the strain enthalpy layer can be formed entirely on the substrate of the transistor region. Further, the fifth embodiment of the present invention is advantageous in that the same patterned photoresist is used in the process of performing the amorphous austenite process and the high-concentration ion implantation process. Furthermore, the doping and activation of the doping well and the formation of the strain enthalpy use the same tempering process and can be performed in the same chamber, so there is no need to leave the vacuum state. Moreover, as shown in Fig. 17b, if the order of the # wafer process and the doping process is exchanged, the process of another strain cell of the invention can be changed. The above is only the preferred embodiment of the present invention, and all changes and modifications made by the patent application of the present invention are within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 to 5 are schematic views showing a process for fabricating a transistor according to a first preferred embodiment of the present invention. FIG. 9 to FIG. 9 are schematic diagrams showing a process of manufacturing a transistor of 201005832 according to a second preferred embodiment of the present invention. Figure 10a is a flow chart showing the steps of the first preferred embodiment of the present invention. Figure 10b is a flow chart showing the steps of the second preferred embodiment of the present invention. Figure 10c is a flow chart showing the steps of the third preferred embodiment of the present invention. 11 to 13 are schematic views showing the process of fabricating a transistor according to a fourth preferred embodiment of the present invention. Fig. 14 to Fig. 16 are schematic views showing the process of fabricating a transistor according to a fifth preferred embodiment of the present invention. Fig. 17a is a flow chart showing the steps of the fourth preferred embodiment of the present invention. Figure 17b is a flow chart showing the steps of the fifth preferred embodiment of the present invention. Figure 17c is a flow chart showing the steps of the sixth preferred embodiment of the present invention. [Main component symbol description] 10 substrate 12 first transistor region 14 second transistor region 16 shallow trench isolation structure 18 first stress layer 20 second stress layer 22 first silicon oxide layer 24 first tantalum nitride layer 26 Tetra-oxide layer 28 second tantalum layer 30 first strain layer 32 second strain layer 34 photoresist 36 P-type doping well 22 201005832 38 photoresist 40 掺杂 type doping well 42 gate. pole 44 gate 46 N-type source/drain-doped 48 Ρ-type source/drain-doped region 50 N-type transistor 52 Ρ-type transistor 110 substrate 112 transistor region 16 shallow trench isolation structure 118 first stress layer 〇122 An oxygen layer 124 first tantalum nitride layer 130 first strain layer 134 photoresist 136 doping well 142 gate 146 source/drain doping region 150 transistor reference 23