201003075 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體，特 ^ 一半導體晶圓上的積體電別係關於用於對形成於 ⑽Μ探針卡。 【先前技術】 現代半導體的製造包含了複 影、物質沈積與蝕刻，以在一片。。^驟，其具有微 形成複數個個別的半導體裝置或：獨的半導體矽晶圓上 製造常用的半導體晶圓的直徑可電路晶片。目前所 其中直徑十二吋的晶圓為—種常貝疋吋或六吋以上， 於上述晶圓上的某些個別的晶片，的^寸。然而，形成 導體製造的製程中可能出現的“可能因為在複雜的半 陷。在晶圓切割而將上述積體：：或問題而具有-些缺 鬥八銼夕乂八料V•紅、兔路晶片自上述半導體晶 困分狀刖，f對㈣㈣片料電 測試並同時在一既定期間對直造.私Αχ 丁/、延仃激發（例如晶圓級燒入 測試）。這些測試通常可能包含布局與線路㈣比㈣⑽ versus schematic ; LVS)的確認、靜態電流測試（mDq testing)等等。從每個晶片或受測裝置（deviceunder ; DUT)所產生的結果電性訊號則被具有測試電路系統的自 動測試設備（automatic test equipment; ATE)所捕捉與分 析’以判定一晶片是否具有缺陷。 為了幫助晶圓級燒入測試(burn-in testing)與同時捕 捉來自晶圓上的多個晶片的電性訊號，是使用習知的 DUT板或探針+。探針卡在本質上為印刷電路|^nted 0503-A33786T\VF/ciwwang 4 201003075 circuit board ; PCB)，其包含複數個金屬電 與形成於上述晶圓上的上述半導妒a 、— ·十用以 電性接點（contact)或接頭（terminal)—。每—^數個對應的 個接點或接頭，每-個接點或接頭必具有複數 存取。因此，-般的晶圓級測試於測試的 、而女運仃遠超過 晶片接點或接頭與錢賊電路“之間的電性 因此，為了實施精確的晶圓級測試，精確地將 針卡接點與上述晶圓上的晶片接點對準、以及形成確； 的電性連接是很重要的。探針卡通常是安穿於上二201003075 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor, and an integrated circuit on a semiconductor wafer is used for pairing a (10) probe card. [Prior Art] The manufacture of modern semiconductors involves replication, material deposition and etching in one piece. . In other words, it has micro-formed individual semiconductor devices or a diametrically configurable semiconductor wafer on a semiconductor wafer. At present, the wafer with a diameter of 12 turns is a type of constant-shell or six-inch wafer, and some individual wafers on the above wafers. However, the process of forming a conductor can occur "may be due to the complex half-sink. In the wafer cutting, the above-mentioned integrated body:: or the problem has - some lack of fighting, eight 锉 乂 料 V V V, red rabbit The circuit chip is trapped from the above-mentioned semiconductor crystal, and the f-to-fourth (four) chip material is electrically tested and simultaneously subjected to direct fabrication, such as wafer-level burn-in test (for example, wafer level burn-in test). Include layout and line (4) ratio (4) (10) versus schematic; LVS) confirmation, quiescent current test (mDq testing), etc. The resulting electrical signal from each chip or device under test (DUT) is tested with a circuit The system's automatic test equipment (ATE) captures and analyzes 'to determine if a wafer has defects. To help wafer-level burn-in testing and simultaneously capture multiple wafers from the wafer. The electrical signal is a conventional DUT board or probe +. The probe card is essentially a printed circuit |^nted 0503-A33786T\VF/ciwwang 4 201003075 circuit board; PCB), which contains a plurality of The electric conductor is formed on the above-mentioned wafer with the above-mentioned semi-conducting 妒a, -10 for electrical contacts or terminals - each of a plurality of corresponding contacts or joints, each - The contacts or connectors must have multiple accesses. Therefore, the general wafer level test is performed on the test, and the female machine far exceeds the electrical connection between the wafer contacts or the connector and the money thief circuit. Therefore, in order to implement the accuracy Wafer-level testing, it is important to accurately align the pin-card contacts with the wafer contacts on the wafer and to form an electrical connection. The probe card is usually worn on the top two
測試設備中，並作為上述晶片或受測裝置與上述== 試設備的碰觸之間的界面。 動/、J 隨著半導體製程技術持續進行發展，半 的晶片的電性測試接觸塾之間、旦曰曰3 減。如第1圖所示，其是例示^ 次世代的半導體晶片或受測裝置，測試塾間距令人滿： 米或更小。上述受測裝置測試塾110的二 的：；、、'由連接線130而連接之上述受測裝置上 的石夕貝牙油rough silicon via; TSV)接觸塾120之 二==中可為17微米。然而，現存的測試探： 卡W又口十所考受生的技術拖历百I贫益 文何瓶頌疋其無法支援如此小的測試墊 間距。 土 已知的探針卡具有—多層㈣線基底或空間 (SpaWf_er)，其是置於結合於受 ^ 整之測試印刷電路板與探糊如指狀探針(fingers) = 狀探針(職伽）等等）之間。上述空間變換器是在上述印 0503 "A33786TWF/dwwarig 201003075 刷電路板與探針之間傳遞、^ ^ 述空間變換器在其—側：與電源訊號。上 amv . Rr Λ、m 有—球間陣列（bali挪 一 C4， 連I线’其是與上勒m㈣電路板與 的接 Si 媒：ed CGllaPSe Ghlp eQnneCtiGn)内連線系統上 婵^^； ’而上述接點則是與上述測試探真的上半部 _ 丄 —、的二間交換斋的最小的C4接觸墊 為：150微米’而無法符合支援 :::…米或更小的C4接觸塾節距分佈喊 呈右’業界需要改良的測試探針卡空間變換器，立 具有較微細的C4接觸墊間距。 、 [發明内容】 制i = h《供—種半導體測試探針卡^變換器的 = 以縮小—接觸測試墊的節距分佈。在一實施 去匕3 .棱供一空間變換器，其底部是一 八邛具有複數個第一接觸測試墊於一侧以 置的電性測試，在上述第-接觸測試塾:::： 層於上述基底上；沈積一第一介電層於上“ 上，形成稷數個第二接觸測試墊， 之間定義有異於上述第—節距分佈的一第二節藝 以及形成複數個重佈引腳於上述第一介電層上 述第一接觸測試墊電性連接 夺上 -實施例中，上、弟-接觸測試墊。在 、 上以弟一接觸測試墊是嵌於或封於—第二 0503-A3j786TWF/dwwang 201003075 保護層t。 在另一實施例t，一種半導 器的製造方法包含：提供—空間變換哭；：：：間變換 與複數個第Μ卜基底 -目"士罢Μ 述基地的—第—侧以執杆為 繼的電性測試，在上述第一 = 丁又 分佈，上述第-測試接點具有複數:^: 層於上述基底的上述第-側上；沈積—第一：：：：面 述金屬接地平面層上；圖形化上述第-介雷層二層：ΐ f個凹部於其令；以-導體金屬填入上述；部的 :;二數個重佈引腳；以及形成複數個第二測 4接』上34弟二測試接點之間定義有小於上述第 Γ刀知的—第二節距分佈，上述第二測試接點的至少一 ㈣腳電性連接至上述第—測試接點 一實施财，上述方法更包含以-保 k層舲上述弟一接觸測試墊封入其中的一步驟。 _在另一貫施例中，一種半導體測試探針卡空間變換 :的，造方法包含··提供一空間變換器，其具有一基底 ㈣數個第-接觸測試墊於—侧以執行受測裝置的電性 測試，在上述第-接觸測試墊之間定義有—第—節距分 佈；形成複數個第二接觸測試墊於上述基底上，上述第 二^妾觸測試墊之間定義有異於上述第—節距分佈的一第 一即距分佈；以及形成複數個重佈引腳，以將上述第— 接觸測試墊電性連接至上述第二接觸測試塾。在一實施 例中，上述方法更包含以-倾層將上述第—接觸測試 〇503-A33786TWF/dwwang 7 201003075 墊與上述第二接觸測試墊封人其中。上述方法較 ㈣成貫穿上述保護層的複數個導體井狀通道，以= ^第二接觸測試墊延伸至上述保護層的―暴露表面\ 。稷數個载切針形成電性接觸，心進 晶片的晶圓級測試。 '版电路 根據本發明的另—觀點，具有微細接觸測試 分佈的一完成製造的半導體丨 p巨 入.甘产* %w切木針卡空間變換器包 :觸二：？、具有—第—邊與一第二邊；複數個第- 中：二複：述第一邊與上述第二邊的上述基底 ^ ’旻數個弟一接觸測試墊於上述第一邊上。一 =實:晴，上述第二接觸測試墊的節距分佈小於上 述弟-接觸測試塾的節距分佈。在另—實施例中，上、丄、 空間變換器具有複數個重佈引腳，其電性連接至少一： 上述第二接觸測試墊盥上 二 又另-實崎，上述觸測試塾。在 墊的一保護層。 …有-盖上述弟-接觸測試 哭'的穿迕方法'1:中·半導體測試探針卡空間變換 :供广一接觸測試塾的節距分佈，包含： 、-^ ’上述基底的上表面具有複數個第-接觸 面受測裝置的電性測試、與複數個金屬平 =在、上述弟一接觸測試塾之間$義有—第 、，，亡述金屬平面分別環繞每個上述第—接觸 : f與每個上述第—接觸測試墊電性隔離，上述全^平面 :=為接地平面;沈積-第-介電層 的上表面上，並暴露出上述第—測婦；形成複數個重 〇503-A33786TWF/dwwang 8 201003075 佈引腳於上述第一介電層上並分別電性連接上述第一接 觸測試塾，每個上述重佈引腳之位於上述第 的-端點之間，定義有異於上述 距分佈的心一 節距分佈。 乐一 【實施方式】 特徵、和優點能更 並配合所附圖式， 為讓本發明之上述和其他目的 明顯易懂，下文特舉出較佳實施例 作詳細說明如下： 第2圖所顯示的—你丨丨千ώΑ ^ ’、的貫施例是已藉由本發明提 出的方法來修改的一可從古 」仗市面上取得的測試探針卡 200 ’其具有空間變換器24〇，处 &間變換益' 240具有微細 間距的C4接觸墊陣列。測試据上 彳成衣針卡200可以是任何適當 的可從市面上取得的測試探針卡，例如但不限於來自 Went雨th Laboratories，Inc. 〇f Βγ〇〇μ^ ct 的呈有針 狀探針的Cobra®卡、或是可從〜啊咖⑧。f 腑e, \+ CA取得的具有MkroSpdng®針狀探針的探針卡。上述探 針卡較好為選擇測試針狀探針的間隔或間距可達5 〇微米 或更小者，以與受測裝置上之具有相同間隔或間距的測 試墊110 (請參考第1圖）媒合。 請參考第2圖，測試探針卡200具有一測試印刷電 路板210，其具有一上表面212與一下表面214、黏著於 其上的一安裝環（mounting ring)220、受到安裝環220支 撐的一測試探針頭260、與一空間變換器240。在一實施 例中’測試探針頭260具有複數個可從市面上取得的測 0503-A33786TWF/dwwang 9 201003075 試採針230,剛試探針23〇可以是任何適當的型號或架構 例如針狀或鎖狀，上述型號或架構在一實施例中可提供 一適當的節距分佈，以支援50微米或更小的測試墊間 距。每個劍試探針230各具有一下端點，上述下端點的 架構或排列是用以與將要進行測試的一受測裝置250上 的一對應的測試墊252媒合。測試探針23〇較好為具有 一間距Pn’間延h是與受測裝置250上的測試墊252的 間距Ρτ媒合。在一例示的實施例中，間距PT與PN的值 可以是約50微米。 明無續參考第2圖，在一可能的實施例中，每個測 試探針230可各具有一上半部234，其是由測試探針頭 260内的一穿透式的中間探針支撐器232所支撐。穿透式 的中間探針支撐器232的材質較好為非導體材料，例如 為ΛΚ U女邁半力膠片（p〇lyamide nlylar)。每個測試探針230 的上半部234可延伸至最上端部分的一放大的接觸端236 為止’以與空間變換器240上的對應的接點媒合。在某 些實施例中’測試探針頭260可更包含一下基板226、一 上基板222、與一間隔物224，如第2圖所示，測試探針 230的延伸是受到下基板226的引導並穿過下基板226， 上基板222的架構是用以收納探針的上半部234與放大 的接觸端236 ’間隔物224是介於下基板226與上基板 222之間。放大的接觸端236的延伸較好為穿透上基板 222，以與空間變換器240上的接觸墊連接。本發明的適 用亚不限於此處所敘述的測試探針頭26〇的架構或特 敏’亦可以提供、使用其他任何架構的測試探針23〇的 0503- A33786T WF/dw wang 10 201003075 支撐結構。 在某些實施例中，空間變換器240的底部可以是— 多層有機（multi-]ayered organic ; MLO)或多層陶究 (multi-layered ceramic)内連線基底245。空間變換器24〇 具有一 C4侧400與一相反面的球閘陣列侧4〇2，侧 )〇〇具有一下表面24]，下表面241具有—微細間距的二 觸測試墊陣列242,用以與測試探針頭260上的放大的接 觸端236咬合與媒合；相反面的球閘陣列側4〇2具有一 上表面243,上表面243具有一球間陣列，用以與測試= 刷電路板210上的對應的接觸墊2U媒合。上述球間陣 列可具有一間距Ρβ，其定義為球狀體之間的間距， 球狀體的材質可以是軟銲料或其他適當的材料。 a 接下來請參考第3〜14圖，依序敛述本發明所提出的 修改一現有可從市面上取得的測試探針卡綱的方法的 製造流程的第一實施例，以製造具有微細間距的C 4接觸 塾陣列的一空間變換器赛與第2 = 間變換器240安装於_、、p,丨_德厶± "丁 <將工 比，第3 : 台時的正常操作位置相 弟3〜M圖所不的空間變換器24〇 的反向位置。除非另右# _ 疋 >、八相反 物質、”㈣二 以下所敘述的各種微影、 物貝4、與物貝移除的製程均 半導體製造的已知製程。 貝用於从機包或 請參考第3圖，提供—介 於一内連線基底245上的其具有形成 •在某些實施例中，内 =^C4接觸塾陣列 機或多層陶甍基底。在5可以是一多層有 K也歹中，現存C4接觸塾陣歹 0503-A33 786TWF/d wwang 201003075 ;1〇二：觸墊之間具有約15〇微米的一原始節距分佈 上以超音波清潔下表面241與上表面243，以使 上述表，處於可接納導體材料的狀態。 導體ΐΓο \圖所不的下個步驟巾，藉由濺鍍法將一金屬 = 在一實施例中為銅-沈積在相反面的球 閑陣列侧402上與空間變換器240的上表面243上，^ 2個導體通道3G1相互電性連接或短路。在某此實施 = 傳統的手法對金屬導體鳩進二刻， 鍍膜法將—金屬導 二不喊由 G接觸墊么;㈣接觸塾陣列彻，以使 基底245的高度。：第4圖：ί間= 的内連線 二：=:與複數個 凊翏考第5圖，在某歧每 積於下表面241上下著面、:貝& ' ’將金屬例如銅沈 進行阻抗的控制，：用二=成;接地面3°2, 如習知的已知良品晶片(k °八.〇默姆測試的需求’例 R 口口 日日月（known g00(j . ym、， 第6圖中，對接地面3〇2施以一值/’/GD)測試。在 驟，以如圖所示藉由在 、、’、的微影與蝕刻的步 P气踏在輸入/輸出測試墊304的月囹语A 間隙奶，而將輪入/輪出測試墊3 ^圍建立 用於微機電或半導體 、止 ^立。可猎由任何 例，來進行上述_步=、#統製程例如以祕刻為 製 / '考弟7圖’藉由任何用於微機電或半導體的 05 03-A3 j 786T WF/dwwang 201003075 造的適當傳統製程，將一第—八 C4 ^ T ^ ® w電層310塗覆或沈積於 次下矛面241上，並覆蓋接地 較好為一電性絕緣材料H=〇2。弟一介電層310 φ Φ ^ . t 乂隔離形成於内連線基底245 中的主動7L件與引腳。在較 31〇矸以Η取林 1 土的男把例中，弟一介電層 U可广Μ 練或—㈣氧樹脂為基材的光阻，例 ；s"； ^ 光阻，然而亦可使用其他適當的光阻。 請參考第8圖，接下步兹Λ # 阻材料/要下來猎由傳統的微影與相關的光 阻材料夕除製程例如灰化（ashing)，將第—介電層3 於C4接地測試墊303 |匸4於a /"^山 h、皁別入/輸出測試塾3〇4上 部分移除，將C4接地測試墊3〇3 | 、 304開口而使w ψ / μ C4輸入/輸出測試墊 於介電層則，以暴露接地面3。2的一部= 接地接點350 (請參考例如第 胳一:參Ϊ第9 ^，接下來藉由濺鍍或其他適當的方法， :弟一導體金屬層320-例如較好為銅一沈 接地面302的C4側4〇η μ 从、兹丛 、、匕括 瑞m μ L4側400上。弟二導體金屬層320是在後 、嘴於後文對第1!圖所敘述的導體金屬沈積步驟。 在第1G圖中，藉由傳統的微機電或半導體技術 一光阻330塗伟於a辆(·、’ 肘 # w Γ 加以圖形化。圖形化的In the test equipment, and as an interface between the above-mentioned wafer or device under test and the above-mentioned == test equipment. Motion/, J With the continuous development of semiconductor process technology, the electrical test of half of the wafer is in contact with 塾3. As shown in Fig. 1, it is a semiconductor wafer or a device under test that exemplifies the next generation, and the test pitch is full: meters or less. The above-mentioned device under test tests the two of the 塾110:;, 'the silicon wafer of the above-mentioned device to be tested connected by the connecting line 130; the TSV) contact 塾120=== can be 17 Micron. However, the existing test probes: the card W and the ten test results of the technical tracing of the poor I can not support such a small test pad spacing. The known probe card has a multi-layer (four) wire substrate or space (SpaWf_er), which is placed on the test printed circuit board and the probe such as fingers (probes). Gam) and so on). The above space transformer is transmitted between the above-mentioned printing 0503 "A33786TWF/dwwarig 201003075 brush circuit board and the probe, and the spatial converter is on its side: and the power signal. On the av. Rr Λ, m have - the inter-ball array (bali move a C4, even the I line 'is connected to the upper M (four) board and the Si media: ed CGllaPSe Ghlp eQnneCtiGn) on the internal connection system ^ ^; 'The above contact is the smallest C4 contact pad of the two exchanges with the above test _ 丄 、, the second C4 contact pad is: 150 micron' and cannot meet the support:::...m or smaller C4 The contact 塾 pitch distribution is shouting right. The industry needs improved test probe card space converters, which have a finer C4 contact pad spacing. [Invention] The system i = h "Supply semiconductor test probe card converter = to reduce - the pitch distribution of the contact test pad. In an implementation, a space transformer is provided with a space transformer having a plurality of first contact test pads on one side for electrical testing at the bottom, and the above-mentioned first-contact test 塾:::: layer Depositing a first dielectric layer on the upper surface to form a plurality of second contact test pads, defining a second artefact different from the first-thickness distribution and forming a plurality of weights The cloth pin is electrically connected to the first contact test pad of the first dielectric layer - in the embodiment, the upper and the second - contact test pads. The touch test pad is embedded or sealed on the The second 0503-A3j786TWF/dwwang 201003075 protective layer t. In another embodiment t, a manufacturing method of a semiconductor device includes: providing - spatial transformation crying;::: inter-transformation and plural Μ 基底 base-目" The electrical test of the first-side of the base is performed on the first-side, and the first test-contact has a plurality of points: ^: the layer is on the first side of the base Deposition - first:::: face metal ground plane layer; graphically The second layer of the first-layer layer: ΐ f recesses in the order; the conductor metal is filled in the above; the part: the second number of red cloth pins; and the plurality of second measurement 4 connections A second pitch distribution is defined between the test contacts and less than the first cutter, and at least one (four) of the second test contacts is electrically connected to the first test contact, and the method further includes In the other embodiment, a semiconductor test probe card spatially transforms: in another embodiment, the method includes: providing a space transformer having a substrate (four) of a plurality of first-contact test pads on the side to perform electrical testing of the device under test, a -first-pitch distribution is defined between the first-contact test pads; and a plurality of second contact test pads are formed On the substrate, a second first distance distribution is defined between the second touch test pads, and a plurality of red cloth pins are formed to electrically connect the first contact test pads. Sexually connected to the second contact test described above. In an embodiment, the method further comprises sealing the first contact test 〇503-A33786TWF/dwwang 7 201003075 pad and the second contact test pad by a tilting layer. The method is (4) forming a plurality of conductors extending through the protective layer. The well-like channel extends to the "exposed surface" of the above protective layer with the = ^ second contact test pad. The number of the dicing pins forms an electrical contact, and the wafer level test of the cardinal wafer. Another point of view, a semiconductor contact with a fine contact test distribution, the manufacturing of the semiconductor 丨p giant. Gan production * %w cutting needle card space converter package: touch two:?, with - the first side and a second side; The plurality of first-medium: two-fold: the first side and the second side of the substrate are connected to the test pad on the first side. One = real: sunny, the pitch distribution of the above second contact test pad is smaller than the pitch distribution of the above-mentioned brother-contact test 。. In another embodiment, the upper, upper, and space transformers have a plurality of redistributable pins electrically connected to at least one of: the second contact test pad is on the other side, and the other is - the actual test. A protective layer on the mat. ...with-covering the above-mentioned brother-contact test crying's wearing method'1: medium-semiconductor test probe card space conversion: for the wide-contact test 塾 pitch distribution, including:, -^ 'the upper surface of the above substrate An electrical test having a plurality of first-contact surface test devices, and a plurality of metal flats = between the above-mentioned brothers and one contact test tester, and a metal plane surrounding each of the above-mentioned first- Contact: f is electrically isolated from each of the above-mentioned first contact test pads, wherein the above-mentioned full-plane: = is a ground plane; the upper surface of the deposition-first dielectric layer is exposed, and the above-mentioned first-testing women are exposed; 〇503-A33786TWF/dwwang 8 201003075 is disposed on the first dielectric layer and electrically connected to the first contact test port, and each of the redistributing pins is located between the first end point Define a distribution of the heart pitch that is different from the above-described distance distribution. The above and other objects of the present invention will be apparent from the following description. The preferred embodiments are described in detail below as follows: FIG. The "test probe card 200" which has been modified from the ancient market by the method proposed by the present invention has a space transformer 24" & Interchange '240 has a fine pitch C4 contact pad array. The test needle card 200 can be any suitable commercially available test probe card such as, but not limited to, a needle probe from Went Rain th Laboratories, Inc. 〇f Βγ〇〇μ^ ct Needle Cobra® card, or can be from ~ ah coffee 8. f 腑e, \+ CA Obtained probe card with MkroSpdng® needle probe. Preferably, the probe card is selected to have a test needle probe spacing or pitch of up to 5 〇 micrometers or less to have the same spacing or spacing of the test pads 110 on the device under test (please refer to FIG. 1). Match. Referring to FIG. 2, the test probe card 200 has a test printed circuit board 210 having an upper surface 212 and a lower surface 214, a mounting ring 220 adhered thereto, and supported by the mounting ring 220. A test probe head 260, and a space transformer 240. In one embodiment, the test probe head 260 has a plurality of commercially available test 0503-A33786TWF/dwwang 9 201003075 test needles 230, which may be of any suitable type or architecture such as needles. Alternatively or in the form of a lock, the above model or architecture may provide an appropriate pitch distribution in one embodiment to support a test pad pitch of 50 microns or less. Each of the sword test probes 230 has a lower end point, and the lower end end is constructed or arranged to mate with a corresponding test pad 252 on a device under test 250 to be tested. The test probe 23A preferably has a pitch Pn' interval h which is matched to the pitch τ of the test pad 252 on the device under test 250. In an exemplary embodiment, the values of the pitches PT and PN may be about 50 microns. Referring to FIG. 2, in a possible embodiment, each test probe 230 can have an upper half 234 that is supported by a penetrating intermediate probe within the test probe head 260. Supported by 232. The material of the transmissive intermediate probe holder 232 is preferably a non-conductor material, such as a p〇lyamide nlylar film. The upper half 234 of each test probe 230 can extend to an enlarged contact end 236 of the uppermost portion to mate with a corresponding contact on the space transformer 240. In some embodiments, the test probe head 260 can further include a lower substrate 226, an upper substrate 222, and a spacer 224. As shown in FIG. 2, the extension of the test probe 230 is guided by the lower substrate 226. And passing through the lower substrate 226, the upper substrate 222 is configured to receive the upper half 234 of the probe and the enlarged contact end 236 'the spacer 224 is between the lower substrate 226 and the upper substrate 222. The enlarged contact end 236 preferably extends through the upper substrate 222 for connection to a contact pad on the space transformer 240. The applicable sub-theme of the present invention is not limited to the architecture or the feature of the test probe head 26 此处 described herein. A 0503-A33786T WF/dw wang 10 201003075 support structure of the test probe 23 of any other configuration may also be provided. In some embodiments, the bottom of the space transformer 240 can be a multi-layered organic (MLO) or multi-layered ceramic interconnect substrate 245. The space transformer 24A has a C4 side 400 and an opposite surface of the ball grid array side 4〇2, the side) has a lower surface 24], and the lower surface 241 has a fine pitch two-touch test pad array 242 for Engaged with the amplified contact end 236 on the test probe head 260; the opposite side of the ball gate array side 4〇2 has an upper surface 243, and the upper surface 243 has an inter-ball array for testing with the brush circuit The corresponding contact pads 2U on the board 210 are meshed. The inter-ball array may have a pitch Ρβ, which is defined as the spacing between the spheroids, and the spheroid may be made of soft solder or other suitable material. a Next, referring to Figures 3 to 14, the first embodiment of the manufacturing flow of the method of modifying a commercially available test probe card obtained by the present invention is sequentially described to produce a fine pitch. A space converter of the C 4 contact 塾 array and the 2 = inter-converter 240 are mounted on _, p, 丨 _ 厶 & & & & 将 将 将 将 将 将 将 将 将 将 第 第 第 第 第 第 第 第 第 第 第 第 第The reverse position of the space transformer 24〇 is not the same as that of the M-M diagram. Unless otherwise _ _ 疋 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Referring to Figure 3, there is provided that - on an interconnect substrate 245 it has a formation - in some embodiments, an internal = ^ C4 contact tantalum array machine or a multilayer ceramic substrate. There are K also in the middle, the existing C4 contact 塾 歹 歹 歹 050 050 050 050 050 TW 060 060 060 060 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 050 The surface 243 is such that the above-mentioned watch is in a state in which the conductor material can be received. The next step of the conductor ,ο, the metal is deposited by sputtering, in one embodiment, copper-deposited on the opposite side. On the ball idle array side 402 and the upper surface 243 of the space transformer 240, the two conductor channels 3G1 are electrically connected or short-circuited with each other. In some implementations = the traditional method of breaking the metal conductor into two, the coating method will be - The metal guide does not shout the G contact pad; (4) contact the 塾 array to make the base The height of the bottom 245.: Figure 4: The inner line of the ί = = two: =: and a plurality of reference pictures 5, in the case of a certain difference on the lower surface 241 up and down,: Bay & ' ' Control the impedance of a metal such as copper sink: use 2 = 2; ground plane 3 ° 2, as known by known conventional wafers (k ° VIII. 〇 默 test demand 'example R mouth day and month ( Known g00 (j. ym, in Figure 6, the ground plane 3〇2 is given a value / '/ GD) test. In the step, as shown in the figure, by lithography and etching Step P is stepped on the input/output test pad 304 of the monthly slang A gap milk, and the wheeled/rounded test pad 3 is built for MEMS or semiconductor, and can be hunt by any example. Performing the above-mentioned _step=,# system process, for example, by secret engraving / 'Caudi 7', by any suitable traditional process made by 05 03-A3 j 786T WF/dwwang 201003075 for MEMS or semiconductor, The first-eight C4 ^ T ^ ® w electrical layer 310 is coated or deposited on the sub-spray surface 241, and the grounding is preferably an electrical insulating material H = 〇 2. The dielectric layer 310 φ Φ ^ . t 乂 isolation is formed in Connect the active 7L parts and pins in the base 245. In the male case where the forest 1 soil is taken from the 31st, the dielectric layer U can be widely used or - (4) the light of the base material of the oxygen resin Resistance, example; s"; ^ photoresist, however, other suitable photoresist can be used. Please refer to Figure 8, followed by step Λ # 阻材料 / to go down hunting by traditional lithography and related photoresist materials In addition to the ashing process, the first dielectric layer 3 is partially removed from the C4 ground test pad 303 | 匸 4 in a / " ^ mountain h, soap input / output test 塾 3 〇 4, Ground the C4 ground test pad 3〇3 |, 304, and make the w ψ / μ C4 input/output test pad on the dielectric layer to expose the ground plane 3. 2 part = ground contact 350 (please refer to for example一一: Ϊ Ϊ 9 ^, followed by sputtering or other suitable method: a conductor metal layer 320 - for example, preferably the copper side of the ground plane 302 C4 side 4 〇 η μ from the , 匕 瑞 瑞 m μ L4 side 400. The second conductor metal layer 320 is a conductor metal deposition step described later in the first and third figures. In Fig. 1G, a conventional MEMS or semiconductor technology, a photoresist 330, is applied to a vehicle (·, ' elbow # w 加以 to be graphically patterned.
无阻3 3 0產生了 ―条石μ ηπ加。。。 J 糸列的凹部332,以供後續形成具有 肢重佈引腳334(請束考第12网、 ¥ 、月 > 芩弟12圖）的—重佈芦 ㈣1Stnb咖n layer ; RDL)，以改變來自即將形成的^ 的、具有較細微的間距的接觸測試墊陣列2们與具有較 J3 0503-A33786TWF/dwwang 201003075 ，現存間距的原始、現存的接觸測試墊陣列 被的路徑。上述光阻的圖形化亦在其内 ：成 :輸入/輸姉《 3G4、C4接地賴墊撕、口 阻tst幻5〇 (請參考例如第14圖）。此外，形成穿透光 阻330的新的凹部335，以暴露第二導體成攻先 ^續形成新的輸入/輸出接點352 (請參考例二二 屬—: = ί = 由_(一)將導體金 ΓΛ/Ι 例中為銅—沈積於内連線基底245的 C4側400上，而填入打開了的凹部说 呈= 個導體導體重佈弓丨腳334的一 ^有複數 導體重佈引腳3 3 4較好為在第曰^ Α例中， r； ^ itc λα ^ ^ "电層3 1 0上進行植螃 以將新的接觸測試墊陣列2 4 2 〜仃-線 靠。，此情況最好參考第16:=的C4接觸塾陣 重佈層是連接至並連接於^== _實際上的 接地測試墊303之間輸出測試塾烟與α •^间興對應的新的C4接妯桩科Λ 新的輸入/輸出接點352之 ， ” 繪示於剖面圖中）。第η圖二八^亚未將上述情況 阻330中相關於輸 ： i屬沈積製程亦填入光 -、新的和C4接地賴 凹部。輸入/輸出測試塾3〇4 輪出接點352的 這個步驟中完成。然而這個步、驟試塾烟是在 C 4接地接，點3 5 〇與新 ，、疋建立銅基材給新的 續的步驟中完成。 月1】μ *點352，其將會在後 口月參考弟12圖’接下來如圖所示，將光阻330移除 0503-Aj3786TWF/dwwang 14 201003075 而邊下輸入/輸出測試塾 、 C4接地接點35η、μ C4接地測試墊303、新的 ”、 、新的輸入7輪出接點352、與導體重佈 用rp 可使M用崎統的光阻材料移除製程，例如使 二;2水氣體灰化、或-液態溶劑(例如丙酮)。 :之^ 3G移除之外’較好為在完成光阻330的移 ^ f1"績進行蝕刻’以回蝕並移除光阻330下方的 334—=峨320的部分。如此，是將導體重佈引腳 jΓ及輸入/輸出測試墊304與C4接地測試墊 之間的弟一介雷声31Π異兩山+ 好Aο 層 出來。第—介電層310較 二 =:有電絕緣體性質的材料，以如圖所示，將導 聊334及新的輸入/輸出接點352電性隔離於接 2 ΓΛ上述回❹驟之後，僅有部分的第二導體金 ^召卜，其封於導體接地面302與第11圖所示步 ‘中沈積的金屬層之間’以形成新的導體重佈引腳334。 你考第13圖’如圖所示將—保護層340沈積或塗 =於内^線基底245的則彻上。而在某些實施例 中，可較好為以-介電材料來形成保護層34〇。保護層 34^交好為__電性、絕緣材料，以隔離形成於内連線基^ 分a“的主動兀件與引腳。在—實施例中，保護層34〇的 貝較好為—光阻材料，更好為1環氧樹脂為基材的 7b ^ ^ MicroChem Corporation of Newton, ΜΑ SU-8光阻。然而，亦可以使用其他適當的保護層 材枓與介電質。然後較好為進行微影製程，而將保護層 340圖形化’並形成暴露新的⑷妾地接點35〇與新的^ 入/輸出接點352的複數個凹部開口 342。 0503-A3j786TWF/dwwang ^ 201003075 請參考第Η圖，將一、#雕 342中以形成複數個井狀通ζ體金屬鍍上並填入凹部開口 點35〇與新的輪入/輪^逼3^ ’其將新的CM接地接 的-第二表面， =352建立至至少保護層340 面。在-例示的實施例f 較好為稍高於上述表 料可以是NiCo (錄敍），甘 ''井狀通道351的導體材 井狀通道351 It於先⑼&貝為具有良好的硬度。鎳鈷 第11圖所作的敘诚。^ — 2銅基材上’請參考前文對 狀通道351的頂端部八，侄的實施例中，將金鍍於井 新的輸入/輸出接點352 接地接點350與 好的傳導性與抗練。頂端接觸：:：義；提：良 間距的C4接觸測試墊_ 疋義了一檨細 放大的接觸端探針頭遍的 導體金屬與合金來形成井= 353。此外，亦可使用其他適當的導體金屬== 丽述任何製程步驟中所舉出的例示材料。 來取代 經重製與修改後的空間變換器240是示於第15圖 ^ 35Q _ _入/輸出接點352的 曰疋疋義了新的微細間距的C4接觸測試墊陣列 242,以與測試探針頭26〇的放大的接觸端 236咬合及媒 合。與具有原始的間距P〇的原始的以輸入/輪出測試墊 304與原始的C4接地測試塾3〇3所定義的原始的a墊 相比，新的C4接觸測試墊陣列242較好為具有小於間距 p〇的間距pC4。在某些實施例中，間距Pc4較好為％微 米或更小。球閘陣列244的原始間距^可保留於。4接 0503 -A337 86TWF/dwwang 16 201003075 觸測試墊陣列242的相应辆,_ _ 側402。此外，此處所: 就疋相反面的球閘陣列 245中的所有”線:敘述的例示方法㈣留内連線基底 了清楚顯示而的導體路控跡線，例如是為 360,因此仍使^?車乐15圖的代表性的—單—跡線 路板21。(!會示於歹二2:二距PB仍與測試印刷電 容。請注意C4輸入‘二/塾211的間距相 θ ^ 私出測试墊304與C4接地測試墊 弟15圖中所示的第二保護層340嵌於或封於内連 、.泉基底24)巾，並可藉由單__跡線36 =::Γ"°2、藉由導體重伟引心= 4c觸“墊陣列242電性連通至C4側彻。 尹是顯示緣示於第15圖的已修改的空間變換 二=〇的C4 <則4〇〇的俯視圖。第二保護層3 第 16圖中移除，以方#甚 上_ 疋仗弟 陣請的接點。如圖:=在=的C4接觸塾 C4接觸測試塾陣列2 在—:‘貫爾的新的 陣列242 η#; 1 Ρ〇如圖所不，新的接觸測試墊 干 %猎由具有導體重佈引腳334的新的重佈層， =連接至具有C4輸入/輸出測試墊3〇4#c4接地频 墊303之原始的C4接觸墊陣列4]〇。 、 中的方法與一已修改的空間轉換器的實施例 中了不品使用第5圖中所示的一接地面3〇2或第 :介電層311，而將上述具有導體重佈引腳334 的新的重佈層直接建立於空間變換器的内連線基底⑷ 上此方去亦可消除對第6圖所示之將C4輸入/輸出測 〇503-A33786TWF/dwwang ]? 201003075Unobstructed 3 3 0 produces a "strip stone μ ηπ plus. . . J 糸 的 recess 332, for subsequent formation of limbs with cloth 334 (please refer to the 12th network, ¥, month > 芩 brother 12 map) - heavy cloth (four) 1Stnb coffee n layer; RDL), The contact test pad array 2 from the near-formed ^ with a finer pitch is changed to the path of the original, existing contact test pad array with the existing spacing of J3 0503-A33786TWF/dwwang 201003075. The patterning of the above-mentioned photoresist is also in it: into: input/transmission "3G4, C4 grounding pad tearing, mouth resistance tst magic 5" (please refer to, for example, Figure 14). In addition, a new recess 335 is formed through the photoresist 330 to expose the second conductor to form a new input/output contact 352 (refer to Example 2-2):: = ί = by _(1) The conductor gold ΓΛ/Ι is copper deposited on the C4 side 400 of the interconnect substrate 245, and the filled recess is filled with a conductor conductor splicing 334. Cloth pin 3 3 4 is preferably in the second example, r; ^ itc λα ^ ^ " electrical layer 3 1 0 is implanted to place a new contact test pad array 2 4 2 ~ 仃-line In this case, it is best to refer to the 16:4 C4 contact 重 matrix redistribution layer is connected to and connected to ^== _ actually ground test pad 303 output test smog and α • ^ The new C4 interface is the new input/output contact 352, which is shown in the cross-sectional view. The η-Fig. 28 is not related to the above-mentioned situation 330: i is a deposition process Also filled in the light-, new and C4 grounding recesses. The input/output test 塾3〇4 rounds out the contact 352 in this step. However, this step, the test smoke is grounded at C 4 , point 3 5 〇 with new, 疋 疋 build copper substrate to complete the new continuation steps. Month 1] μ * point 352, which will be in the back mouth month reference brother 12 picture 'Next, as shown The photoresist 330 is removed 0503-Aj3786TWF/dwwang 14 201003075 while the side input/output test 塾, C4 ground contact 35η, μ C4 ground test pad 303, new "," new input 7 wheel out contact 352, Re-distribution of the conductor with rp allows the M to use a photoresist removal process, such as two; 2 water gas ashing, or - liquid solvent (such as acetone). It is preferable to perform the etching of the photoresist 330 to etch back and remove the portion of 334 -= 峨 320 under the photoresist 330. In this way, the conductor is re-wired on the pin jΓ and the input/output test pad 304 and the C4 ground test pad are separated from each other by a brother-in-law thunder 31 different mountains + good Aο layer. The first dielectric layer 310 is a material having an electrical insulator property, and as shown in the figure, the conduction 334 and the new input/output contact 352 are electrically isolated from each other after the above-mentioned returning step, only There is a portion of the second conductor, which is sealed between the conductor ground plane 302 and the metal layer deposited in the step 'shown in FIG. 11 to form a new conductor redistribution pin 334. In the case of Figure 13, the protective layer 340 is deposited or coated as shown in the figure below. In some embodiments, the protective layer 34 is preferably formed of a dielectric material. The protective layer 34 is made of __electricity and insulating material to isolate the active components and pins formed on the interconnecting component a". In the embodiment, the protective layer 34〇 is preferably - Photoresist material, preferably 7b ^ ^ MicroChem Corporation of Newton, ΜΑ SU-8 photoresist, which is based on 1 epoxy resin. However, other suitable protective materials can be used for the dielectric and dielectric. Preferably, the lithography process is performed, and the protective layer 340 is patterned 'and forms a plurality of recess openings 342 exposing the new (4) ground contacts 35 〇 and the new ^ input/output contacts 352. 0503-A3j786TWF/dwwang ^ 201003075 Please refer to the figure for the first, #雕雕342 to form a plurality of well-shaped through-metal metal plated and fill the recess opening point 35〇 with the new wheel / wheel ^ 3 ^ ' it will be new The second surface of the CM is grounded, and =352 is established to at least the surface of the protective layer 340. The exemplary embodiment f is preferably slightly higher than the above-mentioned surface material, which may be NiCo (recorded), Gan ''well channel 351 The conductor material well channel 351 It is first (9) & be a good hardness. Nickel cobalt is shown in Figure 11. ^ 2 copper base Above, please refer to the top end of the opposite channel 351. In the embodiment, the gold is plated on the new input/output contact 352. The ground contact 350 is well conductive and resistant. Top contact: : 义; mention: good spacing C4 contact test pad _ 疋 檨 a finely amplified contact tip probe head through the conductor metal and alloy to form a well = 353. In addition, other suitable conductor metal can also be used == Representing the exemplary materials cited in any of the process steps. Instead of the reworked and modified space transformer 240, it is shown in Figure 15 that the 35Q _ _ in/out contact 352 has a new meaning. The fine pitch C4 contacts the test pad array 242 to engage and match with the enlarged contact end 236 of the test probe head 26A. The original input/round test pad 304 with the original pitch P〇 is original with The new C4 contact test pad array 242 preferably has a pitch pC4 less than the pitch p〇 compared to the original a pad defined by the C4 ground test 塾3〇3. In some embodiments, the pitch Pc4 is preferably %. Micron or smaller. The original pitch of the ball gate array 244 can be retained. 0503 -A337 86TWF/dwwang 16 201003075 Touch the corresponding vehicle of the test pad array 242, _ _ side 402. In addition, here: all the "wires in the opposite side of the ball gate array 245": the illustrated example method (four) stays inline The line substrate has a conductor track trace that is clearly shown, for example, 360, and thus still represents a representative-single circuit board 21 of the car. (! will be shown in 歹 2 2: PB is still tested with printed capacitors. Please note that the C4 input 'two / 塾 211 spacing phase θ ^ private test pad 304 and C4 ground test pad 16 shown in the figure The second protective layer 340 is embedded or sealed in the inner joint, the spring base 24), and can be touched by a single __ trace 36 =:: Γ " ° 2, by the conductor heavy core = 4c touch Array 242 is electrically connected to the C4 side. Yin is a top view showing the modified spatial transformation of the modified spatial transformation 2 = 〇 C4 < 4 。. The second protective layer 3 is removed in Figure 16. , #方上# 疋仗 阵 请 请 。 。 。 。 。 。 。 。 = 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 塾 塾 塾 塾 塾 4 4 4 4 4 4 4 The new contact test pad is hunted by a new redistribution layer with conductor redistribution pins 334, = connected to the original C4 with C4 input/output test pad 3〇4#c4 grounding pad 303 The contact pad array 4], the method of the method and the modified space converter embodiment do not use a ground plane 3〇2 or the dielectric layer 311 shown in FIG. 5, but The above has a conductor redistribution pin 334 New RDL established directly within the space transformer substrate on the side of this connection to also eliminate ⑷ shown in FIG. 6 of the C4 input / output measured 〇503-A33786TWF / dwwang]? 201003075
試塾3 04隔離於I 實施例中，在本::==二在此替換的 步驟之後，接著完成示於第於第4圖的 C4側彻上並將其圖形 阻層330於 心用以形成具有複數個導體重：引=稷數個凹部 層，上述新的重佈声早 1腳334的新的重佈 連接至第15與16日圖所_、°的C4接觸墊陣列410電性 陣列242。鈇後，二成不、4的微細間距的接觸測試墊 圖所示步：成/此本說明如 藉由新的輪入/輪出接心2 :成導體重佈引腳334，其 出測試墊3 04、並!^/ "性連接原始的C4輸入/輸 始賴接地測試===35。電性連接原 修改或已重製的空㈣方法所形成的已 與μ圖所示，，是：有!:：外^ ^ 疋/又有接地面320與第一介雷层ς 接下來請參考第丨7〜23圖 ^ 。 ,,.. 圖’依序敘述本發明所接屮 的改一現有可從市面上取 ^ ^ 的製造流程的第二實施例，十卡200的方法 觸墊陣列的-空間變換哭心：，細間距的C4接 笛9 吳〇〇 Μ〇 (緣不於第23圖），以取代 弟2、15圖所示的空間變換器24〇。*第2 之將空間變換器240安裝於^ /、圖所不 置相比，第⑽圖=正常操作位 J工間茭換态540的位置是虚 ^目反的反向位置。除非另有提示，以下所敘述的各種 心、物質沈積、與物質移除的製 機電或半導體製造的已知製程。 ' 請參考第Π目，提供1内連線基底⑷，在其上表 0503-A33786TWF/dwwang ^ ^ 201003075 . /、有原始的現存C4接觸墊陣列7丨〇，在其下 上具有複數個接觸塾601。C4接觸墊陣列710 ΐ = 觸測試墊6〇3與接觸墊601之間，分別藉由 通路66^通路Μ""而電性連接。在本實施例中，導體 是由下細3與上表面541之間的多層電路 接於各層電路之間的連通導體所構成；在另 盥=列中，内連線基底545僅具有分別位於下表面M3 穿=W的二個導電層，而導體通路66〇則直接貫 底545 IT】43與上t面Μ之間。另夕卜，在内連線基 结—、、面541 ’過具有複數個金屬平面004分別環 :母測試墊603、並與每個接觸測試墊6。墙 面6〇4是接地而作為接地平面。在某些實施 例中’内連線基底545可以是— 一— ^夕層有機攻多層陶瓷基 &在—貫施例中，現存c4接觸塾障歹，】7 _之間具有'請微米的-原始節距分佈P。。首I 以超音波清潔上表面541與下夺面以^ 、\〇、、百先 於可接納其他層積於上的各層材料的狀態/上这表面處 請參考第18圖，在下一個步驟中，藉由任何用 ^電^半導體的製造的適當傳統製程，將—第—介❹ ㈣塗復、黏貼或沈積於上表面541: 604。第一介電層61〇較好為 ^孟屬千面 成於内連線基底545中的主動元件二緣材科，以隔離形 τ w 土動兀件與引腳。在較佳 鉍例中，第一介電層61〇可是 只 層、聚酿亞胺層或一以環氧樹敏性貝的聚酿胺 請C禮emCorp咖材的層，例如為可 p n 0f Newt〇n, ΜΛ 取得的 su_8 050j -A3 3 7 86TWF/dwwang ^ 201003075 具光敏性質的薄腹，& 性質的薄膜、U亦可使用其他適當的具有光敏 a疋不具有光敏性質的介電質薄膜。 ^ 603 ^^ ^ 電層610圖形化，暴露出接觸測試 摊# 疋弟—介電層6丨〇本身具有光敏性質，則可直 ;使=應的光罩進行曝光、顯影而完成圖形化；若是 本身不具有光敏性質，則可在其上形成 二猎♦統的微影、钱刻等步驟而完成圖形化。 曰-〇—例如在一實施例中為銅一分別 t j連線基底545的下表面543上、以及上表面541 弟介電層610與曝露的接觸測試墊603上，以使每 ㈣角=墊咖相互電性連接或短路、每個接觸測試塾聊 -目互電性逆接或短路，以利後續的金屬沈積製程。 接下來仍參考第19圖，藉由傳統的微機電或半導體 技術’將-光阻㈣塗佈於晶種層62〇上並 ，形化的光阻33。產生了—系列的凹部㈣，以供後續匕形 成具有導體重佈引腳634(請參考第2〇圖）的一重佈層 ^—layer;RDL)，以改變來自即將形成的& 的、具有較細微的間距的接觸測試墊㈣⑷（請泉 23圖）與具有較大的現存間距的原始、現存的接觸測試塾 陣列的電性訊號的路徑。其中，沈積於接觸測試墊6〇3 士上方的晶種層620,較好為至少或部分位於凹部6 範圍内。 現在請參考$ 20目，藉由鍍膜法（ρΜη§)例如電锻 法，將導體金屬-例如在-實施例中為銅—沈積於暴露 0503-A33786TWF/dwwang 20 201003075 在凹邛632而形成具有複數個 一重佈層。在-實施例中—H !腳咖的 好為在第一介電芦 们¥肢重佈引腳634較 晶種層620而電^ 進行繞線’而使其—端點經由 點635延伸至第的接觸測試塾•另一端 節距分佈為具有里於:ρ610上。此時每個端點奶的 中，間距Ρ θ /…間距Ρ〇的間距心4。而在本實施例 间跑心4疋小於間距ρ〇。 會你it下來請參考第21圖，將光阻⑽移除而留下導- 重佈引腳634及其端點635於第一介電：m: 用任何傳統的光阻材料移:。可使 體灰化/钱刻、或„、夜能例如使用乾式電裝氣 移除之外，萨Μ心/谷蜊（例如丙酮）。除了將光阻630 行蝕勹 议^為在完成光阻630的移除之後，繼續推 糊，以回钕並移除 ：進 以外沾曰絲赶μ Γ力的¥ 里饰引腳634 、日日種層620。如此，是將導^^舌德sh,、<， 第一介電層⑽暴露出來。I::;佈'腳634以外的 -部分而不再顯示。 “見“-重佈引讀的 凊參考第22圖，如圖所千於嚷._ w 或涂佈於笛入一弟二介電層640沈積 宜t弟一層610及導體重佈引腳634上。而在 芦，可作為—保護層或封裝 夕曰卜連線基底545内部的元件及/或電路層不受 較^ 或腐钱、破壞性因子的侵襲。第二介電層64〇 :-電性絕緣材料，以隔離形成於内連線基底⑷ 的元件與引腳。在—實施例中，第二介電層刚 '貝&好為具有光敏性質的聚酿胺層、㈣亞胺層或 〇5〇3-A33786TWF/dwwang 21 201003075 一以環氧樹脂為基材的層，更好為一以壤氧樹腊為基材 的光阻，例如為可從 MicroChem Corporation of Newton, MA取得的SU-8光阻。然而，亦可以使用其他適當的保 護層材料與介電質。然後較好為進行微影製程，而將第 二介電層640圖形化，並形成暴露端點635的複數個凹 部開口 642。 請參考第23圖，將一導體金屬填入凹部開口 642中 而分別電性連接於導體重佈引腳634的端點635，形成新 的C4接地接點650，而在某些實施例中新的C4接地接 點650較好為稍高於上述表面。在一例示的實施例中， 用於新的C4接地接點650的導體材料可以是NiCo (鎳 鈷），其性質為具有良好的硬度。而在形成新的C4接地 接點650之前，較好為先在曝露於凹部632的端點635 上鑛上一金層，此金層可作為防止端點635受到腐钱的 保護層及/或作為端點635與新的C4接地接點650之間 的黏著層，以提供良好的傳導性與抗钱性。上述金層及 新的C4接地接點650的形成可分別使用電鍍法，將端點 635那一側浸入一電鍍液（未繪示）中，從位於内連線基底 545的下表面543的金屬導體600連接一電源（未繪示）， 此時端點635亦經由導體重佈引腳634、接觸測試墊 603、導體通路660、接觸墊601至金屬導體600的電性 連接，而亦連接上述電源而成為陰極，而可在端點635 鑛上前述的金屬材料。此外，亦可使用其他適當的導體 金屬與合金來取代前述任何製程步驟中所舉出的例示材 料。在後續步驟中，可視需求移除金屬導體600。在一實 0503-A33786TWF/dwwang 22 201003075 施例中’新的C4接地接點65〇為輸入/輸出 已完成的每個新的…妾地接 上= 具有異於間距p。的間〜而在本實施例中^ 於間距P。。也就是，新的C4接地接點65〇^4 了-新的微細間距的C4接觸測試墊陣列5 ::義 2圖所示的C4接觸測試塾陣列扣而與測試 代乐 ::二大的接觸端236咬合及媒合。與具有原始的二 的原始的C4接觸測試塾6〇3之原始的現存以接 〇The test 塾 3 04 is isolated from the I embodiment. After the step of replacing::==2, the C4 side shown in FIG. 4 is completed and the patterned resist layer 330 is used for the core. Forming a plurality of conductor weights: a plurality of recess layers, the new redistribution sounds a new repeat of the first leg 334 connected to the C4 contact pad array 410 of the 15th and 16th days. Array 242. After the ,, 20%, 4, fine pitch contact test pad diagram shown: Cheng / this description, such as by the new wheel / wheel out the center 2: into the conductor redistributed pin 334, its test Pad 3 04, and !^/ " sexual connection to the original C4 input / output grounding test ===35. The electrically connected original modified or reworked empty (four) method is formed with the μ map, which is: there is !:: outside ^ ^ 疋 / there is a ground plane 320 and the first Jie Lei layer ς Next Refer to Figure 7~23 Figure ^. FIG. 2 is a second embodiment of a manufacturing process in which the present invention can be taken from the market, and the method of the ten-pad 200 method of space-space transformation is crying: The fine pitch C4 is connected to the flute 9 Wu Hao (not in the 23rd picture) to replace the space transformer 24 shown in the brothers 2, 15 diagram. * The second place is to mount the space transformer 240 to ^ /, and the figure is not compared with the figure. (10) = normal operation position The position of the 工 茭 540 is the reverse position of the virtual object. Known processes for electromechanical or semiconductor fabrication of various cores, materials, and material removals, as described below, unless otherwise indicated. ' Please refer to the second item, providing 1 interconnected substrate (4) on the table 0503-A33786TWF/dwwang ^ ^ 201003075 . /, with the original existing C4 contact pad array 7丨〇, with multiple contacts underneath塾601. The C4 contact pad array 710 ΐ = between the test pad 6 〇 3 and the contact pad 601, and is electrically connected by a path 66 Μ "" respectively. In the present embodiment, the conductor is composed of a connecting conductor between the lower layer 3 and the upper surface 541 connected between the layers of the circuit; in the other column, the interconnecting substrate 545 has only the lower The surface M3 wears two conductive layers of =W, and the conductor path 66〇 directly passes between the bottom 545 IT]43 and the upper t-plane. In addition, the interconnect wiring base, the surface 541' has a plurality of metal planes 004, respectively: a female test pad 603, and each contact test pad 6. The wall 6〇4 is grounded as a ground plane. In some embodiments, the 'internal connection substrate 545 can be a one-to-one organic layer multi-layer ceramic substrate& in the embodiment, the existing c4 contact barrier layer, 】 between 7 _ have micron - the original pitch distribution P. . The first I cleans the upper surface 541 and the lower face with ultrasonic waves. The state of each layer of the material that can be received on the upper surface is referred to the figure 18, in the next step. The first layer is coated, pasted or deposited on the upper surface 541: 604 by any suitable conventional process for the fabrication of the semiconductor. The first dielectric layer 61 is preferably an active component of the interconnecting substrate 545 to isolate the τ w earth moving element and the lead. In a preferred embodiment, the first dielectric layer 61 can be a layer only, a poly-imine layer, or a layer of a melamine-sensitive shellfish, such as pn 0f. Newt〇n, 取得 obtained su_8 050j -A3 3 7 86TWF/dwwang ^ 201003075 Thin film with photosensitive properties, & nature of film, U can also use other suitable dielectrics with photosensitive a 疋 not photosensitive properties film. ^ 603 ^^ ^ The electrical layer 610 is patterned, exposing the contact test booth # 疋 — - dielectric layer 6 丨〇 itself has a photosensitive property, it can be straight; the = mask should be exposed, developed to complete the graphics; If it does not have the photosensitive property itself, it can form a lithography, money engraving and the like on the two to complete the patterning.曰-〇—for example, in one embodiment, a copper-to-tj connection on the lower surface 543 of the substrate 545, and an upper surface 541 of the dielectric layer 610 and the exposed contact test pad 603, such that each (four) angle = pad The coffee is electrically connected or short-circuited, and each contact test is electrically-reversed or short-circuited to facilitate subsequent metal deposition processes. Next, referring to Fig. 19, a photoresist (4) is applied to the seed layer 62 and patterned by a conventional microelectromechanical or semiconductor technique. A series of recesses (four) are created for subsequent formation of a repeating layer of solder conductors 634 (see Figure 2) (RDL) to change from the & The finer-pitch contact test pads (4) (4) (see Figure 23) are routed to the electrical signal of the original, existing contact test 塾 array with a larger existing spacing. Wherein, the seed layer 620 deposited on the contact test pad 6 〇 3 is preferably at least partially located within the recess 6 . Referring now to the $20 mesh, a conductor metal, such as copper in the embodiment, is deposited on the exposed 0503-A33786TWF/dwwang 20 201003075 by a coating method (for example, electric forging). A plurality of layers. In the embodiment - H! is good for the first dielectric reed, the limb re-spinning pin 634 is electrically wound than the seed layer 620 and the end point is extended via the point 635 to The first contact test 塾 • the other end pitch distribution is in the range: ρ610. At this time, in each end of the milk, the spacing Ρ θ / ... spacing Ρ〇 spacing of the heart 4 . In the present embodiment, the running center 4 is smaller than the spacing ρ〇. Will you step down, please refer to Figure 21, remove the photoresist (10) leaving the conduction-re-wiring pin 634 and its end point 635 in the first dielectric: m: Move with any conventional photoresist material: It can make the body ashing / money engraving, or „, night can be removed, for example, using dry electric gas, Μ Μ heart / gluten (such as acetone). In addition to the photoresist 630 勹 勹 为After the removal of the 630, continue to push the paste to return and remove: into the outside of the 赶 赶 赶 Γ 的 里 里 里 634 634 634 634 634 634 634 634 634 634 634 634 634 634 634 634 634 634 。 。 。 。 。 。 。 。 。 。 。 。 。 Sh,, <, the first dielectric layer (10) is exposed. I::; cloth - other than the foot 634 and no longer displayed. "See "- redraw the reference 凊 reference to Figure 22, as shown Thousands of 嚷._ w or coated on the flute into a second dielectric layer 640 deposition should be a layer 610 and the conductor redistribution pin 634. And in the reed, can be used as a protective layer or package 曰 曰 连The components and/or circuit layers inside the substrate 545 are not affected by the damage or destructive factors. The second dielectric layer 64 is: - an electrically insulating material to isolate the components formed on the interconnect substrate (4) In the embodiment, the second dielectric layer is just a 'bean & good as a photosensitive amine layer, (iv) imine layer or 〇5〇3-A33786TWF/dwwang 21 201003075 an epoxy tree The grease is a substrate layer, more preferably a photoresist based on lyophilized wax, such as SU-8 photoresist available from MicroChem Corporation of Newton, MA. However, other suitable protections may also be used. Layer material and dielectric. The lithography process is then preferably performed to pattern the second dielectric layer 640 and form a plurality of recess openings 642 that expose the end 635. Referring to Figure 23, a conductor metal Filled into the recess opening 642 and electrically connected to the end point 635 of the conductor redistribution pin 634, respectively, to form a new C4 ground contact 650, and in some embodiments the new C4 ground contact 650 is preferably slightly Higher than the above surface. In an exemplary embodiment, the conductor material for the new C4 ground contact 650 may be NiCo (nickel cobalt), which is of good hardness and forms a new C4 ground contact. Before 650, it is preferred to first deposit a gold layer on the end point 635 exposed to the recess 632. The gold layer can serve as a protective layer for preventing the end point 635 from being subjected to money and/or as an end point 635 and a new C4 ground. Adhesive layer between contacts 650 to provide good conductivity and resistance The gold layer and the new C4 ground contact 650 are formed by electroplating, respectively, and the side of the end 635 is immersed in a plating solution (not shown) from the metal located on the lower surface 543 of the interconnect substrate 545. The conductor 600 is connected to a power source (not shown). At this time, the terminal 635 is also electrically connected via the conductor redistributing pin 634, the contact test pad 603, the conductor via 660, and the contact pad 601 to the metal conductor 600. The power source becomes the cathode, and the aforementioned metal material can be applied to the end point 635. In addition, other suitable conductor metals and alloys may be used in place of the exemplary materials recited in any of the preceding process steps. In a subsequent step, the metal conductor 600 can be removed as desired. In a real 0503-A33786TWF/dwwang 22 201003075 example, the new C4 grounding contact 65〇 is the input/output. Each new one that has been completed is connected to the ground = with a spacing p. In the present embodiment, the spacing is P. . That is, the new C4 grounding contact 65〇^4 - the new fine pitch C4 contact test pad array 5: the meaning of the C4 contact test 塾 array buckle shown in Figure 2 and test Daile:: two The contact end 236 is engaged and meshed. The original existing contact with the original C4 contact test with the original two 塾6〇3
列71〇相比，新的C4接觸測試塾陣％ : P 於間距P。的間距PC4。在某些實施例中，間距 5广〇微米或更小。—球料列（未可與位於内連以 f/45的下表面543的接觸墊叫妾合，上述球it :接的原始間距^可保留於^ 塾 列M2的相反侧。此外，此處所敘述的例示方法仍2 $連線基底545巾的所有”線路或其 師 線，因此仍使上述球閑陣列的間距 :::=2，的接觸墊-_ = 發明已以較佳實施例揭露如上，然其並非用以限 ^ ^明，任何本發明所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範_，當可料許之更 = 本發明之保護範圍當視後㈣請專利 犯圍所界定者為準。 y〜 0503’A33786TWF/dwwang 201003075 【圖式簡單說明】 a第1圖為—例示的半導體受測裝置的俯視佈局圖， 妹員不次世代之電性測試墊的架構與間距。 督2 _本發明〜實_之具有—空㈣換器的測 σ 式才木針卡的剖面側視圖。 2圖戶Γ-3:】4圖為—系列之部分剖面側視圖，用以顯示第 探針卡的空間轉換器的製造流程。 視圖弟圖為第2圖之空間轉換器的詳細的部分剖面側 第16圖為第〗5圖的办 圖中將頂端的—第4= 轉換器的上平面視圖，在 點。 $一保瘦層拿掉以顯示其下的電性接 第i 7〜2。圖為—系列 另一實施例之測試探針卡的圖，用以顯示 製造的空間轉換器可取 T 的製造流程，所 間轉換器。 圖所不的測試探針卡的空 【主要元件符號說明】 110〜測試墊11 〇 ; 120〜矽貫穿接觸墊 200〜測試探針卡； 211〜接觸墊； 214〜下表面； 222〜上基板； 226〜下基板； 130〜連接線； 210〜測試印刷電路板； 212〜上表面； 22〇〜安裝環； 224〜間隔物； 230〜測試探針； 0503-A33786TWF/dwwang 24 201003075 232〜穿透式的中間探針支 234〜上半部； 3 50〜新的C4接地接點； 352〜新的輸入/輸出接點； 360〜單一跡線； 402〜相反面的球閘陣列側 410〜C4接觸塾陣列； 542〜C4接觸測試墊陣列 543〜下表面； 600〜金屬導體； 603〜接觸測試墊； 610〜第一介電層； 630〜光阻； 撐器 240〜空間變換器； 2 42〜接觸測試塾陣列 244〜球閘陣列； 250〜受測裝置； 260〜測試探針頭； 301〜導體通道； 303〜C4接地測試墊； 305〜間隙； 311〜開口； 3 3 0〜光阻； 334〜導體重佈引腳； 340〜保護層； 236〜放大的接觸端； 241〜下表面； 243〜上表面; 24 5〜内連線基底； 252〜測試墊； 300〜金屬導體； 302〜接地面； 304〜輸入/輸出測試墊 3 1 〇〜第一介電層； 320〜第二導體金屬層； 332〜凹部； 335〜新的凹部； 342〜凹部開口； 351〜井狀通道； 353〜頂端接觸表面； 400〜C4側； 541〜上表面； 545〜内連線基底； 601〜接觸墊； 604〜金屬平面； 6 2 0晶種層； 632〜凹部； 0503-A33786TWF/dwwang 25 201003075 634〜導體重佈引腳； 640〜第二介電層； 650〜新的C4接地接點； 710〜C4接觸墊陣歹丨J ; Pbga〜間距；Compared to column 71〇, the new C4 contact test 塾 % % : P at the pitch P. The pitch is PC4. In some embodiments, the pitch is 5 microns or less. - Ball column (not in contact with the contact pad located in the lower surface 543 of the f/45, the original pitch of the ball: the original spacing ^ can be retained on the opposite side of the column M2. The exemplified method of narration still doubles all the "lines of the base 545 towel or its division, so that the spacing of the above-mentioned ball-free array is still:::=2, the contact pad -_ = the invention has been disclosed in the preferred embodiment As above, it is not intended to limit the scope of the present invention to those skilled in the art without departing from the spirit and scope of the present invention. Please refer to the definition of patent offense. y~ 0503'A33786TWF/dwwang 201003075 [Simple description of the diagram] a Figure 1 is a schematic top view of the semiconductor device under test, the electrical test of the next generation. The structure and spacing of the mats. 2 _ The present invention ~ real _ has a cross-sectional view of the σ-type wooden needle card of the empty (four) converter. 2 Figure Γ-3:] 4 picture is a part of the series Side view, used to display the manufacturing process of the space converter of the probe card. The detailed partial section side of the space converter of Fig. 2 is the upper plan view of the top-of-fourth converter in the diagram of Fig. 5, at the point. $一保瘦层The electrical connection under the i i 7~2 is shown. The figure is a diagram of a test probe card of another embodiment of the series, which is used to show the manufacturing process of the manufactured space converter, and the converter between the two. No test probe card empty [main component symbol description] 110~ test pad 11 〇; 120~矽 through contact pad 200~ test probe card; 211~ contact pad; 214~ lower surface; 222~ upper substrate; 226 ~ lower substrate; 130~ connection line; 210~ test printed circuit board; 212~ upper surface; 22〇~ mounting ring; 224~ spacer; 230~ test probe; 0503-A33786TWF/dwwang 24 201003075 232~transmission Intermediate probe branch 234~ upper half; 3 50~ new C4 ground contact; 352~ new input/output contact; 360~ single trace; 402~ opposite face of ball gate array side 410~C4 contact塾 array; 542~C4 contact test pad array 543~ lower surface; 600~ metal guide 603~contact test pad; 610~first dielectric layer; 630~resistance; bracing 240~space converter; 2 42~contact test 塾array 244~ball gate array; 250~device under test; 260~test Probe head; 301~ conductor channel; 303~C4 ground test pad; 305~ gap; 311~ opening; 3 3 0~ photoresist; 334~ conductor redistributed pin; 340~ protective layer; 236~ amplified contact 241~ lower surface; 243~ upper surface; 24 5~ inner wiring substrate; 252~ test pad; 300~ metal conductor; 302~ ground plane; 304~ input/output test pad 3 1 〇~1 first dielectric layer 320~ second conductor metal layer; 332~recess; 335~new recess; 342~recess opening; 351~well channel; 353~top contact surface; 400~C4 side; 541~upper surface; Line substrate; 601~contact pad; 604~metal plane; 6 2 0 seed layer; 632~recess; 0503-A33786TWF/dwwang 25 201003075 634~ conductor redistributed pin; 640~second dielectric layer; 650~new C4 ground contact; 710~C4 contact pad array J; Pbga~ pitch;
Pn〜間距， Ρτ〜間距。 635〜端點； 642〜凹部開口； 660〜導體通路； ΡΒ〜間距； P C 4〜間距， Ρ〇〜間距， 0503~A33786TWF/dwwang 26Pn~ pitch, Ρτ~ pitch. 635~end point; 642~recess opening; 660~conductor path; ΡΒ~pitch; P C 4~pitch, Ρ〇~pitch, 0503~A33786TWF/dwwang 26