201001632 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體封裝方法，特別是將不同尺寸大小及功能 之晶粒進行重新配置之封裝封方法。 【先前技術】 半導體的技術已經發展的相當的迅速，因此微型化的半導體晶粒(〇丨^) 必須具有多樣化的魏的需求，使得半導體晶粒必須要在很小的區域中配 置更多的輸入/輸出墊(I/O pads)，因而使得金屬接腳的密度也快速的 提咼了。因此，早期的導線架封裝技術已經不適合高密度之金屬接腳；故 發展出一種球陣列(Bal1GridArray:BGA)的封裝技術，球陣列封裝除了有比 導線架封裝更⑤密度之優點外，其錫球也比較不容㈣害與變形。 隨著3C產品的流行，例如：行動電話(Cell ph〇ne )、個人數位助理(pDA ) 或是iPod等，都必須要將許多複雜的系統晶片放入一個非常小的空間中， 因此為解决此問通，一種稱為「晶圓級封裝（⑽以；w^p)」 之封裝技術已經發展出來，其可以在切割晶圓成為一顆顆的晶粒之前，就 、 先對晶圓進行封裝。細專利公㈣5,323,〇51號專利即揭露了這種「晶圓 級封裝」技術。然而，這種「晶圓、級封裝」技術隨著晶粒主動面上的焊飾心） 數目的增加’使得·(pads)之間距過小，除了會導致訊_合或訊號干擾 的問題外’也會因為悍塾間距過小而造成封裝之可靠度降低等問題。因此， 當晶粒再更進-步的縮小後，使得前述的封裝技術都無法滿足。 為解決此-問題’制專利公告第7，19MG8號已揭露了—種將完成半 導體製程之晶圓’經過測試及切割後，將測試結果為良好的晶粒（㈣此） 重新放置於另-健板之上，然後再進行封裝製程，如此，使得這些被重 新放置的晶粒間具有較寬的間距，故可以將晶粒上的焊墊適當的分配，例 如使用向外延伸（fan〇ut)技術，因此可以有效解決因間距過小，除了會導 5 201001632 致訊號耦合或訊號干擾的問題。 然而，為使半導體晶片能夠有較小及較薄的封裝結構，在進行晶圓切 割前，會先對晶圓進行薄化處理，例如以背磨（滅—㈣啤）方式將晶 圓薄化至2〜2GmU，然後再切割成—顆顆的晶粒。此—經過薄化處理之晶 粒，經過重新配置在另—基板上，再以注模方式將複數個晶粒形成-封裂 體；由於晶粒很薄，使得封裝體也是非常的薄，故當封裝體脫離基板之後， 封袭體本身的應力會使得封裝體產生翹曲，增加後續進行_製程的困難。 另外，在晶圓切割之後，重新配置在另—個基板時，由於新的基板的 尺寸較原來的尺寸為大’因此在後續植球製程巾，會無法對準，其封裝結 構可靠度降低4此，本發明提供—種預先將銅柱形成於晶粒上的焊墊， 然後再藉㈣化製簡鋼柱曝露出來，故可以有效地解決植球雜法對準 以及封裝體產生翹曲的問題。 此外，在整個封裝的過程中，還會產生植球時，製造設備會對晶粒產 生局部過大的壓力，而可能損傷晶粒的問題；同時，也可能因為植球的材 料造成與晶粒上的焊墊間之電阻值變大，而影響晶粒之性能等問題。為此， 本發明提縣-觀先將練職於晶粒上的雜，紐縣由薄化製程 將銅柱暴露出來，接著再以向外延伸（fan⑽技術將植球做適#的配置， 除可有效解決損傷晶粒的問題，也可同畴鱗墊之間距過小等問題。 【發明内容】 有雲於發明背景中所述之植球對準以及封裝體赵曲的問題，本發明提 供-種利用晶粒重新配置之封袈結構及其方法，來將複數個晶粒重新進行 配置並進行封狀方法。故本㈣之主要目的在提供—種在晶粒上形成導 電柱’然後藉由薄化製程將導電柱曝露出來，以便在晶粒重新配置之封裝 過程中可以對準，可有效提高製造之良率及可靠度。 本發明之另一主要目的在提供一種在晶粒重新配置之封裝方法，係將 201001632 不同尺寸大小及功能之晶粒重新配置在一基板上之封裝方法。 此外，本發明還有一主要目的在提供一種晶粒重新配置之封裝方法， 其可以將12吋晶圓所切割出來的晶粒重新配置於8吋晶圓之基板上，如此 可以有效運用8吋晶圓之即有之封裝設備，而無需重新設立12吋晶圓之封 裝設備，可以降低12吋晶圓之封裝成本。 本發明之再一主要目的在提供一種晶粒重新配置之封裝方法，使得進 行封裝的曰曰片都疋已知疋功也正常之晶片’’（Kn〇wn g0〇d die)，可以節省 封裝材料，故也可以降低製程之成本 根據以上所述，本發明提供一種晶粒重新配置之封裝結構，包括:一晶 粒，其主動面上配置有複數個焊墊；—第—高分子材料層，覆蓋於晶粒之 主動面上並經由複數個導電柱與焊墊電性連接；一封膠體，用以包覆晶粒 之四個面；-第二南分子材料層，覆蓋於封膠體以及第—高分子材料層上 並曝露出複數個導餘；複數條扇$之金屬線段覆蓋於第二高分子材料層 上且每一金屬線段之一端與每一導電柱電性連接；複數個導電元件與每一 金屬線段之另-端電性連接；-基板，係由一黏著層與晶粒之下表面固接。 本發明接著提供-種模㈣t之乡晶粒封裝結構，包括:複數個晶粒，每 -晶祕有—主動面及—下表面且於每—晶粒之主動面上配置有複數個焊 塾；-馬分子材料層’覆蓋於每-晶粒之主動面上並曝露出複數個焊墊；複 數個導電柱，翻高分子材料叙fa1並與減轉露之科電性連接； -封膠體，係«於每-晶粒之四個面且曝露出每—晶粒之下表面以及主動 面上之高分子材料層與每—導電柱；_第二高分子材料層，覆蓋於封膠體以 及第-高分子材料層上並曝露出複數個導電柱；複數個_化之金屬線段， 覆蓋於第二高分子材料層上，部份圖案化之金屬線段之兩端電性連接一^導 電柱，而部份圖案化之金屬線段之—端電性連接另—些導電柱；—圖案化之 保護層’係覆蓋圖案化之金屬線段以及第二高分子材料層之上並曝露部份圖 案化之金屬線段之另-端；複數個導電元件，係與曝露之金祕段之另一端 7 201001632 電性連接；-基板，係藉由-黏著層與晶粒之下表面固接。 本發明接著提供多晶粒封裝方法，包括:提供—晶圓且於主動面上形成 有複數個晶粒區且每-晶粒區之主動上配置有複數個焊塾;形成一第一高分 子材料層於晶圓上，以覆蓋該些晶粒區之該主動面上之該些焊塾； 個第:開口，係於第-高分子材料層上形成複數個第一開口並曝露出每一焊 墊;形成複數個導電柱於每-第i 口中且複數個導電柱之一端與焊墊電性 連接；切_晶圓’以形成複數個獨立之晶粒；取放晶粒至—基板上，將該 晶粒之下表面固接於基板上;形成一第二高分子材料層於基板上並環覆每一 , 晶粒錢覆蓋每-晶粒上之第—高分子材料層及每-導電柱；薄化該第二高 分子材料層以曝露出第-高分子材料層及每一導電柱;形成複數個圖案化之 金屬線段，部份圖案化之金屬線段之兩端電性連接每—些導電柱，而部份圖 案化之金祕段之-端雜連接另—些導電柱;稍—_化之㈣層以覆 蓋圖案化之金屬線段並曝露部份圖案化之金屬線段之另一端;形成複數個導 電兀件並電性連接在圖案化之金屬線段之另一端上；及切割該封裝體，以形 成複數個多晶粒封裝結構。 一種模組化之多晶粒封裝方法，包括:提供至少一晶圓，每一晶圓之主 動面上形成有複數個晶粒區，其中每一晶圓之晶粒區之主動面上配置有不同 錢的焊墊，·形成-第-高分子材料層於每—晶圓上並覆蓋每—晶粒區上之 焊塾；形成複數個開口，係於每一晶圓之第一高分子材料層上形成複數個開 口，以曝露出該些焊墊；形成複數個導電柱於每一開口中餅與焊墊電性連 接；切割該些晶圓，以形成複數個具有不同焊墊數量之晶粒；取放晶粒至一 基板上，係將具有不同焊墊數量之晶粒固接於基板上；形成一第二高分子材 料層於基板上並環覆每一晶粒以及覆蓋每一晶粒上之第一高分子材料層及 母導電柱，薄化第一尚分子材料層，以曝露出第一高分子材料層及每一導 電柱；形成複數個圖案化之金屬線段，部份圖案化之金屬線段之兩端電性連 接一些導電柱，而部份圖案化之金屬線段之一端電性連接該些導電柱；形成 8 201001632 一圖案化之保護層以覆蓋圖案化之金屬線段，並曝露部份圖案化之金屬線段 之另一端;形成複數個導電元件並電性連接在已曝露之圖案化之金屬線段之 另-端上；及切_封裝體，以形成複數個模組化之多晶粒封裝結構。 有關本發_特徵與實作’賊合圖示作最佳實施鱗細說明如下。 (為使對本發明的目的、構造、特徵、及其功能有進一步的瞭解，兹配合 實施例詳細說明如下。） 【實施方式】 本發明在此所探討的方向為—種晶粒重新配置之封裝方法，將複數個 晶粒重新配置於另-基板上，雌進行封裝的方法。為了鎌底地瞭解本 發明’將在下列的㈣巾提料盡的步驟及其組成。雜地，本發明的施 行並未限定晶片堆疊的方式之技藝者所熟習的特殊細節。另—方面，眾所 周知的晶片職方式以及晶片薄化等後段製程之詳細步驟並未描述於細節 中’以避免造成本發明不必要之關。細，對於本發_較佳實施例， 則會詳細描述如下，'然而除了這些詳細描述之外，本發明還可以廣泛地施 行在其他的實關中，且本發_細不受限定，其敗後的專利範圍為 準。 在現代的半導體封裝製程中，均是將一個已經完成前段製程（Fr〇ntEnd Process)之晶圓10 (wafer)先進行薄化處理（Thinning pr〇⑽），例如將 晶片的厚度研磨至2〜20 mil之間，如第1A圖所示。然後，在晶圓1〇的主 動面上形成一高分子材料層110，例如；P〇LYIMIDE，使高分子材料層ιι〇 覆蓋主動面上的複數個焊墊102，如第1B圖所示，其中虛線1〇5係表示每 一顆晶粒之位置，其亦可作為後續之切割線。再接著，以半導體之顯影製 程，將每一焊墊位置上的高分子材料層11〇移除，以形成孔洞ιΐ2並曝露出 每一個焊墊102，如第1C圖所示。然後，使用物理氣相沉積製程（pVD) 或是化學氣相沉積製程（CVD)將一金屬材料形成並填滿於每一個孔洞112 9 201001632 中，以形成一導電柱115，此導電柱115與焊墊1〇2電性連接如第1D圖 所示在本發明之一較佳實施例中，高分子材料層11〇之厚度可以是 mil而導電柱115之厚度可以是〇5〜3mil ;同時，導電柱之材料可以 疋種硬度大的金屬，例如：銅或是其他含有銅成份之合金。 接著’進行沿著虛線105對晶圓進行切割（sawingpr〇cess)，以形成一 顆顆的晶粒1〇〇;然後，使用取放裝置（pickandplace)將一顆顆的晶粒1〇〇 逐一放置於另一個基板2〇〇上，如第2A圖所示，其中基板2〇〇上已配置一 黏著層120，此黏著層⑽為一具有彈性之黏著材料，例如矽橡膠(smc〇n rubber)、矽樹脂(silicon resin)、彈性pu、多孔pu、丙烯酸橡膠以成㈣ 或晶粒切割膠等。因此，晶粒1〇〇之背面可固定於基板2〇〇上。很明顯地， 基板200上的晶粒間隔區域比晶圓1〇中的晶粒間隔區域大，因此，可以使 得這些被重新放置的晶粒1〇〇間具有較寬的間距，故可以將晶粒1〇〇上的 烊墊適當的分配。此外，本實施例所使用的封裝方法，可以將12吋晶圓所 切割出來的晶粒1GG重難置於8 之基板上，如此可以有效運用8 叶晶圓之即有之封裝設備，而無需重新設立12 $晶圓之雜設備，可以降 低12吋晶圓之封裝成本。然後要強調的是，本發明之實施例並未限定使用 8吋晶圓大小之基板，其只要能提供承栽的功能者，例如：玻璃、石英、陶 瓷、電路板或金屬薄板（metal foil)等，均可作為本實施例之基板2〇〇，因 此基板200的形狀也未加以限制。 接著，請繼續參考第2B圖，當複數個包含有導電柱115的晶粒1〇〇已 被準確地放置並貼附至基板200上的黏著層12〇之後，接著，於基板2〇〇 及每一晶粒上100上形成一高分子材料層3〇〇,以使高分子材料層3〇〇填滿 於晶粒100之間並且每一顆晶粒100的五個面（除了晶粒1〇〇之背面與黏 著層120接觸）均由高分子材料層300所包覆，以形成一封裝體2〇。其中 此高分子材料層300可以是矽膠、環氧樹脂、丙烯酸（acrylic)、及苯環丁 烯（BCB)等材料。然後，可以選擇性地對平坦化的高分子材料層3〇〇進 201001632 行一烘烤程序’以使高分子材料層300固化。 再接著’請繼續參考第2C圖，對封裝體20之高分子材料層300進行 薄化處理，以使位於每一顆晶粒100主動面上的導電柱115曝露出來；然後， 再於每一顆晶粒1〇〇主動面上形成一高分子材料層13〇 ;再接著，以半導體 之顯影製程，將每一導電柱115位置上的高分子材料層13〇層移除，以曝露 出每一個導電柱115 ;然後，以向外延伸（fanout)技術形成複數個圖案化 之金屬線段140 ’每一條金屬線段14〇之一端與導電柱115電性連接，而另 一端則向外延伸形成一自由端，很明顯地，此自由端不會形成在晶粒1〇〇 的焊墊1〇2之上，如第2D圖所示。此外，金屬線段丨如可以是由銅、金或 銅合金等材料所形成，同時，金屬線段14〇也可以是由一 υβΜ金屬層來形 成，此UBM金屬層之材料可以是Ti/Cu或是Tiw/Cu。 在前述將封裝體20之每一顆晶粒完成圖案化之金屬線段14〇後，緊接 著，要進行對外連接元件的配置。如第2E圖所示，在封裝體之金屬線段14〇 的面上，形成一圖案化之保護層16〇 (例如：p〇lyimide)以覆蓋複數個圖案 化之金屬線段14G，並便曝露出複數個_化之金祕段14G的自由端。此 形成圖案化之保制16G的步驟包括:形成—保護層16G在複數侧案化之 金屬線段⑽上；利用半導體製程，例如顯影，先形成一圖案化之光阻層(未 在圖中表示)在保護層16〇上；接著，在進行顯影後，移除相對於複數個圖 案化之金屬線段之向外延伸之自由端，即可曝露出每—侧案化之金 屬線段140之向外延伸之自由端，如第2F圖所示。 —緊接著’如第2G圖所示，係在每—個曝露之自由端處形成複數個導電 70件其t導f：7L件4GG可岐錫球(SGldei> ball)或是金屬凸塊㈣y bump)。很明顯地，導電元件彻可以依據電路設計之需求進行配置，例如. 配置成:種球_ (BGA)之配置’如第3 _示。最後，即可切割封裝 體’以形成複數個完成封裝之模組。很明顯地，第4A圖是相對第3圖之广 cc線段之剖式圖。在此要強調’在進行第2A圖之黏晶過程中，亦可以選 11 201001632 擇將黏著層I25預先配置於每一顆晶粒1〇〇之背面上，例如：使用一轉 帶^TAPE)’其同樣可以達到將晶粒1〇〇固定於基板2⑻之上，故此製程之 黏著層125僅配置於晶粒1〇〇之區域上，如第4B圖所示。很明顯地，第犯 圖與第4A圖之差異處僅在黏著層（即⑼與如的配置，其中第从圖 中的黏膜層120是配置在整個封裝體之基板200上。另外，也要強調，本 實施例的封裝結構中，並未將基板2〇〇移除，故可藉由基板2〇〇作為散熱 之基板。 請參考第5A圖至第％圖及第όΑ圖至第0C圖，係本發明之另一實施 例之示意®。職地’在已_薄化處理之· 1()社動面上形成一光阻 層Π0 ’使絲層170覆蓋主動面上的複數個焊塾1〇2 ;然後，以半導體之 顯影製程，將每一焊塾位置上的光阻層17〇移除後，再以物理氣相沉積製 程(PVD)或是化學氣相沉積ta(CVD)在焊墊1〇2上形成一導電柱^， 使，導電柱1丨5與焊墊1〇2電性連接’如第SA圖所示，其中虛線⑽係表 不每-顆晶粒之位置’其亦可作為後續之切娜。在本實施射，導電柱 之材料了以疋種硬度大的金屬，例如··銅或是其他含有銅成份之合金。 接著，隨即將晶圓10上的光阻層170移除，因此可以在晶圓1〇的主 動面之每一晶粒100之每一焊塾102上形成複數個凸出的導電柱⑴，如第 5B圖所示。再接著，進行沿著虛線1〇5對晶圓進行切割（贿屢⑷， 以形成-麵的晶粒1GG，·猶，使脉放裝置（piekaiidpiaee)將一麵 的晶粒100逐-放置於另一個基板2〇〇上，如第5C圖所示，其中基板2〇〇 上已配置-黏著層12G ’絲著層12〇為-具有雜之黏著材料，例如石夕橡 膠(silicon rubber)、矽樹脂(silie〇n resin)、彈性pu、多孔pu、丙烯酸橡膠 (aoylic rubber)或晶粒切割膠等。因此，晶粒_之背面可固定於基板2〇〇 上。 接著，請繼續參考第6A ® ’當包含有複數個凸出導電柱115的晶粒1〇〇 已被準確地放置並蘭至基板上的黏著層12G之後；接著，於基板2〇〇 12 201001632 及每一晶粒上100上形成一高分子材料層300,以使高分子材料層300填滿 於晶粒100之間並且每一顆晶粒100的五個面（除了晶粒100之背面與黏 著層120接觸）均由高分子材料層300所包覆，以形成一封裝體20。其中 此高分子材料層300可以是矽膠、環氧樹脂、丙烯酸（acrylic)、及苯環丁 烯（BCB)等材料。然後，可以選擇性地對平坦化的高分子材料層300進 行一烘烤程序，以使高分子材料層300固化。 再接著，請繼續參考第6B圖，對封裝體20之高分子材料層300進行 薄化處理’以使位於每一顆晶粒1〇〇主動面上的導電柱115曝露出來；然後， 再於每一顆晶粒1〇〇主動面上形成一高分子材料層130 ;再接著，以半導體 之顯影製程，將每一導電柱115位置上的高分子材料層130層移除，以曝露 出母一個導電柱115 ;然後，以向外延伸（fan〇ut)技術形成複數個圖案化 之金屬線段U0，每一條金屬線段14〇之一端與導電柱115電性連接，而另 一端則向外延伸形成一自由端，很明顯地，此自由端不會形成在晶粒1〇〇 的焊墊102之上，如第6C圖所示。此外，金屬線段HO可以是由銅、金或 銅合金等材料所形成，同時，金屬線段14〇也可以是由一 U3M金屬層來形 成，此UBM金屬層之材料可以是Ti/Cu或是Tiw/Cu。 在前述將封裝體20之每一顆晶粒完成圖案化之金屬線段14〇後，緊接 著，要進行對外連接元件400的配置，其過程與第2E圖至第2(}圖之過程 相同，故不再重複贅述之。㈣顯地，導電元件4〇〇可以是錫球(祕过祕) 或是金屬凸塊(metal bump)。同時，導電元件4〇〇可以依據電路設計之需求 進行配置’例如··酉己置成一種球陣歹,KBGA)之配置。最後，即可切割封 裝體’以形成複數個完成封裝之她。很鴨地，第7圖亦是相對第3圖 之沿CC線段之剖式圖。糾’在本實施财，亦可以選擇將另—黏著層 125預先配置於每一顆晶粒刚之背面上，例如：使用一轉帶（丁細）， 其同樣可以達到將晶粒⑽固定於基板2⑽之上，故此製程之黏著層⑵ 僅配置於晶粒之區域上，如第8 _示。另外，也還要_，在本實 13 201001632 2〇〇移除，故可藉由基板2〇〇作為散熱之 施例的封裝結射，並未將基板 基板。 戈可述實施^，包覆每一顆晶粒_高分子材料層卿的方 式了選擇使用習知的機械逐模（siampingpr〇⑽）或是注模 process)來形成。 6 、j明在將複數個好的晶粒丨㈣新配置在另一基板細的過程中，由 2 B曰粒100力主動面上都有曝露之導電柱115，故可解決後續進行金屬 \接時的鮮_。，絲本發_祕之料，可賴數個相同 或是不相同的好的晶粒議封裝在一起，然後以半導體製程來形成圖案化 的金屬線4〇〇 ’將所要組合成模組（M〇DULE)的複數個晶粒電性連 接在-起。、例如：將4顆2細的DRAM晶粒以串連或並連的方式封裝在 一起’形成-個記憶容量為1G之記憶模組；或是，將複數個發光二極體 (LED)串接成—個柱狀光源或是並連成—面狀光源；或是，將不同功能、 不同大小之晶粒封裝成一系統等，都可藉由本實施例來達成。 第9圖係顯示本發明之系統級封裝(System-In-Package ; SIP)之上視圖。 當複數個晶圓所製造出的複數個具有不同功能之晶粒，例如：晶粒5〇5為 一微處理裝置、晶粒510為一記憶體控制裝置而晶粒515為一顆記憶體裝 置裝置；將上述不同功能之晶粒依據前述製程並放置於另一基板200上之 後，可經由第2A圖至第2F圖之過程，將複數顆不同功能之晶粒（包括晶 粒505、晶粒51〇及晶粒515)形成一封裝體，然後，經由對封裝體之高分 子材料層之薄化過程，可以使得封裝體上的複數顆不同功能之晶粒（包括 晶粒505、晶粒510及晶粒515)中的每一導電柱115曝露出來。在此要強 調，本發明使用導電柱115之另一主要目的，即是可藉由控制導電柱U5 之厚度（或稱為高度）來使得不同功能以及不同大小或是厚度之晶粒，可 以藉由對封裝體之高分子材料層的薄化過程，使得不同功能以及不同大小 或是厚度之晶粒上的導電柱115能夠曝露在同一平面上。故可以有效地解決 201001632 對準的問題。 然後’再於封農體上的每一顆晶粒之主動面上形成一高分子材料層 130，再接著’以轉體之聽餘，將每_導電柱lls位置上的高分子材 料層130層移除，以曝露出每一個導電柱115 ;再接著，使用一電鍛製程， 以便在高分子材料層3GG上形成-金騎（未顯示於圖中），同時^屬層與 每-個導電柱H5形成電性連接。接著，利用半導體製程技術，例如：以塗 佈、顯影及侧等方式，先形成一圖案化光阻層(未在圖中表示)在金屬層之 上；然後以侧方式來移除部份金屬層之後，再齡圖案化之光阻層〔因 此’可以依據所需要的電性連接方式來形成複數個圖案化之金屬線段她 而在本實施例中’每-圖案化之金屬線段彻之向外延伸之兩端係電性連 接至相鄰之每—晶粒上之複數個導餘115，使得相㈣每—晶粒彼此係以 串聯或並聯的方式電性連接成—系統，如第嫩圖所示；在此要說明的是， 此串聯或並聯的雛連接方式僅為本個之—實施例，其目的僅在揭露使 用圖案化的金屬製程’可⑽複數個晶粒依據所要的·連接方式完成連 在前述將封频20之概駄似金觀段_完成她k電性連 接後，緊接著，要進行對外連接元件·的配置，其過程與第π圖至第犯 圖之過程相同，故其相關過程不再重複贅述之。很明顯地，導電元件彻 可以是錫球(S〇lder ba戦是金屬凸塊(她】bu_。同時，導電元件可 =依據電路設狀需求進行配置，例如：，成—種球_ 之配 f ’如第10B圖所示。最後，即可依據切割線1〇5切割封裝體，以形成複 數個完成封裝之模組，如第11A圖所示。很明顯地，第Μ圖是相對第9 圖之沿CC線段之剖_。糾，在本實施财，柯 先配置於每-顆晶粒卿之背面上，例如：使用一郷帶（聰者)層 ==可以達_粒_雜基板之上，故聽程之黏著層125 僅配置於晶粒繼之區域上，如第11B圖所示。另外，也還要強調，在本 15 201001632 實施例的封裝結構巾，並未將基板移除，故可藉由基板作為散熱 之基板。 明參考第12圖，係顯示本發明之系統級封裝之另一實施例。如第12圖 所不，其在形成導電柱115之過程與第5A圖至第5c圖以及第6八圖至第 6C圖之過程相同’故其_過程不再_贅述之。鎌，在前述將封裝體 2〇之複數顆晶粒以金屬線段14〇完成系統化之電性連接後，緊接著，要進 行，外連接元件400的配置，很明顯地，導電元件_可以是錫球(s〇lderbaU) 或是金屬凸塊(metal bump)。同時，導電元件4〇〇可以依據電路設計之需求 進行配置，例如：配置成一種球陣列（BGA)之配置。最後，即可依據切 割線105切割封裝體，以形成複數個完成封裝之模組。很明顯地，第13A 圖亦是相對第9圖之沿CC線段之剖視圖。另外，在本實施例中，亦可以選 擇將另-點著層125預先配置於每-顆晶粒⑽之背面上，例如：使用一 郷帶（TAPE)，其同樣可以達到將晶粒丨⑻目定於基板勘之上，故此製 秋之黏著層Π5僅配置於晶粒励之區域上，如第l3B圖所示。另外，也 還要強調’在本實施例的封裝結構^，並未將基板細移除，故可藉由基 板200作為散熱之基板。 很明顯地，當封裝體中的複數個晶粒是相同功能及相同大小之晶粒； 例如：LED ;其同樣地可以使用金屬線段⑽將複數個晶粒以串聯或並聯方 式形成一模組(module)，金屬線段140可以是由銅、金或銅合金等材料所形 成，同時，金屬線段140也可以是由一 XJBM金屬層來形成，此ubm金屬 層之材料可以是Ti/Cu或是TiW/Cu。 當所要封裝之複數個晶粒為發光二極體(led)時，即可將每一發光二極 體的P電極與相鄰的發光二極體的p電極電性連接；而發光二極體的N電 極係與相鄰的發光二極體的N電極電性連接，且每一發光二極體電極 及P電極係經由導電柱115分別金屬線段ho電性連接。同樣地，本發明 也不限定發光一極體之數量或是其電性連接之方式，例如：將複數個發光 16 201001632 二極體（LED)串接成一個柱狀光源或是並連成一面狀光源；同時，本發明 也不限定發光二極體之發光顏色，即發光二極體可以是紅光發光二極體或 綠光發光二極體或藍光發光二極體或其他顏色之發光二極體（例如：白光） 或是前述發光二極體之組合等。最後，如第2E至第2F圖過程，於曝露之 金屬線段U0之自由端上形成導電元件400。 而當封裝體中的複數個晶粒是相同功能及相同大小之晶粒均無DRAM 時；例如：將4顆256MB的DRAM晶粒以串聯或並聯的方式封裝在一起 時，其同樣地可以使用金屬線段140將複數個晶粒以串聯或並聯方式形成 一個記憶容量為1GB之記憶模組。由於形成金屬線段14〇及導電元件4〇〇 之過程與前述相同，故不再重複贅述。 雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發 明，任何熟習相像技藝者，在不脫離本發明之精神和範圍内，當可作些許 之更動與潤飾，因此本發明之專利保護範圍須視本說明書所附之申請專利 範圍所界定者為準。 【圖式簡單說明】 第1A〜1D圖係表示於晶粒上形成導電柱之示意圖； 第2A〜2G圖係根據本發明所揭露之製造過程示意圖； 第3圖係根據本發明所揭露之上視圖； 第4A〜4B圖係根據本發明所揭露之技術剖視圖； 第5A〜5C圖係根據本發明另一實施例之示意圖； 第6A〜6(:圖係根據本發明之另一實施例之製造過程示意圖； 第7圖係根據本發明之另一實施例之剖視圖； 第8圖係根據本發明之再一實施例之剖視圖； 17 201001632 第9圖係根據本發明 少戍多晶粒封裝實施例之上視 圖； 表示在 =圖係根據本發明之形成多晶粒封裝實施例中， 複數個金屬線段蛾贿層之示意圖. 表示在 第10B圖係根據本發 漏㈣w ㈣之她多日日日崎裝實施例中， 封裝結構上喊魏轉tit件之示意圖； 第11A〜11B圖係表示第9圖沿BB線段之剖式圖； 第圖係、根據本發a月之形成多晶粒封裳之另一實施例之示意圖；及 視圖第13A〜UB _係、根據本發明之形成多晶粒封裝之另—實施例之剖 【主要元件符號說明】 100 晶粒 102 焊墊 105 切割線 110 高分子材料層 112 開口 115 導電柱 120 黏著層 125 黏著層 130 高分子材料層 140 金屬線段 160 保護層 18 201001632 200 基板 300 封膠體 400 導電元件 505 微處理裝置 510 記憶體控制裝置 515 記憶體裝置201001632 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor packaging method, and more particularly to a package sealing method for reconfiguring die of different sizes and functions. [Prior Art] The technology of semiconductors has been developed quite rapidly, so the miniaturized semiconductor die (〇丨^) must have a variety of requirements, so that the semiconductor die must be configured in a small area. The input/output pads (I/O pads) allow the density of the metal pins to be quickly improved. Therefore, the early lead frame packaging technology is not suitable for high-density metal pins; therefore, a ball array (Bal1GridArray: BGA) packaging technology has been developed. The ball array package has the advantages of 5 density than the lead frame package, and its tin. The ball is also less tolerant (four) damage and deformation. With the popularity of 3C products, such as Cell ph〇ne, Personal Digital Assistant (pDA) or iPod, it is necessary to put many complicated system chips into a very small space, so to solve In this connection, a packaging technology called "wafer-level packaging ((10) to; w^p)" has been developed, which can be performed on the wafer before the wafer is diced into individual dies. Package. This "wafer-level packaging" technology is disclosed in the patents (4) 5, 323, and 〇 51. However, this "wafer, grade-package" technology increases with the number of soldering hearts on the active side of the die. 'The distance between the pads is too small, except for problems that cause interference or signal interference.' There is also a problem that the reliability of the package is lowered because the pitch of the crucible is too small. Therefore, when the die is further stepped down, the aforementioned packaging technique cannot be satisfied. In order to solve this problem, Patent No. 7, 19, MG8 has revealed that the wafer that will complete the semiconductor process has been tested and cut, and the test result is a good grain ((4)). On top of the board, and then the encapsulation process, so that the repositioned dies have a wider spacing, so that the pads on the dies can be properly distributed, for example, using an outward extension (fan〇ut Technology, so it can effectively solve the problem that the pitch is too small, in addition to the signal coupling or signal interference. However, in order to enable the semiconductor wafer to have a smaller and thinner package structure, the wafer is thinned prior to wafer dicing, for example, by back-grinding (off-(four) beer). To 2~2GmU, and then cut into - grain. This—the thinned grain is reconfigured on the other substrate, and then the plurality of grains are formed into a crack-forming body by injection molding; since the crystal grain is thin, the package is also very thin, so After the package is separated from the substrate, the stress of the seal body itself causes warpage of the package, which increases the difficulty of subsequent processing. In addition, after the wafer is diced, when the other substrate is re-arranged, since the size of the new substrate is larger than the original size, the subsequent ball-making process can not be aligned, and the reliability of the package structure is reduced. Therefore, the present invention provides a solder pad in which a copper pillar is formed on a crystal grain in advance, and then exposed by a (four) chemical steel column, so that the misalignment of the ball and the warpage of the package can be effectively solved. In addition, during the entire packaging process, when the ball is generated, the manufacturing equipment will locally exert excessive pressure on the crystal grains, which may damage the crystal grains. At the same time, it may also be caused by the material of the ball and the crystal grains. The resistance value between the pads becomes large, which affects the performance of the die. To this end, the present invention will be the first to apply the job on the grain, New County will expose the copper column by thinning process, and then extend outward (fan (10) technology will be the configuration of the ball. In addition to the problem of effectively solving the damaged crystal grains, the distance between the same scale and the scale pad can be too small. [Summary of the Invention] The present invention provides the problem of the ball alignment and the package curvature described in the background of the invention. a sealing structure and method for reconfiguring the crystal grains to reconfigure a plurality of crystal grains and sealing the same method. Therefore, the main purpose of the present invention is to provide a conductive pillar on the crystal grains. The conductive pillars are exposed by a thinning process to be aligned during the re-distribution of the die, which can effectively improve the yield and reliability of the manufacturing. Another main object of the present invention is to provide a reconfiguration in the die. The encapsulation method is a packaging method for reconfiguring the different sizes and functions of the 201001632 on a substrate. In addition, the main object of the present invention is to provide a method for packaging a die reconfiguration. It can reconfigure the die cut from the 12-inch wafer on the substrate of 8吋 wafer, so that it can effectively use the packaged device of 8吋 wafer without re-establishing the packaging equipment of 12吋 wafer. The packaging cost of the 12-inch wafer can be reduced. A further main object of the present invention is to provide a method for packaging a die re-arrangement, such that the packaged wafers are known to have a good work-like wafer ('Kn 〇 g g 〇 g ) ) ) ) 可以 可以 g g ) 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据a solder pad; a first layer of polymer material covering the active surface of the die and electrically connected to the pad via a plurality of conductive posts; a colloid for coating the four faces of the die; The second molecular material layer covers the sealant and the first polymer layer and exposes a plurality of guides; the plurality of metal segments of the fan cover the second polymer material layer and one end of each metal segment Each The electric column is electrically connected; a plurality of conductive elements are electrically connected to the other end of each metal line segment; and the substrate is fixed by an adhesive layer to the lower surface of the crystal grain. The present invention further provides a seed crystal of the type (4) t The granular encapsulation structure comprises: a plurality of crystal grains, each of which has an active surface and a lower surface, and a plurality of solder bumps are disposed on each active surface of the crystal grain; a layer of the horse molecular material is covered by each A plurality of solder pads are exposed on the active surface of the die; a plurality of conductive pillars are turned over, and the polymer material is fa1 and electrically connected with the body of the dew; - the sealant, the system is «four per crystal grain And exposing each of the lower surface of the die and the polymer material layer on the active surface and each of the conductive pillars; the second polymer material layer covering the sealant and the first polymer layer and exposing the plurality a plurality of conductive metal segments, covering a second polymer material layer, the two ends of the partially patterned metal wire segments are electrically connected to a conductive pillar, and the partially patterned metal wire segments are - The terminal is electrically connected to another conductive column; the patterned protective layer Covering the patterned metal line segment and the second polymer material layer and exposing the other end of the partially patterned metal line segment; the plurality of conductive elements are electrically connected to the other end of the exposed gold secret segment 7 201001632; The substrate is bonded to the lower surface of the die by an adhesive layer. The present invention further provides a multi-die package method comprising: providing a wafer and forming a plurality of die regions on the active surface and actively arranging a plurality of solder bumps on each of the die regions; forming a first polymer The material layer is on the wafer to cover the solder pads on the active surface of the die regions; the first opening is formed on the first polymer layer to form a plurality of first openings and expose each a pad; forming a plurality of conductive posts in each of the i-ports and one of the plurality of conductive posts is electrically connected to the pad; cutting the wafer to form a plurality of independent grains; and picking up the die onto the substrate Fixing the lower surface of the die on the substrate; forming a second polymer material layer on the substrate and ringing each of them, and covering the first polymer layer and each layer on the die a conductive pillar; thinning the second polymer material layer to expose the first polymer material layer and each of the conductive pillars; forming a plurality of patterned metal line segments, and electrically connecting the two ends of the partially patterned metal wire segments - some conductive columns, and some of the patterned gold secrets - the end of the miscellaneous connection - some of the conductive columns a layer of (4) is formed to cover the patterned metal line segment and expose the other end of the partially patterned metal line segment; a plurality of conductive elements are formed and electrically connected to the other end of the patterned metal line segment; The package is diced to form a plurality of multi-die package structures. A modular multi-die package method includes: providing at least one wafer, wherein a plurality of die regions are formed on an active surface of each wafer, wherein an active surface of a die region of each wafer is disposed Different cost solder pads, forming a -first polymer layer on each wafer and covering the solder bumps on each of the die regions; forming a plurality of openings, the first polymer material of each wafer Forming a plurality of openings on the layer to expose the pads; forming a plurality of conductive pillars in each of the openings and electrically connecting the pads; cutting the wafers to form a plurality of crystals having different numbers of pads Grain; picking and placing the crystal grains onto a substrate, fixing the crystal grains having different number of pads to the substrate; forming a second polymer material layer on the substrate and covering each crystal grain and covering each crystal a first polymer material layer and a mother conductive column on the particle, thinning the first molecular material layer to expose the first polymer material layer and each of the conductive columns; forming a plurality of patterned metal line segments, part of the pattern The two ends of the metal wire segment are electrically connected to some conductive columns, One end of the partially patterned metal line segment is electrically connected to the conductive pillars; forming a 2010 20103232 patterned protective layer to cover the patterned metal line segments and exposing the other end of the partially patterned metal line segments; forming a plurality of The conductive element is electrically connected to the other end of the exposed patterned metal line segment; and the die-package is formed to form a plurality of modularized multi-die package structures. The best implementation scales for the present _characteristics and implementation thief combination diagram are as follows. (In order to further understand the object, structure, features, and functions of the present invention, the following detailed description will be given in conjunction with the embodiments.) [Embodiment] The present invention is directed to a package for grain reconfiguration. In the method, a plurality of crystal grains are re-arranged on another substrate, and the female is packaged. In order to thoroughly understand the steps of the present invention which will be extracted in the following (four) towels and their compositions. Miscellaneous, the implementation of the present invention does not define the specific details familiar to those skilled in the art of wafer stacking. On the other hand, the detailed steps of the well-known wafer job mode and the wafer thinning process are not described in detail to avoid unnecessary unnecessaryness of the present invention. For the present invention, the preferred embodiment will be described in detail below, however, the present invention can be widely implemented in other practical aspects in addition to the detailed description, and the present invention is not limited, and The scope of the latter patent shall prevail. In the modern semiconductor packaging process, a wafer 10 (wafer) that has completed the front-end process (Fr〇ntEnd Process) is first thinned (Thinning pr〇 (10)), for example, the thickness of the wafer is polished to 2~ Between 20 mils, as shown in Figure 1A. Then, a polymer material layer 110 is formed on the active surface of the wafer 1 , for example, P〇LYIMIDE, so that the polymer material layer ιι covers the plurality of pads 102 on the active surface, as shown in FIG. 1B. The dotted line 1〇5 indicates the position of each crystal grain, which can also be used as the subsequent cutting line. Next, the polymer material layer 11 of each pad position is removed by a semiconductor development process to form holes ι 2 and expose each pad 102 as shown in Fig. 1C. Then, a metal material is formed and filled in each of the holes 112 9 201001632 using a physical vapor deposition process (pVD) or a chemical vapor deposition process (CVD) to form a conductive pillar 115, and the conductive pillar 115 is The conductive pad 1〇2 is electrically connected as shown in FIG. 1D. In a preferred embodiment of the present invention, the thickness of the polymer material layer 11〇 may be mil and the thickness of the conductive pillar 115 may be 〇5 to 3 mil; The material of the conductive column can be made of a metal having a high hardness, such as copper or other alloy containing copper. Then, the wafer is cut along the dashed line 105 to form a single crystal grain; then, the pick and place is used to pick up the individual crystal grains one by one. Placed on another substrate 2, as shown in FIG. 2A, wherein an adhesive layer 120 is disposed on the substrate 2, and the adhesive layer (10) is an elastic adhesive material such as 矽mc rubber. ), silicon resin, elastic pu, porous pu, acrylic rubber to (4) or die cutting glue. Therefore, the back surface of the die 1 can be fixed on the substrate 2A. Obviously, the grain spacing area on the substrate 200 is larger than the grain spacing area in the wafer 1 ,, so that the repositioned crystal grains 1 can have a wider pitch, so the crystal can be crystallized. The pad on the granules 1 is properly dispensed. In addition, the packaging method used in the embodiment can make the die 1GG cut by the 12-inch wafer difficult to place on the substrate of 8, so that the packaged device of the 8-leaf wafer can be effectively used without Re-establishing 12$ wafers of miscellaneous equipment can reduce the packaging cost of 12-inch wafers. It is then emphasized that embodiments of the present invention do not limit the use of 8-inch wafer-sized substrates as long as they provide the functionality of the substrate, such as glass, quartz, ceramic, circuit boards, or metal foils. The substrate 2 can be used as the substrate of the present embodiment, and therefore the shape of the substrate 200 is not limited. Next, referring to FIG. 2B, after a plurality of crystal grains 1 including the conductive pillars 115 have been accurately placed and attached to the adhesive layer 12 on the substrate 200, then on the substrate 2 A polymer material layer 3 is formed on each of the crystal grains 100 so that the polymer material layer 3 is filled between the crystal grains 100 and five faces of each of the crystal grains 100 (except for the crystal grains 1) The back side of the crucible is in contact with the adhesive layer 120) and is covered by the polymer material layer 300 to form a package body 2〇. The polymer material layer 300 may be a silicone, an epoxy resin, an acrylic, or a benzene butadiene (BCB) material. Then, the planarized polymer material layer 3 can be selectively subjected to a baking process of 201001632 to cure the polymer material layer 300. Then, please continue to refer to FIG. 2C to thin the polymer material layer 300 of the package 20 so that the conductive pillars 115 on the active surface of each of the crystal grains 100 are exposed; then, each A polymer material layer 13 is formed on the active surface of the crystal grain; and then, a layer of the polymer material layer 13 at the position of each of the conductive pillars 115 is removed by a semiconductor developing process to expose each layer a conductive post 115; then, a plurality of patterned metal segments 140 are formed by a fanout technique. One end of each of the metal segments 14 is electrically connected to the conductive post 115, and the other end is extended outward to form a The free end, it is obvious that this free end is not formed on the pad 1〇2 of the die 1, as shown in Fig. 2D. In addition, the metal line segment may be formed of a material such as copper, gold or a copper alloy, and the metal line segment 14 may be formed of a layer of a υβΜ metal, and the material of the UBM metal layer may be Ti/Cu or Tiw/Cu. After the metal line segment 14 in which each of the crystal grains of the package body 20 has been patterned is described above, the arrangement of the external connection elements is performed. As shown in FIG. 2E, a patterned protective layer 16 (eg, p〇lyimide) is formed on the surface of the metal line segment 14 of the package to cover a plurality of patterned metal segments 14G, and exposed. The free end of 14G of multiple _ _ _ _ _ _ _ The step of forming the patterned 16G includes: forming a protective layer 16G on the plurality of side-formed metal line segments (10); using a semiconductor process, such as development, first forming a patterned photoresist layer (not shown in the figure) On the protective layer 16〇; then, after development, removing the outwardly extending free ends of the plurality of patterned metal segments, the outward appearance of each of the side-formed metal segments 140 is exposed The free end of the extension, as shown in Figure 2F. - immediately following 'as shown in Figure 2G, a plurality of conductive 70 pieces are formed at each free end of the exposure. The t-conducting f: 7L piece of 4GG can be tin ball (SGldei > ball) or metal bump (four) y Bump). Obviously, the conductive components can be configured according to the needs of the circuit design, for example, configured as: the configuration of the bulb _ (BGA) as shown in the third embodiment. Finally, the package can be cut to form a plurality of modules that complete the package. Obviously, Fig. 4A is a cross-sectional view of the cc line segment relative to Fig. 3. It should be emphasized here that in the process of the die-bonding of Figure 2A, it is also possible to select 11 201001632 to pre-position the adhesive layer I25 on the back side of each die, for example: using a tape ^ TAPE) 'It is also possible to fix the die 1 之上 on the substrate 2 (8), so the adhesive layer 125 of the process is only disposed on the region of the die 1 as shown in FIG. 4B. Obviously, the difference between the first map and the fourth graph is only in the adhesive layer (ie, the configuration of (9) and the like, wherein the mucous layer 120 in the first figure is disposed on the substrate 200 of the entire package. It is emphasized that in the package structure of this embodiment, the substrate 2 is not removed, so that the substrate 2 can be used as a substrate for heat dissipation. Please refer to FIG. 5A to FIG. 1 and FIG. It is a schematic diagram of another embodiment of the present invention. The job site 'forms a photoresist layer Π0' on the active surface of the thinned surface 1 to make the silk layer 170 cover a plurality of solders on the active surface.塾1〇2; then, in the semiconductor development process, the photoresist layer 17〇 at each solder joint position is removed, and then physical vapor deposition process (PVD) or chemical vapor deposition ta (CVD) A conductive pillar is formed on the bonding pad 1〇2, so that the conductive pillars 1丨5 are electrically connected to the bonding pads 1〇2 as shown in FIG. SA, wherein the dotted line (10) indicates the position of each of the crystal grains. 'It can also be used as a follow-up to Chena. In this implementation, the material of the conductive column is made of a metal with a high hardness, such as copper or other copper. Then, the photoresist layer 170 on the wafer 10 is removed, so that a plurality of protruding conductive pillars can be formed on each of the pads 102 of each of the die 100 of the active face of the wafer 1 (1), as shown in Fig. 5B. Then, the wafer is cut along the dotted line 1〇5 (bribe (4) to form the -faced crystal 1GG, and the piekaiidpiaee will be one. The surface die 100 is placed on the other substrate 2 逐, as shown in FIG. 5C, wherein the substrate 2 is disposed on the --adhesive layer 12G ′ the silk layer 12 〇 is - has a sticky adhesive material, For example, silicon rubber, silie〇n resin, elastic pu, porous pu, aoylic rubber or die cutting glue, etc. Therefore, the back surface of the crystal grain can be fixed to the substrate 2〇 Next, please refer to Section 6A ® 'When the die 1包含 containing a plurality of protruding conductive pillars 115 has been accurately placed and applied to the adhesive layer 12G on the substrate; then, on the substrate 2〇 〇12 201001632 and a polymer material layer 300 is formed on each of the crystal grains 100 to make the polymer material layer 300 The five faces of each of the crystal grains 100 (except that the back surface of the die 100 is in contact with the adhesive layer 120) are filled with the polymer material layer 300 to form a package body 20. The polymer material layer 300 may be a material such as silicone, epoxy resin, acrylic, or benzocyclobutene (BCB). Then, the planarized polymer material layer 300 may be selectively baked. The procedure is to cure the polymer material layer 300. Then, referring to FIG. 6B, the polymer material layer 300 of the package 20 is thinned to be placed on the active surface of each of the crystal grains. The conductive pillar 115 is exposed; then, a polymer material layer 130 is formed on the active surface of each of the crystal grains; and then, the polymer at the position of each conductive pillar 115 is formed by a semiconductor developing process. The material layer 130 is removed to expose the parent conductive pillar 115; then, a plurality of patterned metal segments U0 are formed by an outwardly extending technique, one end of each of the metal segments 14 and the conductive pillar 115 Electrically connected while the other end is outward Extending to form a free end, it is apparent that the free end is not formed over the pad 102 of the die 1 , as shown in Fig. 6C. In addition, the metal line segment HO may be formed of a material such as copper, gold or a copper alloy, and the metal line segment 14〇 may also be formed by a U3M metal layer. The material of the UBM metal layer may be Ti/Cu or Tiw. /Cu. After the foregoing metal line segment 14 in which each of the crystal grains of the package body 20 is patterned, the configuration of the external connection element 400 is performed, and the process is the same as that of the second to second embodiments. Therefore, the details of the conductive elements 4 can be solder balls or metal bumps. At the same time, the conductive elements 4 can be configured according to the needs of the circuit design. 'For example, I have set up a ball array, KBGA. Finally, the package body can be cut to form a plurality of packages that complete the package. Very ducky, Figure 7 is also a cross-sectional view taken along line CC of Figure 3. In this implementation, it is also possible to pre-dispose another adhesive layer 125 on the back surface of each of the crystal grains, for example, using a rotating belt (small), which can also be used to fix the crystal grains (10) to Above the substrate 2 (10), the adhesive layer (2) of the process is disposed only on the area of the die, as shown in FIG. In addition, it is also removed from the package, so that the substrate 2 can be used as a package for heat dissipation, and the substrate substrate is not used. Goco said that the method of coating each of the grains _ polymer material layer was selected using a conventional mechanical mold-by-mold (simpingpr〇(10)) or injection molding process. 6. In the process of dividing a plurality of good crystal grains (four) into another substrate, the conductive pillars 115 are exposed on the active surface of the 2 B granules, so that the subsequent metal can be solved. Fresh _. , silk hair _ secret material, can be packaged together with several identical or different good grain, and then form a patterned metal wire in a semiconductor process 4 〇〇 'to be combined into a module ( A plurality of dies of M〇DULE) are electrically connected. For example, four 4-cell DRAM dies are packaged in series or in parallel to form a memory module with a memory capacity of 1G; or, a plurality of LEDs can be serially connected. It can be realized by the present embodiment by connecting a columnar light source or a parallel light source into a planar light source; or encapsulating different functions and different sizes of crystal grains into a system. Figure 9 is a top view showing the system-in-package (SIP) of the present invention. When a plurality of wafers are manufactured by a plurality of wafers having different functions, for example, the die 5〇5 is a micro processing device, the die 510 is a memory control device, and the die 515 is a memory device. After the dies of the different functions are placed on the other substrate 200 according to the foregoing process, a plurality of different functional dies (including the dies 503, the dies) may be processed through the processes of FIGS. 2A to 2F. 51〇 and the die 515) form a package, and then, through the thinning process of the polymer material layer of the package, a plurality of different functional crystal grains on the package (including the die 505 and the die 510) Each of the conductive pillars 115 in the die 515) is exposed. It should be emphasized here that another main purpose of the present invention is to use the conductive pillars 115, that is, to control the thickness (or height) of the conductive pillars U5 so that different functions and grains of different sizes or thicknesses can be borrowed. The thinning process of the polymer material layer of the package enables the conductive pillars 115 on different functions and different sizes or thicknesses to be exposed on the same plane. Therefore, the problem of 201001632 alignment can be effectively solved. Then, a polymer material layer 130 is formed on the active surface of each of the crystal grains on the sealing body, and then the polymer material layer 130 at the position of each of the conductive pillars 11s is formed by the listening body. The layers are removed to expose each of the conductive pillars 115; and then, an electric forging process is used to form a gold ride on the polymer material layer 3GG (not shown in the figure), while the ^ layer and each The conductive pillars H5 form an electrical connection. Then, using a semiconductor process technology, for example, in a coating, developing, and side manner, a patterned photoresist layer (not shown) is formed on the metal layer; then part of the metal is removed in a side manner. After the layer, the re-aged patterned photoresist layer [hences] can form a plurality of patterned metal line segments according to the required electrical connection. In this embodiment, the 'per-patterned metal line segment is completely in the direction. The two ends of the outer extension are electrically connected to a plurality of adjacent drains 115 on each of the dies, so that the phases (4) are electrically connected to each other in series or in parallel to form a system, such as As shown in the figure, it is to be noted that the connection mode of the series or parallel connection is only the present embodiment, and the purpose thereof is only to disclose the use of the patterned metal process 'may (10) a plurality of crystal grains according to the required The connection method is completed in the foregoing, and the general description of the frequency-sealing frequency 20 is completed. After completing the electrical connection, the configuration of the external connection component is performed, and the process and the process from the πth to the first-figure diagram are performed. The same, so the related process is no longer heavy Repeat it. Obviously, the conductive element can be a solder ball (S〇lder ba戦 is a metal bump (she) bu_. At the same time, the conductive element can be configured according to the circuit design requirements, for example: f 'As shown in Fig. 10B. Finally, the package can be cut according to the cutting line 1〇5 to form a plurality of modules for completing the package, as shown in Fig. 11A. Obviously, the first figure is relative 9 Figure along the CC line section _. Correction, in this implementation, Ke Xian is placed on the back of each grain, for example: using a 郷 belt (Cong) layer == can reach _ grain _ miscellaneous Above the substrate, the adhesive layer 125 of the listening process is only disposed on the area of the die, as shown in FIG. 11B. In addition, it is also emphasized that the package structure towel of the embodiment of the present invention does not have the substrate. The substrate can be used as a substrate for heat dissipation. Referring to FIG. 12, another embodiment of the system-in-package of the present invention is shown. As shown in FIG. 12, the process of forming the conductive pillar 115 is the same as The processes from 5A to 5c and 6th to 6C are the same 'so the _ process is no longer _ narration.镰After the above-mentioned electrical connection of the plurality of dies of the package 2 is completed by the metal wire segment 14 ,, and then, the configuration of the external connection component 400 is performed, it is obvious that the conductive component _ may be a solder ball (s〇lderbaU) or metal bump. At the same time, the conductive element 4〇〇 can be configured according to the needs of the circuit design, for example: configured as a ball array (BGA) configuration. Finally, it can be cut according to the The line 105 cuts the package to form a plurality of modules for completing the package. Obviously, the 13A is also a cross-sectional view along the line CC along the ninth figure. In addition, in this embodiment, it is also possible to select another - The glazing layer 125 is pre-disposed on the back surface of each of the dies (10), for example, using a ruthenium tape (TAPE), which can also achieve the grain 丨 (8) on the substrate, so that the adhesive layer of the autumn Π 5 It is only disposed on the area of the grain excitation, as shown in FIG. 3B. In addition, it is also emphasized that the package structure in the embodiment does not remove the substrate finely, so that the substrate 200 can be used as a heat sink. Substrate. Obviously, when the package The plurality of crystal grains are the same function and the same size of the crystal; for example: LED; similarly, the metal segments (10) can be used to form a plurality of crystal grains in series or in parallel to form a module, and the metal line segment 140 can be It is formed of a material such as copper, gold or copper alloy. At the same time, the metal line segment 140 may also be formed by an XJBM metal layer. The material of the ubm metal layer may be Ti/Cu or TiW/Cu. When a plurality of crystal grains are LEDs, the P electrodes of each of the LEDs can be electrically connected to the p electrodes of the adjacent LEDs; and the N-electrode of the LEDs can be electrically connected. The N electrodes of the adjacent LEDs are electrically connected, and each of the LED electrodes and the P electrodes are electrically connected to each other via the conductive pillars 115. Similarly, the present invention does not limit the number of light-emitting diodes or the manner in which they are electrically connected. For example, a plurality of light-emitting 16 201001632 diodes (LEDs) are connected in series to form a columnar light source or connected to one side. At the same time, the present invention does not limit the color of the light emitting diode, that is, the light emitting diode may be a red light emitting diode or a green light emitting diode or a blue light emitting diode or other color light emitting two. A polar body (for example, white light) or a combination of the foregoing light-emitting diodes. Finally, as in the 2E to 2F process, the conductive member 400 is formed on the free end of the exposed metal segment U0. When a plurality of dies in the package have the same function and the same size of the dies are DRAM-free; for example, when four 256 MB DRAM dies are packaged in series or in parallel, they can be used equally. The metal segment 140 forms a memory module having a memory capacity of 1 GB in series or in parallel. Since the processes of forming the metal line segments 14 and the conductive members 4 are the same as those described above, the description thereof will not be repeated. While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The patent protection scope of the invention is subject to the definition of the scope of the patent application attached to the specification. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are diagrams showing the formation of conductive pillars on a crystal grain; FIGS. 2A to 2G are schematic views of a manufacturing process according to the present invention; and FIG. 3 is a diagram based on the present invention. 4A to 4B are cross-sectional views of the technology according to the present invention; FIGS. 5A to 5C are diagrams according to another embodiment of the present invention; and FIGS. 6A to 6(: are diagrams according to another embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a cross-sectional view of another embodiment of the present invention; FIG. 8 is a cross-sectional view of still another embodiment of the present invention; 17 201001632 FIG. 9 is a small encapsulation and multi-die package implementation according to the present invention A top view of an example of a multi-die package in accordance with the present invention, showing a plurality of metal line moth layers. It is shown in Fig. 10B that she is in accordance with the present invention (four) w (four) In the example of the Nissaki installation, a schematic diagram of the Wei-turned to the tap member is shown in the package structure; the 11A-11B diagram shows a sectional view along the BB line in the ninth diagram; the first diagram, the formation of the multi-grain according to the present month Illustration of another embodiment of Fengshang And the view of the 13A~UB_, the other embodiment of the multi-die package according to the present invention [section of the main components] 100 die 102 pad 105 cutting line 110 polymer material layer 112 opening 115 conductive Column 120 Adhesive layer 125 Adhesive layer 130 Polymer material layer 140 Metal line segment 160 Protective layer 18 201001632 200 Substrate 300 Encapsulant 400 Conductive element 505 Microprocessing device 510 Memory control device 515 Memory device