201001580 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種銲線連接方法，更詳而言之，係有 關一種用以電性導接複數電子元件之銲線連接方法。 【先前技術】 一般半導體封裝件中，為提供半導體晶片與基板間形 成電性連接，主要係將形成於半導體晶X主動面上之銲墊 打線至基板上，藉以構成該半導體晶片與基板之電性耦合 關係。 再者，於半導體晶片之電路設計時，為增加電流量或 為提升半導體晶片之電性品質，常需在半導體晶片之主動 面上設置接地銲墊或電源銲墊，且在同一接地銲墊或電源 銲墊上以二條以上之銲線電性連接至基板之接地墊（接地 壞）或電源塾（電源壞），而為滿足在半導體晶片之单一鲜塾 上打設二條以上銲線之需求，業界遂發展出長銲墊之設 計，該長銲墊之尺寸係較一般之銲墊尺寸大約一倍以上， 如此方可提供足夠之銲墊面積以在同一銲墊上打設多條銲 線。 請參閱第1A及1B圖，係顯示接置於基板11上之半 導體晶片10之主動面上設有一般銲墊101與長銲墊102, 該銲墊101係用以供該半導體晶片10與基板11間訊號傳 遞，而該長銲墊102係用以供半導體晶片10與基板11形 成接地或電源之電性連接，因此該基板11上係設有接地墊 (或為接地環）12,以供半導體晶片10之長銲墊102透過多 3 19260D1 201001580 條銲線13而電性連接至該接地墊（接地環）i2，該些銲線i3 係利用銲線機（Wireb〇nder)反覆進行打線作業，以使該 長銲墊102電性導接至該接地環(接地環）12 ^ 由圖中可看出長銲墊之功效係為了連接出多條銲 線，然而，由於長銲墊n之面積係數倍於一般銲墊，因此 於晶片面積固定下，長銲墊將佔用晶片之可用面積’使得 晶片上的銲墊數量減少。 夕，之，具有長銲墊之晶片其總面積必須加大以容納更 多數量之銲塾’然而這卻與晶片朝小尺寸化之趨勢相違。 復請參閱第2圖，如美國專利第號所揭露 顯示另―習知之半導體封裝件示意圖，其係為多晶 隹：E之半導體封裝件，該半導體寺 植, 袭件係包括基板21、 口又於5亥基板21上之第一晶片2〇a ^ H 2〇a μ -y ^ - 乂及植設於該第一晶 上之弟二晶片20b，為供該第〜 — 電怕违拉s斗甘， 及弟二晶片20a，20b 兒卜生連接至該基板21，該第一晶片2 以供該第二晶片施藉由銲線23a =有長銲墊2〇2, 片2〇a之長銲塾搬，再由該第一曰曰曰片連接至該第一晶 轉由銲線咖電性連接至基板21。 ^之長銲墊搬 、惟，以長粹墊進行多層晶片 塊的習知缺點。 之電性連接 亦具有如前 a η扠供一種銲線連接方 7中所存在之缺失，實為當今亟待改善雨 【發明内容】 考之课題。 夂一目的在於 鑒方；以上所述習知技術之缺點，本發明 19260D1 4 201001580 提供一種可於單一接點上連接出複數條銲線之銲線連接方 法。 本發明之又一目的為提供一種銲線連接方法，俾增加 晶片之可用面積與節省製程成本。 本發明之另一目的為提供一種銲線連接方法，俾符合 晶片小尺寸化之趨勢。 為達上揭目的，本發明揭示一種銲線連接方法，以供 電性連接複數電子元件，係包括：先於第一電子元件之電 性接點上形成導電凸塊；自第二電子元件之電性接點上打 線至該導電凸塊；接著自該導電凸塊上打線至該第二電子 元件，以於該導電凸塊上連接複數條銲線，且構成該第一 及第二電子元件之電性連接。 於實施本發明之製程時，係利用打線機（Wire bonder ) 之銲嘴將金線熔成一球狀而形成導電凸塊（金質凸塊(Au stud))於第一電子元件之電性接點上，並於第二電子元件之 電性接點上形成一球型接點（ball bond)，再移動該銲嘴 至導電凸塊，接著截斷該銲線以於該導電凸塊上形成一第 一缝接銲點（stitch bond )，接著利用打線機於該導電凸 塊之第一缝接銲點上形成球型接點，再移動該銲嘴至該第 二電子元件，接著截斷該銲線以形成一第二缝接銲點，而 完成該第一及第二電子元件間之打線作業。 該第一電子元件可為半導體晶片，其電性接點係為設 於該半導體晶片主動面上之銲墊，該第二電子元件可為基 板，其電性接點係為設於該基板上之接地墊（環）或電源墊 5 19260D1 201001580 (環）等。另該第二電子元件亦可為導線架，且其電性接 點係為該導線架中之接地導腳或晶片座等。 承前述之銲線連接方法之要點，本發明之銲線連接方 法亦可應用於多數電子元件間之電性連接’尤為半導體晶 片堆疊結構中相互之電性連接，係包括：於複數電子元件 中至少其中一者之電性接點接置導電凸塊；自該電子元件 中，異於該導電凸塊所對應之電子元件之電性接點打線至 該導電凸塊；接著自該導電凸塊打線至另一電子元件上， 以於該導電凸塊上連接出複數條銲線而電性連接各該電子 元件。 於一實施態樣中，該些電子元件係為基板、接置於該 基板上之第一晶片以及接置於該第一晶片上之第二晶片。 其係先於第一晶片銲墊形成導電凸塊，接著自該基板打線 至該第一晶片之導電凸塊，以形成該第一晶片與基板之電 性連接，然後再自該第二晶片打線至該第一晶片之導電凸 塊，以構成第一及第二晶片之電性連接。亦或先於該第一 及第二晶片銲墊形成導電凸塊，接著利用反向銲線技術自 該基板打線至該第一晶片之導電凸塊，以及自該第一晶片 之導電凸塊打線至該第二晶片之導電凸塊，以構成該基 板、第一及第二晶片之電性連接。 於另一實施態樣中，該複數之電子元件係分別為基 板、以及堆疊於該基板上而成複數階梯狀之半導體晶片， 係先於該底層晶片銲墊上設置導電凸塊，以自該基板之電 性接點打線至該底層晶片之導電凸塊，以及由其餘各層晶 6 19260D3 201001580 片打線至該底層晶片之導電凸塊，以供接置於基板上之多 層晶片藉本發明之銲線連接方法達成各層晶片、以及晶片 至該基板的電性連接。另外，亦可於該基板以外之各層晶 片上設置導電凸塊，以利用反向銲線製程之技術電性連接 基板至底層晶片之導電凸塊^再依序由下層晶片之導電凸 塊措由反向鲜線技術打線至上層晶片之導電凸塊’以構成 基板與堆豐其上之晶片間的電性連接。 相較於習知技術中必須以加長之銲墊連接複數銲線 而造成佔用晶片可用面積之現象，藉由本發明之銲線連接 方法，將打線作業集中於單一導電凸塊上，以不加長晶片 銲墊之前提下使一晶片銲墊可連接多條銲線，進而增加晶 片之可用面積。 另外，習知技術為了於一具加長銲墊之晶片上保持銲 墊之數量，只能將晶片以較大之尺寸設計，而本發明之銲 線連接方法，因不須設置加長之銲墊即可便利地於單一銲 墊上連接多條銲線，因此晶片可朝小尺寸化之趨勢持續發 展。 再者，本發明之銲線連接方法所需之製程技術，以既 有的機台設備即可達成，無論應用於晶片與導線架或基板 之電性連接，或應用於多層晶片的電性連接皆具有良好之 效益。 由上可知，本發明之銲線連接方法可改善習知缺點並 具節省成本之功效，實具備高度產業利用價值。 【實施方式】 7 19260D1 201001580 以下係藉由特定之且體者# __ 夂 版只％例說明本發明之實施方 式，熟習此技藝之人士可由太々犯含乂1 κ 田本5兄明書所揭示之内容輕易地 瞭解本發明之優點與功效。 ι 第一實施例 請參閱第3Α圖至第3Γ)同 /么丄 〃— 弟D圖，係本發明之銲線連接方 法第一貫施例之示意圖。 如第3Α圖所示，係將第—電子元件接置於第二電子 兀件上’該^料元件為半導體晶片I該第二電子元 件為基板31，該第一及第二雷 、 电子70件上係設有電性接點， 如形成於δ玄半導體晶片30主動而μ 王勒面上之銲墊3〇1，以及形成 於該基板31上之接地墊（戋接 Α接地壤）32(亦可為電源墊或 電源環），且於該半導體晶片3〇 A川之至少一銲墊301上形成 導電凸塊34’該導電凸塊34可盔入所 T為金貝凸塊（Au Stud )， 其係利用銲線機燒結金線而成型於鲜塾上 如第3B圖所tf ’利用反向鲜線技術（⑽· 自基板3!之接地墊（環）32上銲接鲜線…至該導電凸 塊34,使該銲線33a以接近水平之角度銲結於該導電凸塊 34。该銲線33a係為金線，其係利用—打線機（b〇nder ) 之銲嘴35於邊基板31之接地墊（環）32上利用銲嘴35先形 成一球型接點331a (ball bond)，再移動該銲嘴％至該 導電凸塊34’接著截斷該銲線33a以形成一縫接銲點332a (stitch bond) ’而完成自該基板31上之接地塾（環）32 至該半導體晶片30上之導電凸塊34之打線作業。復請配 合麥閱第3C圖，係為對應第3B圖之上視圖，用以顯示接 19260D1 201001580 置於第二電子元件（基板）上之第一電子元件（半導體晶片） 利用銲線而相互形成電性導接。 如第3D圖所示，再利用一般打線作業，以自先前形 成於該導電凸塊34上之缝接銲點332a上銲接銲線33b至 該基板31之接地墊（環）32。該打線作業係於導電凸塊34 之缝接銲點332a上先形成一球型接點331b，再移動銲嘴 35至該基板31之接地墊（環）32，接著截斷該銲線33b 以形成另一缝接銲點332b，而完成該第一及第二電子元件 (晶片及基板）間之重覆打線作業，如第3E圖所示，係為顯 示該第3D圖之上視圖。另，由於該半導體晶片30與該基 板31之第一次銲線連接係由該基板31打線至該導電凸塊 34，藉著銲線33a以接近水平角度銲結於該導電凸塊34， 而不影響後續於該導電凸塊34之銲線33a之缝接銲點 332a上形成銲線33b之製程。 第二實施例 請參閱第4圖，係本發明之銲線連接方法第二實施例 之示意圖。 本發明之第二實施例與第一實施例大致相同，其主要 差異係在於第二實施例中，該第二電子元件係為導線架 41，該導線架41具有一晶片座411以及複數設於該晶片座 41周圍之導腳412,以供如半導體晶片40之第一電子元件 接置於該晶片座411上，且於該半導體晶片40之銲墊401 上係設有導電凸塊44，以利用銲線43a及銲線43b先後自 該導腳架之電性接點，亦即該導腳412(例如為接地導腳） 9 19260D1 201001580 電性連接至該半導體晶片40之導電凸塊44，再自該導電 凸塊44電性連接至導腳412。 另該導線架之電性接點除可為導腳外，亦可為晶片 座，以利用該晶片座提供半導體晶片接地作用。 第三實施例 請參閱第5A圖至第5C圖，係本發明之銲線連接方 法第三實施例之示意圖，用以電性連接複數電子元件。 如第5A圖所示，該些電子元件係具有晶片承載件， 例如基板51、接置於該基板51上之第一晶片50a、以及接 置於該第一晶片50a上之第二晶片50b，於該基板51、第 一晶片50 a及第二晶片50b上係分別設有接地墊510、 銲墊501a及銲墊501b等電性接點，且於該第一晶片50a 之鲜塾5 01 a上設置有導電凸塊54。 如第5B圖所示，接著，利用反向銲線作業以自未設 有導電凸塊之電子元件，打線至該導電凸塊，亦即自該基 板51之接地墊510銲接銲線53a至該第一晶片50a之導電 凸塊54。該反向銲線作業係於基板51之接地墊510上利 用銲嘴55先形成有一球型接點531a (ball bond) ’再移 動該銲嘴55至該導電凸塊54，接著截斷該銲線53a以形 成一缝接銲·點532a ( stitch bond )，而完成自該基板51之 電性接點（接地墊510)至該第一晶片50a之導電凸塊54之 打線作業。另外，該基板51之電性接點除可為接地墊外亦 可為電源墊等。 如第5C圖所示，於該第二晶片50b之銲墊501b上以 10 19260D3 201001580 銲嘴55形成一球型接點531b，再移動該銲嘴55至該導電 凸塊54上之缝接銲點532a，以形成銲線53b，接著截斷該 銲線53b而形成另一缝接銲點532b，以形成該第二晶片50b 至第一晶片50a之電性連接。 另外，該第一、二晶片50a,50b間之銲線連接亦可以 反向銲線製程之技術來達成，如第5D圖所示，可先於該 第二晶片50b之銲墊501b上形成有一導電凸塊54’，當完 成該基板51與該第一晶片50a間之銲線連接後，可於缝接 銲點532a上形成球型接點531b’並由該球型接點531b’以 反向銲線之技術銲接銲線53b’至該第二晶片50b之導電凸 塊54’，而完成該第一、二晶片50a，50b間之打線作業。 第四實施例 請參閱第6圖，係應用本發明之銲線連接方法第四實 施例所形成之半導體結構之示意圖。 本發明之第四實施例係與第三實施例大致相同，其主 要差異在於該半導體結構具一基板61以及接置於該基板 61上之複數層半導體晶片，包括位於底層之第一晶片 60a、設於該弟·晶月60a上之弟二晶片60b、以及接續設 於該第二晶片60b上之第三晶片60c，而形成一階梯狀之 半導體結構。該多晶片堆疊之半導體結構中，至少該第一 晶片60a之銲墊上接置有導電凸塊64。 本實施例係自該基板61之電性接點以反向銲線之技 術銲接銲線63a至該第一晶片60a之導電凸塊64，接著於 該第二晶片60b上形成球型接點65a並由該球型接點65a 11 19260D1 201001580201001580 VI. Description of the Invention: [Technical Field] The present invention relates to a wire bonding method, and more particularly to a wire bonding method for electrically connecting a plurality of electronic components. [Prior Art] In the general semiconductor package, in order to provide electrical connection between the semiconductor wafer and the substrate, the pad formed on the active surface of the semiconductor crystal X is mainly wired to the substrate, thereby forming the electricity of the semiconductor wafer and the substrate. Sexual coupling relationship. Furthermore, in the circuit design of the semiconductor wafer, in order to increase the amount of current or to improve the electrical quality of the semiconductor wafer, it is often necessary to provide a ground pad or a power pad on the active surface of the semiconductor wafer, and on the same ground pad or The power pad is electrically connected to the ground pad (ground fault) or the power port (power supply) of the substrate by two or more bonding wires, and the need to set two or more bonding wires on a single fresh chip of the semiconductor chip, the industry遂 The design of the long pad has been developed. The size of the long pad is more than double the size of the conventional pad, so that sufficient pad area can be provided to create multiple bonding wires on the same pad. Referring to FIGS. 1A and 1B, it is shown that a general pad 101 and a long pad 102 are provided on the active surface of the semiconductor wafer 10 mounted on the substrate 11, and the pad 101 is used to supply the semiconductor wafer 10 and the substrate. 11 signals are transmitted, and the long solder pads 102 are used to form a ground connection or a power connection between the semiconductor wafer 10 and the substrate 11. Therefore, the substrate 11 is provided with a ground pad (or ground ring) 12 for The long solder pad 102 of the semiconductor wafer 10 is electrically connected to the ground pad (grounding ring) i2 through a plurality of 3 19260D1 201001580 bonding wires 13 , and the bonding wires i3 are repeatedly wired by a wire bonding machine (Wireb〇nder). So that the long solder pad 102 is electrically connected to the grounding ring (grounding ring) 12 ^ It can be seen from the figure that the function of the long soldering pad is to connect a plurality of bonding wires, however, due to the long bonding pad n The area factor is twice that of a typical pad, so the long pad will occupy the available area of the wafer when the area of the wafer is fixed, so that the number of pads on the wafer is reduced. In the meantime, wafers with long pads must have a larger total area to accommodate a larger number of solder pads', however this is inconsistent with the tendency of the wafers to be smaller. Referring to FIG. 2, a schematic diagram of another conventional semiconductor package, which is a semiconductor package of polycrystalline germanium: E, is disclosed as disclosed in US Pat. No. 6, the semiconductor device includes a substrate 21 and a port. And the first wafer 2〇a ^ H 2〇a μ -y ^ - 乂 on the 5th substrate 21 and the second wafer 20b implanted on the first crystal are provided for the first The squadron, the second wafer 20a, 20b is connected to the substrate 21, and the first wafer 2 is used for the second wafer to be applied by the bonding wire 23a = having a long pad 2 〇 2, a sheet 2 〇 a The long solder paste is moved, and the first die is connected to the first crystal turn to be electrically connected to the substrate 21 by the wire bond. ^The long solder pad is moved, but the long-standing multilayer block has the disadvantages of the multilayer die. The electrical connection also has the absence of the former a η fork for a type of bonding wire connection 7, which is urgently needed to improve the rain [invention] The subject of the examination. One object is to identify the defects; the above-mentioned shortcomings of the prior art, the present invention 19260D1 4 201001580 provides a wire bonding method for connecting a plurality of bonding wires at a single joint. It is still another object of the present invention to provide a wire bonding method which increases the usable area of the wafer and saves process cost. Another object of the present invention is to provide a bonding wire bonding method which is in line with the trend of miniaturization of wafers. In order to achieve the above, the present invention discloses a wire bonding method for electrically connecting a plurality of electronic components, comprising: forming a conductive bump before an electrical contact of the first electronic component; and electrically generating electricity from the second electronic component Wire the wire to the conductive bump; then wire the conductive bump to the second electronic component to connect the plurality of bonding wires to the conductive bump, and constitute the first and second electronic components Electrical connection. In the process of implementing the invention, the gold wire is melted into a ball shape by using a wire bonder (Wire bonder) to form a conductive bump (a gold stud) to be electrically connected to the first electronic component. Pointing a ball bond on the electrical contact of the second electronic component, moving the soldering tip to the conductive bump, and then cutting the bonding wire to form a conductive bump a first seam bond, then forming a ball joint on the first seam of the conductive bump by using a wire bonding machine, moving the tip to the second electronic component, and then cutting the solder The wire is formed to form a second seam joint to complete the wire bonding operation between the first and second electronic components. The first electronic component can be a semiconductor wafer, and the electrical contact is a solder pad disposed on the active surface of the semiconductor chip, and the second electronic component can be a substrate, and the electrical contact is disposed on the substrate. Ground pad (ring) or power pad 5 19260D1 201001580 (ring) and so on. The second electronic component can also be a lead frame, and the electrical contact is a ground lead or a wafer holder in the lead frame. The wire bonding method of the present invention can also be applied to the electrical connection between most electronic components, especially the electrical connection between the semiconductor wafer stack structures, including: in the plurality of electronic components. At least one of the electrical contacts is connected to the conductive bump; from the electronic component, an electrical contact of the electronic component corresponding to the conductive bump is wired to the conductive bump; and then the conductive bump is The wire is routed to another electronic component, so that a plurality of bonding wires are connected to the conductive bump to electrically connect the electronic components. In one embodiment, the electronic components are a substrate, a first wafer attached to the substrate, and a second wafer attached to the first wafer. Forming a conductive bump before the first wafer pad, and then wireting the conductive bump from the substrate to the first wafer to form an electrical connection between the first wafer and the substrate, and then wire the second wafer. Conducting bumps to the first wafer to form electrical connections between the first and second wafers. Or forming conductive bumps before the first and second wafer pads, and then bonding the conductive bumps from the substrate to the first wafer by using reverse bonding technology, and wiring the conductive bumps from the first wafer Conducting bumps to the second wafer to electrically connect the substrate, the first and second wafers. In another embodiment, the plurality of electronic components are respectively a substrate and a plurality of semiconductor wafers stacked on the substrate, and the conductive bumps are disposed on the underlying wafer pads from the substrate. The electrical contacts are wired to the conductive bumps of the underlying wafer, and the remaining bumps 6 19260D3 201001580 are wired to the conductive bumps of the underlying wafer for the multilayer wafers placed on the substrate by the bonding wires of the present invention The connection method achieves the electrical connection of the respective layers of wafers and the wafers to the substrates. In addition, conductive bumps may be disposed on the wafers other than the substrate to electrically connect the substrate to the conductive bumps of the underlying wafer by the technique of the reverse bonding process, and then sequentially control the conductive bumps of the underlying wafer. The reverse fresh wire technology wires the conductive bumps of the upper wafer to form an electrical connection between the substrate and the wafer on the stack. Compared with the prior art, it is necessary to connect a plurality of bonding wires with an elongated pad to occupy a usable area of the wafer. With the wire bonding method of the present invention, the wire bonding operation is concentrated on a single conductive bump to not lengthen the wafer. The pad is lifted before the wafer pad can be connected to a plurality of bonding wires, thereby increasing the available area of the wafer. In addition, in order to maintain the number of pads on a wafer with an extended pad, the conventional technology can only design the wafer in a larger size, and the wire bonding method of the present invention does not need to be provided with an elongated pad. It is convenient to connect a plurality of bonding wires to a single pad, so that the wafer can be continuously developed in a small size. Furthermore, the process technology required for the wire bonding method of the present invention can be achieved by existing machine equipment, whether applied to the electrical connection of the wafer to the lead frame or the substrate, or to the electrical connection of the multilayer wafer. Both have good benefits. As can be seen from the above, the wire bonding method of the present invention can improve the conventional disadvantages and save cost, and has a high industrial utilization value. [Embodiment] 7 19260D1 201001580 The following is a description of the embodiments of the present invention by way of a specific example. The person skilled in the art may be accustomed to the 乂1 κ 田本5兄明书The disclosure reveals the advantages and benefits of the present invention. ι First Embodiment Please refer to Fig. 3 to Fig. 3). Fig. 3 is a schematic view showing the first embodiment of the wire bonding method of the present invention. As shown in FIG. 3, the first electronic component is the semiconductor chip I, and the second electronic component is the substrate 31. The first and second lightning electrodes 70 are connected to the second electronic component. The device is provided with electrical contacts, such as a pad 3〇1 formed on the active surface of the δ-Xuan semiconductor wafer 30, and a ground pad formed on the substrate 31. (Can also be a power pad or a power ring), and a conductive bump 34 is formed on at least one pad 301 of the semiconductor wafer. The conductive bump 34 can be mounted into the gold bump (Au Stud). ), which is formed by sintering a gold wire by a wire bonding machine and forming it on a fresh enamel. As shown in Fig. 3B, using the reverse fresh wire technique ((10) · welding the fresh wire from the grounding pad (ring) 32 of the substrate 3! The conductive bumps 34 are soldered to the conductive bumps 34 at a nearly horizontal angle. The soldering wires 33a are gold wires, which are used by a soldering machine 35 of a wire cutter (b〇nder). A ball bond 331a (ball bond) is formed on the ground pad (ring) 32 of the edge substrate 31 by the tip 35, and the tip % is moved to the conductive bump. 34' then cuts the bond wire 33a to form a seam bond 332a to complete the wire bonding operation from the ground rim (ring) 32 on the substrate 31 to the conductive bumps 34 on the semiconductor wafer 30. Please refer to the 3C figure of the wheat, which corresponds to the top view of the 3B figure, and is used to display the first electronic component (semiconductor wafer) placed on the second electronic component (substrate) by 19260D1 201001580. Electrically conductive. As shown in FIG. 3D, a general wire bonding operation is used to weld the bonding wire 33b to the ground pad (ring) of the substrate 31 from the seam solder joint 332a previously formed on the conductive bump 34. 32. The wire bonding operation first forms a ball joint 331b on the seam solder joint 332a of the conductive bump 34, and then moves the tip 35 to the ground pad (ring) 32 of the substrate 31, and then cuts the wire 33b. To form another seam solder joint 332b, the repeating wire bonding operation between the first and second electronic components (wafer and substrate) is completed, as shown in FIG. 3E, which is a top view of the 3D. In addition, due to the first bonding of the semiconductor wafer 30 and the substrate 31 The substrate is wired to the conductive bump 34 by the substrate 31, and is soldered to the conductive bump 34 at a nearly horizontal angle by the bonding wire 33a without affecting the seam welding of the bonding wire 33a subsequent to the conductive bump 34. The process of forming the bonding wire 33b on the point 332a. The second embodiment is shown in Fig. 4, which is a schematic view of the second embodiment of the bonding wire bonding method of the present invention. The second embodiment of the present invention is substantially the same as the first embodiment. The main difference is that in the second embodiment, the second electronic component is a lead frame 41 having a wafer holder 411 and a plurality of guide pins 412 disposed around the wafer holder 41 for, for example, a semiconductor wafer. The first electronic component of the semiconductor device 40 is placed on the wafer holder 411, and the conductive bumps 44 are disposed on the solder pads 401 of the semiconductor wafer 40, so that the bonding wires 43a and the bonding wires 43b are successively used from the guiding frame. The electrical contact, that is, the lead 412 (for example, a ground lead) 9 19260D1 201001580 is electrically connected to the conductive bump 44 of the semiconductor wafer 40, and is electrically connected to the lead 412 from the conductive bump 44. In addition to being a lead, the electrical contact of the leadframe can also be a wafer holder to provide grounding of the semiconductor wafer by the wafer holder. THIRD EMBODIMENT Referring to Figs. 5A to 5C, there is shown a schematic view of a third embodiment of a bonding wire bonding method of the present invention for electrically connecting a plurality of electronic components. As shown in FIG. 5A, the electronic components have a wafer carrier, such as a substrate 51, a first wafer 50a attached to the substrate 51, and a second wafer 50b attached to the first wafer 50a. Electrical contacts such as a ground pad 510, a pad 501a, and a pad 501b are respectively disposed on the substrate 51, the first wafer 50a, and the second wafer 50b, and are sinusoidal on the first wafer 50a. A conductive bump 54 is disposed thereon. As shown in FIG. 5B, next, the reverse bonding wire operation is used to wire the conductive bumps from the electronic components not provided with the conductive bumps, that is, the bonding wires 53a are soldered from the ground pad 510 of the substrate 51 to the The conductive bumps 54 of the first wafer 50a. The reverse wire bonding operation is performed on the ground pad 510 of the substrate 51 by using a soldering nozzle 55 to form a ball bond 531a (ball bond) and then moving the tip 55 to the conductive bump 54 and then cutting the bonding wire. 53a forms a stitch bond 532a to complete the wire bonding operation from the electrical contact of the substrate 51 (the ground pad 510) to the conductive bump 54 of the first wafer 50a. In addition, the electrical contact of the substrate 51 may be a power pad or the like in addition to the ground pad. As shown in FIG. 5C, a ball joint 531b is formed on the pad 501b of the second wafer 50b by using a 10 19260D3 201001580 tip 55, and then the seam welding of the tip 55 to the conductive bump 54 is performed. Point 532a is formed to form a bonding wire 53b, and then the bonding wire 53b is cut to form another seaming pad 532b to form an electrical connection of the second wafer 50b to the first wafer 50a. In addition, the bonding of the first and second wafers 50a, 50b can also be achieved by the technique of the reverse bonding wire process. As shown in FIG. 5D, a bonding pad 501b of the second wafer 50b can be formed. The conductive bump 54' can form a ball joint 531b' on the seam solder joint 532a and be reversed by the ball joint 531b' when the wire bonding between the substrate 51 and the first wafer 50a is completed. The bonding of the first and second wafers 50a, 50b is completed by soldering the bonding wire 53b' to the conductive bump 54' of the second wafer 50b. Fourth Embodiment Referring to Figure 6, there is shown a schematic view of a semiconductor structure formed by a fourth embodiment of a wire bonding method of the present invention. The fourth embodiment of the present invention is substantially the same as the third embodiment. The main difference is that the semiconductor structure has a substrate 61 and a plurality of semiconductor wafers mounted on the substrate 61, including the first wafer 60a on the bottom layer, The second wafer 60b disposed on the younger crystal moon 60a and the third wafer 60c connected to the second wafer 60b form a stepped semiconductor structure. In the semiconductor structure of the multi-wafer stack, at least the conductive bumps 64 are connected to the pads of the first wafer 60a. In this embodiment, the bonding pads 63a are soldered from the electrical contacts of the substrate 61 to the conductive bumps 64 of the first wafer 60a by the technique of reverse bonding wires, and then the ball contacts 65a are formed on the second wafer 60b. And by the ball type contact 65a 11 19260D1 201001580
Kc3 t Kep t /* 1 -7— V X- Α-/Γ β I I ✓* /Λ >_ iir #3½¾ m » /_ A 1—-*» 1 . 1 隹手接隹早、線c>3d至該弟一晶乃〇0a之等電凸现〇4，问稼地， 於該第三晶片60c上形成一球型接點65b，並由該球型接 點65b銲接銲線63c至該第一晶片60a之導電凸塊64，而 使該第一晶片60a所具之導電凸塊64上連接有多條銲線。 應注意的是，本實施例亦可以參照前述第三實施例之 反向銲線製程之技術電性連接各層之晶片，在此一情況下 除了該基板61外各層之晶片均具有導電凸塊。 因此，該多晶片堆疊之半導體結構可藉此銲線連接方 法電性連接各元件，其中所有的半導體晶片皆藉一正常尺 寸之電性連接墊即可同時具有複數條銲線以連接至上層及 下層之半導體晶片。此外，該多晶片之堆壁數目不以本圖 式之3層晶片為限。 再者，前述之多晶片堆疊之半導體結構中亦可使用導 線架作為晶片承載件，並得利用銲線以供堆疊於該導線架 上之複數層半導體晶片電性連接至該導線架之晶片座及導 腳。 相較於習知必須以加長之電性連接墊連接複數銲線 而造成佔用晶片可用面積之現象，藉由本發明之銲線連接 方法，將打線作業集中於單一導電凸塊上，以不加長電性 連接墊之前提下使一電性連接墊可連接多條鲜線，進而增 加晶片之可用面積。 另外，習知技術為了於一具加長電性連接墊之晶片上 保持電性連接墊之數量，只能將晶片以較大之尺寸設計， 而本發明之銲線連接方法，因為不須具有加長之電性連接 19260D1 201001580 墊即可便利地於單一電性連接墊上連接多條銲線，因此晶 片可朝小尺寸化之趨勢持續發展。 再者，本發明之銲線連接方法所需之製程技術以既有 的機台設備即可達成，無論應用於由晶片電性連接至具導 腳之導電裝置或應用於多層晶片的電性連接皆具有良好之 效益。 惟以上所述之具體實施例，僅係用以例釋本發明之特 點及功效，而非用以限定本發明之可實施範疇，在未脫離 本發明上揭之精神與技術範疇下，任何運用本發明所揭示 内容而完成之等效改變及修飾，均仍應為下述之申請專利 範圍所涵蓋。 【圖式簡單說明】 第1A及1B圖係顯示習知技術之銲線連接方法應用 於電性連接晶片與基板； 第2圖係顯示習知技術之銲線連接方法應用於電性連 接具多層晶片之半導體封裝件； 第3A至第3E圖係說明本發明之銲線連接方法之第一 具體實施例； 第4圖係說明本發明之銲線連接方法之第二具體實施 例； 第5A至第5D圖係說明本發明之銲線連接方法之第 三具體實施例；以及 第6圖係說明本發明之銲線連接方法之第四具體實施 例。 13 19260D1 201001580 【主要元件符號說明】 10 半導體晶片 101 一般銲墊 102 長銲墊 11 基板 12 接地環 13 銲線 21 基板 20a 第一晶片 20b 第二晶片 202 長銲墊 23a 銲線 23b 銲線 30 半導體晶片 31 基板 301 銲墊 32 接地墊（環) 33a 銲線 331a 球型接點 332a 缝接銲點 33b 銲線 331b 球型接點 332b 缝接銲點 34 導電凸塊 201001580 . 35 銲嘴 40 半導體晶片 401 銲墊 41 導線架 411 晶片座 412 導腳 43a 銲線 43b 銲線 44 導電凸塊 50a 第一晶片 501a 銲墊 50b 第二晶片 501b 銲墊 51 基板 510 銲線墊 53a 銲線 531a 球型接點 531b 球型接點 532a 缝接銲點 532b 缝接銲點 53b,53b， 銲線 54,54， 導電凸塊 55 銲嘴 60a 第一晶片 201001580 60b /φ ___ « } j 第-—bb Jn 60c 结一曰 弟二曰曰月 61 基板 63a 銲線 63b 銲線 63c 銲線 64 導電凸塊 65a 球型接點 65b 球型接點Kc3 t Kep t /* 1 -7— V X- Α-/Γ β II ✓* /Λ >_ iir #31⁄23⁄4 m » /_ A 1—-*» 1 . 1 hand pick up early, line c> 3d to the other brother of the crystal is 0a, the electric current is convex, and the ball is formed on the third wafer 60c, and the ball joint 65b is welded to the third wafer 60c. The conductive bumps 64 of the first wafer 60a are connected to the conductive bumps 64 of the first wafer 60a with a plurality of bonding wires. It should be noted that the present embodiment can also electrically connect the wafers of the respective layers with reference to the technique of the reverse bonding wire process of the third embodiment. In this case, the wafers of the layers except the substrate 61 have conductive bumps. Therefore, the semiconductor structure of the multi-wafer stack can be electrically connected to each component by a wire bonding method, wherein all of the semiconductor wafers can have a plurality of bonding wires to connect to the upper layer by a normal size electrical connection pad. Lower semiconductor wafer. In addition, the number of walls of the multi-wafer is not limited to the 3-layer wafer of the present figure. Furthermore, in the semiconductor structure of the multi-wafer stack, a lead frame can also be used as a wafer carrier, and a bonding wire is used for electrically connecting a plurality of semiconductor wafers stacked on the lead frame to the wafer holder of the lead frame. And guide feet. Compared with the conventional method, it is necessary to connect a plurality of bonding wires with an elongated electrical connection pad to occupy a usable area of the wafer. With the wire bonding method of the present invention, the wire bonding operation is concentrated on a single conductive bump to not lengthen the electricity. Before the connection pad is lifted, an electrical connection pad can be connected to the plurality of fresh wires, thereby increasing the available area of the chip. In addition, in order to maintain the number of electrical connection pads on a wafer having a long electrical connection pad, the conventional technology can only design the wafer in a larger size, and the wire bonding method of the present invention does not need to be lengthened. The electrical connection of the 19260D1 201001580 pad makes it easy to connect multiple bonding wires to a single electrical connection pad, so the wafer can continue to evolve toward a smaller size. Furthermore, the process technology required for the wire bonding method of the present invention can be achieved by existing machine equipment, whether it is applied to a conductive connection from a wafer to a conductive device with a lead or to a multilayer wafer. Both have good benefits. However, the specific embodiments described above are merely used to illustrate the features and functions of the present invention, and are not intended to limit the scope of the present invention, and may be applied without departing from the spirit and scope of the present invention. Equivalent changes and modifications made to the disclosure of the present invention are still covered by the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B show a conventional method of bonding a wire bonding method for electrically connecting a wafer to a substrate; and FIG. 2 is a view showing a conventional method of bonding a wire bonding method for an electrical connection with a plurality of layers a semiconductor package of a wafer; FIGS. 3A to 3E are diagrams showing a first embodiment of the bonding method of the bonding wire of the present invention; FIG. 4 is a view showing a second embodiment of the bonding method of the bonding wire of the present invention; Fig. 5D is a view showing a third embodiment of the bonding wire bonding method of the present invention; and Fig. 6 is a view showing a fourth embodiment of the bonding wire bonding method of the present invention. 13 19260D1 201001580 [Description of main components] 10 Semiconductor wafer 101 General solder pad 102 Long solder pad 11 Substrate 12 Ground ring 13 Solder wire 21 Substrate 20a First wafer 20b Second wafer 202 Long pad 23a Bond wire 23b Wire bond 30 Semiconductor Wafer 31 substrate 301 pad 32 ground pad (ring) 33a bond wire 331a ball joint 332a seam weld 33b bond wire 331b ball joint 332b seam solder joint 34 conductive bump 201001580 . 35 tip 40 semiconductor wafer 401 pad 41 lead frame 411 wafer holder 412 lead 43a bonding wire 43b bonding wire 44 conductive bump 50a first wafer 501a pad 50b second wafer 501b pad 51 substrate 510 wire pad 53a bonding wire 531a ball joint 531b ball joint 532a seam joint 532b seam joint 53b, 53b, wire 54, 54, conductive bump 55 tip 60a first wafer 201001580 60b / φ ___ « } j first - bb Jn 60c knot One brother, two months, 61, substrate 63a, bonding wire 63b, bonding wire 63c, bonding wire 64, conductive bump 65a, spherical contact 65b, spherical contact