TW200939759A - Solid state image capturing apparatus and camera apparatus - Google Patents

Abstract

A solid state image capturing apparatus is disclosed. A pixel array section has unit pixels containing photoelectric conversion elements, the unit pixels being two-dimensionally arranged in a matrix, and column signal wires correspondingly to columns of the matrix of the unit pixels. A line scanning section selectively controls lines of the matrix of the unit pixels of the pixel array section. An analog-to-digital conversion section converts an analog signal outputted from unit pixels of a line of the matrix of the unit pixels selected by the line scanning section through a corresponding column signal line to a digital signal. A conversion clock supply section selectively generates a conversion clock having a first clock period or a second clock period. An addition section adds unit pixel digital signals converted in the analog-to-digital conversion section by the conversion clocks having the first clock period and the second clock period, respectively.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image capturing device and a photographic device having a solid-state image capturing device, and in particular to converting an analog signal outputted from a unit pixel through a line signal conductor into a digital position. The present invention contains the subject matter of the Japanese Patent Application No. JP 2008-051365, filed on Jan. 29, 2008, the entire entire content of . [Prior Art] In recent years, a CMOS image sensor equipped with a row parallel ADC has been proposed. In this CMOS image sensor, an analog-to-digital converter (hereinafter abbreviated as an ADC) is arranged corresponding to a row of a matrix of unit pixels. 1 is a block diagram showing a structure of a CMOS image sensor 1A equipped with a row parallel adc. In Fig. 1, a unit pixel 101 has a photodiode and an in-pixel (in_pixel) amplifier. The elements 101 are two-dimensionally arranged in a matrix shape and constitute a pixel array section 102. The line control wires 103 (103-1, 103-2, etc.) and the row signal wires 104 (104-1, 104-2, etc.) are individually configured with individual lines for the matrix shape pixel arrangement of the pixel array section 102. And individual lines. The line address and line scan of the pixel array section 102 are controlled by the line scanning circuit 1〇5 through the line control lines 1〇3-1, 1〇3_2 and the like. ADCs 1 〇 6 corresponding to the row signal conductors 104-1, 104-2, etc. are arranged on one end side of the respective row signal conductors, and constitute a row of processing sections 135444.doc 200939759 (row parallel ADC block) 1 07. A digit to analog converter ι 8 (hereinafter referred to as a DAC) for generating a ramp waveform reference voltage Vref of the ADC 106 is arranged. In addition, a counter 1 〇 9 is arranged for the ADCs 106. The counter 1 〇 9 is synchronized with a clock having a predetermined period ′ and a time of a comparator 110 is measured, which will be described later, for performing a comparison operation. The ADC 106 has the comparator 11A, which compares an analog signal and a DAC obtained by selecting one of the line unit pixels 101 from one of the matrices via the row signal conductors 104-1, 104-2 or the like. A ramp waveform reference voltage Vref generated by 108. In addition, the ADC 106 has a memory lu that stores a count value of the counter 1〇9 based on a comparison output of the comparator 110 to provide conversion of an analog signal supplied from the unit pixels 101 into an N-bit. A function of a digital bit signal. The row address and line scan of the ADC 106 of the row processing section 107 is performed by a row of scanning circuits 112. In other words, the N-bit digital signal digitally converted by the ADCs 106 is scanned by the row scanning circuit 12, read by a horizontal output conductor 113 having a 2N bit width, and is output by a horizontal output conductor. 113 is passed to a signal processing circuit 114. The signal processing circuit 114 is constituted by 21 < [sensing circuit, 2N subtracting circuit, 2N output circuit, etc. corresponding to the 2N-bit wide horizontal output wire 113. A timing control circuit 115 generates a clock signal and a timing signal based on a main clock MCK, and the line scan circuit 105, the ADC 106, the DAC 1〇8, the counter 1〇9, the line scanning circuit 112, and the like This operates. The clock signal and timing signal generated by 5 荨 are supplied to the relevant circuit area 135444.doc 200939759. Next, the operation of the CMOS image sensor 10 shown in Fig. 1 will be outlined with reference to the timing charts shown in Figs. 2A to 2C. Figure 2A shows a horizontal sync signal (H sync). Figure 2B shows a clock supplied to the DAC 108 and the counter 1〇9. Figure 2C shows a ramp waveform reference voltage Vref output from the DAC 108. When the clock occurs, the voltage of the ramp waveform changes. The voltage of the ramp waveform is compared to the output of one unit pixel. The count value corresponding to the voltage of the unit pixel obtained by the comparison is stored in a memory i 1 i. The count value stored in the memory lu becomes a digit value of the unit pixel, and is output. 3A to 3F are timing charts showing an example of a more detailed operation of the image sensor 1 。. Referring to FIG. 3A to FIG. 3F, a unit pixel from a selected line has been established. After the first read operation of the 1-to-1 row signal conductors 104-1, 104-2, etc., a ramp waveform reference voltage Vref shown in FIG. 3A is supplied from the DAC 1〇8 to the comparator 110. The comparators 丨1〇 compare the signal voltages Vx of the row signal conductors 104-1, 1〇4·2, etc. with the reference voltage Vref. In this comparison operation, when the reference Vx becomes the signal voltage Similarly, the polarity of the output of the comparator 110 is inverted. When the output of the comparator 11 is inverted, the memory 111 stores a count value of the counter 109 corresponding to the comparison time of one of the comparators 110. Figure 3C shows a clock that produces a count value. Figure 3D shows the change in count value N. In this first read operation, as shown in Figure 3E, each unit image is read 135444.doc 200939759 The reset component Δν of 10 1. The reset component Δ contains a fixed type of noise that varies with the unit pixel i 01 , α acts as an offset, however, the fluctuation of the reset component is generally small, and in all pixels, the reset level is common. Therefore, in the first read operation, Yan Hai The signal voltage Vx of each of the equal-line signal wires is almost known. As a result, when the reset component Δν is read in the first read operation, by adjusting the ramp waveform reference voltage Vref, it is relatively Shortening the comparison time of the comparator 110. In the second reading operation, in addition to the reset component Δν, a signal component corresponding to the amount of incident light of each of the unit pixels 101 is associated with the first The reading operation is read in the same manner. In other words, after the first reading operation from the unit pixel 101 of the selected line to the row signal lines 104-1, 104-2, etc. has been established, the ramp waveform is The reference voltage %^ is supplied from the DAC 108 to the comparator 11. The comparators u〇 compare the signal voltages of the row signal conductors 104-1, 1〇4·2, etc. with the reference voltage Vref. When the reference voltage Vref is supplied to the comparators n ,, The counter 109 performs a second counting operation. In the second counting operation, when the reference voltage Vref becomes the same as the reference voltage vx, the polarity of the output of the comparator 110 is inverted. When turning, as shown in FIG. 3F, the memory 1U stores a count value N2 of the counter 109 corresponding to one of the comparison times of the comparators 11. At this time, the first count value N1 and the second count value The N2 system is stored at different locations of the memory 1. After the foregoing sequence of the AD conversion operations has been completed, the row scanning circuit 112 scans the respective rows. As a result, the first and 135444.doc 200939759 second N-bit digital signals stored in the memory u are supplied to the k-th processing circuit 114 through the 2N wide horizontal output line U3. A subtraction circuit (not shown) of the signal processing circuit 114 performs a subtraction process of the (second operation signal)_(first operation signal) and thereafter outputs the resultant signal to the outside of the CMOS image area 10. Thereafter, the same operation is repeated for each line, and thereby a two-dimensional image is produced. The unexamined Patent Application Publication No. 2005-278135 (hereinafter referred to as Patent Document 1) describes one of the solid states shown in FIG. An example of an image capture device. SUMMARY OF THE INVENTION In order to capture an image at a high speed, a technique of reading pixel information while performing miniaturization to improve the frame rate can be used. Using this technique, the frame rate can be improved from 30 frames per second to 6 frames per second in a full pixel reading system that reads signals for all pixels in a frame. In other words, if the pixel information of the output is read and reduced every other line, and the number of lines to be subtracted is reduced by this, the frame rate can be doubled. When the pixels are reduced, for example, a technique of reducing them in the vertical direction and a technique of adding pixels in the vertical direction are simultaneously reduced, and the resolution in the vertical direction is reduced. For example, it is assumed that, as shown in FIG. 4, a pixel R having a red filter and a pixel G having a green filter are alternately arranged in the vertical direction as a unit pixel of the CMOS image sensor 1 A vertical configuration of 〇1. This configuration is an example of one of the main color Bayer configurations of color filters. Assuming that the number of pixels in the vertical direction is reduced to 1/2 of the original number, the signals of two adjacent I35444.doc 200939759 pixels R are simply added, and thereby an added pixel signal Rx is generated. Similarly, the signals of two adjacent pixels G are simply added, and thereby an added pixel signal Gx is generated. The spatial position of the center of gravity of the added pixel signal Rx or the added pixel signal Gx is added to the intermediate position β of the two pixels R or the two pixels G. However, as shown in FIG. 4 The equal red pixel R and the green pixels G are alternately arranged, and the spatial position of the center of gravity of the added pixel signal Rx and the added pixel signal Gx becomes irregular. In other words, when the spatial position of the added pixel signal Rx and the center of gravity of the added pixel signal Gx shown in the right hand side of the upper inspection view 4 are arranged, the first signal is separated from the (^) The system is very short, and the first letter is similarly long, and the interval between the interval Gx and the second signal 1 is long. Alternately becomes short, long, short, long, etc. If the direction is 4 in the vertical direction The two pixels are simply added together, and the pseudo-color may be disadvantageously present in the resulting added signal. The example will be explained in the following specific embodiment. A paradigm of the appearance of false colors. In short, it can be said: 'Can say: when

In the pixel signal where the color is greatly changed.

The image signal causes degradation of its image quality.

135444.doc 200939759 to digital conversion section, a conversion clock supply section, and an addition section. The pixel array section has unit pixels including photoelectric conversion elements which are two-dimensionally arranged in a matrix, and the row signal conductors are arranged corresponding to the matrix of the unit pixels. The line scan segment selectively controls the line of the matrix of unit pixels of the pixel array segment. The analog-to-digital conversion section converts an analog signal to a digital signal, and the analog signal is output from a line of the matrix of the unit pixels of the selected iH from the line scan section through a corresponding row signal line. Unit pixel. The conversion clock supply section selectively generates a conversion clock having a first clock period or a conversion clock having a second clock period supplied to the analog to digital conversion section, and one has been generated The conversion clock is supplied to the analog to digital conversion section. The addition sections are separately added to the unit pixel to digital signal converted by the conversion clock of the first clock period and the second clock period in the analog to digital conversion section, and output a phase Add a pixel signal. According to an embodiment of the invention, there is provided a photographic apparatus comprising the solid state image capture device and an image signal processing section. The image signal processing section processes the digital signal output from the addition section to become an image signal having a predetermined format. According to a specific embodiment of the present invention, when the analog-to-digital conversion block digitally converts a unit pixel signal, # is a pixel signal converted by an analog-to-digital conversion section driven by a clock having a first-clock period And alternately switching by a pixel signal system converted by an analog digital conversion section having a clock pulse different from the first clock period of the first clock period. Obtained. The converted digital signals are weighted differently when the clock cycles are changed. Therefore, when the addition section adds a signal having the first clock period "clock digital conversion" to a signal converted by the clock having the second clock period, the plurality of differently The weighted pixel signals are added. As a result, the position of the center of gravity of the added signal can be shifted from the position of a simple summed signal. ❹

According to a specific embodiment of the present invention, when the addition section adds a signal having a clock digital conversion of the first clock period to a signal having a clock digital conversion of the second clock period , adding a plurality of pixel signals that are weighted differently. As a result, the position of the center of gravity of the added signal can be shifted from the position of a simple summed signal. Therefore, the unit pixels can be configured to prevent false colors from being prevented. As a result, the specific embodiment of the present invention exerts an effect of improving image quality once the number of pixels to be read is reduced and thereby the frame rate is improved. [Embodiment] Next, a first specific embodiment of the present invention will be described with reference to Figs. 5 to 1B. In Figs. 5 to 10, sections similar to those of Figs. 1 to 4 are denoted by like reference numerals, and the description thereof will be omitted. Fig. 5 is a schematic view showing an example of the structure of a solid-state image capturing device according to this embodiment. Like the solid-state image capturing device according to the prior art shown in FIG. 1, the solid-state image capturing device according to this embodiment is a CMOS image sensor equipped with a row-parallel ADC having a matrix corresponding to one of the unit pixels. Analog to digital conversion (ADC) section. 135444.doc -11 - 200939759 The CMOS image sensor 100 equipped with the row parallel ADC has unit pixels 101, each of which constitutes a pixel. Each of the unit pixels 101 has a photodiode and an in-pixel amplifier. The unit pixels 101 are two-dimensionally arranged in a matrix shape and constitute a pixel array section 102. The matrix shaped pixel arrangement of the pixel array section 102 provides line control conductors 103 (103-1, 103-2, etc.) corresponding to individual lines of the matrix; and row signal conductors 104 (104-1, 104-). 2, etc., which corresponds to individual rows of the matrix. The line address and line scan of the pixel array section 102 are controlled by the line scan circuit 105 through the line control lines 103-1, 103-2 and the like. The ADCs 120 corresponding to the row signal conductors 104-1, 104-2, and the like are disposed on one side of the respective signal conductors, and constitute a row of processing sections (row-by-parallel ADC blocks) 107. A digital analog converter (hereinafter referred to as DAC) 108 is arranged which generates a ramp waveform reference voltage Vref for each of the ADCs 120. Each of the ADCs 120 corresponding to the respective rows supplied by the output of the DAC 108 has a comparator 11A, and a counter κι, which measures the time of the comparator 110 to perform a comparison operation. Each row of comparators 110 compares a ramp waveform supplied from the DAC 108 with a signal of a respective unit pixel of the matrix. The counter 121 performs a counting operation in synchronism with a clock supplied from a frequency divider 116 (serving as a switching clock supply section) (to be described later), and measures the time of the comparator 11 以 to perform a comparison. The count value N of the measured time is operated, latched, and the count value N is output. In this embodiment, the counter 121 performs the counting operation and the latching operation. Instead, a 135444.doc -12-200939759 latch circuit or a memory circuit storing the counter output of the counter can be arranged separately from the counter 121.

In this embodiment, a timing control circuit 115, which constitutes a digital conversion clock supply section, supplies a clock to the DAC 108 and the counter 121 via a frequency divider U6. The frequency divider 116 selectively divides the clock frequency under the control of the timing control circuit 115 to change the clock frequency. The frequency divider 116 changes, for example, the frequency of the clock signal output from the timing control circuit 5 to a clock signal having a frequency which is one of the inverse of one of the original frequencies. Instead, the frequency of the clock can be changed to a frequency other than the reciprocal of one of the two of the original frequencies. The state in which the frequency divider 11 ό changes the state of the clock frequency or does not change the clock frequency is set under the control of the timing control circuit 115 for the mother-sampling period of the unit pixels 10 1 . However, the process of changing the clock frequency is performed when the vertical direction is reduced by the unit pixel signals. When the pixel signals are not reduced in the vertical direction, the clock system is fixed at a frequency. The state of changing the clock frequency will be explained later. The clock generated in this manner is supplied to the DAC 108 as a ramp waveform generating clock, and supplied as a count operation clock to each of the counters 121 corresponding to the individual lines. Each of the ADCs 120 corresponding to the individual rows has a comparator 110' that compares an analogy of the unit pixels 101 obtained from one of the selected lines of the matrix through the row signal conductors 104-1, 104_2 or the like. The signal is associated with the reference voltage Vref. In addition, each of the ADCs 120 has a counter 121 that performs a count 135444.doc • 13· 200939759 operation in synchronization with the clock CK supplied from the frequency divider 116. The counter 121 measures a time of the comparator 110 to perform the comparison operation, latches a count value N of the measured time, and outputs the count value N to convert an analog signal supplied from a unit pixel 101 into a N Bit digital signal. The row address and line scan of the ADC 120 of the row processing section 107 is controlled by a row of scanning circuits 112. In other words, an N-bit digital signal converted by each of the adcs 120 is read by the row scanning circuit 112 into a 2N-bit wide horizontal output conductor 113 and transmitted through the horizontal output conductor 113. It is transmitted to a signal processing circuit 114 (serving as an addition section). The signal processing circuit 114 is constituted by a 2N sensing circuit, a 2N subtracting circuit, a 2N output circuit, and the like corresponding to the 2N-bit wide horizontal output wire 113. An image signal processed by the signal processing circuit 丨4 is output from an output section 1. Based on the main clock MCK, the timing control circuit 115 generates a clock signal and a timing signal for operating the X-ray scanning circuit 1〇5, the ADC 12〇, the line scanning circuit, and the like, and Supply to the DAc 108 ^ the clock of the #121. The generated clock signals and timing k are supplied to the corresponding circuit segments. Figure 6 is a schematic diagram showing an example of an array of pixels ^ 〇 1 \ of the CMOS image sensor. Figure 6 shows a P-plate of the array of pixels 1 〇 1 and the array shown in Figure 6 is repeated for the number of pixels. The color filter array shown in the figures illustrates the signal levels obtained from individual pixels of the primary color array. The square of Figure 6 shows the position of the unit pixel, the scale shown in the individual squares, and (10) represents the type of the color filter: 135444.doc -14- 200939759 Red, Green and Blue "by each of R, G and B The two leading digital values represent the position of the pixel. The left digital value represents the vertical pixel position counted from the topmost position of the array, and the right digital value represents the horizontal pixel position counted from the leftmost position of the array. For example, the pixel "R35" indicates that the color shirt of the filter is red, and the pixel is in a third vertical position from the top and a fifth horizontal position from the left side. • In the example shown in Figure 6, a digital value below R, G, or B represents the signal level of light received from that pixel. This signal level represents a value that has been digitally converted by the corresponding ADC 120 shown in FIG. If the adc 12 is an 8-bit converter, the signal level of each unit pixel ranges from "〇" to "255". In Fig. 6, there are pixels of the signal level system "〇" and "1〇〇,. In the state shown in Fig. 6, the signal level is greatly changed from "1〇〇" to "〇" between the leftmost third and leftmost fourth pixels in the horizontal direction. In the region where the signal level is largely changed, the pixel signals are difficult to accurately interpolate by subtracting them, and as described in "Invention", pseudo color Q colors tend to appear. Figure 6 illustrates the case where the signal levels change in the horizontal direction. Pseudo-colors tend to appear more often in the case where the signal levels change in the vertical direction. In this embodiment, the structure shown in Fig. 5 is used to complete the processing for effectively preventing the occurrence of false colors. Next, a process for preventing the occurrence of pseudo colors will be exemplified. 7A to 7E are timing charts showing the operational state of the CM〇s* image sensor shown in Fig. 5. The timing chart shown in Fig. 7A to Fig. exemplifies the operational state of the image sensor 135444.doc -15-200939759 in the case where the pixel is reduced in the vertical direction. Fig. 7A shows a horizontal synchronizing signal (Η sync). Figure 7B shows a clock supplied to the DAC 108 and the counters 〇9. Figure 7C shows the type (dl or d2) of the clock supplied to the DAC 108 and the counters 121. Figure 7D shows a ramp waveform reference voltage Vref output from the DAC 108. The voltage of the ramp waveform changes synchronously with the occurrence of a clock. The voltage of the ramp waveform is compared to the output of one unit pixel. Detect corresponding in this comparison

A count value of the voltage of the unit pixel is stored by the counter 12 。. The count value stored by the counter 121 becomes a digit value of the unit pixel, and is output. Although the change of the count value of the counter i2i is not shown in Fig. 7A to Fig. 3, the processing for changing the count value shown in Figs. 3A to 3F can be applied. In other words, as shown in Fig. 3D, in each of the reset component (four) period and the one-pixel signal component detection period, the count value is counted up. Therefore, in the - horizontal synchronization period, the count value can be counted up twice. Instead, the count value can be counted up in another way, as will be explained later. Returning to the description of FIGS. 7A to 7E, as shown in FIG. 7C, for each horizontal period, a clock heart having a first clock cycle or a clock d2 having a second clock cycle is selected as An output of the frequency divider ιΐ6. Fig. 7C shows an "example" of the case where the frequency divider 116 selects the first clock period for the horizontal synchronization period and selects the second clock period for the next two horizontal synchronization periods. Therefore, there are two state high frequency states and a low frequency state 135444.doc -16 · 200939759 state which are supplied to the clocks of the DAC (10) and the counters 121 as shown in Fig. 7B. Similarly, when changing the clock frequency, there are two states of the ramp signal: a high resolution state and a low resolution state. However, for each line 'fixed data phase range' and only the resolution is changed. In this manner, the ramp waveform is supplied to the comparator 110' of each ADC 12'' and compared to the unit pixel signal. The comparison output has a counter value of the changed counter and is stored. Therefore, the stored value becomes a signal weighted according to the clock period. The value stored in the counter m is output as the - digit value of the unit pixel. The signal processing circuit 114 adds the signals of adjacent pixels of the same color filter. The output section 117 outputs the obtained added signal. In the example shown in Figs. 7A to 7E, the ADC 120 of a specific line processes a red (R) unit pixel signal in the first horizontal synchronization period on the leftmost side. In the next horizontal sync period, the ADC 120 processes a green (G) unit pixel signal. In the next horizontal sync cycle, the ADC 12〇 processes the red (R) unit pixel signal. In this case, as shown in Fig. 7E, two red (R) unit pixel signals separated by a horizontal synchronization period are added. In addition, the two green (G) unit pixel signals separated by a horizontal synchronization period are added. The two added signals are signals that have been digitally converted at different resolutions. Therefore, the already added signals have been weighted. When all the unit pixels 1〇1 of the pixel array section 1〇2 are read (that is, the pixels are not added), the clock system shown in FIG. 7B is fixed at a high frequency, and thus in this case The resolution of the ramp waveform does not change. Figure 8 illustrates a vertical addition state of this embodiment. As a vertical array 135444.doc ‘17- 200939759 column of the unit pixel 1〇1 of a CMOS image sensor in a vertical ,1, a red filter pixel scale and a green filter pixel G are assumed to be arranged. This array is the same as that shown in Fig. 4. If the number of pixels is reduced to half in the vertical direction, the signals of two adjacent pixels R are added 'and the generated-added pixel signal Ra is generated. Similarly, the signals of two adjacent pixels G are added, and an added pixel signal Ga is generated.

Since the two pixel signals are differently weighted before the addition, the added pixel signal Ra and the added pixel signal (the spatial position of the gravity center of the ^) deviate from the gravity of the simple addition signal shown in FIG. The position of the center. In the example of shifting the spatial position of the added pixel signal Ra and the center of gravity of the added pixel signal, it is displayed on the right hand side of FIG. 8, and the pixel signal Ra is added The interval L of the spatial positions of the center of gravity of the added pixel signals is almost equal. It is necessary for the U field to select the frequency of the two clocks output by the frequency divider 116 so that the intervals L are several turns; (a # AL 1戍干相相. However, if compared with the one of the prior art, Figure 4 does not look at the P-Bud U3 ^

At equal intervals, the spacing L of the spatial positions of the center of gravity is closer to the equally spaced intervals, thus preventing false colors. Therefore, the equal spacing of the spatial locations of the center of gravity is not a condition for obtaining the effects of this particular embodiment. Therefore, the pixels are added in accordance with this embodiment so that the positions of the centers of gravity of the added pixel signals are almost (four), and thus the pseudo color can be effectively prevented. As a result, the image quality of the captured signal is improved. In this case, the CMOS image can be provided to the prior art image sensor by using the frequency divider 丨i 6 by the sensor 1i 6 Moving a control 135444.doc -18- 200939759 The frequency division of the crossover HU6 is achieved with a relatively simple structure. In the foregoing specific embodiment, the positions of the added unit pixels are merely an example. Therefore, the present invention is not limited to this addition structure. Furthermore, in the foregoing specific embodiment, two types of clock cycles (clock frequencies) are provided for selection. Instead, three or more clock cycles may be provided, and it may be appropriate to *select 'to make the spatial positions of the added images nearly equally spaced. • In addition, in the description t with respect to Figs. 7A to 7C, the count value of the counter 121 is counted up in each of the reset component price measurement period and the pixel signal detection period. Instead, another count state can be selected. For example, in each of the reset component detection period and the pixel signal detection period, the count value may be counted down. Alternatively, the count value may be counted down in the reset component detection period and counted up in the pixel signal detection period. Further, in a plurality of vertical synchronization periods, the count value may be continuously counted up or down. In the foregoing description, an output of the counter 121 of the ADC 120 is read by the signal processing circuit 114, and the signal processing circuit ι4 adds a plurality of unit pixel signals. Alternatively, a plurality of unit pixel signals can be added to the ADC 120 (or immediately after outputting it from the ADC 12〇). For example, the latch section of the counter 121 can store a plurality of pixel signals and will These unit pixel signals are added. Next, an example of the structure of a photographing apparatus having a CMOS image sensor i of the first embodiment of the present invention will be described with reference to FIG. In this example, the CMOS image sensor 1 获得 obtains a captured image signal based on image light entering the CMOS image sensor 100 through an optical system 201 such as 135444.doc 19 200939759. The acquired captured image signal is supplied as a signal output from the signal processing circuit 114 to a downstream image signal processing section. In this example, an image signal output from the signal processing circuit 114 is supplied to a still image signal processing section 202 or a moving image signal processing section 203. The still image signal processing section 2〇2 and the moving image signal processing section 203 perform image signal processing to separately process image signals into the predetermined still image and moving image format. An image signal processed by one of the processing sections 202 and 203 is stored in a storage section (recording section) 204. The processing from the image capture processing to the storage processing is performed under the control of a control section 205. Figure 10 is a flow chart showing an example in which the control section 205 of the photographing apparatus shown in Figure 9 controls the operation of the CMOS image sensor 100 in accordance with the capture mode. First, when capturing an image, the control section 2〇5 determines that the current image capture mode is a low frame rate (eg, 3〇fps) mode for still image capture, or a high for moving image capture. a frame rate (for example, 6 〇 fps) mode (in step SI ip, if the determined result indicates that the current mode is the low frame rate mode, the control section 205 is fixedly supplied to the DAC 1 〇 8 and the Waiting for the period of the clock of the counter i2i (at step 812), outputting all the unit pixel signals, and obtaining an image signal (in step s 13). If the current mode is the high frame rate mode &lt;, the control area The segment 2〇5 changes 135444.doc -20- 200939759 to the period of the clock of the DAC 108 and the counters 121 (in step S14), and outputs a small number of unit pixel apostrophes caused by the addition of unit pixels, And obtaining an image signal (in step S15). Since the frequency of the clock in the CMOS image sensor 100 is changed depending on the mode set in the photographing device, it is obtained that an image can be appropriately captured in each mode. An effect. - A person, a second embodiment of the present invention will be described with reference to Fig. 11. In Fig. 11, the sections corresponding to Figs. 1 and 8 are denoted by like element symbols. In this embodiment, A so-called top/bottom read type image sensor is provided. One row of processing sections 1 〇 7a is arranged on the upper side of a pixel array section i 〇 2, and a row of processing sections 〇 7b is arranged in the pixel array area The lower processing section 107a has an ADC 120a that digitally converts signals of every other vertical line. Each of the ADCs 120a has a comparator 110a and a counter i2ia for The digital processing section 107b has an ADC 120b that digitally converts signals that are not supplied to every other vertical line of the upstream processing section 107a. Each of the ADCs 120b has a comparator 110b. And a counter mb for the digital bit conversion process. A DAC 108 supplies a ramp waveform to the comparator 110a of the upstream processing sector 丨0% and the comparator 〇 〇b of the downstream processing section 107b. Frequency divider 116 will supply a clock The counter 135444.doc • 21 · 200939759 state 121 a and the counter 丨 2 丨 b of the downlink processing section 1 〇 7b to the upstream processing section 107a. The clock is supplied to the DAC through the frequency divider 116 108 and the counters 21b. The frequency dividers 116 are operated under the same conditions as the first embodiment. In this embodiment, the row scanning circuits 丨丨2&amp; and 丨丨2b are respectively Arranged on the top and bottom of the CMOS image sensor. A signal output from the horizontal output conductor 丨丨3 a on the upstream processing section 1 〇 7a side and a signal output from the horizontal output conductor 113b on the downstream processing section 1 〇 7b side are supplied to a signal processing circuit 114. '(as an addition section)' to form an image signal of a frame. The image signal processed in the signal processing circuit 丨j 4 is output from an output section 丨17. The other structure of this second embodiment is the same as the CMOS image sensor 100 shown in FIG. In this top/bottom read type CMOS image sensor, the same effect as the first embodiment is obtained by changing the clock frequency when pixels are added, thereby preventing the occurrence of false colors, and Improve image quality. The top/bottom reading structure shown in Figure 11 is merely an example. Therefore, the structure of this embodiment is not limited to that shown in the drawings. In Fig. i, the unit pixels of the respective lines (vertical lines) are alternately read by the upper and lower processing sections. However, various types of top/bottom reading structures that have been proposed or actually used can be applied. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur, depending on the design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more fully understood from the following detailed description of the appended claims <RTIgt; 1 is a schematic diagram showing an example of the structure of a solid-state image capturing device according to a prior art; FIG. 2A to FIG. 2C are timing charts showing the signal output operation of the solid-state image capturing device shown in FIG. FIG. 3A to FIG. 3F are timing diagrams showing an example of a signal output operation of the solid-state image capturing device shown in FIG. j in more detail; FIG. 4 is a schematic diagram showing a pixel according to a prior art. An example of addition; FIG. 5 is a schematic diagram showing an example of the structure of a solid-state image capturing device according to a first embodiment of the present invention; FIG. 6 is a schematic diagram showing the first embodiment according to the present invention. An example of a pixel configuration of a solid-state image capturing device of a specific embodiment; &amp; FIGS. 7-8 to 7E are timing charts showing the first device according to the present invention An example of a signal output operation of the solid-state image capturing device of the embodiment is shown in FIG. 8 as a schematic diagram showing an example of pixel addition according to the first embodiment of the present invention. FIG. 9 is a schematic diagram showing An example of the structure of a photographing apparatus of a first embodiment of the present invention; FIG. 10 is a flowchart showing an example of processing of a mode of a photographing apparatus according to the first embodiment of the present invention; Figure 11 is a schematic view showing an example of the structure of a solid state capture device according to a second embodiment of the present invention 135444.doc -23.200939759. [Main component symbol description]

10 CMOS image sensor 100 CMOS image sensor 101 unit pixel 102 pixel array section 103-1, 103-2 line control conductor 104-1, 104-2 row signal conductor 105 line scan circuit 106 analog to digital converter 107 line processing section 107a, 107b row processing section 108 digital to analog converter 109 counter 110 comparator 110a, 110b comparator 111 memory 112 row scanning circuit 112a, 112b row scanning circuit 113 horizontal output conductor 113a, 113b horizontal output Wire 114 Signal Processing Circuit 114' Signal Processing Circuit 115 Timing Control Circuit 135444.doc -24- 200939759 116 Frequency Divider 117 Output Section 120 Analog to Digital Converter 120a, 120b Analog to Digital Converter 121 Counter 121a, 121b Counter 201 Optical System 202 Still Image Signal Processing Section 203 Moving Image Signal Processing Section 204 Storage Section 205 Control Section Reference 135444.doc -25-

Claims (1)

200939759 VII. Patent application scope: 1. A solid-state image capturing device, comprising: a pixel array segment having unit pixels including photoelectric conversion elements, wherein the unit pixels are two-dimensionally arranged in a matrix, and a signal conductor is configured corresponding to a row of the matrix of the unit pixels; a line scan segment configured to selectively control a line of the matrix of the unit pixels of the pixel array segment; a digital conversion section configured to convert an analog signal to a digital signal, the analog signal outputting a line of the matrix selected from the line scan section through the corresponding row signal line a unit pixel; a conversion clock supply section configured to selectively generate a transition clock having a -first clock period for the analog to digital conversion section or having a second time a transition clock of the pulse period, and supplying a generated conversion clock to the analog to digital conversion section; and, like an addition section, the system Conversion unit pixels during respective clock cycles by adding Shore having a first clock cycle and the first class than to the r-digital conversion section converts the pulse of the digital signal, and outputting a phase is added to the pixel signals. 2. The solid-state image capturing device of claim 1, wherein in the pixel array section, color filters of a plurality of colors are arranged in a predetermined order for respective unit pixels, and wherein the first color is separately included The unit pixel digital signals converted by the pulse period and the transition clock of the second clock period are configured to have the signals of the unit pixels of the color filter of the same color. 3. The solid-state image capturing device of claim 2, wherein a spatial virtual position of the added signal of the unit pixel of the color filter configured with the first color added by the addition section, and the addition area The spatial position of the added signal of the unit pixel of the color filter in which the second color filter has been added is almost equally spaced. 4. The solid-state image capture device of claim 3, wherein the conversion clock supply section has a frequency divider configured to convert the conversion clock having the first-clock period to have the The transition clock of the second clock cycle. 5. A photographing apparatus comprising: a pixel array section having a unit pixel containing a photoelectric conversion element; the unit pixel systems are two-dimensionally arranged in a matrix, and the row signal conductors correspond to the unit pixels The row of the matrix is configured; a line scan segment configured to selectively control a line of the matrix of unit pixels such as shai of the pixel array region; an analog to digital conversion segment Converting the analog signal to a -number (four)', the analog signal output is free from the line scan segment through which the unit pixel of the matrix of the unit pixels selected by the corresponding row signal line is selected; a section configured to selectively generate a transition clock having a first clock period or a transition clock having a second clock period supplied to the analog to digital conversion section, and A generated conversion clock is supplied to the analog to digital conversion section; 135444.doc 200939759 Addition section 'which is configured to be separately added in the analog to digital conversion zone The unit-pixel digital signal converted by the conversion clock of the first clock and the second clock period, and outputs an added pixel signal; and the image ## processing area@, which is configured The image signal outputted from the addition section is processed to become an image signal having a predetermined format. 6. The photographing apparatus of claim 5, wherein when the addition section does not add the digit signals, the conversion from the conversion clock supply section to the analogy to the digit conversion section is performed. Trusging in the first clock cycle, and when the summing section increases the number S ° υ 4, the switching clock supply section selectively generates the first clock cycle and the second respectively These transition clocks of the clock cycle 0 135444.doc