200939444 九、發明說明： 【發明所屬之技術領域】 本案係指一種積體電路，特別是一種用於靜電放電防護的積 體電路。 【先前技術】 目前使用橫向擴散金屬氧化物半導體(Laterally diffused metal ❹ oxide semiconductor，LDMOS)製程所製造的積體電路，基本上是利 用其本身驅動器（driver)的大面積，而做靜電放電(Electr〇statie Discharge，ESD)防護，一般而言ESD的防護效果均不佳。因 LDMOS元件的結構不易誘使寄生於LDM〇s的雙極性接面電晶 體路徑(BJTpath)動作。而且開放式沒極輸入/輸出(〇penDrainI〇) 元件更是因為僅有單一路徑到接地端，更是不容易做ESD防護。 目前大多數採用磊晶層(Epitaxial layer)加上N型埋層，來誘使寄生 於LDMOS的雙極性接面電晶體路徑(BJTpath)動作，以提昇esd Q 防護的層次。 第一圖為習知技術之橫向擴散金屬氧化物半導體元件之靜電 放電的電流走向示意圖。請參閱第一圖，當汲極12與源極14之 間的距離d值較小時，咖電流先走第⑴路徑，即橫向的雙極性 路徑(此沉&11^〇131^对11)，再引發走第(2)路徑，即垂直向的雙極性 路徑(vertical bipolarpath) ’此時ESD電流經過^^型井區1ό，流到 Ν型埋層18，再經Ν型井區16，流到源極14 ;當d值較大時， 200939444 則ESD電流只走第⑴路徑，即橫向的雙極性路徑卿以 bipolar path) 〇 - ㈣蟲晶81較為昂貴許多，因此利縣晶層加上N型埋層的 解決方案，雖然較僅僅利用驅動器具有大面積的方法，在ESD防 護效杲上改善許多，但仍械本太高㈣題，因此有必要開發其 他技術的解決方案，以同時具有優異的咖防護效果及較經濟的 製造技術。本發贿域_概念與解決方法，财效解決上述 〇 問題，大幅降低生產成本。 【發明内容】 屬為提供—種積體電路，其包括第—橫向擴散金 , i體’其具有第一深N型井區與受該第-深N + ^辰度影響的第—受控制路# ;及第二橫向擴散 金屬氧化物半導體電晶體，其具有第二㈣型井區與受該第= Ν财區之第二摻雜濃度辟料二餘 0 Γ路㈣聯於該第-受控制路徑，該第-受控制==二 又控制路徑具有相同的類型但具有不同 Ν型與Ρ型其中之一。 鄕質且_型為 根據上述構想’其中該第—郎型編 決定該第1向擴散金屬氧化物半導體電晶體的第-崩潰^度 遠第二深井區的該第二摻雜濃度決定 =電晶體的第二崩潰電壓，且該第二崩潰電= 6 200939444 根據上述構想，其中該第二橫向擴散金屬氧化物半導體電 晶體具有一閘極端與一源極端，且該閘極端與該源極端之間耦合 一電阻器。 σ 根據上述構想，其中該第二橫向擴散金屬氧化物半導體電 晶體的一汲極接觸至複晶矽閘極距離大於該第一橫向擴散金屬氧 化物半導體電晶體的汲極接觸至複晶矽閘極距離。 Ο ❹ 一根據上述構想，其中該第一深!^型井區包覆該第一受控制 路€，且s亥第一深Ν型井區包覆該第二受控制路徑。 本案之另一目的為提供一種積體電路的靜電放電防護方 ^ ’其中該積體電路包括具有―第―㈣财區與第—受控制路 徑的第—橫向擴散金屬氧化物半導體電晶體，且該第—深Ν工型井 區，第-摻雜濃度決定該第—橫向擴散金屬氧化物半導體電晶體 =第-崩潰電壓，而該方法包括下列步驟：提供具有第二深Ν型 體區受控制路徑的第二橫向擴散金屬氧化物半導體電晶 文控制路徑具有相同的類型，而該類型為Ν型血Ρ型射 細；蝴該第:受 高於構射該第二深Ν型賴_第二摻雜漢度 於-_的該第—摻雜濃度；當該積體電路遭受高 半導t —靜電放電電壓時，該第二橫向擴散金屬氧化物 +導體電晶體較該第—橫向擴散金屬氧化物半導體電晶體先^ 7 200939444 通；及該第二橫向擴散金屬氧化物半導體電晶體防護該第一橫向 擴散金屬氧化物半導體電晶體，以防止該第一橫向擴散金屬氧化 物半導體電晶體受該靜電放電電壓的損害。 根據上述構想，其中該第二橫向擴散金屬氧化物半導體電 晶體具有一閘極端與一源極端，且該方法更包括下列步驟：耦合 一電阻器於該閘極端與該源極端之間。 根據上述構想，其中該電阻器由一N型金屬氧化物半導體 ❹電晶體或複數N型金屬氧化物半導體電晶體的串聯所構成。 根據上述構想，其中該電阻器由一 P型金屬氧化物半導體 電晶體或複數P型金屬氧化物半導體電晶體的串聯所構成。 根據上述構想，其中該第一橫向擴散金屬氧化物半導體電 晶體受配置為一開放式汲極輸入/輸出元件。 根據上述構想，其中該靜電放電防護方法更包括下列步 驟：使該第二橫向擴散金屬氧化物半導體電晶體的一波極接觸至 複晶石夕’距離大於該第-橫向擴散金屬氧化物半導體電晶體的 Q 一没極接觸至複晶石夕閘極距離。 根據上述構心其中该第一橫向擴散金屬氧化物半導體電 晶體與該第二橫向擴散金屬氧化物半導體電晶體不包括蠢晶層或 N型埋層。 根據上述構想，其中該靜電放電防護方法更包括下列步 驟.使該第/木N型井區包覆該第一受控制路握；及使該第二深 N型井區包覆該第二受控制路徑。 本案之又-目的為提供一種積體電路，其包括：第一橫向 200939444 擴散金屬氧化物半導體電晶體，其ι 、 控制路徑，其中該第-㈣斷區轉^井區與第一受 路徑的-第-導通性質；及第二橫向擴散金^交控制 :’ =_第一受控制路捏的第二受控制路徑，= =:=受控制路徑具有相同的類型，且該類= 【實施方式】 "本發明將藉由下述讀佳實_並配合圖示，作進一步之 細說明。 〔第一實施例〕 第二圖為本發明第-實施例之橫向擴散Ν型金屬氧化物半導 體元件之靜電放電的電流走向示意圓。請參照第二圖，橫向擴散 Ν型金屬氧化物半導體(LDNM〇s)電晶體結構2〇包括一間極η、 〇 -没極22、-源極24、一没極22與源極24之間的一 N型漂移區 23 (Ν-drift)、一深 N 型井區 25 (N weU)和一 p 型基底 27。 /木N型井區25包覆漂移區23，深N型井區25的摻雜濃度可 影響N型漂移區23的特性，例如：導通性質。深ν型井區的摻 雜濃度決定LDNMOS電晶體的一崩潰電壓Vbdi，而崩潰電壓Vbdi 決定N型漂移區23的導通性質；當LDNM〇s電晶體遭受高於一 預定電壓的一靜電放電電壓時，此導通性質可使LDNM〇s電晶體 導通’以作為一放電路徑。 200939444 BD1 當深N型井區的摻雜濃度較原有者為高時，崩潰賴v, ^低，型井區的摻雜濃度較原有者為低時，崩潰電壓％ 將升间。錄22接觸至複晶㈣極21的距離之大小亦可押崩 潰電塵W當閘極21與源極24之間另外麵合 響 時，將可進一步穩定崩潰 W禾顯不) 小可選擇約為㈣。％其中電阻器的典型電阻值大 在本實施财，深N财區25轉歸度設 ❹ _〇S電晶體者為高’且_接觸至複晶補㈣的距離 設計為較-般LDNMOS電晶為大，因此可在n型漂移區^ 誘發腳的電流，除了走第⑹路徑外，即由汲極22走横向的雙 極性路徑極24，錢_職，㈣祕Μ雜靠底層的 深N型賴25 ’流至源極24，因此本實施繼提做佳的腳 防護效果。 值得注意的是本實施例的LDNM〇s電晶體結構2〇不包括蟲 晶層或N型埋層。由於對深N型井區25進行較高濃度的換雜， ❹較採縣晶層加上N魏層的職讀，在製造成本上降低許 多，所以可以節省資源’而又同時能達到高效能表現。 〔第二實施例〕 第二圖為本發明第二實施例之橫向擴散p型金屬氧化物半導 體元件之靜電放電的電流走向示意圖。請參照第三圖，橫向擴散P 型金屬氧化物半導體(LDPMOS)電晶體結構30包括一閘極31、一 汲極32、一源極34、一沒極32與源極34之間的一 N型井區33、 200939444 - N型井區36、一深N型井區叫 深N型井區35包覆尺型 1基底37 度可影響N型井區33的特性，γ ’深N型井區35的摻雜濃 生，例如：導、时 机 摻雜漠度蚁LDPM〇S電晶體的 ^ ^型井區的 VBD2決定N型井區33的導通 ·肴秘％，而崩潰_ -預定電_-靜電放電時=LDPM〇S電晶體遭受高於 體導通，以作為-放電路彳^轉_可__電晶 ❹ 將二當深_井區的接雜濃度較原有者為= = vBD2;t_31_34 彻相且 ==嫩物壓y爾阻值= 古此時y罙N型井區35的掺雜濃度設計為較一般ld觸§者 為焉且車交N型井區33的掺雜濃度為高，因此可在N型井區33 ❹誘發ESD的電流，除了走第(Μ)路徑外，即由汲極走橫向的雙 極性路徑，經N型井區33，流至源極34，也走第㈣路徑，即由 汲極32經N型井區33、經下方的深N型井區％，再經N型井區 33 ’流至源極34，因此本實施例能提供較佳的ESd防護效果。 值得〉主意的是本實施例的LDPMOS電晶體結構30不包括磊 曰曰層或N型埋層。與第一實施例同樣地，本實施能降低製造成本， 節省資源，而又同時能達到高效能表現。 200939444 〔第二實施例〕 第四圖為本發明第三實施例之電路示意圖。請參照第四圖， 電路4包含一被保護的橫向擴散N型金屬氧化物半導體(ldnm〇s) 元件40b與一配合元件40’而配合元件40可包括一保護用橫向擴 散N型金屬氧化物半導體(LDNM〇s)元件4〇a。 被保護LDNMOS元件40b可包括一 LDNMOS電晶體，且具 有一閘極端Gb、一汲極端Db、一源極端Sb、一 N型受控制通道 ❹ 40b卜與一深N型井區働2。深N型井區40b2的摻雜濃度DTb 影響N型受控制通道40bl，例如：影響N型受控制通道4〇μ的 導通性質。汲極端Db耦合於一輸入輸出墊PA1，且源極端sb耦 合於一地參考電位VSS。 保護用LDNMOS元件40a可包括一 LDNMOS電晶體，且具 有閘極、〇a、一汲極端Da、一源極端Sa、一:N型受控制通道 4〇al、與一深N型井區40a2。深N型井區40a2的摻雜濃度DTa 影響N型受控制通道40al，例如，影響N型受控制通道4〇&ι的 ©導通性質。沒極端Da耦合於輸入輸出墊pAl，且源極端Sa耦合 於地參考電位VSS，亦即N型受控制通道40al並聯於N型受控 制通道40b 1。 深N型井區40b2的摻雜濃度DTb決定被保護1^_〇8元件 40b的第朋 >貝電壓’深N型井區40a2的摻雜濃度DTa決定保 護用LDNMOS元件40a的一第二崩潰電壓，為了達到靜電放電 (ESD)的防護效果’可控制摻雜濃度勵與摻雜濃度而之間的 高低關係’使保護用LDNMOS元件40a所具有的第二崩潰電壓小 12 200939444 於被保護LDNMOS元件40b所具有的第一崩潰電壓。 深N型井區40b2可包覆㈣受控制通道侧，㈣型井區 40a2可包覆N型受控制通道40al ; #Ν型受控制通道樣與n 型受控制通道40al具有相同的結構特性時，可將摻雜濃度㈣調 整為高於摻雜浪度DTb，以使第二崩潰電壓小於第一崩潰電壓。 舉例而言’第二崩潰電壓可為31V，且第—赌電壓可為爪。 在第二崩潰電壓小於H責賴之元件特性的情況下，當 〇 護電路4遭受高於-預定電壓的一靜電放電電壓時，保護用 LDNMOS元件偷較被保護LDNM〇s元件條先導通。如此， 保護用LDNMOS元件40a可防護被保護LDNM〇s元件，以 防止被保護LDNMOS元件40b受靜電放電電壓的損害。 為了使配合元件40的操作較為穩定，如第四圖所示，配合元 件40可包括保護用LDNMOS元件40a與一電阻器42。電阻器42 耦合於保護用LDNMOS元件40a的閘極端Ga與源極端如之間， 其中電阻器22的典型電阻值大小可選擇約為。 © 在本實施例中，被保護LDNMOS元件40b可以為開放式沒極 輸入/輸出元件’提供ESD防護的LDNMOS元件40a的深N型井 區40al的掺雜濃度DTa大於被保護LDNMOS元件40b的深N型 井區40bl的掺雜濃度DTb，且提供ESD防護的LDNM〇s元件 40a的汲極接觸至複晶矽閘極的距離較被保護LDNM〇s元件 的汲極接觸至複晶矽閘極的距離為大，例如加大約3至5μιη，所 以可使提供ESD防護的LDNMOS元件40a的崩潰電壓小於被保 護的LDNMOS元件40b的崩潰電壓。當電路4遭受到高於某一預 13 200939444 定電壓的ESD電壓時’提供ESD防護的LDNM〇s元件伽會先 導通，因此可以防止被保護的LDNM〇s元件4〇b受到esd電壓 的損害。 〔第四實施例〕 第五圖為本發明第四實施例之電路示意圖。請參照第五圖， 電路5與第二實施例中的電路4相似，主要不同之處在於：電路4 ❺中的電阻器42被電路5中的nmos元件52所取代，而 元件52的閘極並連接至VDD端。 同第三實施例所述，本實施例中的配合元件50中的提供ESD 防護的LDNMOS元件40a的深N型井區的掺雜濃度大於被保護 的LDNMOS元件40b的深N型井區的掺雜濃度，且提供ESD防 護的LDNMOS元件40a的沒極接觸至複晶石夕閘極的距離較被保護 的LDNMOS元件40b的沒極接觸至複晶矽閘極的距離為大，所以 可使提供ESD防護的LDNMOS元件40a的崩潰電壓小於被保護 〇 的LDM〇S元件40b的崩潰電壓。當電路5遭受到高於某一預定 電壓的ESD電壓時，提供ESD防護的LDNMOS元件4〇a會先導 通’因此可以防止被保護的LDNMOS元件40b受到ESD電壓的 損害。 〔第五實施例〕 第六圖為本發明第五實施例之電路示意圖。請參照第六圖， 電路6與第四實施例中的電路5相似，主要不同之處在於，電路5 200939444 中的NMOS元件52被電路6中的PM〇s元件62所取代β 本實施例中的配合元件60可以防止被保護的LDNM〇s元件 40b受到ESD電壓的，原理如第四實施例所述，在此不再重 述。 〔第六實施例〕 第七圖為本發明第六實施例之電路示意圖。請參照第七圖， ❹電路7與第四實施例中的電路5相似，主要不同之處在於，電路5 中的配合元件50僅包含-個NM0S元件52，而電路7中的配合 元件70則包含串聯的2個NMOS元件組72。 同樣地’本實施例中的配合元件7G可以防止被保護的 LDNMOS元件40b受到ESD電麼的損害，原理如上述，在此不 再重述。 當然，依本發明之精神，串聯的2個_〇8元件組72也可 改為串聯更多NMOS S件，或者也可改為串聯多個pM〇s元件。 ❹ 〔第七實施例〕 ’ 第八圖為本發明第七實施例之電路示意圖。請參照第八圖， 電路8包含-橫向擴散P型金屬氧化物半導體(LDpM〇s)元件麟 與-配合元件80’而配合猶8G可包括—橫向擴散p型金屬氧化 物半導體(LDPMOS)元件80a。 LDPMOS it件8Gb可包括- LDPMOS電晶體，且具有一閘 極端Gd、一汲極端Dd、一源極端Sd、一 N型井區_卜與一深 15 200939444 N型井區80b2。深N型井區80b2的一摻雜濃度DTd影響N型井 區80M，例如：影響N型井區80bl的導通性質。汲極端Dd耦合 於一輸入輸出墊PA2，且源極端Sd耦合於一電源參考電位VDD。 LDPMOS元件80a可包括一 LDPMOS電晶體，且具有一閘極 端Gc、一汲極端Dc、一源極端Sc、一 N型井區80a卜與— 型井區80a2。深N型井區8〇a2的一摻雜濃度DTc影響N型井區 8〇al，例如：影響N型井區8〇al的導通性質。汲極端Dc耦合於200939444 IX. Description of the invention: [Technical field to which the invention pertains] This case refers to an integrated circuit, in particular, an integrated circuit for electrostatic discharge protection. [Prior Art] At present, an integrated circuit manufactured by using a vertically diffused metal ❹ oxide semiconductor (LDMOS) process basically uses a large area of its own driver to perform electrostatic discharge (Electr) 〇statie Discharge, ESD) protection, in general, ESD protection is not good. The structure of the LDMOS device is not easy to induce the bipolar junction transistor path (BJTpath) that is parasitic on LDM 〇s. Moreover, the open-type input/output (〇penDrainI〇) component is because it has only a single path to the ground, and it is not easy to do ESD protection. At present, most of the Epitaxial layer and the N-type buried layer are used to induce the bipolar junction transistor path (BJTpath) that is parasitic to the LDMOS to enhance the level of esd Q protection. The first figure is a schematic diagram of the current flow of the electrostatic discharge of the laterally diffused metal oxide semiconductor device of the prior art. Referring to the first figure, when the distance d between the drain 12 and the source 14 is small, the coffee current first goes to the (1) path, that is, the lateral bipolar path (this sink & 11^〇131^11 ), and then lead to the (2) path, that is, the vertical bipolar path. 'At this time, the ESD current passes through the ^^ type well area, flows to the Ν-type buried layer 18, and then passes through the 井-type well area 16 Flow to source 14; when d value is large, 200939444 ESD current only goes to the (1) path, that is, the lateral bipolar path is bipolar path) 〇- (4) worm crystal 81 is more expensive, so Lixian crystal layer In addition to the N-type buried layer solution, although the driver has a large area method and improved many ESD protection effects, it is still too high (4), so it is necessary to develop solutions for other technologies. At the same time, it has excellent coffee protection effect and economical manufacturing technology. This bribe domain _ concept and solution, financial solutions to the above problems, significantly reduce production costs. SUMMARY OF THE INVENTION The present invention provides an integrator circuit including a first-transverse diffusion gold, and an i-body having a first deep N-type well region and a first controlled by the first-deep N + ^ And a second laterally diffused metal oxide semiconductor transistor having a second (four) type well region and a second doping concentration of the second = The controlled path, the first-controlled == two-control path has the same type but has one of different types and types. The enamel and _ type is determined according to the above concept, wherein the first slang type determines the first-to-diffusion degree of the first-direction diffusion metal oxide semiconductor transistor, and the second doping concentration is determined by the second doping concentration=electricity a second breakdown voltage of the crystal, and the second breakdown electric power = 6 200939444. According to the above concept, wherein the second laterally diffused metal oxide semiconductor transistor has a gate terminal and a source terminal, and the gate terminal and the source terminal A resistor is coupled between them. According to the above concept, wherein a drain contact of the second laterally diffused metal oxide semiconductor transistor to the polysilicon gate is greater than a gate contact of the first laterally diffused metal oxide semiconductor transistor to the polysilicon gate Extreme distance. According to the above concept, the first deep well region covers the first controlled road, and the first deep well region of the shai covers the second controlled path. Another object of the present invention is to provide an electrostatic discharge protection device for an integrated circuit, wherein the integrated circuit includes a first-transverse-diffused metal oxide semiconductor transistor having a "fourth" (fourth) financial region and a first controlled path, and The first deep processing well region, the first doping concentration determines the first-lateral diffusion metal oxide semiconductor transistor = the first-crash voltage, and the method comprises the following steps: providing the second deep-type body region The second laterally diffused metal oxide semiconductor electro-texture control path of the control path has the same type, and the type is a scorpion-type blood scorpion-type swell; the butterfly: the first: is higher than the structuring of the second squat type _ The first doping concentration of the second doping Hanta at -_; when the integrated circuit is subjected to a high semiconducting t-electrostatic discharge voltage, the second laterally diffused metal oxide + conductor transistor is more diffuse than the first lateral diffusion a metal oxide semiconductor transistor first; and the second laterally diffused metal oxide semiconductor transistor protects the first laterally diffused metal oxide semiconductor transistor to prevent the first lateral diffusion gold Oxide semiconductor transistor compromised electrostatic discharge voltage. According to the above concept, wherein the second laterally diffused metal oxide semiconductor transistor has a gate terminal and a source terminal, and the method further comprises the step of coupling a resistor between the gate terminal and the source terminal. According to the above concept, the resistor is constituted by a series connection of an N-type metal oxide semiconductor germanium transistor or a plurality of N-type metal oxide semiconductor transistors. According to the above concept, the resistor is constituted by a series connection of a P-type metal oxide semiconductor transistor or a plurality of P-type metal oxide semiconductor transistors. According to the above concept, the first laterally diffused metal oxide semiconductor transistor is configured as an open drain input/output element. According to the above concept, the electrostatic discharge protection method further includes the step of: contacting a wave of the second laterally diffused metal oxide semiconductor transistor to the polycrystalline spine by a distance greater than the first-lateral diffusion metal oxide semiconductor The Q of the crystal is infinitely contacted to the cristobalite gate distance. According to the above configuration, the first laterally diffused metal oxide semiconductor transistor and the second laterally diffused metal oxide semiconductor transistor do not include a stray layer or an N-type buried layer. According to the above concept, the electrostatic discharge protection method further comprises the steps of: coating the first/wood N-type well region with the first controlled road grip; and wrapping the second deep N-type well region with the second received Control path. A further object of the present invention is to provide an integrated circuit comprising: a first lateral 200939444 diffusion metal oxide semiconductor transistor, an ι, a control path, wherein the first-(four)-break region and the first path are - a first-conducting property; and a second lateral diffusion gold-crossing control: ' = _ the first controlled path of the first controlled way pinch, = =: = the controlled path has the same type, and the class = [implementation The method of the present invention will be further described in detail by the following description. [First Embodiment] The second figure is a schematic diagram showing a current course of electrostatic discharge of a laterally diffused Ν-type metal oxide semiconductor element according to a first embodiment of the present invention. Referring to FIG. 2, the laterally diffused germanium-type metal oxide semiconductor (LDNM〇s) transistor structure 2 includes a pole η, a 没-dipole 22, a source 24, a gate 22 and a source 24. An N-type drift region 23 (Ν-drift), a deep N-type well region 25 (N weU), and a p-type substrate 27. The /N-type well region 25 encases the drift region 23, and the doping concentration of the deep N-type well region 25 can affect the characteristics of the N-type drift region 23, for example, conduction properties. The doping concentration of the deep ν-type well region determines a breakdown voltage Vbdi of the LDNMOS transistor, and the breakdown voltage Vbdi determines the conduction property of the N-type drift region 23; when the LDNM〇s transistor suffers an electrostatic discharge voltage higher than a predetermined voltage This conduction property allows the LDNM〇s transistor to conduct 'as a discharge path. 200939444 BD1 When the doping concentration of the deep N-type well is higher than the original, the collapse depends on v, ^ is low, and the doping concentration of the well is lower than the original, the breakdown voltage % will rise. The distance of the contact 22 to the polycrystalline (four) pole 21 can also be used to collapse the electric dust W. When the other surface between the gate 21 and the source 24 is combined, the stability can be further stabilized. For (4). The typical resistance value of the resistor is large in this implementation. The depth of the deep N financial zone is set to ❹ 〇 电 电 电 电 电 电 电 电 电 电 电 电 电 接触 接触 接触 接触 复 复 复 复 复 复 复 复 复 复 复 复 复 复 复 复 复 复 复The crystal is large, so the current of the foot can be induced in the n-type drift region, except for the path (6), that is, the bipolar path pole 24 that is laterally moved by the bungee 22, the money_ job, (4) the secret is deep in the bottom layer. The N-type Lai 25' flows to the source 24, so this implementation is followed by a better foot protection effect. It is to be noted that the LDNM〇s transistor structure 2〇 of the present embodiment does not include a worm layer or an N-type buried layer. Due to the higher concentration of the deep N-type well 25, the 晶 ❹ 采 晶 晶 加上 加上 加上 加上 加上 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N which performed. [Second Embodiment] The second figure is a schematic diagram showing the current flow of the electrostatic discharge of the laterally diffused p-type metal oxide semiconductor element according to the second embodiment of the present invention. Referring to FIG. 3, the laterally diffused P-type metal oxide semiconductor (LDPMOS) transistor structure 30 includes a gate 31, a drain 32, a source 34, and a N between the gate 32 and the source 34. Well type 33, 200939444 - N type well area 36, a deep N type well area called deep N type well area 35 coated ruler type 1 base 37 degree can affect the characteristics of N type well area 33, γ 'deep N type well The doping concentration of the region 35, for example, the VBD2 of the well-type well region of the LDPM〇S transistor of the lead and timing doping ALD 〇M 〇S transistor determines the conduction and the secret of the N-type well region 33, and collapses _ - predetermined electricity _-Electrostatic discharge = LDPM〇S transistor suffers higher than body conduction, as a - discharge circuit 彳 ^ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ vBD2;t_31_34 phase and == tender pressure y er resistance = ancient at this time y 罙 N type well region 35 doping concentration is designed to be more than the general ld contact 焉 and the car intersection N type well 33 The impurity concentration is high, so the current of ESD can be induced in the N-type well region 33, except for the path of the (Μ) path, that is, the bipolar path from the bungee to the lateral direction, through the N-type well region 33, to the source 34, also take the fourth (four) path, that is, by 32 by the N-type well region 33 via a deep N-well region below%, and then the N-type well region 33 'flows to the source 34, the present embodiment can therefore provide a better protective effect ESd. It is worth noting that the LDPMOS transistor structure 30 of the present embodiment does not include an epi-layer or an N-type buried layer. As in the first embodiment, the present embodiment can reduce manufacturing costs and save resources while achieving high performance. 200939444 [Second Embodiment] A fourth diagram is a circuit diagram showing a third embodiment of the present invention. Referring to the fourth figure, the circuit 4 includes a protected laterally diffused N-type metal oxide semiconductor (ldnm〇s) device 40b and a mating component 40'. The mating component 40 may include a lateral diffusion N-type metal oxide for protection. Semiconductor (LDNM〇s) element 4〇a. The protected LDNMOS device 40b may include an LDNMOS transistor having a gate terminal Gb, a drain terminal Db, a source terminal Sb, an N-type controlled channel ❹ 40b and a deep N-type well region 働2. The doping concentration DTb of the deep N-type well region 40b2 affects the N-type controlled channel 40b1, for example, affecting the conduction property of the N-type controlled channel 4〇μ. The NMOS terminal Db is coupled to an input and output pad PA1, and the source terminal sb is coupled to a ground reference potential VSS. The protective LDNMOS device 40a may include an LDNMOS transistor having a gate, 〇a, a drain terminal Da, a source terminal Sa, an N-type controlled channel 4〇al, and a deep N-type well region 40a2. The doping concentration DTa of the deep N-type well region 40a2 affects the N-type controlled channel 40al, for example, affecting the © conducting property of the N-type controlled channel 4〇 & No extreme Da is coupled to the input and output pad pAl, and the source terminal Sa is coupled to the ground reference potential VSS, that is, the N-type controlled channel 40al is connected in parallel to the N-type controlled channel 40b1. The doping concentration DTb of the deep N-type well region 40b2 determines the doping concentration DTa of the deep N-type well region 40a2 of the protected first-level device 40b, and a second of the protective LDNMOS device 40a. The breakdown voltage, in order to achieve the electrostatic discharge (ESD) protection effect 'controllable the relationship between the doping concentration excitation and the doping concentration', so that the second breakdown voltage of the protection LDNMOS element 40a is small 12 200939444 is protected The first breakdown voltage possessed by the LDNMOS device 40b. The deep N-type well region 40b2 can cover (4) the controlled channel side, and the (4)-type well region 40a2 can cover the N-type controlled channel 40al; #Ν-type controlled channel-like and n-type controlled channel 40al have the same structural characteristics The doping concentration (4) may be adjusted to be higher than the doping level DTb such that the second breakdown voltage is less than the first breakdown voltage. For example, the second collapse voltage can be 31V and the first bet voltage can be a paw. In the case where the second breakdown voltage is less than the component characteristics of the H-rejected, when the protection circuit 4 is subjected to an electrostatic discharge voltage higher than the predetermined voltage, the protection LDNMOS element is turned on first by the protected LDNM〇s element strip. Thus, the protection LDNMOS element 40a can protect the protected LDNM 〇 s element from being protected from the electrostatic discharge voltage by the protected LD NMOS element 40b. In order to make the operation of the mating component 40 relatively stable, as shown in the fourth figure, the mating component 40 may include a protective LDNMOS component 40a and a resistor 42. The resistor 42 is coupled between the gate terminal Ga of the protection LDNMOS device 40a and the source terminal, wherein the typical resistance value of the resistor 22 can be selected to be approximately. In the present embodiment, the doped concentration DTa of the deep N-type well region 40a of the LDNMOS device 40a, which can be protected by the protected LDNMOS device 40b for the open-type input/output device', is greater than the depth of the protected LDNMOS device 40b. Doping concentration DTb of N-type well region 40b1, and the distance between the drain of the LDNM〇s element 40a providing ESD protection and the gate of the polycrystalline germanium gate is closer to the gate of the protected LDNM〇s element to the gate of the polycrystalline germanium gate The distance is large, for example, by about 3 to 5 μm, so that the breakdown voltage of the LDNMOS element 40a providing ESD protection can be made smaller than the breakdown voltage of the protected LDNMOS element 40b. When the circuit 4 is subjected to an ESD voltage higher than a predetermined voltage of 1339439444, the 'LDNM〇s element providing the ESD protection will be turned on first, thus preventing the protected LDNM〇s element 4〇b from being damaged by the esd voltage. . [Fourth Embodiment] Fig. 5 is a circuit diagram showing a fourth embodiment of the present invention. Referring to the fifth figure, the circuit 5 is similar to the circuit 4 in the second embodiment, the main difference being that the resistor 42 in the circuit 4 is replaced by the nmos element 52 in the circuit 5, and the gate of the element 52 And connected to the VDD terminal. As described in the third embodiment, the doping concentration of the deep N-type well region of the ESD-protected LDNMOS device 40a in the mating component 50 in this embodiment is greater than that of the deep N-well region of the protected LDNMOS device 40b. The impurity concentration, and the distance between the immersive contact of the LDNMOS element 40a providing the ESD protection to the cermet gate is larger than the distance between the immersive contact of the protected LDNMOS element 40b and the gate of the polysilicon, so that it can be provided The breakdown voltage of the ESD-protected LDNMOS element 40a is less than the breakdown voltage of the protected LDM 〇S element 40b. When the circuit 5 is subjected to an ESD voltage higher than a predetermined voltage, the LDNMOS element 4a that provides ESD protection is turned on first. Therefore, the protected LDNMOS element 40b can be prevented from being damaged by the ESD voltage. [Fifth Embodiment] Fig. 6 is a circuit diagram showing a fifth embodiment of the present invention. Referring to the sixth figure, the circuit 6 is similar to the circuit 5 in the fourth embodiment, the main difference being that the NMOS element 52 in the circuit 5 200939444 is replaced by the PM 〇s element 62 in the circuit 6 in this embodiment. The mating component 60 can prevent the protected LDNM〇s component 40b from being subjected to the ESD voltage. The principle is as described in the fourth embodiment and will not be repeated here. [Sixth embodiment] A seventh diagram is a circuit diagram of a sixth embodiment of the present invention. Referring to the seventh figure, the germanium circuit 7 is similar to the circuit 5 in the fourth embodiment, the main difference being that the mating component 50 in the circuit 5 includes only one NMOS component 52, and the mating component 70 in the circuit 7 Two NMOS element groups 72 are connected in series. Similarly, the mating component 7G in this embodiment can prevent the protected LDNMOS component 40b from being damaged by ESD power. The principle is as described above and will not be repeated here. Of course, in accordance with the spirit of the present invention, the two _ 〇 8 element groups 72 connected in series may be replaced by a series of more NMOS S elements, or a plurality of pM 〇 s elements may be connected in series.第七 [Seventh Embodiment] The eighth figure is a circuit diagram of a seventh embodiment of the present invention. Referring to the eighth figure, the circuit 8 includes a laterally diffused P-type metal oxide semiconductor (LDpM〇s) device and a mating component 80'. The juxta 8G may include a laterally diffused p-type metal oxide semiconductor (LDPMOS) device. 80a. The LDPMOS it piece 8Gb may include an -LDPMOS transistor having a gate terminal Gd, a terminal extreme Dd, a source terminal Sd, an N-type well region _b and a deep 15 200939444 N-type well region 80b2. A doping concentration DTd of the deep N-type well region 80b2 affects the N-type well region 80M, for example, affecting the conduction property of the N-type well region 80b1. The NMOS terminal Dd is coupled to an input and output pad PA2, and the source terminal Sd is coupled to a power supply reference potential VDD. The LDPMOS device 80a may include an LDPMOS transistor having a gate terminal Gc, a drain terminal Dc, a source terminal Sc, an N-type well region 80a, and a well region 80a2. A doping concentration DTc of 8〇a2 in the deep N-type well region affects the N-type well region 8〇al, for example, affecting the conduction property of the 8〇al of the N-type well region.汲 Extreme Dc is coupled to
〇輸入輸出塾PA2 ’且源極端Sc搞合於電源參考電位vss，亦即N 型井區80al並聯於n型井區80bl。藉由控制摻雜濃度DTd與摻 雜濃度DTc，可使N型井區8〇Μ與N型井區8〇al具有不同的導 通性質。 深N型井區80b2的摻雜濃度DTd決定LDpM〇s元件8此的 第-崩潰賴’深N型井區雜雜濃度DTe蚊LDpM〇s 疋件80a的第二崩潰電壓’為了達到具有差異的導通性質，可控 制摻雜濃度DTd與摻雜濃度DTc之間的高低關係，使LDpM〇s ❹το件80a所具有的第二崩潰電壓小於LDpM〇s元件所具有的 第一崩潰電壓。 深N型井區80b2可包覆N型井區_，深n型井區漏 可包覆N型井區80al;#N型井區8〇_Ν型井區·i具有相 同的、’Ό構特&時，可將摻雜》農度DTe調整為高於摻雜濃度， 、使第一朋⑶電壓小^第―朋潰電壓。舉例而言，第二崩潰電壓 可為31V，且第一崩潰電壓可為35V。 在第二崩潰電壓小於第一崩潰電壓之元件特性的情況下，當 16 200939444 電路8遭受高於一預定電壓的一靜電放電電壓時，LDpM〇s元件 80a較LDPMOS元件80b先導通。如此，LDpM〇s元件8〇a可防 護LDPMOS元件80b，以防止LDPMOS元件_受靜電放電電 壓的損害。 為了使配合元件80的操作較為穩定，如第八圖所示，配合元 件80可包括LDPMOS元件80a與一電阻器82。電阻器82耦合於 LDPMOS元件80a的閘極端Gc與源極端sc之間，其中電阻器82 ❹的典型電阻值大小可選擇約為1尬。電阻器82所具有的電阻值亦 可利用其他的元件來替代，例如NM0S電晶體、PM〇s電晶體或 其結合元件。 在本實施例中’ LDPMOS元件80b可為開放式汲極輸入/輸出 元件，LDPMOS元件80a的沒極接觸至複晶石夕閘極的距離較 LDPMOS元件80b的汲極接觸至複晶石夕閘極的距離為大，例如加 大約3至5μιη，可進一步調整第二崩潰電壓與第一崩潰電壓之間 的關係，以使LDPMOS元件80a的崩潰電壓小於LDpM〇s元件 ❹ 的崩潰電壓。 〔第八實施例〕 第九圖為本發明第八實施例之電路示意圖。第九圖的電路9 為第四圖的電路4之變形。請參照第九圖，電路9包含一 LDNM〇s 元件40b與LDNMOS元件40a。 LDNMOS元件40b可包括一 LDNMOS電晶體，且具有一閘 極端Gb、一没極端Db、一源極端Sb與一 n型漂移區40M。汲 17 200939444 極端Db柄合於一輸入輸出墊PA卜且源極端北耦合於一地參考 電位VSS。 / LDNMOS元件40a可包括一 LDNM〇s電晶體，且具有一問 極端Ga、一沒極端Da、一源極端Sa、一 N型漂移區4〇&卜盥一 深N型井區撕2。深N型井區40a2的一摻雜濃度咖決定n'型 漂移區40al的-導通性質。汲極端Da耗合於輸入輸出塾pA卜 且源極端Sa麵合於地參考電位vss，亦即N型漂移區偏並聯 ❹於N型漂移區40M。藉由控制摻雜濃度咖，可使N型漂移區 40M與N型漂移區40al具有不同的導通性質。 LDNMOS 件40b具有-崩潰電壓，深N型井區彻的換 雜濃度DTa決定LDNMOS元件40a的第二崩潰電壓，為了達到 具有差異的導通性質，可控制摻雜濃度DTa，使LDNM〇s元件 儀所具有的第二崩潰電壓小於LDNM〇s元件他所具有的第一 崩潰電壓。 在第二崩潰電壓小於第-崩潰電壓之元件特性(例如：閉極端 ❹Ga加上適當的偏壓’或閘極端Ga與源極端s b之間輕合一電阻器） 的情況下’當電路9遭受高於—預定電壓的—靜電放電電壓時， LDNMOS元件40a較LDNM〇s元件働先導通。如此，ldnm〇s 元件40a可防護LDNM0S元件.，以防止ldnm〇s元件働 受靜電放電電壓的損害。 第九圖的電路9可輕易地轉換為兩個LDpM〇s元件並聯情況 的電路，此處省略敘述。 知上所述’本案提供-種具有靜電放電(ESD)防護功能的電路 200939444 及其方法，利用提高在深>^型井區的捧雜濃度，及增加沒極接 至複晶石夕閘極的距離，來達成極佳的咖防護功能，同時由於不 使用蟲晶層及N型埋層’所以可以較現有技術顯著地降低生產成 本0 本案得由熟悉本技藝之人士任施匠思而為諸般修飾，然皆不 脫如附申請專利範圍所欲保護者。 【圖式簡單說明】 ❹第-圖為習知技術之橫向擴散金屬氧化物半導體元件之靜電放 電的電流走向示意圖。 第二圖為本發明第-實施例之橫向擴散N型金屬氧化物半導體 元件之靜電放電的電流走向示意圓。 第二圖為本發明第二實施例之橫向擴散p型金屬氧化物半導體 元件之靜電放電的電流走向示意圖。 第四圖為本發明第三實施例之電路示意圖。 Q 第五圖為本發明第四實施例之電路示意圖。 第六圖為本發明第五實施例之電路示意圖。 第七圖為本發明第六實施例之電路示意圖。 弟八圖為本發明第七實施例之電路示意圖。 第九圖為本發明第八實施例之電路示意圖。 【主要部分代表符號說明】 4、5、6、7、8、9:電路 12、22、32 :没極 19 200939444 14、24、34 :源極 16、33、80al、80bl : N 型井區 18 : N型埋層 20 : LDNMOS電晶體結構 21、31 :閘極 23、40al、40bl : N 型漂移區 25、35、40a2、40b2、80a2、80b2 :深N 型井區 27、37 : P型基底 〇 30 : LDPMOS電晶體結構 40、50、60、70、80 :配合元件 40a、80a :提供ESD防護的LDMOS元件 40b、80b :被保護的LDMOS元件 42、82 :電阻器 52 : NMOS 元件 62 : PMOS 元件 ❹ 72 :串聯的NMOS元件 (1)、（2)、（al)、（a2)、¢1)、（b2):電流路徑The input/output port 塾PA2' and the source terminal Sc are engaged with the power reference potential vss, that is, the N-type well region 80al is connected in parallel to the n-type well region 80b1. By controlling the doping concentration DTd and the doping concentration DTc, the N-type well region 8〇Μ and the N-type well region 8〇al have different conduction properties. The doping concentration DTd of the deep N-type well region 80b2 determines the LDpM〇s element 8 of this first-crash lag' deep N-type well impurity concentration DTe mosquito LDpM〇s element 80a's second breakdown voltage' in order to achieve the difference The conduction property can control the relationship between the doping concentration DTd and the doping concentration DTc, so that the second breakdown voltage of the LDpM〇s ❹το member 80a is smaller than the first breakdown voltage of the LDpM〇s device. Deep N-type well area 80b2 can cover N-type well area _, deep n-type well area leakage can cover N-type well area 80al; #N-type well area 8〇_Ν type well area·i have the same, 'Ό In the case of the composition &, the doping "agricultural degree DTe" can be adjusted to be higher than the doping concentration, so that the first (3) voltage is small and the first - the voltage is broken. For example, the second breakdown voltage can be 31V and the first breakdown voltage can be 35V. In the case where the second breakdown voltage is less than the component characteristic of the first breakdown voltage, when 16 200939444 circuit 8 is subjected to an electrostatic discharge voltage higher than a predetermined voltage, LDpM 〇 s element 80a is turned on first than LD PMOS element 80b. Thus, the LDpM 〇 s element 8 〇 a can protect the LD PMOS element 80b from being damaged by the electrostatic discharge voltage. In order to make the operation of the mating component 80 relatively stable, as shown in the eighth figure, the mating component 80 can include an LDPMOS component 80a and a resistor 82. Resistor 82 is coupled between gate terminal Gc of LDPMOS device 80a and source terminal sc, wherein the typical resistance value of resistor 82 可选择 can be selected to be approximately 1 尬. The resistance value of the resistor 82 can also be replaced by other components such as an NMOS transistor, a PM 〇s transistor or a combination thereof. In the present embodiment, the LD PMOS device 80b can be an open 汲 输入 input/output device, and the LDPMOS device 80a has a immersive contact with the smectic gate of the LD PMOS device 80b. The distance between the poles is large, for example, by about 3 to 5 μm, and the relationship between the second breakdown voltage and the first breakdown voltage can be further adjusted so that the breakdown voltage of the LDPMOS element 80a is smaller than the breakdown voltage of the LDpM〇s element 。. [Eighth Embodiment] A ninth embodiment is a circuit diagram of an eighth embodiment of the present invention. The circuit 9 of the ninth diagram is a modification of the circuit 4 of the fourth figure. Referring to the ninth diagram, the circuit 9 includes an LDNM〇s element 40b and an LDNMOS element 40a. The LDNMOS device 40b may include an LDNMOS transistor and has a gate terminal Gb, a terminalless drain Db, a source terminal Sb, and an n-type drift region 40M.汲 17 200939444 The extreme Db shank is integrated into an input/output pad PA and the source terminal is coupled to a ground reference potential VSS. The LDNMOS device 40a may include an LDNM 〇s transistor having a maximum of Ga, an extreme Dar, a source terminal Sa, an N-type drift region 4 〇 & a deep N-type well region tear 2 . A doping concentration of the deep N-type well region 40a2 determines the conduction property of the n'-type drift region 40al. The 汲 extreme Da is depleted by the input and output 塾pA b and the source terminal Sa is integrated with the ground reference potential vss, that is, the N-type drift region is connected in parallel to the N-type drift region 40M. By controlling the doping concentration, the N-type drift region 40M and the N-type drift region 40al can have different conduction properties. The LDNMOS device 40b has a breakdown voltage, and the deep N-type well region has a complete impurity concentration DTa that determines the second breakdown voltage of the LDNMOS device 40a. In order to achieve a different conduction property, the doping concentration DTa can be controlled to make the LDNM〇s component device The second breakdown voltage is less than the first breakdown voltage that the LDNM〇s component has. In the case where the second breakdown voltage is less than the component characteristic of the first-crash voltage (for example, the closed terminal ❹Ga plus the appropriate bias voltage or the light-resistance between the gate terminal Ga and the source terminal sb), when the circuit 9 suffers When the electrostatic discharge voltage is higher than the predetermined voltage, the LDNMOS element 40a is turned on first than the LDNM〇s element. Thus, the ldnm〇s element 40a protects the LDNMOS component from being damaged by the electrostatic discharge voltage. The circuit 9 of the ninth diagram can be easily converted into a circuit in which two LDpM〇s elements are connected in parallel, and the description is omitted here. Known as described above, the present invention provides a circuit with an electrostatic discharge (ESD) protection function 200939444 and a method thereof, which utilizes an increase in the concentration of a well in a deep well, and an increase in the connection to the polycrystalline stone gate Extreme distance, to achieve excellent coffee protection, and because the use of insect layer and N-type buried layer' can significantly reduce production costs compared to the prior art. This case is to be considered by those skilled in the art. For the sake of all kinds of modifications, it is not to be protected as intended by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] is a schematic diagram showing the current flow of electrostatic discharge of a laterally diffused metal oxide semiconductor device of the prior art. The second figure is a schematic diagram of the current direction of the electrostatic discharge of the laterally diffused N-type metal oxide semiconductor device of the first embodiment of the present invention. Fig. 2 is a schematic view showing the current flow of the electrostatic discharge of the laterally diffused p-type metal oxide semiconductor device according to the second embodiment of the present invention. The fourth figure is a circuit diagram of a third embodiment of the present invention. Q is a circuit diagram showing a fourth embodiment of the present invention. Figure 6 is a circuit diagram showing a fifth embodiment of the present invention. Figure 7 is a circuit diagram showing a sixth embodiment of the present invention. FIG. 8 is a schematic circuit diagram of a seventh embodiment of the present invention. Figure 9 is a circuit diagram showing an eighth embodiment of the present invention. [Main part representative symbol description] 4, 5, 6, 7, 8, 9: circuit 12, 22, 32: no pole 19 200939444 14, 24, 34: source 16, 33, 80al, 80bl: N-type well area 18 : N type buried layer 20 : LDNMOS transistor structure 21 , 31 : gate 23 , 40al , 40bl : N type drift region 25 , 35 , 40a2 , 40b2 , 80a2 , 80b2 : deep N type well region 27 , 37 : P Type substrate 30: LDPMOS transistor structure 40, 50, 60, 70, 80: mating elements 40a, 80a: LDMOS elements 40b, 80b providing ESD protection: protected LDMOS elements 42, 82: resistor 52: NMOS elements 62 : PMOS device ❹ 72 : NMOS devices in series (1), (2), (al), (a2), ¢1), (b2): current path
Da、Db、Dc、Dd :没極端 DTa、DTb、DTc、DTd :摻雜濃度Da, Db, Dc, Dd: no extreme DTa, DTb, DTc, DTd: doping concentration
Ga、Gb、Gc、Gd :閘極端 PA1、PA2 :輸入輸出墊Ga, Gb, Gc, Gd: gate terminal PA1, PA2: input and output pad
Sa、Sb、Sc、Sd :源極端Sa, Sb, Sc, Sd: source extreme
Vbdi、Vbd2 :崩潰電壓 20Vbdi, Vbd2: breakdown voltage 20