26534twf.doc/n 200935565 九、發明說明： 【發明所屬之技術領域】 ^發明是有關於-種晶片的封裝結構及封裝製程，且 特别疋有關於-種光學晶片的封裝結構及封裝製程。 【先前技術】 近年來’隨著電子技術的日新月異，高科技電子產品 不斷推陳出新，各種產品無不朝向輕、薄、短、小的趨勢 ❹設計，以提供更便利舒適的使用。在電子產品的製程中， 電子封裝扮演著重要的角色。舉例來說，數位相機仰幽 Camera)或數位攝影機(Digital Vide〇 camera)之所以能夠 感測影像’主要在於其包括感光元件，而感光元件中的感 光晶片可以感測光線強度，並且可以依照光線強度轉換成 電子訊號，以進行處理。藉由封裝製程，一方面使感光曰 片可以透過承載器與外界電路電性連接，另一方 : 程可以保護感光晶片，以避免雜質掉落或水氣影響到= ❹二It)光區域上’以提高感光晶片的感測靈敏度 圖1A是習知一種晶片的封裝結構示意圖。請參 1A，習知晶片的封裝結構101包含一晶片11〇、 3 120、-透明基板130以及一黏著材料14〇。其中 ^ 是由一晶圓（未繪示）所切割而成，晶片11〇且10 區域112、多個電子元件114以及多個接點ιΐ6。、 ^ ⑴與多個接點116位於晶片11〇之一主動表面=域 且多個接點m分佈於感光區域lu的周圍。多個電子元 200935565 26534twf.doc/n 件114配置於晶片H〇的内部。感光區域112上配置有一 濾光片12及多個微小透鏡14，以聚集並過濾來自外界之 光線，電子元件114可感測來自感光區域112並經過濾光 後的光線強度，以發出對應於此光線強度的電子訊號。 晶片110配置於承載器120上，承載器120的材質為 硬性材質。承載器120具有多個接點122，這些接點122 位於承載器120之一表面120a上，且分佈於晶片110所配 φ 置之區域的周圍。接點116以及接點122藉由多條焊線10 連接，使得晶片110與承載器120之間電性連接。 當晶片110與承載器120連接後，先把一大塊的透明 基板（圖未示）切割成多個一單位之透明基板13〇，再將 每一單位之透明基板130對準於承載器12〇，且利用黏著 材料140而將每一單位之透明基板丨3〇結構性地連接於承 載器120上。其中，透明基板13〇的材質為玻璃，黏著材 料140的材質為環氧樹脂(epoxy resin)。黏著材料14〇圍繞 於晶片110與多條焊線10外，使得承載器120、透明基板 UO與黏著材料140之間構成一密閉空間15〇。然後，於承 載器120之另一表面uob上形成多個焊球18，藉以將承 載器120電性連接至一印刷電路板(未繪示）。之後，再切 割承载器120成為多個獨立的晶片封裳體1〇1。 圖1B是習知另一種晶片的封裝結構示意圖。請參照 圖1B，習知晶片封裝結構2〇1包含一晶片21〇、一承載器 220、多個凸塊230、一透明基板240、一黏著材料250以 及一底填膠體26〇(un(ierfill)。其中，晶片21〇具有感光的 26534twf.doc/n 200935565 功月b，其結構可以參考圖1A中晶片no之結構，在此不 再贅述。 凸塊230配置於晶片210的多個接點216上，晶片21〇 透過凸塊230連接於承載器220。承載器220包含一金屬 層220a與一絕緣層220b，而承載器220例如是一軟性電 路板(Flexible Circuit Board，FCB)等電路板。接著，可於晶 片210與承載器220之間填入底填膠體26〇，並包覆凸塊 ❹ 230。而後’在透明基板240經過切割之後，可以利用黏著 材料250將其貼附於承載器220上。此時，由晶片21〇、 透明基板240、承載器220、凸塊230以及底填膠體260 所包圍的區域，會構成一密閉空間27〇。繼之，再切割承 載器220，以形成多個獨立的晶片封裝體2〇1。 值付庄思的是’在製作上述圖1A及圖iB之封裝結構 101、201時，均是在後段封裝製程中才將透明基板13°〇、 240貼附到晶片110、21〇上，因此晶片11〇、21〇之感光 〇區域112、212會暴露在潔淨度較差的環境，空氣中的許多 微小塵埃粒子容易沈積到晶片11〇、21〇之感光區域112、 212上’因而影響晶# 11〇、21〇之封装良率。為了提升晶 片110、210的封裝良率’上述的習知技術在將透明基板 130、240貼附到晶片11〇、21〇上之前，會進行一清潔步 驟，以去除沈積於晶片110、210上的雜質。上述的清潔製 程-方面使晶片的生產成本上升，另一方面也使封裝製程 的產能(throughput)下降。此外，在習知技術中，除了須先 將晶圓切割成晶片外’還須將透明基板切割成相應大小 7 200935565 26534twf.doc/n 後，才透過黏著材料將透明基板一片一片地接合至晶片 上，製程步驟較為繁複。 【發明内容】 本發明提供一種光學晶片的封裴結構，以提高光學晶 片的封裳良率。 本發明另提供一種光學晶片的封袭製程，以提升光學 晶片的封裝製程的產能。 Ο 本發明提出一種光學晶片的封裝結構，其包括一透明 基板、-光學晶片以及-承載器。其中，透明基板具有一 線路層，其中線路層包括多個引腳，且各引腳具有一内引 腳與-外引腳。光學晶片配置於透明基板上並與内引腳 電性連接，其中光學晶片具有-朝向透明基板之主動區 域。承載器配置於透明基板上，並與外引腳電性連接。 在本發明之:實施例中，上述之光學晶片包括一影像 感測晶片、一光感測晶片或一發光晶片。 在本發明之一實施例中，上述^影像感測器包括一電 〇荷輕合元件(CC戦—互補錢半導體影職測器(CM0S image sensor) 〇 在本發明之-實施例中，上述之光學晶片 塊，且光學晶片透過凸塊與内引腳電性連接。/、夕凸 在本發明之一實施例中，上述之承载器包括-軟性電 路薄膜或一電路板。 在本發明之-實施例中，上述之承载器配置於透明基 板具有線路層的表面上，而承載器具有一開口，且光學晶 26534twf.doc/n 200935565 片位於開口内。 在本發明之一實施例中，上述之光學晶片的封裝結構 更包括一底填膠體，配置於光感測晶片與透明基板之^以 覆蓋内引腳。 a 在本發明之一實施例中，上述之承載器配置於透明基 板不具有線路層的表面上，而承載器具有一開口以暴露= 透明基板。 ❹ 在本發明之一實施例中，上述之光學晶片的封裝結構 更包括一黏著層，黏著於透明基板與承載器之間。 在本發明之一實施例中，上述之光學晶片的封裝結構 更包括多條焊線’連接於外引腳與承載器之間。 在本發明之一實施例中，上述之光學晶片的封裝結構 更包括一封裝膠體，至少配置於光學晶片與透明基間 以覆蓋内引腳，並包覆焊線。 本發明另提出一種光學晶片的封裝製程，其包括提供 〇 —晶圓’晶圓包括多個光學晶片，其中各光學晶片具有一 主動區域。以及提供一透明母材，透明母材具有多個線路 層，其中各線路層包括多個引腳，且各引腳具有—内引腳 與一外引腳。而後，將透明母材與晶圓接合，以使各線路 層中的内引腳與其中一個光學晶片電性連接。接著，切割 透明母材與晶圓，以形成多個單體，其中各單體包括一透 明基板與一個與透明基板接合之光學晶片。以及將各單體 與一承載器電性連接。 在本發明之一實施例中，上述之晶圓是透過多個凸塊 9 26534twf.doc/n 200935565 與透明母材接合。 在本發明之一實施例中’上述之單體與承載器的電性 連接方式包括將承載器配置於透明基板具有線路層的表面 上，其中承載器具有一開口，且光學晶片位於開口内。 在本發明之一實施例中’上述之光學晶片的封裝製程 更包括於光學晶片與透明基板之間形成一底填膠體^ 蓋内引腳。 復 在本發明之一實施例中，上述之單體與承载器的電性 連接方式包括將承載器配置於透明基板不具有線路層的表 面上，其中承載器具有一開口以暴露出透明基板。 ❹26534twf.doc/n 200935565 IX. Description of the Invention: [Technical Field of the Invention] The invention relates to a package structure and a packaging process of a wafer, and particularly relates to a package structure and a packaging process of an optical wafer. [Prior Art] In recent years, with the rapid development of electronic technology, high-tech electronic products continue to evolve, and various products are designed to be lighter, thinner, shorter, and smaller, to provide more convenient and comfortable use. Electronic packaging plays an important role in the manufacturing of electronic products. For example, a digital camera (Camera) or a digital camera (Digital Vide〇camera) can sense an image 'mainly because it includes a photosensitive element, and the photosensitive wafer in the photosensitive element can sense the light intensity and can follow the light. The intensity is converted into an electronic signal for processing. By means of the packaging process, on the one hand, the photosensitive cymbal can be electrically connected to the external circuit through the carrier, and the other side: the process can protect the photosensitive wafer to prevent impurities from falling or moisture affecting the light region of the It2) In order to improve the sensing sensitivity of the photosensitive wafer, FIG. 1A is a schematic diagram of a package structure of a conventional wafer. Referring to FIG. 1A, the package structure 101 of the conventional wafer includes a wafer 11A, 3120, a transparent substrate 130, and an adhesive material 14A. Wherein ^ is formed by a wafer (not shown), the wafer 11 and 10 regions 112, a plurality of electronic components 114 and a plurality of contacts ι6. , (1) and a plurality of contacts 116 are located on one of the active surfaces of the wafer 11 = domain and a plurality of contacts m are distributed around the photosensitive region lu. A plurality of electronic elements 200935565 26534twf.doc/n 114 are disposed inside the wafer H〇. The light-receiving area 112 is provided with a filter 12 and a plurality of tiny lenses 14 for collecting and filtering light from the outside, and the electronic component 114 can sense the intensity of the light from the photosensitive area 112 and filtered, to correspond to this. Electronic signal of light intensity. The wafer 110 is disposed on the carrier 120, and the material of the carrier 120 is a hard material. The carrier 120 has a plurality of contacts 122 that are located on one surface 120a of the carrier 120 and that are distributed around the area where the wafer 110 is disposed. The contacts 116 and the contacts 122 are connected by a plurality of bonding wires 10 to electrically connect the wafer 110 and the carrier 120. After the wafer 110 is connected to the carrier 120, a large transparent substrate (not shown) is first cut into a plurality of units of the transparent substrate 13A, and then each unit of the transparent substrate 130 is aligned with the carrier 12. Then, each unit of the transparent substrate 〇3〇 is structurally connected to the carrier 120 by the adhesive material 140. The material of the transparent substrate 13A is glass, and the material of the adhesive material 140 is epoxy resin. The adhesive material 14 is disposed around the wafer 110 and the plurality of bonding wires 10 such that a space 15 is formed between the carrier 120, the transparent substrate UO and the adhesive material 140. Then, a plurality of solder balls 18 are formed on the other surface uob of the carrier 120, thereby electrically connecting the carrier 120 to a printed circuit board (not shown). Thereafter, the carrier 120 is again cut into a plurality of independent wafer sealing bodies 1〇1. FIG. 1B is a schematic diagram of a package structure of another conventional wafer. Referring to FIG. 1B , the conventional chip package structure 2 〇 1 includes a wafer 21 , a carrier 220 , a plurality of bumps 230 , a transparent substrate 240 , an adhesive material 250 , and an underfill 26 〇 (un(ierfill) The wafer 21A has a photosensitive 26534 twf.doc/n 200935565 power month b, and its structure can refer to the structure of the wafer no in FIG. 1A, and details are not described herein. The bump 230 is disposed on the plurality of contacts of the wafer 210. 216, the wafer 21 is connected to the carrier 220 through the bump 230. The carrier 220 includes a metal layer 220a and an insulating layer 220b, and the carrier 220 is a flexible circuit board (FCB) circuit board, for example. Then, the underfill 26 〇 can be filled between the wafer 210 and the carrier 220 and covered with the bump ❹ 230. Then, after the transparent substrate 240 is diced, it can be attached to the carrier by the adhesive material 250. At this time, the area surrounded by the wafer 21, the transparent substrate 240, the carrier 220, the bumps 230, and the underfill 260 will constitute a sealed space 27〇. Then, the carrier 220 is re-cut, To form multiple independent chip packages 2〇1. The value of Zhuangsi's is that when the package structures 101 and 201 of the above-mentioned FIG. 1A and FIG. 1B are produced, the transparent substrates 13°, 240 are attached to the wafers 110 and 21 in the subsequent packaging process. Therefore, the photosensitive germanium regions 112, 212 of the wafers 11 and 21 are exposed to a poorly clean environment, and many fine dust particles in the air are easily deposited on the photosensitive regions 112, 212 of the wafers 11 and 21'. Therefore, the package yield of the crystals #11〇, 21〇 is affected. In order to improve the package yield of the wafers 110 and 210, the above-mentioned conventional technique will attach the transparent substrates 130 and 240 to the wafers 11 and 21 before they are attached. A cleaning step is performed to remove impurities deposited on the wafers 110, 210. The cleaning process described above increases the production cost of the wafer and, on the other hand, reduces the throughput of the packaging process. Further, in the prior art In addition, the wafer must be first cut into wafers. The transparent substrate must be cut into the corresponding size 7 200935565 26534twf.doc/n, then the transparent substrate is bonded to the wafer one by one through the adhesive material. SUMMARY OF THE INVENTION The present invention provides a sealing structure for an optical wafer to improve the sealing yield of the optical wafer. The present invention further provides a sealing process for an optical wafer to improve the packaging process throughput of the optical wafer. The invention provides a package structure of an optical wafer, comprising a transparent substrate, an optical wafer and a carrier, wherein the transparent substrate has a circuit layer, wherein the circuit layer comprises a plurality of pins, and each pin has an internal lead Foot and - outer pins. The optical wafer is disposed on the transparent substrate and electrically connected to the inner leads, wherein the optical wafer has an active region facing the transparent substrate. The carrier is disposed on the transparent substrate and electrically connected to the outer pin. In an embodiment of the invention, the optical wafer comprises an image sensing wafer, a light sensing wafer or a light emitting wafer. In an embodiment of the invention, the image sensor includes an electrical load-carrying component (CC S 互补 钱 半导体 〇 〇 〇 〇 〇 - 实施 , , , , , , , , , , An optical wafer block, and the optical chip is electrically connected to the inner lead through the bump. In an embodiment of the invention, the carrier comprises a flexible circuit film or a circuit board. In an embodiment, the carrier is disposed on a surface of the transparent substrate having the circuit layer, and the carrier has an opening, and the optical crystal 26534 twf.doc/n 200935565 is located in the opening. In an embodiment of the invention, the above The package structure of the optical chip further includes an underfill layer disposed on the photo-sensing wafer and the transparent substrate to cover the inner leads. In an embodiment of the invention, the carrier is disposed on the transparent substrate and has no On the surface of the circuit layer, the carrier has an opening to expose the transparent substrate. 之一 In one embodiment of the invention, the package structure of the optical wafer further includes an adhesive layer adhered to the transparent layer. In an embodiment of the invention, the package structure of the optical wafer further includes a plurality of bonding wires 'connected between the outer pin and the carrier. In an embodiment of the invention, The package structure of the optical wafer further includes an encapsulant disposed at least between the optical wafer and the transparent substrate to cover the inner leads and to cover the bonding wires. The present invention further provides an optical wafer packaging process, which includes providing a crucible. The wafer 'wafer includes a plurality of optical wafers, wherein each optical wafer has an active area. And a transparent base material is provided. The transparent base material has a plurality of circuit layers, wherein each circuit layer includes a plurality of pins, and each of the leads Having an inner pin and an outer pin, and then bonding the transparent base material to the wafer to electrically connect the inner pins of each circuit layer to one of the optical wafers. Then, cutting the transparent base material and the wafer Forming a plurality of monomers, wherein each of the monomers comprises a transparent substrate and an optical wafer bonded to the transparent substrate, and electrically connecting each monomer to a carrier. In the example, the wafer is bonded to the transparent base material through a plurality of bumps 9 26534 twf.doc/n 200935565. In an embodiment of the invention, the electrical connection between the monomer and the carrier includes loading The device is disposed on the surface of the transparent substrate having the circuit layer, wherein the carrier has an opening, and the optical wafer is located in the opening. In an embodiment of the invention, the packaging process of the optical wafer is further included in the optical chip and the transparent substrate. In the embodiment of the present invention, the electrical connection between the monomer and the carrier includes disposing the carrier on a surface of the transparent substrate that does not have a circuit layer. The carrier has an opening to expose the transparent substrate.
在本發明之一實施例中，上述之光學晶片的封叢製程 更包括透過一黏著層將承載器黏著於透明基板上。 在本發明之一實施例中，上述之單體透過多條焊 承載器電性連接。 /、 在本發明之一實施例中，上述之光學晶片的封裝製程 更包括形成—封裝膠體，其中封裝膠體至少配置於光學晶 片與透明基板之間以覆蓋内引腳，並包覆焊線。 日日 入依照本發明之實施例所述，光學晶片與透明基板的接 口古於，圓層級(waferlevel)的製程，換句話說其接合是 度的環境中執行’故能避免習知空氣中的微：Ξ 學:片區域上的問題，進而提高光 褒良率。再者，在上述的光學晶片的封襄盤藉 曰片的學晶片進行額外的清潔製程，故能提升光學 曰曰片的封裝製簡產能以及降低其生產成本。学 26534tw£doc/n 200935565 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉實施例，並配合所附圖式，作詳細說明如 下。 【實施方式】 【第一實施例】 圖2是依照本發明第一實施例之光學晶片的封裝製程 的流程圖。圖3A至圖3E是依照本發明第一實施例之光學 0 晶片的封裝製程的流程剖面示意圖。 請同時參照圖2與圖3A ’首先，進行步驟S2〇〇與步 驟S202，提供一晶圓300以及提供一透明母材31(^晶圓 300包括多個光學晶片302,每一光學晶片3〇2中具有朝向 透明母材310的主動區域304。主動區域304例如是可以 感測來自於外界而穿過透明母材310之影像或光線，或 者，主動區域304也可以發射光線，而通過透明母材31〇 以傳至外界，因此，這些光學晶片302例如是影像感測晶 片、光感測晶片或發光晶片。因而，這些光學晶片302可 ❹ 以應用在電荷耦合元件(CCD)或互補金氧半導體影像感 測器（CMOS image sensor)等影像感測器中。值得一提的 是，透明母材310可以是玻璃等實質上為透明的材質，但 透明母材310也可以是特定波長可穿透而實質上非透明的 材質。其中，透明母材310具有多個線路層312，每一線 路層312包括多個引腳314，且每一引腳314具有一内引 腳314a與一外引腳314b。 請同時參照圖2與圖3B，而後，進行步驟s2〇4，將 11 26534twf.doc/n 200935565 透明母材310與晶圓300接合，以使各線路層3i2 引腳314a與其中一個光學晶片302電性連接。於本實施例 中，光學晶片302例如是有多個凸塊3〇6，這些凸塊3〇6 例如是藉由焊墊305與光學晶片302中的主動區域3〇4電 性連接，如此一來，光學晶片302中的主動區域304可藉 由凸塊306與透明母材310電性連接。值得一提的是，光 學晶片302上例如是有一層覆蓋於主動區域3〇4的保護層 φ 303，而焊墊305暴露於保護層303中。 請同時參照圖2與圖3C，接著，進行步驟S206，切 割透明母材310與晶圓300 ’以形成多個單體316，其中各 單體316包括透明基板318與一個與透明基板318接合之 光學晶片302。換句話說’沿者圖3B所示的虛線’分別將 晶圓300以及透明母材310切割成多個光學晶片302以及 多個透明基板318，以形成多個單體316。 請同時參照圖2與圖3D ’接著，進行步驟S208，將 各單體316與一承載器320電性連接。其中，承載器320 ❹ 配置於透明基板318具有線路層312的表面上。於本實施 例中，承載器320例如是藉由透明基板318上的外引腳 314b而與單體316電性連接，換句話說，承載器320藉由 與外引腳314b電性連接’而透過内引腳314a、凸塊306 以及焊墊305，進而與光學晶片302的主動區域304電性 連接。其中，承載器320具有一開口 322，因而光學晶片 302位於開口 322内。再者，承載器320例如是軟性電路 薄膜或電路板，因此’單體316藉由承載器320而與外界 12 26534twf.doc/n 200935565 電路連接。值得一提的是’在單體316與承载器320電性 連接後，光學晶片的封裝製程已大致完成，因此，光學晶 片的封裝結構340具有一光學晶片302、一透明基板318 以及一承載器320。 請參照圖3Ε，另一方面，為了使光學晶片3〇2與透明 基板318間之電性連接關係穩固，光學晶片的封裝製程更 包括於光學晶片302與透明基板318之間形成一至少覆蓋 Ο ❹ 内引腳314a的底填膠體324。底填膠體324例如是環氧樹 月曰（epoxy resin) ’可覆蓋内引腳314a，此外，底填膠體 324也可以同時覆蓋凸塊306。如此一來，内引腳以 及凸塊306就不容易受到外界之濕氣、熱量及雜訊等影響 而損壞，因而能穩固光學晶片302與透明基板318之間的 電性連結。 值得一提的是，於本實施例中，光學晶片3〇2與透明 基板318的接合屬於晶圓層級(waferlevd)的製程，故可避 免習知空氣巾的微小灰塵容易沉積至光學晶片的主動區域 上的問題’進祕持主祕_感測靈敏度，以提高光學 晶片的封裝良率。更重要的是，在上述的封裝製程中，不 =額外對光學^執行清潔步驟，故能提升封裝製程的 產月b以及降低其生產成本。 【第二實施例】 至圖4B是依照本發明第二實施例之光學 封裝製程的流程剖面示意圖。 請同時參照圖2與圖4A，本實施例的光學晶片的圭 13 26534twf.doc/n 200935565 裝是依照第一實施例中步驟S200至步驟S2〇8所敘述的流 程來製造，因此光學晶片的封裝結構340’與圖3C中的光 學晶片的封裝結構340相似。然而，於本實施例中，在步 驟S208中，是先透過黏著層326而將承載器32〇配置於 透明基板318不具有線路層312的表面上，再於外引腳 314b與承載器320之間形成多條焊線328，以使各單體316 與承載器320電性連接。因此，光學晶片的封裝結構34〇, ❹ 具有一光學晶片302、一透明基板318、一黏著層326、多 條焊線328以及一承載器320。其中，黏著層326的材質 例如是具雙階特性之熱固性黏著膠材(B-stage adhesive)或 是其他黏著材質。值得一提的是，由於承載器320具有一 開口 322’因而光學晶片3〇2暴露於此開口 322,也就是說， 外界的光線或影像可以藉由此開口 322而經過透明基板 318以到達光學晶片3〇2的主動區域3〇4。 請參照圖4B，另一方面，為了使單體316與承載器 q 320間之電性連接關係穩固，在形成焊線328之後，光學 晶片的封裝製程更包括於光學晶片302與透明基板318之 間形成至少覆蓋内引腳314a以及包覆焊線328的一封裝膠 體330。其中，封裝膠體330例如是環氧樹脂（epoxy resin) ’能覆蓋内引腳314a以及包覆焊線328。如此一來， 内弓丨腳314a以及焊線328就不容易受到外界之濕氣、熱量 及雜訊等影響而損壞，故能穩固單體316與焊線328之間 的電性連接。 综上所述，於上述實施例中，光學晶片與透明基板的 26534twf.doc/n 200935565 接合屬於晶圓層級(wafer level)的製程，故可聽f知空氣 中的微小灰塵容易沉積至光學晶片的主動區域上的問題， 進=保持主動區域的感測靈敏度，以提高光學；的封裝 =曰更重要的是’在上賴封裝製程巾，不需要額外對 、’執行清潔步驟’故能提升封裝製㈣產能以及降 低/、生產成本。In an embodiment of the invention, the sealing process of the optical wafer further comprises adhering the carrier to the transparent substrate through an adhesive layer. In one embodiment of the invention, the plurality of cells are electrically connected through a plurality of solder carriers. In an embodiment of the invention, the packaging process of the optical wafer further comprises forming a package colloid, wherein the encapsulant is disposed at least between the optical wafer and the transparent substrate to cover the inner leads and to cover the bonding wires. According to an embodiment of the present invention, the interface between the optical wafer and the transparent substrate is ancient, the wafer level process, in other words, the engagement is performed in a degree environment, so that it can avoid the conventional air. Micro: Ξ: The problem in the area of the film, which in turn increases the light yield. Furthermore, in the above-mentioned optical wafer sealing disk, an additional cleaning process is performed by the wafer of the wafer, so that the packaging capacity of the optical film can be improved and the production cost can be reduced. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. [Embodiment] FIG. 2 is a flow chart showing a packaging process of an optical wafer according to a first embodiment of the present invention. 3A to 3E are schematic cross-sectional views showing the flow of a packaging process of an optical 0 wafer in accordance with a first embodiment of the present invention. Referring to FIG. 2 and FIG. 3A simultaneously, first, step S2 and step S202 are performed to provide a wafer 300 and provide a transparent base material 31. The wafer 300 includes a plurality of optical wafers 302, each of which is 3 〇. 2 has an active area 304 facing the transparent base material 310. The active area 304 can, for example, sense images or light rays that pass through the transparent base material 310 from the outside, or the active area 304 can also emit light through the transparent mother. The material 31 is transferred to the outside, and therefore, the optical wafers 302 are, for example, image sensing wafers, light sensing wafers or light emitting wafers. Thus, the optical wafers 302 can be applied to charge coupled devices (CCD) or complementary gold oxides. In an image sensor such as a CMOS image sensor, it is worth mentioning that the transparent base material 310 may be a substantially transparent material such as glass, but the transparent base material 310 may also be a specific wavelength. The transparent base material 310 has a plurality of circuit layers 312, each of the circuit layers 312 includes a plurality of pins 314, and each of the pins 314 has an inner lead 314a and an outer lead. Foot 314b. Please refer to FIG. 2 and FIG. 3B at the same time, and then proceed to step s2〇4 to bond 11 26534 twf.doc/n 200935565 transparent base material 310 to wafer 300 so that each circuit layer 3i2 pin 314a and one of them The optical wafer 302 is electrically connected. In the present embodiment, the optical wafer 302 has, for example, a plurality of bumps 3〇6, such as the pads 305 and the active regions 3 in the optical wafer 302. 4, the electrical connection, in this way, the active area 304 in the optical wafer 302 can be electrically connected to the transparent base material 310 by the bump 306. It is worth mentioning that, for example, the optical wafer 302 has a layer covering the active area. 3 〇 4 of the protective layer φ 303, and the bonding pad 305 is exposed to the protective layer 303. Referring to FIG. 2 and FIG. 3C simultaneously, then proceeding to step S206, the transparent base material 310 and the wafer 300' are cut to form a plurality of sheets. Body 316, wherein each of the cells 316 includes a transparent substrate 318 and an optical wafer 302 bonded to the transparent substrate 318. In other words, the "dashed line shown in FIG. 3B" cuts the wafer 300 and the transparent base material 310 into a plurality. Optical wafer 302 and a plurality of transparent substrates 318 to The plurality of cells 316. Please refer to FIG. 2 and FIG. 3D simultaneously. Then, step S208 is performed to electrically connect each of the cells 316 to a carrier 320. The carrier 320 is disposed on the transparent substrate 318 and has a circuit layer. In the embodiment, the carrier 320 is electrically connected to the unit 316 by, for example, the outer lead 314b on the transparent substrate 318. In other words, the carrier 320 is connected to the outer lead 314b. The electrical connection is electrically connected to the active region 304 of the optical wafer 302 through the inner lead 314a, the bump 306, and the pad 305. The carrier 320 has an opening 322 such that the optical wafer 302 is located within the opening 322. Moreover, the carrier 320 is, for example, a flexible circuit film or a circuit board, so that the 'single 316 is connected to the outside world by the carrier 320. It is worth mentioning that 'the optical wafer packaging process 340 has an optical wafer 302, a transparent substrate 318 and a carrier after the monomer 316 is electrically connected to the carrier 320. 320. Referring to FIG. 3A, on the other hand, in order to stabilize the electrical connection between the optical wafer 3〇2 and the transparent substrate 318, the packaging process of the optical wafer further includes forming at least one coverage between the optical wafer 302 and the transparent substrate 318. The underfill 324 of the inner pin 314a. The underfill 324, such as an epoxy resin, can cover the inner leads 314a, and the underfill 324 can also cover the bumps 306 at the same time. As a result, the inner leads and the bumps 306 are less susceptible to damage from external moisture, heat, and noise, thereby stabilizing the electrical connection between the optical wafer 302 and the transparent substrate 318. It should be noted that, in this embodiment, the bonding of the optical wafer 3〇2 and the transparent substrate 318 belongs to a wafer level process, so that the micro dust of the conventional air towel can be easily deposited onto the optical wafer. The problem in the area 'into the secret secret _ sensing sensitivity to improve the packaging yield of optical wafers. More importantly, in the above packaging process, the cleaning step is not performed on the optical device, so that the production cycle b of the packaging process can be improved and the production cost can be reduced. [Second Embodiment] Fig. 4B is a schematic cross-sectional view showing the flow of an optical package process in accordance with a second embodiment of the present invention. Referring to FIG. 2 and FIG. 4A simultaneously, the optical wafer of the present embodiment is manufactured according to the flow described in steps S200 to S2 and 8 in the first embodiment, and thus the optical wafer is The package structure 340' is similar to the package structure 340 of the optical wafer of Figure 3C. However, in the embodiment, in step S208, the carrier 32 is disposed on the transparent substrate 318 without the surface of the circuit layer 312 through the adhesive layer 326, and then the outer lead 314b and the carrier 320 are disposed. A plurality of bonding wires 328 are formed to electrically connect the respective cells 316 to the carrier 320. Therefore, the package structure 34 of the optical wafer has an optical wafer 302, a transparent substrate 318, an adhesive layer 326, a plurality of bonding wires 328, and a carrier 320. The material of the adhesive layer 326 is, for example, a B-stage adhesive having a double-stage property or other adhesive material. It is worth mentioning that since the carrier 320 has an opening 322', the optical wafer 3〇2 is exposed to the opening 322, that is, external light or image can pass through the transparent substrate 318 through the opening 322 to reach the optical The active area 3〇4 of the wafer 3〇2. Referring to FIG. 4B , on the other hand, in order to stabilize the electrical connection between the cell 316 and the carrier q 320 , after the bonding wire 328 is formed, the packaging process of the optical wafer is further included in the optical chip 302 and the transparent substrate 318 . An encapsulant 330 is formed between at least the inner lead 314a and the over bond wire 328. The encapsulant 330, for example, an epoxy resin, can cover the inner leads 314a and the overlying bonding wires 328. As a result, the inner bow 314a and the bonding wire 328 are not easily damaged by external moisture, heat and noise, so that the electrical connection between the unit 316 and the bonding wire 328 can be stabilized. In summary, in the above embodiment, the optical wafer and the transparent substrate 26534twf.doc/n 200935565 are joined to the wafer level process, so that it is easy to know that tiny dust in the air is easily deposited on the optical wafer. The problem in the active area, the input sensitivity to maintain the active area to improve the optical; the package = 曰 more importantly, 'in the packaging process towel, no need for additional pairs, 'perform cleaning steps' can improve Packaging (4) Capacity and reduction / production costs.
、，然本發明已以—較佳實施例揭露如上，然其並非用 以限^本發明’任何熟習此技藝者’在不脫離本發明之精 巧祀圍内’當可作些許之更域潤飾，@此本發明之保 護範圍當視後附之申請糊範_界定者為準。 【圖式簡單說明】 圖1A是習知一種晶片的封裝結構示意圖。 圖1B是習知另一種晶片的封裝結構示意圖。 圖2疋依照本發明第一實施例之光學晶片的封装 的流程圖。 圖3A至圖3E是依照本發明第一實施例之光學晶片的 封裝製程的流程剖面示意圖。 圖4A至圖4B是依照本發明第二實施例之光學晶片的 封裝製程的流程剖面示意圖。 【主要元件符號說明】 10 :焊線 12 :濾光片 14 :透鏡 18 :焊球 101 :晶片的封裝結構 15 200935565 26534twf.doc/n 110 :晶片 110a :主動表面 112 :感光區域 114 :電子元件 116 :接點 120 :承載器 120a、120b :表面 122 :接點 130 :透明基板 140 :黏著材料 150 :密閉空間 201 :晶片的封裝結構 210 :晶片 212 :感光區域 214:電子元件 216 :接點 220 :承載器 220a :金屬層 220b :絕緣層 230 :凸塊 240 :透明基板 250 :黏著材料 260 :底填膠體 270 :密閉空間 16 200935565 26534twf-doc/n S200〜S208 :步驟 300 :晶圓 302 :晶片 303 :保護層 304 :主動區域 305 :焊墊 306 :凸塊 φ 310:透明母材 312 :線路層 314 :引腳 314a :内引腳 314b :外引腳 316 :單體 318 :透明基板 320 :承載器 322 :開口 ❹ 324 :底填膠體 326 :黏著層 328 :焊線 330 :封裝膠體 340、340’ ：光學晶片的封裝結構 17The present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the invention to any skilled person in the art. , @The scope of protection of this invention is subject to the application of the attached _ defined. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic view showing a package structure of a conventional wafer. FIG. 1B is a schematic diagram of a package structure of another conventional wafer. Figure 2 is a flow chart showing the packaging of an optical wafer in accordance with a first embodiment of the present invention. 3A to 3E are schematic cross-sectional views showing the flow of a packaging process of an optical wafer according to a first embodiment of the present invention. 4A to 4B are schematic cross-sectional views showing the flow of a packaging process of an optical wafer in accordance with a second embodiment of the present invention. [Main component symbol description] 10: Wire bond 12: Filter 14: Lens 18: Solder ball 101: Package structure of the wafer 15 200935565 26534twf.doc/n 110: Wafer 110a: Active surface 112: Photosensitive region 114: Electronic component 116: contact 120: carrier 120a, 120b: surface 122: contact 130: transparent substrate 140: adhesive material 150: sealed space 201: package structure 210 of the wafer: wafer 212: photosensitive area 214: electronic component 216: contact 220: carrier 220a: metal layer 220b: insulating layer 230: bump 240: transparent substrate 250: adhesive material 260: underfill 270: confined space 16 200935565 26534twf-doc/n S200~S208: step 300: wafer 302 : wafer 303 : protective layer 304 : active region 305 : pad 306 : bump φ 310 : transparent base material 312 : circuit layer 314 : pin 314a : inner pin 314b : outer pin 316 : monomer 318 : transparent substrate 320: carrier 322: opening 324 324: underfill 326: adhesive layer 328: bonding wire 330: encapsulant 340, 340': package structure of optical wafer 17