TW200931806A - Three dimensional programmable devices - Google Patents

Abstract

In a first aspect, a three dimensional programmable logic device (PLD) comprises a plurality of distributed programmable elements located in a substrate region; and a contiguous array of configuration memory cells, a plurality of said memory cells coupled to the plurality of programmable elements to configure the programmable elements, wherein: the memory array is positioned substantially above or below the substrate region; and the memory array and the substrate region layout geometries are substantially similar. In a second aspect, the 3D PLD comprises a contiguous array of metal cells, each metal cell having the configuration memory cell dimensions and a metal stub coupled to a said configuration memory cell and to one or more of said programmable elements.

Description

200931806 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to programmable logic devices. 1 [Prior Art] • Traditionally, integrated circuit (1C) devices such as custom, semi-custom or application-specific integrated circuit (ASIC) devices have been used in electronics to reduce cost, enhance performance or meet space constraints. . However, the design and manufacture of custom or semi-custom ICs can be time consuming and expensive. Customization involves a long design cycle during the product definition phase and high acyclic engineering (NRE) costs during the manufacturing phase. In order to absorb design modifications or to find logic errors in custom or semi-custom 1C during the final test phase, it may be necessary to repeat design and manufacturing cycles with longer simulation and prototyping cycles to further increase time to market and NRE costs. As a result, ASICs only serve specific applications and are built for high capacity and low cost. Another type of semi-S device, called a gate array (including a platform ASIC and a fabric ASIC), is used to customize the module area by reducing the NRE cost by synchronizing the sham meter using a soft phantom & Piece. Structural gauge C provides a larger module block than the closed rim J, and may or may not provide a pre-made "pulse network" to simplify design efforts. In both cases, a software tool/seeking history and subsequent lines that converge on timing, RC" takes a few long iterations. In submicron program technology, the line delay is extremely complicated and difficult. Predicting. Lost stone ridges quasi-design confirms that the inter-pole array produces multiple pins and longer design iterations, which further deteriorates - quickly set up ten solutions: mode. Most users need iterative fine-tuning of the design to make Its 134,972.doc 200931806 is perfect* In recent years, the trend has deviated from custom or semi-custom ICs and can be programmed into the field. Its function is not to use the "live" terminal before using the integrated circuit. The user decides. Spot general programmable logic devices (PLDs) or field programmable gate array (FPGA) products greatly simplify the design cycle. These products provide software that is easy for users to use to customize the logic to fit the device through programmability and provide the ability to fine-tune and optimize the design to improve performance. Because of the pre-characterized line "RC" delay, the user is able to achieve complex placement and timing closure very quickly and extremely accurately. This flexibility of programmability or changeability is expensive in terms of area, but reduces the design cycle and the cost of prepaid Nre to the designer. In this disclosure, the terms FPGA and PLD are used interchangeably to mean a programmable device. FPGAs (including PLDs) offer low recycling engineering costs, fast turnarounds (usually placed in FPGAs and routing designs in minutes to hours), and the advantages of low risk, as they can be easily corrected later in the product design cycle design. There are only a few cost benefits in the use of more traditional ASIC methods for mass production operations. Compared to PLDs and FPGAs, an ASIC has a hard-wired logic connection that is identified during the chip design phase. The ASIC does not have multiple logic options. There are no multiple routing options and no configuration memory for custom logic and routing. This is a large wafer area and cost savings for the ASIC, i.e., the FPGA area can be 10 to 40 times larger than the ASIC area due to such a stylized additional burden. The smaller eight 81 (:: grain size results in better performance and better A. A fully custom ASIC also has custom logic functions, which are implemented with the same logic function PLD and FPGA 134972.doc 200931806 The scheme may require fewer gates than the solution. Therefore, an ASIC is significantly smaller, faster, cheaper, and more reliable than an equivalent gate count FPGA. The tradeoff is time to market (FPGA advantage) versus low and better. Between reliability (ASIC advantages). The cost of the scalable area provided by the *FPGA compared to the ASIC determines the user's reconfigurability of the logic function and the logic module. The additional cost of routing is included. Programmability includes additional memory MUX in the configuration memory and FPGA. © 10 to 40x矽 area defects lead to significant cost and performance inequality between ASIC and FPGA. One of the obvious burdens is consumed by the programmable interconnects in an FPGA (including associated configuration memory). Removing the routing to reduce the extra burden makes an FPGA unusable. It has been referenced in IDS, especially in Application sequence Nos. 10/267, 483, 10/267, 484, and 10/267, 51 1 disclose a preferred 3D FPGA with better logic gate 矽 density improvement than 2D FPGAs. This technique reduces FPGA and ASIC logic gate 矽 regions. The ratio is 2 to 10 times. Reduce the loss of FPGA logic area - improve the value of the FPGA compared to the ASIC. When the Si area ratio reaches a near limit (which is determined by the life capacity requirement of the device) It will 'eliminate the need for ASIC design, and FPGA design will become the new standard for system design. A complex logic design is divided into smaller logic blocks and programmed into logic elements or logic blocks provided in the FPGA. The logic element provides a sequence and combinatorial logic design implementation. The combinatorial logic has no memory and outputs a function that separately reflects the input. By inserting the memory into the logical path 134972.doc 200931806 to store the past history to implement the sequence Logic. Current FPGA architectures include transistor pairs, N AND or gates, multiplexers, look-up tables (LUTs), and AND-OR structures as a basic logic component. In a traditional FpGA, The basic logic 7L component is identified as a macrocell. Hereinafter the term logic component will include a logical 7L component, a macrocell, an architectural logic unit, and any other basic logic unit to implement a portion of a logic function. An FP(}a The granularity refers to the logical content of a basic logic component (small or large complex logic design is divided into fitting custom FP (JA particles. In the fine particle architecture, a smaller basic logic component is enclosed in the routing matrix). And copy. These architectures provide a logical fit at the expense of complex routing. In a coarse-grained architecture, many of the basic logic 7L pieces are wrapped in a logical block with greater functionality using region routing, which is then replicated. Logical block copying uses global routing techniques. Larger logic blocks make logic fitting difficult and make routing easier. One of the challenges of the FPGA architecture is to provide easy logic fitting (like fine particles) and maintain easy routing (like coarse particles). The inputs and outputs for logic elements, logic cells, or logic blocks are selected from the programmable routing matrix. A route is dedicated to each. Figure i shows an exemplary routing matrix containing the logic elements described in Reference 1 (Seals & Whapsh(m). In this example, the input and output (4) from the logic elements (8) to ι〇4 have 22 horizontal and 12 vertical interconnections connected to the materialization channel. These connections may be fuses, anti-fuse or SRAM controlled transfer gate transistor elements 101 including a connected state and an open state. The output is shown as being lightly coupled to one of the inputs to component 1 in the darker line: because vertical line #3 is used to complete the face. One of the outputs of element I34972.doc 200931806 is also shown as One of the inputs of element 104 in the black line is lightly coupled: because vertical line #8 is used to complete the coupling. Thus each input and each output occupies one or more dedicated lines to complete the coupling. The number of lines required, the line segments, the programmable connections, and the Si area grow rapidly with the number n of logic elements in the fabric. Figure 2 shows the logic of a built-in 〇 flip-flop with the 丨 routing. Component 'parameter 1, wherein elements 2〇1, 2〇2, and 203 are respectively controlled by an input signal of 2:1 MUX. Element 204 is an OR gate and 205 is a D flip-flop. With the clear signal set, eight inputs feed the logic block and one output leaves the logic block. The nine lines are shown in Figure 1 as having programmable connectivity. Therefore, the nine lines must be assigned. To connect the logic elements shown in Figure 2. All 2 inputs, all 3 inputs, and some 4 input variable functions are implemented in the logic block and latched to the D flip-flop. In reference 1 (seais & Whapshott) and Reference 2 (Sharma) discuss the Fpga architecture for various commercial devices. Provide a comprehensive topic on FPGA routing architecture in Reference 3 (Betz, Rose & Marquardt) and Reference 4 (Lemieux & Lewis) The routing block circuit structure defines how the logical blocks are connected to each other. The adjacent logic elements and the die relative corner logic elements may need to be connected. The output signal is attached by the output buffer attached to the logic element, and the driving strength is not Change line Description of path lengths. Longer lines may require repeaters to periodically update the signal. Buffers and transponders consume large Si areas and are extremely expensive. Line delays become unpredictable because the line length is at 134972. Doc -10- 200931806 The logic optimization period is randomly chosen to best fit the design to a given FPGA. The FPGA also takes long run times during the timing-driven optimization of the split logic. Because the FPGA is in grain size The upper growth is larger, so the number of line segments and the length of the connection logic are increased. The line delay controls the wafer efficiency. The line delay grows in proportion to the square of the line length and is reversed to the distance of the adjacent line. The maximum wafer size is maintained at a mask size of approximately 2 cm per side, and the metal line spacing is reduced with the technology scale. A good timing optimization requires a deep understanding of the specific Fp(}A fitter, the length of the line segment and associated program parameters; the techniques not found within the design shell are fitted. In the segmented line architecture, expensive Fixed buffers to drive global signals on selected lines. These buffers are too few 'because they are too expensive and only provide a one-way data flow. Predictable timing is another challenge for FPGAs. This will enhance the placement of FPGAs and Routing tool capabilities to best fit and optimize timing critical logic designs. More lines make the problem worse, and fewer lines keep the problem manageable, reducing FPGA costs. IDS reference referenced in this application The prior art FPGA architecture is discussed in detail. These patents disclose special routing blocks for connecting logic elements in the FpGA and macro units in the PLD. In all references, a fixed routing block is programmed. To define the inputs and outputs for the logic block, and the logic block implements a specific logic function. Such dedicated interconnect lines cause the cost of the FPGA to exceed the equivalent power. Sexual asic. The user manual for programming the FPGA is maintained in the FPGA configuration memory coupled to the logic in the FpGA. To program the use of a volatile FpGA 134972.doc 200931806 The specification is also external Copying in the memory chip, but the data from the memory chip is captured and loaded on the wafer volatile configuration memory to configure the FPGA. Therefore, the FPGA referenced by IDS incurs configuration memory on the wafer and The huge loss of MUX required for stylization "some people go in one step and need expensive off-chip boost ROM to keep the configuration data. So the configuration memory cost is twice that of the SRAM-based FPGA." There are four ways to display a point-to-point connection between a programmatic and programmable switch and a programmable vertical and horizontal point between A and B. A configuration circuit for programming this connection is not shown. All patents listed in IDS Use one or more of these basic connections to configure logic elements and programmatic interconnects. The user implements this decision by stylizing a memory bit. This configuration is different from a software finger. 'Because the memory bit system generates a control signal on the entity to actively implement the decision. In Figure 3A, a conductive fuse link 310 connects A to B. It is normally connected and has high current or laser The transfer of the beam will cause the conductor to blow. In Figure 3B, a capacitive anti-fuse element 32 is turned off 0 to A to B. The system is normally turned on and the high current transfer will be taken out. The insulator is shorted to the terminals. The fuse and the anti-fuse are sub-programmable due to the irreversibility of the change. In Figure 3C, the transfer gate device 33 is connected to A to B. The gate signal s〇 determines the nature of the connection, ie, on or Closed = A non-destructive change. The gate signal is generated by manipulating logic signals or by a configuration circuit comprising 5 memories. The choice of memory varies depending on the user. In Fig. 3A, the floating transfer gate device 34 is connected eight to = θ to control the gate signal S 〇 to couple a portion of the device to the floating gate. The electrons captured in the 5 volt gate determine the on or off state of the connection. I34972.doc 200931806 Thermoelectric and Fowler-Nordheim wear two mechanisms for injecting charge onto a floating gate. When a high quality insulator encapsulates the floating gate, the trapped charge remains for more than 10 years. These provide non-volatile memory. • EPROM, EEPROM, and flash memory use floating gates and are non-swing

• Hairy. Anti-fuse and SRAM-based architectures are widely used in commercial FPGAs, while EPROM, EEPROM, anti-fuse and fuse links are widely used in commercial PLDs. Volatile SRAM memory does not require high program voltages and is freely available for every logic program. It is compatible with standard CMOS® SRAM memory, giving program and voltage scaling and has become the practical choice for modern very large FPGA devices. Unfortunately, it requires an externally expensive boost ROM to save configuration data. A configurable circuit based on a six-crystal SRAM is shown in Figure 4A. The SRAM memory component can be a 6-cell transistor, a 5-transistor, a cell based on a full COMS, R-load or TFT PMOS load, and the like. The two inverters 403 and 404 connected back to back form the memory element. This memory component is a latch. The latch can be a full CMOS, R load, PMOS PMOS load or any other load. The power and ground terminals for these inverters are not shown in Figure 4A. Accessing NMOS transistors 401 and 402 and storing 'take lines GA, GB, BL, and BS provide components for configuring the memory elements. Zero and one are applied to BL and BS respectively, and GA and GB rise enable are written to zero in device 401 and in device 402. Output S0 delivers logic one. One and zero are applied to the BL and the BS, respectively, and the GA and GB rise enable are written in the device 401 and zero in the device 402. Output S〇 delivers logic zero. The SRAM configuration allows for the application of only zero signals on the BL or BS to be written in the 134972.doc • 13- 200931806. The SRAM cell can have only one access transistor 4〇1 or 402. As long as the power system is turned on, the 'SRAM latch will maintain the data status. When power is turned off, the SRAM bit needs to be restored from an external permanent memory (ROM) to its previous state. The outer memory is not flashed to the programmable logic to configure the logic, and the data retrieval system is the same as the microprocessor fetching external DRAM memory data for storage and use in the area cache memory. In the literature for programmable logic, this second non-volatile memory is also referred to as configuration memory and should not be confused with the definition of the applicant of the configuration memory coupled to the programmable logic. The SRAM configuration circuit for controlling the logic transfer gate shown in Figure 3C in Figure 4A is illustrated in Figure 4B. Element 450 represents the configuration circuit. The S〇 output, which is directly driven by the memory element of Fig. 4α_, drives the gate electrode of the transfer gate. In addition to the S〇 output and latch, the power, ground, data, and write enable signals in the 450 form the SRAM configuration circuit. The write enable circuit includes the GA, GB, BL, BS signals shown in Figure 4A. An SRAM-based switch is shown in Figure 4B, wherein the pass gate 410 can be a pM 〇 s, NMOS or CMOS transistor pair. The NMOS is preferred due to its higher conduction. The gate voltage S〇 on the gate electrode of NMOS transistor 410 determines whether the connection is turned on or off. S 0 with a logic level of one completes the point-to-point connection, while the logic level zero keeps the nodes disconnected. This logic level is generated by a configuration circuit 450 coupled to the gate of NMOS transistor 410. The symbol for the programmable switch containing the SRAM device and the transfer gate is shown in Figure 4C as a cross-hatched circle 460. The SRAM memory data can be changed at any time in the operation of the device 134972.doc 14- 200931806, thereby instantly changing an application and routing, thus causing the concept of reconfigurable computing in the FPGA device. A programmable MUX utilizes a plurality of point-to-point switches. Figure (4) shows three. Different Pon-based programmable logic constructs. The figure shows a 'programmable 2:1 MUX. In this, two pass gates and 512 allow two inputs (4) to be connected to the output port. A configuration circuit 550 having two complementary output control signals s0 and SQ· provides programmability. When %=1, So 〇, I. The tie is joined to the 〇. When Sg = (), 8. , = 1; "lights to 〇. © 纟 55 具有 has a memory component, - the input system always faces to the output "If two bits are provided in 550, then two Mutually exclusive outputs S〇&S. If there is such a requirement in the logic design, this will not allow I or 1丨 to be coupled to 〇. Figure 58 shows the -programmable by two memory elements 4:1 MUX. When 4 outputs are replaced by 4 memory elements ^ to S3: ^ to 〖3, and a similar structure when the two gates ^ and ^ control the transfer gate is called 4 input. Lookup Table (LUT) The β 4:1 MUX in Figure (3) operates with two memory 7L pieces 561 and 562 included in configuration circuit 56 (not shown). Similar to Figure 5A, I〇, J One of 丨, 12 or 13 is connected to 〇 according to the state. For example, when Si = 1; l is coupled to 0. Similarly, when S0 = 〇 and s = 〇, 13 is coupled to 〇 Figure 5C; shows a 3-bit programmable 3:1 Μυχ. The point 〇 can be connected to A, B or C via a transfer gate 53 1 , 533 or 532 respectively. Included in a configuration circuit 570 (not The memory elements 571, 572, and 573 in the display control these pass gate input signals. Three memory elements are required to connect D to only one point, any two points, or all three points. In the calculation, note 134972.doc -15- 200931806 The information in 70 pieces 571, 572 and 573 can be changed immediately to change the connectivity between A, B, C and D as needed.

In the IDS reference, the three-dimensional concept of building blocks in 3D FpGA construction is revealed. In a first aspect, the 3D FPGA reduces the 矽 region by placing the configuration memory above the programmable logic content. In the second aspect, an expensive user programmable RAM memory system is first used to target a complex design to a programmable device, and when the design freezes, the memory is replaced by a cheap mask programmable ROM memory. Ram. In a third aspect, a thin film electro-crystalline system containing majority carrier conduction is used to construct a 3-dimensional configuration circuit. Thin film SRAM memory has better alpha particle immunity than bulk SRAM. In a fourth aspect, a 3-dimensional thin film transistor SRAM memory component is used to program the programmable logic. In a fifth aspect, the 'MUX system is stacked logically and the configuration memory system is stacked on the MUX to significantly reduce the Shihua coverage area. One or more of the disclosures used individually or in combination with other disclosures demonstrate significant improvements over 3D programmable logic devices of conventional 2d programmable logic devices. SUMMARY OF THE INVENTION This disclosure demonstrates the architectural complexity and innovation associated with 3D FPGA circuits. A 3D FPGA device requires a plurality of I/Os and pads for signal lines to access the chip, a plurality of programmable logic/route components disposed in a regular or irregular configuration of a logic block, and configured a plurality of programmable logic blocks in an array structure, one or more intellectual property (IP) cores frequently used by a user to interface with programmable logic, and one interacting with all of the above components of the fpga Programmable interconnect matrix, and many of its 134972.doc -16- 200931806

=. In a typical 2D FPGA configuration, the configuration memory truncation is interactively built into blocks and, as needed, the metal line handles are coupled to the logical reads. Typically, lower level metalloid layers (e.g., metal t, metal 2 genus 3) are used to construct regional circuitry, such as lightly configurable components to § memory cells. In the standard cell ASIC^, the lower level metallization layer_ is used to construct a standard cell. The configuration of the circuit components plays a vital role in improving logic placement and reducing the cost of 3D wafers. 1 There is no efficient software tool that allows stacking of 3D active components. Therefore, 3D wafer construction requires newer construction techniques. As disclosed herein, the 矽 is efficiently used to couple 3D to a user-defined component (eg, programmable logic, IP, pad, etc.) that is coupled to an efficient interconnect and routing fabric to configure the 3D circuit components. Stylized logic chip. Such programs identify appropriate vertical interconnect methods in the iteration to couple the configuration memory to the programmable logic and to easily construct the interconnect fabric. In addition, 3D FPGAs require lateral interconnects that are stitched together to form longer lines, and vertical interconnects that do not block the efficiencies that can be achieved. Efficient vertical group cancer systems use repetitive structures to achieve 'these structures allow complex programmable logic building blocks with varying user requirements to be easily integrated into wafers composed of varying logic and memory densities, and for systems Design a family of immune delivery economics and efficient 3D programmable wafers. In one aspect, a three-dimensional programmable logic device (PLD) includes: a programmable logic block having a plurality of configurable elements positioned in the logic block in a predetermined layout geometry; Configuring a first array of memory cells, each of the memory cells being coupled to one or more of the 134972.doc -17-200931806 configuration elements to program the logic block to The user specification 'where the first array substantially conforms to the predetermined layout geometry and the first array is positioned substantially above or below the logic block. - Embodiments of the above aspects may include - or more of the following embodiments. • A programmable logic device can include a plurality of programmable logic block barriers. - Logical blocks can be replicated in the array, or a plurality of complex logical blocks can be used in place of the array. A unit can be created with one or more logical blocks and replicated in an array to more efficiently construct a logical region & - The programmable logic block can further include a plurality of programmable logic units and logic elements. The logic unit itself may be duplicated in an array to form the logical block... the logical unit may be referred to as a "logical block" so that the logical block may include a plurality of logical units that have been placed in the array. A programmable logic unit can further include a plurality of programmable elements, such as logic and routing elements. A memory unit can store a portion of the program to program a logic element. Therefore, a user can use the diagnostic data to store an instruction to fully program the PLD. The logic unit can mix the programmable components with the non-configurable circuit components. In one example, a programmable switch can be interactively dispersed using a programmable circuit. In another example, a programmable multiplexer circuit can be interactively dispersed using logic transistors in a programmable circuit. In another example, the latches and flip-flops can be interactively dispersed using a programmable look-up table circuit and a programmable MUX circuit to construct a programmable logic unit. A programmable interconnect structure can connect a plurality of logic cells, or logic blocks, or logic arrays to each other, to a pad structure, and to an IP block. This type of 134972.doc -18· 200931806 interconnect structure completes the functionality of the integrated circuit and forms a connection to the input and output ports. The interconnect structures include - programmable (4). Most of the common relationship - the transfer of the pole device. A transfer closed-pole system can electrically connect two points of an NMOS transistor, a PM〇s transistor or a pair of transistors. A pass gate-conductivity modulation element, including a - connection state and an off state. Other methods of connecting two points include fuse links and anti-fuse combiners. Other methods of connecting two points may include an electrochemical or ferroelectric or ❸

Any other unit. Stylizing such devices includes forming one of a conductive path or a non-conductive path. Passing the gate electrode signal on the gate allows a programmable approach to control - opening and closing the connection. A plurality of transfer interpoles are included in the programmable logic blocks and the programmable circuit structure. The structure may include a circuit comprising a crystal composed of CMOS f, including na, yVERT, 〇R, N0R, lookup table, truth table, hall, arithmetic logic, central processing unit, programmable memory And the transfer between the polar logic logic circuits can be combined into a larger logical block. The configuration circuit is used to provide programmability. The configuration circuit has a memory component and an access circuit to change the memory. Each memory component can be a group of transistors or a pole or an electronic device. The memory components can be fabricated from =〇S devices, capacitors, diodes, resistors, and other electronic components. The memory elements can be electrically conductive, such as thin film transistors (TFTs), thin films. And the film-electrode decimator device manufacturing. The memory component can be selected from a group consisting of volatile and non-volatile! bulk materials. It can also be included from fuses, anti-fuse, SRAM cells, DRAM cells, first-study units, I34972.doc -19- 200931806 The memory element is selected by a group of metal optional links, EPROM, EEPROM, flash memory, magnetic and ferroelectric elements. The memory component can be a conductivity modulation component. One or more redundant memory elements can be provided to control the same circuit block. Such techniques should not be confused with redundancy in traditional dram or flash memory. The memory component can generate an output signal to control the transfer gate logic. The configuration memory component can generate a signal for obtaining a control signal. The configuration memory component can generate a data signal that defines a lookup table. The control signal is coupled to a pass gate logic & component, AND array, NOR array, a MUX or a look up table (LUT) logic. Those skilled in the art will appreciate that a memory component is a conventional memory device that does not produce a control signal. The logic blocks and logic units include outputs and inputs. The logic function performs a logical operation. The logic function manipulates the input signal to provide a desired response in one or more outputs. The input signals can be stored in a storage element. The output signals can be stored in a storage element. The input and output signals can be synchronous or asynchronous signals. The input of the logic function can be received from the memory body, or the input pin on the device, or the output of other logic blocks in the device. The output of the logic block can be coupled to other inputs, or storage devices, or output pads in the device, or used as control logic. Input and output

Coupling to an interconnect fabric D via a programmable switch D uses a basic logic program capable of fabricating a CMOS transistor to fabricate the structural unit. These transistors are formed on a P-type, N-type, epitaxial or SOI substrate wafer. Each integrated circuit is constructed on a substrate layer. The configuration circuit including the configuration memory constructed on the same germanium substrate occupies a larger area; the eve covers the 134972.doc -20-200931806 area. This adds the cost of programming the line structure compared to a similar functional custom line structure. The three-dimensional integration of the transfer gates and configuration circuitry used to connect the lines provides significant cost reduction in the applications incorporated by reference. The transfer gates and configuration circuitry can be constructed over - or a plurality of metal layers. The metal layers can be used for internal and interactive connections of the structural unit. The programmable circuit can be formed by inserting a thin film transistor (TFT) module or a laser fuse model, or any other vertical memory structure. The circuit is formed above the circuit of the . The memory modules can be inserted in any of the via layers, between a metal layer or on top of a metal layer on top of a logic program. The memory component can generate an output signal to control the logic gate. The memory component can generate a signal for obtaining a control signal. A logical block and a logical unit include a layout geometry. Within the layout geometry, the transistors are efficiently configured to reduce the footprint of the turns required for the layout. These electro-crystalline systems are coupled to each other using fixed interconnects and programmable interconnects. A logic unit or a programmable element in a logic block can be randomly configured. Some stylized components can be configured regularly using the layout area. Some of the programmable elements can be spaced closer together, while other programmable elements can be spaced further apart from one another. A logical unit cell can be repeated a plurality of times to form a logical block unit. The programmable elements can be positioned substantially randomly within the logic unit or the logic block to construct individual units with a minimum layout area. A memory unit may be required to program the programmable element. A memory unit can be coupled to a programmable element to program the programmable element. A memory unit can be coupled to a plurality of programmable elements to program the elements. A plurality of memory cells can be programmed into a block 134972.doc -21 - 200931806 block or a logical unit. A plurality of memory cells are constructed more efficiently when constructed as a memory cell array. A programmable logic device can have a #有-第-layout area' which contains a programmable logic block having a plurality of randomly configurable component elements. The device can have a second layout. Any structure that includes an contiguous array of configuration memory cells is constructed by replica-memory cells. To improve the efficiency of the layout, the first layout geometry can be substantially identical to the second layout geometry' and the second layout geometry can be positioned substantially above the first #office geometry. Thus an array of memory cells that are efficiently constructed is designed to be programmed to efficiently construct logical blocks or logic blocks. In addition, a unit of unit containing both logical blocks and memory cell arrays can be replicated to construct a larger building block. In larger building blocks, the memory cells can be combined to form an array of one of the memory cells abutting a more efficient configuration and positioning. Thus the construction of a larger logic unit allows for efficient construction of larger logic arrays. In a first embodiment, the logical block has a first number of independent programmable elements (a separate stylized element means one or more programmable programs that are programmed by a single memory unit) Components). The array of memory cells used to program the logic block has a substantially similar first number of memory cells. The logic block is optimized to include a substantially equal number of memory cells, such that the memory cell regions/geometry closely match the logical block region/geometry comprising the programmable elements . In accordance with the present invention, a 3D PLD can include a 1/0 unit having a first Ϊ/Ο region and a second I/O of a plurality of configurable components with 134972.doc -22· 200931806 located therein. a second array of one of the configuration memory cells having a plurality of configuration memory cells, each of the second array elements being compliant with the first I/O region One or more of the configuration elements to program the I/O unit to a user specification, wherein the second array and the first I/O area substantially conform to the predetermined layout geometry and the second array The system is positioned substantially above or below the first I/O area. Embodiments of the above aspects may include one or more of the following embodiments. 〇 A programmable logic device includes a plurality of I/O units, each of which allows one of the inputs or an output of the PLD to be coupled to an external device. The I/O unit may comprise a block joint' or a stack of areas that are joined as needed. The I/O units can be configured along the perimeter, or configured in a repository, or evenly distributed within the PLD. The I/O units can be coupled to the interconnect fabric of the PLD. The I/O unit can be programmable, and the unit provides one of a plurality of I/O standards to be selected by a user as a desired I/O feature. This I/O unit provides multiple voltage operation options. The I/O unit provides a pin for sharing a plurality of inputs and outputs. The I/O unit can provide one or more of the I/O standards including LVDS, SDR, DDR, LVTTL, LVPECL, LVCMOS, PCI, PCIX, GTL, * GTLP, HSTL, SSTL, BLVDS. Thus a user can configure an I/O unit to a provided feature including, but not limited to, the list shown. An I/O unit includes a layout geometry. Within the layout geometry, the I/O circuit transistors are efficiently configured to reduce the footprint of the turns required for the layout. The I/O circuit transistors occupy an I/O circuit area/geometry. 134972.doc -23- 200931806 The t卯 unit includes a metal pad that occupies one (four) structure or one & The pad geometry can be adjacent to the 1/〇 circuit geometry. The geometrical emission of the I/O circuit includes the first region of the functional material

And a second area of one of the programmable circuits. The second region can be adjacent to the programmable logic geometry, thus forming a larger programmable geometry. The !/〇 晶 system uses a fixed interconnect and a programmable interconnect to mate with each other... and the programmable elements in the cell can be positioned only in the I/O circuit geometry, better positioned in the The second region t is randomly configured to improve layout efficiency. Some programmable elements can be configured regularly using this layout geometry. Some of the programmable elements can be spaced closer together, while other programmable elements can be spaced further apart from one another. A ι/〇 unit can be repeated a plurality of times to form a 1/0 unit group. The 1/〇 circuit geometries can be aggregated to form contiguous regions of circuit elements, including circuitizable elements that form a substantially random-positioned 1/0 circuit layout geometry. A memory unit may be required to program the programmable element. A memory unit can be coupled to a programmable element to program the programmable element. A memory unit can be coupled to a plurality of programmable elements to program the elements. A plurality of memory cells can program an I/O circuit. A plurality of memory cells are constructed more efficiently when constructed as a memory cell array. An I/O unit can have a first-layout geometry that includes one of a plurality of configurable components with random assignments. The apparatus can have a second layout geometry comprising an adjacent array of one of the state memory cells constructed by duplicating a memory cell. In order to improve the efficiency of the layout, the first layout may be substantially the same as the layout structure of the first and second layouts, and the second layout geometry is The scorpion can be substantially above the top layout geometry. Therefore, the memory element is designed to efficiently process the 1/0 unit of the efficient construction. In addition, the 1/0 unit including one of the transfer and ι/〇 circuits can be copied to construct a larger 〇 block. In larger building blocks, memory cells such as 13⁄4 can be combined to form a memory cell: an array of adjacent highly efficient structures and locations. Therefore, the overlay of the memory unit #1/0 unit allows the efficient construction of larger groups. In addition, the array of memory units required for the stylized-programmable logic block array is used. The array of memory cells that are programmed to group the I/Q cells can be further combined to form an adjacent array of memory cells that are efficiently constructed and positioned. In a particular embodiment, all of the programmable π members can be positioned in a substantially rectangular layout geometry, and the contiguous memory cell array can have an identical geometry. The total number of memory cells can be matched to the total number of independently stylized components, so the architecture is efficient. In accordance with the present invention, a PLD can include a programmable intellectual property (ιρ) block having an IP region and a second Ι/p region with a plurality of configurable components positioned within an area; A third array of one of the configuration memory cells having a configuration memory unit and coupled to one or more of the configurable elements in the first area, the plurality of the third array The memory unit is coupled to the plurality of configurable elements in the IP block to program the IP block to a user specification, wherein the third array and the first ip area are 134972.doc • 25- 200931806 The predetermined layout geometry and the third array is positioned substantially above or below the first IP region. Embodiments of the above aspects may include one or more of the following embodiments. * A programmable logic device includes a plurality of IP blocks, each of which allows a user to implement a particular function. A plurality of inputs and outputs couple the "block" to the interconnect fabric. The IP block can be configured along a perimeter, or disposed in a repository, or evenly distributed within the PLD. The IP block can be programmable The block provides one of a plurality of changing functions to select β as a desired feature by a user. The ip block can provide multiple power/performance tradeoffs. The block can have data width and depth. Denatured memory block. The IP block can be a multiply-accumulate unit with varying DSP capabilities. The IP block can be a CPU block with varying instruction set capabilities. The IP block can provide A stylized PLL or DLL block. Therefore - the user can configure an IP block to one of the provided features, including but not limited to the IPs listed above. ❹ A block includes the layout geometry. Within the layout geometry, the IP circuit transistors are efficiently configured to reduce the coverage area required for the layout. The IP circuit transistors occupy a fixed IP circuit geometry and one or more programmable IP circuit geometries Knot In a memory block, the fixed IP geometry can include (單埠, double, etc.) memory cells, and the programmable IP region can include the programmable components to configure the data width. And depth, build the FIFO, and couple the „> block to the interconnect fabric. The programmable circuit area can be adjacent to the programmable logic geometry so that a larger programmable geometry can be formed. These Ip crystal system systems are coupled to each other using fixed interconnects and programmable interconnects. The programmable elements in a block can be located only in the programmable circuit area, which allows the programmable elements to be randomly configured to improve layout efficiency. Some programmable elements can be regularly configured using the layout geometry. Some programmable components can be spaced closer together while other programmable components can be spaced further apart from one another. An IP block can be repeated a plurality of times to form an Ip block group. The ip circuit regions can be gathered to form contiguous regions of circuit elements including programmable elements that form a repeating structure of a substantially randomly positioned Ip programmable element layout geometry. A "remembering unit may be needed to program the stylized component. A memory unit can be coupled to a programmable element to program the programmable element. A memory unit can be coupled to a plurality of programmable elements to program the elements. A plurality of memory cells can be programmed into an IP block. A plurality of memory cells are constructed more efficiently when constructed as a memory cell array. An Ip block can have a first layout geometry that includes an IP circuit having a plurality of configurable elements that are randomly assigned. The apparatus can have a second layout geometry comprising an contiguous array of one of the configuration memory cells, the array being constructed by duplicating a memory cell, the first layout area/geometry to improve the efficiency of the layout The structure can be substantially identical to the second layout area/geometry, and the second layout geometry can be positioned substantially above the first layout geometry. Therefore, the array of memory sheets is set by the "programmed-efficiently constructed IP block." The block of both I3 unprogrammable and programmable circuits can be copied to construct a larger IP block. In larger building blocks, the configuration memory 134972.doc -27- 200931806 body units can be combined to form an array of one of the memory cells adjacent to the more efficient construction and positioning. The configuration memory cells are positioned above the programmable circuit region of the Ip blocks, thereby occupying the same geometry β because of the configuration of an ip block with memory cell coverage allowing for efficiency • Construct a large IP block. In another aspect, a three-dimensional programmable logic device (PLD) includes: a plurality of I/O cells, each I/O cell comprising: a fixed circuit region; and a programmable circuit region having To configure a plurality of programmable elements of the 1/0 unit; and one or more intellectual property (IP) cores, each IP core comprising: a fixed circuit area; and a programmable circuit area, Having a plurality of programmable elements for configuring the IP core; and a programmable logic block array region comprising: a plurality of substantially identical programmable logic blocks replicated to form the array Each of the logic blocks further includes a plurality of programmable elements; and a programmable area 'which includes a positionable programmable element of the programmable logic block array area, and an IP core programmable circuit area One or more and one or more of the 1/0 unit programmable circuit regions, and a configuration memory array including one of the programmable _ components coupled into the programmable region or a memory unit that stylizes the programmable area, wherein: the memory array is substantially positioned above or below the programmable area; and the memory array and the programmable The geometry of the regional layout is essentially the same. In another aspect, a three-dimensional programmable logic device (PLD) includes a plurality of distributed programmable elements that are positioned in a substrate region; 134972.doc • 28- 200931806 and a configuration memory unit One of the adjacent arrays, the plurality of memory cells being coupled to the plurality of programmable elements to configure the programmable elements' wherein: the memory array is substantially positioned above or below the substrate region; Moreover, the memory array and the substrate area layout geometry are substantially similar. The PLD further includes: one of the metal cells abutting the array, each metal cell having a configuration memory cell size and a metal stub coupled to the configuration memory cell and one or more of the programmable elements. Additionally, the array of metal cells is positioned below the array of memory cells and over the programmable elements. Additionally, the two or more metal cells further include a metal line adjacent the metal stub extending from one end of the cell to the opposite end of the cell, wherein two or more adjacent metal cells form a continuous metal line. In another aspect, a vertically configured programmable logic device (PLD) includes: a unit cell, wherein the unit cell geometry includes a first dimension in a first direction and orthogonal to the first a second dimension in one of the directions in the second direction; and an array of one of the memory cells configured to form the memory by placing a memory cell within the unit cell geometry and copying the unit cell a body array; and a plurality of programmable elements positioned in a geometry substantially similar to the geometry of the array of configured memory cells; and an array of the first metal cells, the array Constructed by replicating a first metal array of one of the unit cell sizes in an array, the first metal unit further comprising: a first region consisting of one or more parallel metal bus bars, the bus bar a line extending between opposing cell boundaries in the first or second direction to form an all-pass busbar line 134972.doc •29·200931806; and a second region, the system It is coupled to the first is positioned above the metal studs of the configuration memory cell and one of the metal studs positioned below the first of these metal studs programmable element one or more components. In addition, the 3D PLD further includes: an array of the second metal single t1. The array is constructed by replicating one of the unit single size of the second metal unit in an array, the second metal unit is further advanced The method includes: a first region, which is composed of two or more parallel metal wires, the metal wires extending between opposite cell boundaries in the first or second direction to form a global routing circuit; and a second region It consists of metal short columns and metal wires to facilitate the vertical routing of the configuration memory cells and signals. The advantages of the above specific embodiments may be one or more of the following advantages. These embodiments provide a group of programmable elements and metal interconnects based on the purpose of coupling to vertically positioned configuration elements during construction of the 3D FPGA. This innovation is also about creating unit cells within these layout geometries to facilitate this 3D construction. The programmable blocks can be configured such that all of the programmable elements in the array are combined to form a larger area of the programmable elements. The IP blocks are arranged adjacent to the logical blocks, so the programmable elements are combined into another larger programmable area. The I/O units are configured such that the programmable units in the 1/〇 units are further added to the common stylable area to provide a larger footprint of the programmable elements. These coalesced programmable regions can be constructed to have an accurate (or nearly accurate) size of an array of unit cells. The array can include a plurality of columns of unit cells and N rows, where M&N is an integer greater than one. Preferably, the N and N are integers greater than 100, and more preferably the m&n system 134972.doc -30- 200931806 ❹ ❷ an integer greater than the face. The coalescing region of the programmable component is now coupled to a larger array of vertically positioned configuration memory cells. This light combination is facilitated by a metal stud in an intermediate metal layer. Metal routing, power and grounding are distributed in the same metal layer. Therefore, the principle of “unit metal units” is important for constructing such three-dimensional interconnection systems. Per-memory element output consumption: to - metal short column. Each metal short cylinder is joined to - or a plurality of programmable elements. Vertical interconnections (meaning ζ directions) do not interrupt horizontal interconnections (meaning X and γ directions). Metal busbars are positioned between the metal stubs for the global interconnect and busbars. In the first and second metal layers, the metal lines run in the X or Υ direction (orthogonal to the X direction). There may be a plurality of first metal layers and second metal layers as set forth. The global and regional interconnections are also located in the metal unit. A first region of the metal unit includes a global metal line for interconnection, and a second region of the metal unit includes a region interconnect for the vertical configuration. When a single cell array is used to configure a coalesced programmable element region, rather than using disjoint and inefficiently produced random memory cells or smaller cells, the memory is constructed more efficiently. The current teachings therefore provide a new way to build 3D programmable devices. Such devices include a programmable element constructed in a substrate layer or plane that "configures and aggregates programmable elements within a plurality of circuit blocks such that the programmable elements form a larger cluster on the substrate layer. Each cluster is configured by a configuration memory unit positioned vertically above the programmable elements. A memory cell in the array is coupled to one or more programmable elements. Therefore, a plurality of programmable 134972.doc 31 · 200931806 component clusters are programmed by a plurality of configuration memory cell arrays. This device provides the ability to vertically configure the FPGA to the user's instructions from a user perspective. Once the user is satisfied with the performance and functionality, the user can easily change the configuration memory unit from an expensive 3D RAM element to a cheap ROM element to freeze the design in an ASIC form. This change does not require design activities, saving the designer's considerable NRE cost and time. It further saves expensive boost ROM in the system board. Easy-to-transfer customization from an original smaller, cheaper and faster pd or FPGA ASIC will greatly enhance time to market, © performance and product reliability. [Embodiment] In the following detailed description of the invention, reference to the drawings These specific embodiments are described to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the invention. Definition: The terms "wafer" and "substrate" used in the following description include any structure having an exposed surface, which is used to form the integrated circuit (1C) structure of the present invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to a semiconductor structure during processing and may include other layers that have been fabricated thereon. Both the wafer and the substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, SOI materials, and other semiconductor structures well known to those skilled in the art. The term system is understood to include semiconductors, and the term "insulator" is defined to include any material that is less conductive than a material known as a conductor. Therefore each 134972.doc -32- 200931806 1C includes a substrate. ❹

The "defective module layer" includes a structure fabricated using a series of predetermined program steps. The boundary of the structure is defined by a - program step, - or a plurality of intermediate program steps, and a final program step. The resulting structure is formed. On a substrate, a section of a semiconductor device can be used to identify the boundary of the module layer. It should be understood that some processing steps such as photoresist patterning and cleaning do not leave a junction (4) printed on the module layer. Steps to understand some of the processing steps such as deposition and engraving do not leave the structure imprinted in a module layer. Thus a module layer includes processing steps that may or may not form a structure. The term "pass gate "&"Switch" means a structure that transmits a signal when it is turned on and blocks the signal transmission when it is turned off. - The transfer gate connects two points when it is turned on and turns off two points when it is turned off. The transfer gate couples two points when turned on and decouples two points when turned off. A pass gate can be a floating gate transistor 'an NMOS transistor, a pM 〇s transistor or a CMOS transistor pair . The closed electrode of the crystal determines the connected iL' CMOS pass gate needs to be coupled to the complementary signal of the NM〇s & pM〇s gate electrode. A control logic signal is connected to the transistor for the programmable logic The gate electrode - the transfer interpole can be modulated by a conductivity of 7 L. The conductivity can be varied between a sufficiently conductive state and a sufficiently non-conducting state by a configuration member. The configurable component can comprise a Chemical, magnetic, electrical, optical, and ferroelectric or any other characteristic that allows the element to change its conductivity between the two states. The term "buffer," includes receiving a weak incoming signal and emitting a strong output. One of the structures of the signal. The buffer provides high drive current to maintain signal integrity. 134972.doc -33- 200931806 The buffer includes a repeater that updates the signal integrity in long lines. The buffer further includes a -single-inverter, and a series of connected inverters, wherein each of the inverters in the series is relatively large in size to provide a higher drive current. The 'terminology' bridge includes a structure that manages one of the lines or a set of routes within the cluster. The signals arriving at the bridge on the line can be transmitted to the bridge or multiple other lines. The device includes a simple I transmission, a buffered transmission, a one-way or a multi-directional routing on the line cluster. The bridge includes an open block, a MUX, and a line. The term "configuration circuit" includes one or more Configuring components and connections that can be programmed to control one or more circuit blocks in accordance with a predetermined user desired functionality. The configuration circuit includes the memory component and an access circuit for modifying the memory component (hence the memory circuit). A memory component in the configuration circuit is coupled to a programmable circuit block to configure the circuit block. Therefore, a configuration circuit is different from the memory device. The configuration circuit does not include the logic transfer gate controlled by the memory component. In the specific embodiment, the configuration circuit includes a plurality of memory components to store instructions. state An FpGA ^ In another embodiment, the configuration circuit includes a first selectable configuration in which a plurality of memory elements are formed to store instructions to control one or more circuit blocks. The circuit includes a second alternative configuration in which a predetermined conductive pattern is formed in place of the memory circuit to control substantially identical circuit blocks. The circuit includes a diode such as a diode, a transistor, a resistor, a capacitor a metal link, etc. The memory circuit also includes a thin film element 134972.doc -34-200931806, a τ π acupoint, a configuration circuit including a predetermined conductive pattern including a channel, a resistor, The capacitor circuit or other suitable ROM circuit replaces the RAM circuit to control the circuit block. The configuration circuit should not be confused with the memory circuit in the memory device. The term "time multiplexing" includes distinguishing a value in the time domain. Capability. This value can be a voltage, a signal, or any electrical characteristic in an IC. A plurality of time intervals form an effective time period. During the time period, a value

A plurality of valid states are included: each state is attributed to each time interval within the cycle. S provides a component at this time to identify a plurality of valid values in the day-to-day cycle. The term "geometry" is defined in this application as the shape of a particular structure or circuit. The geometry includes an area and a boundary. Thus circuit geometry refers to the shape or layout footprint of the circuit components of the circuit. In a Cartesian coordinate system, the circuit geometry can take the form of a triangle, a square, a rectangle, a Τ, an L, or any other shape. The rectangular geometric structure is characterized by a first dimension in a first direction and a second dimension in a second direction orthogonal to the first direction. The circuit geometry includes a substrate layer, the area, and the size of the circuit layout footprint on the boundary. The term "horizon" as used in this application is defined as a plane parallel to a conventional plane or surface of a wafer or substrate regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction that is perpendicular to the horizontal direction as defined above. For example, upper ", side", "higher", "lower", "above" The lower layer is defined relative to the conventional plane or surface on the top surface of the wafer or substrate regardless of the orientation of the wafer or substrate. Therefore, 134972.doc -35· 200931806 The following detailed description does not It is considered to be of a limited meaning. ^ Use the programmable transfer gate logic shown in Figure 3 (for a three-dimensional '· 'point connection'. However, the memory component that generates the control signal So is located. The transfer gate logic element is above or below but not adjacent to: the pass gate. A plurality of pass gates can be configured by a plurality of vertical face memory devices. Thin film transistor (TFT) technology or any other suitable technology can be used. A vertical configuration is achieved. Regardless of the vertical position of the memory component, a new vertical interconnection scheme (four) that needs to be navigated through the horizontal interconnection is combined with the plurality of vertical memory components to the plurality of programmable components, such as 33. A plurality of inputs (node A) may be coupled to the plurality of outputs (node B) using the plurality of pass gate logic elements. In one of the switches 3D configuration of Figure 4B, including the entire configuration of the memory elements The circuit can be positioned above the transfer gate. In another embodiment, only the SRAM latch can be positioned above the transfer gate 410 and the decoder transistor (eg, 4〇1, 402 in Figure 4a) can be It is positioned side by side with the transistor 410 in Fig. 4β. Since the gate electrode of the transfer gate 41 is designed without a current leakage path (i.e., it is a high impedance node), an extremely small current level is required to drive the gate. The electrode is turned on or off. The configuration circuit (450 in Figure 4) needs to generate two outputs (logic zero and logic one) to program the NM〇s (or PMOS) pass gate in the connection ^ 3D The configuration circuit 450 includes a memory component. Most of the CMOS SRAM memory delivers a logic zero or a logic one output. The 3D memory component can be configured by the user to select the polarity of the S, thus selecting the state of the connection. Memory component can Volatile or non-volatile. In volatile memory, it can use one or more DRAMs, 134972.doc • 36· 200931806 SRAM, optical or any type of memory component that can output a valid signal s〇 In non-volatile memory, it can be a fuse, a fuse, an EPROM, an EEPR0M, a flash memory, a ferroelectric, a magnetic or any other kind of memory device that can output an effective signal S〇. The signal % can be output directly from one of the memory elements or from an output of the configuration circuit. An inverter can be used to restore the S〇 signal level to the full rail to rail voltage level. The SRAM in configuration circuit 450 can operate at an increased Vcc level to output an increased S〇 voltage level. This is especially feasible when constructing SRAM in a separate TFT module. Other configuration circuits for generating an effective S〇 signal are readily available to those skilled in the art. The TFT transistor, the switching device, and the latch SRAM unit are described in the application Serial No. 10/979,024 filed on Nov. 2, 2004, filed on Nov. 14, 2003. No. 10/413,809 (now US 6,855,988) and the application Serial No. 10/413,810 (now US 6,828,689) filed on Apr. 14, 2003. It shows the components and methods used to construct the 3D transistor and storage device. In a preferred embodiment, the configuration circuit is constructed on a thin film semiconductor layer that is vertically positioned above the logic circuits. The SRAM memory component (such as a thin film transistor (TFT) CMOS latch as shown in FIG. 4A) includes a gate formed substantially different from a first semiconductor single crystal substrate layer and used for a logic transistor structure Two lower performance back-to-back inverters on the two semiconductor film layers of the very polysilicon layer. This latch is stacked on top of a logic circuit for slow memory applications that do not have a loss of cost and cost. This latch is tuned to receive power and ground power in addition to the configuration signal. 134972.doc -37· 200931806 Pressure. Two stylized access transistors for the TFT latches are also formed on the thin film layer. Thus, in Figure 4B, all six configuration cell systems shown in 450 are constructed in a tft layer vertically above the transfer transistor 41A. The electromorph 410 is in the conduction path of the connection and requires a high performance single crystal: a crystal. This vertical integration is economically possible to add an SRAM-based configuration circuit at an additional cost to create a programmable solution. This vertical integration extends to all other memory components that can be vertically integrated above the logic. ❹

A new 3-dimensional programmable logic device utilizing a thin tantalum transistor configurable circuit is disclosed in the application Serial No. 1/267,483, application Serial No. 10/267,484 (now abandoned) and application The serial number is 1〇/267,51 1 (now US 6,747,478). The disclosure illustrates a 3£> programmable device and a programmable application-specific convertible device. The 3D PLD is fabricated using a programmable memory module, wherein the memory module is positioned above the logic module. The ASIC is fabricated using a conductive pattern instead of the memory module in the 3D PLD. Both the memory module and the conductive pattern provide the same control of the logic to preserve the logic functionality mapped to any device. For each set of memory bit patterns, there is a unique conductive pattern to achieve the same logic functionality. The vertical integration of the configuration circuitry results in a significant cost reduction for the PLD, and eliminating the TFT memory for the ASIC allows for additional cost reductions for the user. Next, a wafer having such vertical memory integration will be described. However, such teachings do not teach how to configure the programmable elements in the logic module, how to configure the memory elements in the memory module, and how to interconnect the 134972.doc •38- 200931806 And other modules. One of the obvious innovations in FPGAs comes from interconnected fabrics, which are spliced and non-programmable components – to make them predictable in a soft environment. The current disclosure explains how to construct such 3D PLDs as well as 3D FPGAs.

Figure 6A shows a top plan view of a -3 FPGA (or PLD)-first embodiment in accordance with a first embodiment of the present invention. It comprises a semiconductor wafer (or integrated circuit or region 〇1) obtained by dicing-fully processing the semiconductor wafer by methods and techniques known to those skilled in the art. 6G1 has a boundary, and the boundary has a grain sealing area (not shown) to improve the reliability of the wafer as is known to those skilled in the art. The wafer area has a plurality of pads = domains, such as sealed by the grains. A fully enclosed pad region 6〇2. These pad regions 602 can be aligned along the perimeter shown. The pad regions 6〇2 can be staggered along the perimeter, or configured in rows, columns, or the technique. In any other form known, the chip 601 further includes one or more 3-dimensional circuit blocks, such as block 603. In a preferred embodiment, the circuit block 6〇3 includes configuration circuit blocks, such The block system is arranged in an array as shown in Figure 6 A. The array can be composed of a plurality of columns and N rows, wherein N is an integer greater than or equal to one. A circuit block 603 can be constructed to be positioned on the FPGA. On the TFT layer above the interconnect metal layer. The way block 603 can be constructed on a TFT layer sandwiched between interconnect metal layers of the FPGA. The interconnect facilitates circuit connections of the FPGA circuit. The circuit block 603 can include one or more metal layers to construct the configuration circuit. The first block of one of the 3D configuration circuits 603 is separated from the second block of one of the configuration circuits by the substantial space between the two blocks. Such space 134972.doc •39- 200931806 A wide metal bus bar may be included, such as 604 and 605. The equal metal wires may further include power and ground voltage required to supply power to the wafer. The spaces may further include clocks and other metal signals required by the FPGA. The 3D block is not configured to cover the pad region 602 of Figure 6A to facilitate external wire bonding or flip chip bonding or any other type of bonding to the pads. Circuit block 603 hides the top view of Figure 6A Features in the lower block of the block. In a second preferred embodiment of FIG. 6B, a pad 6〇2 can be further positioned over a configuration circuit block 603 to facilitate block bonding of the pads 602. These pads 602 can be familiar with this The redistribution of the metal layer as understood by the skilled artisan is further coupled to the 1/0 structure. The invention is not limited in scope to the illustrative example of the pad configuration shown, and those skilled in the art will recognize other methods of constructing the pad 603. Figure 6C provides a top view of Figure 6A when the fabrication layer (and any metal over the circuit layer) comprising the circuit block 603 is stripped from the wafer. The removal of the circuit block 603 allows the visibility of the underlying block to be additionally These blocks are hidden. In a preferred 3D wafer configuration, it further demonstrates other metal lines that act as interconnects to the underlying circuitry, such as 606 and 607. It displays the intellectual property (IP) core/IP circuit area. Blocks (eg, 61 〇), programmable logic block arrays (eg, 608), and programmable routing areas (eg, 609). In the preferred configuration shown, an IP block 61 is positioned between a first and second logical block array 608. In Figure 6C, the IP blocks are shown as being positioned along the horizontal and vertical boundaries of the logical block array. In other configurations, such IP blocks may be located only along horizontal boundaries or only along vertical boundaries. In other configurations, the plural 134972.doc • 40· 200931806 ip blocks can be aggregated into a larger block that is mixed with a programmable logic array block (eg, 608). In a specific embodiment, the aggregated blocks may have areas that are qualitatively similar to the array of programmable logic blocks. Therefore, the concepts illustrated in the logic region of constructing a 3D FPGA should not be interpreted in a limiting sense as the illustrative diagram shown. Figure 7A is shown to illustrate prior art techniques in configuring a programmable element of a conventional 2" FpGA device. Figure 7A is a top view of the best technology commercialized by Xilinx. The metal layers and the isolating oxide layers are removed from top to bottom in Figure 7A, so the transistor structure is visible. Therefore, the boundary of the gate active multiple Si region and the contact stamping are seen on the photo. In Figure 7A, it is seen that the SRAM cells (e.g., 7〇7) are arranged in column 7〇4 and the SRAM output is coupled to the programmable elements. Some of the output is constrained in polysilicon (polysilicon) as shown in Figure 7-8, while the other outputs are coupled by metal that has been removed and not visible. In column 〇4, two SRAM cells 70 and 7071) are configured to be back-to-back, and the pair is replicated to form a column of memory cells. The transistors in columns 7〇1, 7〇3, and 7〇5 form buffers, each of which is coupled to the signal input and/or output by a programmable circuit. Columns 702 and 706 show programmable multiplexer circuits, each gate of a MUX is lightly coupled to a sram unit HitUH as seen by more _ or by having removed and cannot See the metal). The programmable elements in Figure 7A (e.g., gate polymorphs in the MUX of columns 7〇2 and 7〇5) are seen as being used with the (four) bits to achieve layout area efficiency. The other columns of the 8 oct. 8 unit similar to column 704 are positioned below the buffer column 7 〇 1 in this device configuration. It should be noted that from the point of view of the memory bit density of 134972.doc -41 - 200931806, the 8 denier "cell density in a columnar region must be independently stylized in the region localized above and below the memory column. Matching. In Figure 7A, each SRAM cell has an output (not shown metal) and the output is coupled to one or more programmable elements. Therefore, "the latest prior art" The components are: (1) mixed with the SRAM cell, (ii) configured in columns to efficiently couple logic to the cell, and (iv) have row stripes orthogonal to the memory column

The stylized and SRAM component matching density in the port, (iv) is the output of the sram unit. The best memory area is achieved when the memory cells are arranged in larger blocks, rather than when the memory cells are placed individually or in pairs. This efficient memory region cannot be used in a 2D FPGA because each memory cell must be coupled to one or more programmable components. A memory block (deeper than a few bits deep) does not have enough space on top of the array to construct the output of each memory cell to - or multiple adjacent programmable elements Metal Interconnects ^ According to the presently preferred embodiment, a logical block of 3D touch eight is constructed in the case where the surface substrate of the Shixi substrate is free of tSRAM cells. Figure 7 shows a - the specific embodiment of the -programmable logic unit. Alternatively, Figure 7A may be referred to as a logical block, a logical = unit-unit unit, a basic logical element, or by any other name. It can provide multiple inputs - complex logic manipulation. The unit includes a plurality of programmable circuits, such as 711 through 717, each of which includes a plurality of randomly located programmable elements (or the # " 7 programmed input nodes to which the control signals must be coupled). The unit may include a first dimension 134972.doc • 42- 200931806 in a first direction and a second dimension orthogonal to one of the first directions in a second direction. In a rectangular rectangular Cartesian coordinate system, the unit can include a rectangular geometry. In a circular coordinate system, the unit may comprise a circular geometry having a characteristic radius. The unit can have a square geometry or any other geometry. Metal interconnects can reside permanently above the cell geometry. The first plurality of metal interconnects can be used as a regional interconnect. A regional interconnect can couple circuit elements within the unit to provide coupling of adjacent nodes. The first plurality of interconnects can be used as a global interconnect. The global interconnect can provide circuit elements in a first unit of cells to couple to circuit elements in a second unit of cells. - or multiple interconnections can be programmatic. — or multiple interconnects can be fixed and not stylized. The unit of Figure 7B includes programmable logic elements in programmable circuit 711. The programmable logic elements can be any of the m (Mux) circuits, a look up table (LUT) circuit, an arithmetic logic unit (ALu) circuit, an AND/OR logic circuit, or a programmable logic device. Among other logic components. In this discussion, the LUT circuit is based on the purpose of explanation to illustrate the use of logic elements in the programmable unit cell without limiting the scope of the present invention to LUT logic. The user configurable data for LUT 711 remains in the configurable memory unit located above the layout area shown in Figure 7B. In other embodiments, it may be advantageous to maintain a checklist of values for the LUT lookup resident on a Si substrate having a LUT geometry adjacent to the circuit block 7ι. - Deaf (3) The structure may include 22 SRAM cells to maintain configuration data, while the -4 input circuit may require 24 SRAMs to hold the F material. A reference to a closed reference 134972.doc • 43· 200931806 reveals a separable LUT structure with 2~ solid configuration bits (for N input LUTs) to efficiently package logic. Therefore, the LUT 7 11 can be a splittable/separable LUT circuit. It can be a 6-input, 8-input or a higher-input LUT circuit selected in the architecture that optimally optimizes the logic unit. One or more LUT structures can be located in a logical unit. A plurality of configuration memory unit holding data as a 3D SRAM of the configuration memory unit is used to program the lookup value of the LUT circuit. Therefore, one of the outputs of a configuration memory bit must be coupled to a LUT circuit 7 11 as a data input (also known as a LUT value input). This input is randomly located within the LUT layout area shown in 711. The output of a vertical positioning memory unit can be buffered prior to being coupled as an LUT value input to the LUT circuit. An LUT circuit can be programmed to construct a logic function by changing the data stored in the configuration memory. A plurality of LUT circuits can be combined to construct a larger (higher input) logic function. A LUT circuit requires one or more primary inputs received in real and question signal levels, wherein the LUT circuit outputs one of the input logic functions in one or more outputs. Such inputs W and outputs can be coupled to a plurality of interconnects by programmable components. A programmable logic unit in Figure 7B can include a programmable input 'MUX, such as 712, 715, and 716. The input MUX can be constructed as a single level or multi-level MUX. One of the first levels of the MUX provides one of a plurality of interconnects that can be programmatically coupled to a logic unit input. One of the second stages of the MUX can provide a plurality of inputs of the logic elements that can be programmatically coupled to a LUT input. Thus there may be a complex level of programmable selection for a given line to couple as an input to a LUT logic. The 134972.doc • 44- 200931806

e Stylized storage slaves are located in the configuration memory above the geometry of Figure 76. The programmable MUX is comprised of - the output memory unit - in the preferred embodiment, the memory unit is a TFT SRAM memory unit. In a preferred embodiment, the (4) unit can include a voltage divider circuit to tap a selectable voltage level that is different from the tft sram operation level. Because of &, a plurality of sram memory cells, a plurality of outputs 'each-output are lighted to — or a plurality of cis X transistor gates to programmatically input MUX 712, 715, and 716. The programmable elements are randomly g& placed in the logical unit. These inputs can be configured in a particular configuration to maximize the connectivity of the input to the interconnect above the unit. In a preferred embodiment, the first level can be located at the circumference of the logic unit. In a preferred embodiment, the second level of the MUX can be gathered near the center of a logical unit. The color ux component is a switch. Providing a connection state and a disconnection type. In the connection state, the MUX is coupled to a first node to a second node in a broken (five) state, and the first node is decomposed from a second node. Reasonable electrical coupling and decoupling to separate a connected state from a broken j state. In an FPGA, this memory output is required to provide this distinction. This distinction is usually not required for memory cells in memory applications. . A programmable logic unit in Figure 7B can include a programmable register. For example, 714. A register can be used to implement the synchronization logic calculations in the logic unit. - The temporary storage 11 can be bypassed to implement the asynchronous logic in the - logical unit. - The scratchpad can be used to store -input or -output in the logic unit or outside of the logic unit 134972.doc -45.200931806. The register can be a latch, a flip-flop or any other storage device used in an electronic circuit. One or more global signals can interact with the storage device. Such signals can be clocked, set, or signal-free. These registers provide the configuration and components of the area inversion signal. In the closed disclosure by reference, the configurable storage device is shown as having a changeable response sequence, such as by orphan or d. Therefore, the register 714 can configure a user desired state. The input to the scratchpad and the output of the scratchpad can be configured as desired. The logic unit can include a plurality of registers. A programmable logic unit in Figure 7B can include a programmable output MUX, such as 717 and 718. The output Mux can be constructed as a single or multi-level MUX. One of the first levels of the MUX provides a programmable interconnect to be coupled to the logic unit input. One of the second stages provides a logic unit output for coupling to a buffered LUT output by a programmable component. Thus there may be a complex level of programmable selection for a given line to couple to one of the buffered outputs of a LUT logic. The programmability is stored in a configuration memory located above the geometry of Figure 7B. The programmable MUX is configured by one of the configuration memory cells. In a preferred embodiment, the memory unit is a SRAM memory unit. Thus, a plurality of SRAM memory cells produce a plurality of outputs, each output coupled to one or more MUX transistor gates to program output MUXs 717 and 718. The programmable components are randomly arranged within the logic unit. The output MUXs can be configured in a particular configuration to maximize the connectivity of the output to the interconnect lines above the unit cell. A 134 134972.doc -46 - 200931806 is a switch. It provides a connected state and a disconnected state. In a connected state, the MUX couples a first node to a second node. In an off state, the MUX decouples a first node from a second node. Therefore, it is necessary to properly couple and decouple to separate a connected state from a disconnected state. * In an FPGA, this memory output is required to provide this distinction, which is usually not required for memory cells in memory applications. A programmable logic unit in Figure 7B can include a programmable routing circuit, such as 713. The routing circuit can be constructed as a single stage or multiple stages 〇 MUX. The routing circuit can include a buffer structure to buffer the signal. A routing circuit can facilitate a first line segment to be coupled to a second line segment by a programmable component. Thus an advanced programmable circuit network can be created by one or more of the plurality of logic cells. Some lines can be terminated in a routing circuit. A termination line can be coupled to one or more other lines in a routing circuit. Some lines can be passed in a routing circuit. A transmission line can be connected to _ or a plurality of other lines in a routing circuit. - Optional, the circuit can include the -first level of the MUX. The first level can provide a plurality of lines to a buffer input: the secret circuit can include a hall-second level. The position of the job "seven' supply phase σ a buffer output to a programmable configuration of a plurality of lines. A bidirectional line connection can be provided in a routing circuit. The routing circuit includes a vertical and horizontal circuit. One or more specific embodiments that may be used in the routing circuit in the 3D FPGA are described in further detail with reference to the closed disclosure. There is a complex level of programmable selection for a given first line to lighten a second line, so a routing tool can efficiently route - 134972.doc -47- 200931806 ❹ ❹ FPGA Interconnect The signal in the fabric. The programmability is stored in a configuration memory located above the geometry, structure of Figure 7B. The programmable routing circuit is configured by engaging one of the outputs of a configuration memory unit of the routing circuit. In a preferred embodiment, the memory cell is a TFT SRAM § memory cell. Thus, a plurality of SRAM memory cells generate a plurality of A-master-output system faces to - or a plurality of transistor idlers to program the routing circuit 713. The programmable circuit component of the routing circuit 713 is disposed in the logic unit. The routing circuits can be configured in a particular configuration to maximize line connectivity between the logic units. A programmable logic unit of Figure 7b can be configured by a configuration memory array as shown in Figure 7C. The memory array includes a memory unit 721. The 圯 圯 memory unit is replicated in an array to construct the contiguous memory array. Each memory cell has a first dimension in a first direction and a second dimension in a second direction orthogonal to the first direction. The memory array can include an _ column and a singular line, and the Μ and Ν are integers greater than or equal to one. Thus the memory array comprises a memory unit. The memory array is positioned above the logic unit shown in Figure 7A. The memory, columns, and logic cells can include substantially similar dimensions. Thus the logical list can be viewed as having an array of unit cells, each unit cell having the size of a memory cell. Each memory unit can include one or more memory elements. In a specific embodiment, the memory unit is - SRAM Single 7". In the preferred embodiment, the memory cell is a -8 transistor SRAM cell as shown. In Figure 7D, the memory cell includes two inverters, such as 731, to form a _ latch. Its package 134972.doc • 48- 200931806 includes an access transistor such as 732 to change the information stored in the latch. In a global reset mode, all of the bits in an array are coupled to the vss line via the access transistor 732 to set all of the bits to a particular shape.

A decode mode is used to write a data state zero to the latch via access transistor 732. One of the data columns (common to a single column line) is simultaneously configured to be written by a data state such as 733, or the data state is retained as needed

A resistor divider circuit of the transistor is used to generate an output signal from the latch. Depending on the state of the latched data, the output signal is at the voltage VccL level or Vss level. For this TFT SRAM latch, the VccL voltage level can be different from VecT. The data state is an output voltage VccL, while the data state is zero output voltage Vss. A detailed configuration circuit is provided for the 3D programmable device by reference to the closed disclosure. In Figure 7c, a single memory cell is efficiently replicated to construct the array. The memory unit can be placed in a unit cell. The unit cell may comprise a single memory unit or may be larger than a single memory unit. The unit cell can be replicated to form the array of configuration memory, each unit having a memory cell placed within the unit cell. Therefore, the entire unit single 70 area or a part of the unit unit area can be occupied by the configuration memory. Unlike the 21) configuration, the memory output lines are vertically coupled (routed) to the underlying programmable elements. Therefore, there are different metal density limitations compared to this 2D configuration. For example, vertical lines do not have a lateral density limit as in a 2D configuration. However, compared to a 2D configuration, the 'vertical line limits how to locate other routing lines. As disclosed herein, 134972.doc • 49· 200931806 shows that in the preferred embodiment, one of the memory cells vertically positioned above the logic cell has an accurate layout area (to the exact layout of the logical cell layout area below) The area is seen to provide the best configuration of one of the PLE) devices. Moreover, as disclosed herein, the number of memory bits in the memory array is optimized to match the total number (accurate or near accurate) of the individual programmable elements in the logic unit. Thus, for a randomly located programmable 7L piece, one of the programmable logic cells has substantially the same layout geometry as the repeating array of memory cells located above the logic cell, according to one of the current teachings. In other embodiments, such layout areas may be substantially similar and inaccurate. Thus, in accordance with the present teachings, a novel 3D FPGA includes: a programmable logic block (FIG. 7B) having a plurality of configurable components (circuits 711 through 718) randomly positioned within the logical block; a first array of state memory cells (Fig. 7C) having a configuration memory unit 721 that is replicated to construct the first array, the memory unit being coupled to one of the configurable components Or a plurality of memory cells in the first array are coupled to the plurality of configurable components in the logic block to program the logic block to a user specification; wherein the first array ( Figure 7A and the programmable logic block (Fig. 7B) have a substantially similar layout geometry and the first array is positioned substantially above the logical block. It should be readily understood that this can be programmed The logic unit and the array of configuration memory above the logic unit can be duplicated to form a programmable logic array. The individual memory arrays of each logic unit are combined with others to form a larger adjacency effective Memory arrays. The logic elements are further 134972.doc -50- 200931806 steps to generate a larger programmable logic region containing randomly assigned programmable elements. Therefore, according to current teachings, a novel 3D FPG A further The method includes: a plurality of programmable logic units (FIG. 7B), each of the logic units having a plurality of randomly assignable programmable elements (circuits 711 to 718) - the plurality of logic units are configured by One of the memory cells (such as each cell in Figure 7D) abuts the array configuration, wherein the array of memory cells includes a layout geometry substantially similar to the plurality of programmable logic cells; and the memory cells The array is positioned on the plurality of programmable logic units, and the plurality of memory cells of the array are coupled to the programmable elements to program the plurality of logic units to a user specification. A 3D FPGA system is relatively easy to construct by replicating an extremely small single programmable logic unit that is efficiently constructed. In one embodiment of the 3D construction The array of memory cells in Figure 7C is positioned over the plurality of programmable elements in the logic cell of Figure 7B. In a preferred embodiment, a plurality of metal layers are positioned at the logic elements And between the memory cells. This configuration requires a special configuration of the metal layers positioned between the two circuit blocks. Figure 8 shows a metal for vertically coupling the configuration memory to the programmable elements. A specific embodiment of the construction. In Fig. 8, a metal stub such as 8〇1 is provided for coupling a unit such as a memory unit in Fig. 7D (the memory cell in Fig. 7A) One of the outputs 721) is output to one or more of the programmable elements of Figure 7B configured by the signal bits. The metal stubs 801 are replicated in an array. The one very small metal unit cell 8〇3 can be configured to have a dimension 805 in a first direction and a dimension 804 orthogonal to the first direction 134972.doc 51 200931806 2:!: direction. The dimensions are matched to the size of the memory array of the configuration memory unit located at the coupling σ, Jl side. The region 803 shows that the metal is positioned one of the early 70s and one of the metal stubs is positioned in the first region and an adjacent metal line is positioned in a second region. The metal lines span the unit cells, so when a metal array is constructed, it forms a continuous global metal line. In a first embodiment, one of the metal wires, such as 8〇2, is positioned between two adjacent stubs in a second direction as shown in FIG. In a second embodiment, a metal wire system such as Xie is located between two adjacent stubs in a first direction, as if Fig. 8 is rotated 9G clockwise... the wire can be used as a power bus, A ground bus, - clock signal, or any other global control signal line. Thus, the output of the array of one of the memory cells (shown in Figure 7C) is coupled to the programmable component of the -programmable logic cell (shown in Figure 7B) in the -3D programmable logic device (pLD) A metal shank layer (shown in FIG. 8) includes a plurality of metal stubs 8〇3 disposed in a first dimension 805 having a first direction and a second dimension 8 in a second direction The first and second dimensions of the array are the same as the size of the memory cell in the memory cell array. One of the metal busbars is positioned in the first or second direction. Between adjacent short columns. This metal layer provides an efficient coupling of the memory array in a 3D FPGA to the underlying logic and provides sufficient metal for the power, ground, and global signal routing required in the 3D architecture. A cross-sectional view of a first embodiment of a 3D FPGA in accordance with the present teachings is shown in FIG. 9A. Among them, the metal stubs 9, 2, 904, 906 provide the coupling between the above 134972.doc -52- 200931806 memory array and the following programmable elements. Metal wire 905 907 is positioned between adjacent stubs. A plurality of memory cells 916 are positioned above the coupling metal layer. One of the memory cells 916 outputs a light U to metal stub 902 that is further coupled to one or more of the programmable elements in the following cross-sectional view. The coupling between the memory unit (4) and the metal stub 902 includes a channel 915. Between the metal stubs 2 and 904, a longer metal line 903 running perpendicular to the view is used for power, ground or global control signals. In other embodiments, a plurality of parallel global control wires can be positioned between two adjacent metal stubs. A memory unit 916 can include a plurality of memory elements. It may comprise a plurality of transistors, specifically a plurality of thin film transistors. It may include one or more configurable components capable of providing a logic input to the metal stubs 9〇2. A thin germanium transistor, an inverter, and a memory cell suitable for 3D SRAM construction are illustrated by reference to the incorporated disclosure. The memory unit 916 can include a RAM or ROM memory element. A RAM memory unit 916 can further include additional metal lines (e.g., 917) to fully construct a memory array. A metal line 917 can be positioned over a power and ground metal layer comprising 9〇1 to 908 as shown in Figure 9A. Metal regions 901 and 908 can be used as pad regions for 3D FPGAs. When constructing a system having multiple wafers, a pad area such as one of the 901 shown may need to be bonded to other ic devices. In a specific embodiment, pad regions 901 and 913 may be free of memory components positioned above the pupil regions. In another embodiment, a metal region 913 can be positioned and lumped to the germanium region 901 similar to the metal region 917 above the memory cell 916. This metal region 913 can form a redistribution 134972.doc • 53· 200931806 pad area. The redistribution pad region can be coupled to a particular pad region 901 by a distribution metal layer. In a preferred embodiment, the memory unit 916 forms a regular § memory array over the metal stub array 903/905/907 to form a valley-coupled coupling scheme, the metal stub 9〇3/ The 9〇5/9〇7 system can be further coupled to the underlying programmable element through one of the vertical and horizontal connection lines. In the illustrated construction, each coupling terminates at a high impedance node in the programmable logic circuit and the line capacitance is used to stabilize the control voltage on the configured node. A cross-sectional view of a second embodiment of a 3D fpga in accordance with the present teachings is shown in Figure 9B. Among them, a RAM element (in Fig. 9A) is replaced by a R〇M element. In this particular embodiment, an r〇m component is only connected to a metal supply or a metal connection. An R〇M component can be a hardwired RAM component to always store a specific data value (it is easy to see that the two sides of a latch can be shorted to the power supply and ground supply, so the latch always maintains a specific data value. ). In Figure 9B, metal lines 942, 944 carry electrical power, while metal lines 943, 945 carry ground. The metal stub 932 can be coupled to electrical power (metal wire 942) or ground (metal wire 943). The metal stub 934 can be similarly grounded to power (wire 944) or ground (wire 943). Therefore—custom metal patterns provide configuration for the following programmable components. A separate metal layer comprising lines 942 through 945 as shown in Figure 提供 provides the ability to provide different power voltages to stubs 932, 934 as compared to the underlying logic power voltage. If the same power and ground voltage are sufficient, additional metal layers such as 942 to 945 are not required; instead, the power and grounded power in the wires 933, 935 are used to supply power to the short columns to the required voltage level. . Thus metal 134972.doc •54· 200931806 short columns 932, 9M can be customized to obtain a predetermined data value to stylize the following programmable elements. Between the metal stubs 932 and 934, a longer metal line 933 that runs perpendicular to the view is used for power, ground or global control signals. In other embodiments, a plurality of parallel global metal lines may be positioned between two adjacent metal stubs. The description of the incorporated disclosure demonstrates converting a RAM-based PLD device to a R〇M-based PLD device, both of which preserve a timing characteristic, or achieve a higher performance conversion' or achieve a lower Power conversion. Metal regions 941 and 946 can be used as pad regions for 3D FPGAs. When constructing a system having multiple wafers, a pad area as shown may need to be bonded to other IC devices. In one embodiment, pad regions 941 and 946 can be positioned along the perimeter of the PLD. In another embodiment, the pad regions can be positioned in a grid above the top surface of the PLD. A redistribution metal layer can be used to couple the perimeter pad region (e.g., 931) to the redistributed pad region (e.g., 940) above the metal stub region 932. The metal stubs 932/934 can be further coupled to the underlying programmable elements through one of the vertical and horizontal connection lines. In the illustrated construction, each twist can be terminated at a high impedance node in the logic circuit, and line capacitance can be used to stabilize the control voltage on such capacitor configurable nodes. Another advantage in the current teaching is that there is no switching signal traversing the vertically configured line segment and the configuration line segment can absorb as many detours as needed to maintain the signal integrity of the timing critical line in the FpGA. Figure 10A shows a preferred embodiment of a configuration memory that constructs a programmable element, a programmable interconnect, and a vertical connection. A transistor is used in the module layer 1〇〇1 to construct a circuit. Such circuits include AND, nand, 〇r 134972.doc -55- 200931806 type logic circuits, inverters, buffers, driver type signal recovery circuits, latches, flip-flops, memory type storage circuits, MUX, switches , crossbar type connectivity circuit, LUT, ALU, DSP, CPU type calculation circuit, PLL, DLL, AtoD, DtoA type analog circuit, and ip block. Therefore, the mode group 1001 includes the programmable found in the typical integrated circuit. And non-programmable circuit components. The module layer 101 may include one or more metal layers to provide a level of interconnection among the transistors. The module layer 101 can include one or more configurable components, and/or one or more components that form the configuration circuitry required for the configuration module O - or a plurality of configurable components One of the knives. A plurality of metal interconnects in the module layers, such as 1002, 1〇〇3, and 1〇〇4, are provided to interconnect circuit blocks within the module layer 101. In a preferred embodiment, a plurality of interconnect lines in the module layer 1002 traverse a first direction. A plurality of interconnect lines in the module layer 1003 traverse a second direction orthogonal to the first direction. A plurality of interconnect lines in the module layer 1004 traverse the first direction. Similarly, a plurality of metal module layers are vertically configured to provide enhanced routing between circuit nodes in the module 1001. Such interconnect lines are present but are not shown in Figure 9A. A module layer 1 〇〇 5 includes a plurality of configuration memory cells such as 916 in Figure 9A. (Not shown in Figure 1A, the metal short column layer 9〇1 to 908 from the figure). A configuration memory unit can include a unit cell area 1006. The unit cells are replicated in a contiguous array to construct the module layer 1005. Each of the module layers 1〇〇5 is coupled to one or more programmable elements in the module layer read, which is not shown in Figure i〇a. In order to facilitate this shank, a new Lai metal layout pattern will be discussed. 134972.doc •56- 200931806

For example, the metal module layer includes a plurality of repeating regions. Within the - region, the first portion includes substantially longer metal lines. The long metal wire may span the entire length ' or the majority of the length in the first or second direction. Within the repeating region, the second portion includes substantially short metal lines. Short metal, can span the length of - unit unit _, several unit units, or one unit single 7L. These lines can traverse the first and second directions as needed. These short lines facilitate the vertical interconnection of the configuration memory cells with the underlying programmable elements. Therefore, it should be noted that the cell touch is vertically coupled to the -short line in the metal module layer 10G4, and then coupled to the one-metal metal line of the module layer, etc. until it is coupled to the module layer 1〇〇1. The stylized logic elements & externally these short lines facilitate the coupling of long lines to the switching TLs in the module layer 1001. For example, if a long line in the module layer 1〇〇3 has to be coupled to a long line in the module layer 1002, it must first traverse one of the switches in the module layer 1〇〇1. The node, and one of the switches, the second node must cross back. This line path can carry a critical switching signal to the design. The configuration shown allows a line to literally pass vertically down the short line area to minimize the timing delay associated with the longer routing offset of the 2D FPGA. A second aspect of one of the novel wafer configurations is then disclosed. Using a 3D structure not shown in FIG. 10A, a smaller vertical line including a unit cell area such as 1006 is specifically formed in each of the module layers (for example, 1〇〇2 to 1〇〇4) to include vertical alignment. structure. A single unit cell from the uppermost configuration module layer 丨〇〇5 to the lowermost logic transistor module layer 〇〇1 is shown in Figure 1 〇B to illustrate this novel 3D configuration in more detail. Top configuration memory module layer 1〇17 (similar to 134972.doc •57· 200931806

912) in Figure 9A now includes a single memory unit. It can be a 4T

Or a 6T or 8T SRAM cell, or any other memory component. In Fig. 10B, the 8T-SRAM cells of Figs. 7C and 7D are displayed for illustrative purposes. Metal layer 1016 (same as 901 through 908 in Figure 9A, which is not shown in Figure 10A) includes metal stubs 902, 904 as shown in Figure 9A. The metal stubs in the module layer 1016 are coupled to the sram unit outputs in the module layer 7 (coupling not shown). The metal lines in the module layer 1016 span the entire long dimension, so the repeating unit forms a long metal line. In other embodiments, a plurality of longer parallel metal lines can be constructed in the module layer 1 〇 16. Another module layer similar to the module layer 1016 but having metal running in the direction orthogonal to the metal in the module 1〇16 is positioned below the module 1〇16. For convenience, the module layer is not shown in Figure 10B. The lines in the module layer 1〇15 are configured to include a first area and a second area. In the first region, a plurality of lines run the entire length of the unit cell in parallel with each other. When the units are repeated in an array, the lines form a long line ❹ in the second area, and the plurality of lines operate a portion of the unit distance. These lines are used for regional interconnections and can be operated in a specific pre-selected direction as needed. Similarly, the unit cells in the module layers 1〇14 to 1012 have similar line configurations. In a preferred embodiment, the long line systems in the 'vertical adjacent module layers are configured to be positive 2 to each other. In other embodiments {column, the first two consecutive module layers may have parallel long interconnects, and the last two consecutive modules: there are parallel long interconnects orthogonal to the first two consecutive module layers. The metal layer under the module layer is not shown in Figure 10B and may be included in the module layer 1011. Position one or more transistors 134972.doc -58- 200931806 within 7L of the module layer 1011 _ 早. This is a non-repetitive geometry. A plurality of unit cell geometries (e.g., 1011) containing different elements form a complete logical block occupying the module layer 1001 in Figure i〇a. Therefore, a repeating metal and configuration unit is fully integrated with one of the modules 1011 of FIG. 10 and one of the randomly configurable programmable elements in the module 1001. Thus, a vertically configured programmable logic device (PLD) in FIG. 10A includes: a unit cell 1006' wherein the unit cell boundary includes a first dimension in the first direction (eg, 8 in FIG. 8). 5) and a second dimension orthogonal to the second direction of the first direction (eg, 8〇4 in FIG. 8); and an array of configured memory cells 1 〇〇5, the array Constructed by placing a memory cell within the boundary of unit cell 1006 and copying the unit cell to form the memory array; and a plurality of programmable elements positioned substantially similar to the array of configuration memory cells An array of geometric structures 1001 of 丨〇〇5; and an array of first metal elements 1 〇〇4, the array being replicated by one of the unit cells 丨〇〇6 in the array The first metal unit further includes: a first region having one or more parallel metal bus bars (such as 802 in the unit cell 803 in FIG. 8), and a bus bar at the first or second Relative cell boundary Extending to form an all-way busbar line; and a first region having a metal stub coupled to one of the configuration memory cells positioned above the first metal stub (eg, unit cell in Figure 8) 801) in 8〇3 and one or more of the programmable elements located below the first metal stub. The apparatus of FIG. 10A further includes: a second metal unit 1〇〇3 array 134972.doc • 59- 200931806, the array is by copying one of the unit cells 1006 in the array to the second metal unit The second metal unit further includes: a first region having two or more parallel metal lines, a metal line extending between opposite cell boundaries in the first or second direction to form a global routing circuit And a second region having metal stubs and metal lines to facilitate vertical routing of the configuration memory cells and signals. The unit of vertical positioning is shown in Figure 1B. The unit cell in FIG. 10B includes: a substrate region 1〇11 including a portion of a circuit block having a programmable element; and a configuration memory unit 1017' coupled to one of the programmable elements Or more, wherein: the memory cell is substantially positioned above the substrate region; and the s-resonant cell and the substrate region geometry are substantially similar. The unit unit 7L further includes: a metal unit 1 〇 16 having a configuration memory unit 10 17 size; and a metal stub coupled to the configuration memory unit 1017 and one of the programmable elements Or more, wherein: the metal unit is positioned below the memory unit and above the substrate area; and the metal unit further comprises one or more metal lines adjacent to the metal stub. To construct a larger programmable logic tile, the structure of Figure 10A is further repeated in an array. Therefore, each of the stylized requirements of the region 1001 must be satisfied by the configuration unit density in the module layer 丨〇〇5. The array of efficiently positioned memory cells can now effectively configure the programmable components of random positioning using a vertically coupled configuration scheme. When the structure of Figure 1A is repeated in an array, resulting in a more efficient positioning of the memory cell array, such an array 134972.doc -60- 200931806 efficiently stylizes the higher density in the lower fabric Programmable components. The IDS reference reveals that prior art FPGA products typically combine a programmable logic block with an ip core. Each FPGA vendor places the ιρ block at a preferred location within the programmable logic fabric and couples both the logic and the logic to the interconnect matrix. This IP integration in the novel 3D product is then revealed. Figure iiA shows a first programmable logic tile 11〇1, a second programmable logic tile 11〇3, and an ιρ block 丨〇2 positioned between the two programmable logic tiles. The programmable logic tile 1101 can include a plurality of programmable logic cells 1101a'. The programmable cells include programmable components having programmable logic elements and programmable routing elements. In a preferred embodiment, the tile 1101 is constructed by duplicating a unit of logic unit U01a in an array. Although FIG. 11A shows a 3×3 array for illustrative purposes, the tile may have a smaller or larger number of unit logic cells. The IP block U 〇 2 includes three regions: a first region adjacent to the tile 11〇1. 11〇2a, a second central region 1102b, and a third region 1102c adjacent to the tile 11〇3. The IP block is further constructed such that the area 11〇2b contains substantially no programmable elements. As an example, if the IP block 丨1〇2 is a double-byte memory area, the area 11 〇2b may include a plurality of double-turn memory bits. The entire area does not include a configurable coupling to the configuration memory bit. node. All configuration elements required to configure IP block 1102 are configured in areas 11 02a and 11 〇 2c. Thus, area 11 〇 2a in IP block 102 includes a plurality of programmable elements, such as logic and routing elements, one or more of which are coupled to a configuration memory unit. Similarly, area 1102c in IP block 1102 includes a plurality of programmable elements, such as logic and routing elements, 134972.doc - 61. 200931806 One or more of these elements are coupled to a configuration memory unit. In the example of the ip 埠 ip ip, such a configuration bit can provide the ability to change the width and depth of the memory block. Such configuration bits can be further provided to combine a plurality of entity 6 memory blocks into a single logical memory block. The advantages of this configuration will become apparent during the construction of the configuration memory to stylize these programmable elements. Figure 11 shows the configuration memory structure used to program the programmable elements, the 11〇3, and the logic elements in the ip block 1102. The configuration memory configuration has three areas: the area containing the configuration memory bits and 1113 ' and the area u丨2 which is clearly free of any configured memory bits. The first part of the memory bit in the region mi is a stylized component of the stylized tile 11〇1. The second portion of the memory bit in region 1111 is a programmable element in the region 11 02a of the programmed IP block 117. The two memory bit portions in region jin are combined to form an contiguous array of cells; a single memory cell as shown in 1111a. This results in a very efficient array of larger hate units compared to two separate memory blocks or random s. Thus, unlike prior art configuration memory configurations, constructing an IP block in the manner illustrated and positioning a programmable tile adjacent to the IP block allows for random positioning in both of the circuit components. The stylized component is programmed by a single contiguous array of memory components. It is easy to note that the adjacent array of stylized ιρ regions 1102c of the memory components in region 1113 and all of the programmable components in the programmable tiles 11〇3. Figure 11C shows the 3D vertical positioning of the configuration memory plane above the programmable tile and the IP block. The vertical group 134972.doc - 62 · 200931806 state (e.g., layers 1012 through 1015 in Figures 10A and 10B) is shown based on simplicity. Such interconnects include channel and line structures that couple a single configuration bit (1111 and 1113) in the configuration plane to one or more programmable elements (no) and 1102a in the plane 1102c, 11〇3). It should be further noted that the vertical area between 1112 and 11〇21? is used in the interconnect layer to locate wide power and ground busbars that require larger metal areas. In a first embodiment, the vertical area between 丨 丨 2 and 1102b also includes the driver circuit components and wiring components required to write data to and read data from the configuration memory plane and the 矽 plane. Thus, the three-dimensional programmable logic device (pLD) of FIG. 1C includes: one or more intellectual property (IP) cores 1102, each ip core comprising: a fixed circuit area 11 〇 2b, and a programmable circuit a region n 〇 2a having a plurality of programmable elements for configuring the IP core; and a programmable logic block array region 11 〇 1 comprising: a plurality of entities replicated to form the array The same programmable logic block (for example, 11〇1 a in FIG. 11A), each of the logic blocks further includes a plurality of programmable elements; and a programmable area (by ^(^和丨丨〇) 2&a region comprising: a randomly locating programmable element of the programmable logic block array region and one or more of the IP block programmable circuit regions; and a configuration memory array 1111 'which includes a configuration memory unit (eg, i丨丨la in FIG. 1B) that is replicated to construct the array, the memory unit being coupled to the programmable portion of the programmable region One or more of the components, the record The memory array stylizes the programmable region, wherein: the memory array 11 11 is substantially positioned above the programmable region; and the memory array geometry is substantially similar to the programmable 134972.doc -63 - 200931806 Areas. Figure 12 illustrates the combination of a plurality of programmable tiles and 11? blocks to achieve the three-dimensional vertical configuration advantages according to the current teaching. Figure 12a shows the layout of four programmable tiles 1201, 1203, 1207 and 1209 Configuration, each watt contains a plurality of programmable logic blocks as shown in Figure 7B. Thus each of the tiles is similar to the tiles iioi and 11 〇 3 shown in Figure 11A. Each of 1203, 1207, and 1209 further includes a plurality of programmable elements randomly positioned on the substantially rectangular geometry of the tile, each of the programmable components being constructed on the substrate layer. Further shown are five IP blocks 1202, 1204, 1205, 1206, and 1208. The substantially rectangular ip block contains a geometry that matches the programmable tiles, and thus is positioned as shown in Figure 12A. Between tiles The combined geometry includes a substantially rectangular geometry as shown. Thus, Figure 12A illustrates a very tight and carefully fabricated germanium substrate footprint that is significantly smaller than other methods of combining specified circuit blocks. The Si coverage areas ip blocks 1202, 1204, 1206, and 1208 are similar in construction to the IP block 102 discussed in Figure ha. In one example, it may be as shown in Figure 丨a Four similar IP blocks 11 〇 2 of the same functionality. In another example, 'they can be four different functional IP blocks, each of which is constructed in the manner illustrated in Figure 11A. Each of the IP blocks 12 02, 1204, 1206, and 1208 includes programmable elements and non-programmable circuit components such as programmable logic elements and/or programmable routing elements. In the IP block 12〇2, the programmable elements are located in regions 1202a and 1202c, and the non-programmable circuit components are located in the region 12〇2b. The IP block 134972.doc • 64· 200931806 1202 is positioned between the programmable tiles 1201 and 1203 such that the region 1202a is adjacent to the tile 1201 and the region 1202c is adjacent to the tile 1203 as shown in Figure 12A. In Figure 12A, it can be seen that the IP block 1204 is positioned between the programmable tiles 1201 and 1207 such that the region 1204a is adjacent to the tile 1201 and the region 1204c is adjacent to the tile 1207. In Figure 12A, it can be seen that IP block 1206 is positioned between programmable tiles 1203 and 1209, such that region 1205a is adjacent to tile 1203 and region 1206c is adjacent to tile 1209. It can be seen in Figure 12A that the IP block 1208 is positioned between the programmable ® tiles 1207 and 1209 such that the region 1208a is adjacent to the tile 1207 and the region 1208c is adjacent to the tile 1209. The IP block 1205 is constructed so that it includes four corner regions 1205 & 1205. 1205 (a programmable element in 1 and 12056, having a non-programmable circuit component in the remaining region 1205b as shown in Figure 12A. When the IP block is positioned at the center in Figure 12A, the equal edge Each of the angularly programmable regions is combined with an adjacent programmable region to form a contiguous larger programmable region. For example, regions 丨2, l202a, l205a, and 1204a form a first programmable quadrant. It includes a randomly configurable programmable element within the region. Similarly, regions 1203, 1202c, 1205e, and 1206a form a second programmable image 'limit' that includes stylized random positioning within the region. Similarly, regions 1209, 1206c, 1205d, and 1208c form a third programmable quadrant that includes randomly located programmable elements within the region. Finally, 'regions 1207, 1204c, 1205c, and 1208a form a fourth. Programmable quadrant 'which contains randomly located programmable elements within the region. As can be seen in Figure 12A, no in regions 1204b, 1205b, 1202b, 134972.doc -65- 200931806 1206b and 1208b The stylized circuit components are combined to form horizontal and vertical tracking between the four programmable quadrants. Thus, Figure 12A shows a Si substrate portion of a 3D semiconductor device comprising a programmable tile and an IP block (or A "substrate area." There may be many such area-domains in the 3D semiconductor device. Figure 12B shows a configuration memory element for programming the vertical positioning of the programmable elements of Figure 12A. There are four adjacencies The configuration memory arrays 1211, 1213, 1219, and 1217' each program the programmable elements in the first, second, third, and fourth quadrants of Fig. 12A, etc. The novel system in Fig. 12B The configuration memory elements form an contiguous array to program the programmable elements in the plurality of varying circuits: the programmable elements in the tiling 1201, the IP block areas 1202a, 1205a, and 1204a (from three The way in which the programmable elements in different IP blocks are used. This allows extremely efficient layout of the adjacent configuration memory arrays to program the pre-isolated underlying programmable elements to make the programmable logic tiles and programmable logic The integration of the IP block to which the access is made is feasible. The area 1212 in Figure 12B is substantially free of the configuration S memory element. This type of area is used for wide metal tracking required for power and ground distribution, and Write/read data to the circuit components required for the vertical configuration memory layer. Figure 3C shows the 3-dimensional configuration of Figures 12A and 12B, wherein Figure 12A forms a first circuit layer on the bottom, and Figure 12B forms the second circuit layer on top of the first layer. It is easy to imagine that the layers can be reversed. There may be a plurality of metal layers between the two layers, such layers being simple based and not shown in Figure 12C. Furthermore, it is readily conceivable that the metal layer may be present above the top layer of 134972.doc -66.200931806 or that there may be no metal layer between the two layers shown. In a given quadrant, a configuration memory element is coupled to one or more programmable elements below the same quadrant. A memory component contiguously disposed in one of the arrays of the first quadrants can be fully (or nearly completely) configured to randomly program the programmable elements in the first quadrant on the bottom layer. Such programmable components may belong to a combination of circuit blocks such as programmable logic circuits, "circuits, and I/O circuits. Thus, Figures 12A-C show a portion of a three-dimensional programmable logic device (PLD), # Including: a programmable © logical block (10) 4e, 12G5e, 12G7, and 12G9a) having a plurality of configurable components randomly positioned within the logical block; and a first array of configuration memory single 7L 1217 Having a configuration memory unit (eg, memory unit 丨丨丨丨a in FIG. i 1B) that is replicated to construct the first array, to which a memory unit is coupled One or more of the plurality of memory cells in the first array are coupled to the plurality of configurable components in the logic block to program the logic block to a user specification; ❹ wherein the An array 1207 and the programmable logic blocks (12〇4c, 1205c, 1207, and 1209a) have a substantially similar layout geometry 'and the first array is positioned substantially above the logic block. 13A and B show a novel 3D PLD Figure 13B is an enlarged view of a portion of Figure 13A for better illustration of the circuit blocks. "On the basis of an illustration, only a few components encountered in a typical PLD are shown. Figure 13 shows a plurality of programmable elements such as 1305. An I/O unit, a plurality of programmable IP blocks such as 13〇4, a plurality of logical blocks such as 1303a-1 or 1303a_2 or 1303a_3. The logical block may be a logical unit or a logic 134972.doc - 67· 200931806 block (1303a_2) or a logic array block (1303a-3). Therefore, FIG. 13 is a three-dimensional programmable logic device (PLD), which includes: a plurality of j/〇 units 1305, each The I/O unit includes: a fixed circuit area (1305a and - 1305b); and a programmable circuit area (1305c) having a plurality of programmable elements for grouping the I/O unit (1305). And one or more intellectual property (IP) cores 1304' each IP core includes: a fixed circuit area (1304b); and a programmable circuit area (1304a or 1304b) having to configure the IP core a plurality of programmable components; and one can be stylized A block array region (1303a-3) comprising: a plurality of substantially identical programmable logic blocks (1303a-2 or 1303 a_l) copied to form the array. Each of the logic blocks further Included in the plurality of programmable elements' and the programmable region 1303a, comprising a randomly configurable programmable component of the programmable logic block array region 13 03a_3, one or more of the ip core programmable circuit regions (eg, 1304a, but adjacent to 1303a_3) and one or more of the I/O unit programmable circuit regions (eg, 13〇k, but adjacent to 1303a_3); and a configuration memory array 1313a that includes replicated a configuration memory unit 131 3a_1 for constructing the array, a memory unit coupled to one or more of the programmable elements in the programmable region, and a memory unit 13 13a stylized The programmable region 丨3〇3a, wherein: the memory array is substantially positioned over the programmable region, and the memory array and the programmable region geometry are substantially identical. In one embodiment, a 3D device, such as a 3D pld or 3D FPGA, provides a common pin to reduce pin count and thus cost. In its specific embodiment, 134972.doc • 68· 200931806, in the specific embodiment, - or a plurality of configuration signals are used to output the output pin of the buckle device, and the king provides the multi-function pin m, the multi-function moon pin The system is coupled to at least one input buffer input and at least one output buffer output. The output of the input buffer can be combined to a programmable circuit, and the input to the output buffer can be tapped to the circuit of the device. - or multiple buffers and programmable assays configurable to achieve a _ high impedance state (ΑΚΑ tristate). These buffers and halls X can be configured by configuring the memory and internal and external control signals that are received through other multi-function contacts. Therefore, the outputs of the buffers are shunted in parallel with the individual control signals, so that each of the shared pins is connected from the buffer to both the control signal and an output. In response to a control signal, the output of the buffer is deactivated (ie, tri-stated), so external configuration data (eg, self-energizing) is read from the shared pin onto the wafer - ❹ = In memory (such as SRAM). When this configuration is performed, this is combined to the other input or output of the 3° wafer. In short, the configuration signal can be received by the „3D: 曰片 controller in response to the same section (for example, reset), and the other devices of the 黧铕 及 and 1^ count the other time and the ancestor of a controller outside the controller ^ Therefore, the 2 ° δ tens of the various configuration signals can be greatly reduced. In another embodiment, a multi-pin is provided to handle the power and pulse input. In this embodiment, the Ms number is temporarily embedded. In order to adjust the power pin from the inside of the house = the power pin in Zhensheng. In the following example, provide the information of the time of the day. In another case, the other connection: > Pins for handling power and resetting inputs. Other pin sharing configurations can also be used. I34972.doc -69· 200931806 In another 35 embodiment, the pins in the device can be configured to be optimized Grounding and power distribution to the wafer. For example, the device can have a large ground or power region at the center of one or more input/output pins and the pins include configurable components coupled to the regions. Illustrated in the disclosure incorporated by reference According to the current teaching of a 3D ic manufacturing, a brief description is provided based on the completeness. By using a standard logic program flow used in the manufacture of asic to form a transistor and routing for programmable and fixed circuit components. After constructing a particular interconnect layer, additional processing steps for forming a 3D configuration memory component are inserted into the logic flow. The following terms used herein are abbreviations associated with certain processes. Abbreviations and their abbreviations The system is as follows: VT threshold voltage LDN lightly doped NMOS drain LDP lightly doped PMOS drain LDD lightly doped bungee RTA rapid thermal annealing Ni nickel Ti Ti Ti Titanium nitride W crane s source D bungee G gate ILD interlayer dielectric 134972.doc -70- 200931806 IMD intermetal dielectric

Cl contact 1 V1 channel 1

Ml metal 1 p 1 polycrystalline 1 P-positive dopant (boron species, bf2) N-negative dopant (phosphorus, arsenic) P+ positively high dopant (shed species, bf2)

N+ negative high dopant (phosphorus, arsenic)

Gox gate oxide C2 contact 2 LPCVD low pressure chemical vapor deposition CVD chemical vapor deposition 氧化物 oxide-nitride-oxide LTO low temperature oxide in the 1C manufacturing industry, a logic program used in a substrate layer A CMOS device is fabricated on it. First, an electro-crystalline system is constructed on the germanium substrate, and a plurality of metal layers are used to interconnect the transistors to form a desired circuit. These circuits are accessed through a pad structure that is coupled to an external device. These cm〇s devices can be used to construct AND gates, 〇r gates, inverters, LUTs, MUXs, adders, multipliers, Ip blocks, memory, and transfer gates in an integrated circuit. Logic function. Circuits constructed using logic programs are well known in the 1C industry and are presented only in this context for illustrative purposes. - An exemplary logic program may include the following steps - or more: 134972.doc -71 - 200931806 p-type substrate startup wafer shallow trench isolation: trench etching, trench filling, and CMP sacrificial oxide '* PMOSVt mask and implant • NMOS VT masks and implants, well implant masks and implants through field well implant masks and implants through field dopant activation and annealing 〇 sacrificial oxide etch gate oxidation /Double Gate Oxide Option Gate Polycrystalline Platinum (GP) Deposition GP Mask and Touch LDN Mask and Implant LDP Mask and Implant Spacer Oxide Deposition and Spacer Etch Ν+Mask And NMOS Ν+ G, S, D Implants + Mask and PMOS Ν+ G, S, D Implants' Ni Deposition • RTA Annealing - Ni Deuterated Metal Deposition (S/D/G Regions and Interconnects)

Unreacted Ni Etching ' ILD Oxide Deposition and CMP

Contact C 1 Masking and Etching Metal M1 Deposition, Metal Masking, and IMD Oxide Deposition and CMP -72-134972.doc 200931806 Channel v 1 masks and etches a plurality of metal and channel patterns to form interconnect passivation oxide deposition The 塾 mask and the remainder of this logic program form a layer of a transistor on a substrate. This logic program builds a plurality of module layers as defined in the disclosure. A first modular layer can be patterned into a single metal layer. A second module layer can include all processing steps from the beginning to including the ILD oxidative deposition and CMP steps. The integrated circuit constructed with a logic program is defined herein as 2D 1C. A CMOSFET thin film transistor (TFT) module layer or a complementary gated FET (TFTated-FET) TFT module layer can be inserted into a logic program at various points throughout the logic process to construct 3D 1C. In a first embodiment, the TFT program can be added after the C1 process and before the M1 process. In a second embodiment, the TFT program can be inserted into the logic program after the Vn process and before the M(n+1) process. In another embodiment, the TFT program can be inserted after the top metal is deposited. Configuring the circuit 〇 All or some of the TFT transistors can be built on top of the logic transistors. An exemplary TFT program can include one or more of the following steps: • Contact masking and etching W germanide (or A1) plug filling and CMP amorphous Pl (polycrystalline germanium 1) deposition P1 masking and etching

Vtn mask and P-implant (NMOS Vt)

Vtp mask and N-implant (PMOS Vt) 134972.doc -73- 200931806 TFT Gox (70A to 200A PECVD) deposited amorphous P2 (polycrystalline germanium 2) deposited N+ mask and implant (NMOS gate and mutual Even) 'P + mask and implant (PMOS gate and interconnect) - Hard mask oxide deposited P2 mask and etched LDN mask and NMOS S/D N-tip implant LDP mask and PMOS S/D P-tip implants © spacer LTO or plasma nitride deposition spacers LTO etch and clean to form spacers and expose P1 and P2 Ni deposits RTA deuterated metal deposition and annealing (S/D/G regions and interconnection)

Excessive Ni etch dopant activation annealing ILD oxide deposition and CMP contact masking and etching VW plug formation and CMP metal deposition and residuals • TFT program technology by creating NMOS and PMOS amorphous germanium or polycrystalline germanium transistors in single crystal It is composed above the NMOS and PMOS devices. These amorphous germanium crystals can be annealed by various techniques (e.g., laser crystallization) that can be used in the processing industry to improve the mobility and transistor characteristics of the TFT. Thus a second layer of a transistor can be fabricated substantially over the first layer of one of the transistors to increase the density of the transistors available in the unit region of the germanium. In a preferred embodiment, 134972.doc-74-200931806, the second layer of the TFT transistor can be used to construct an array of memory cells to program the random positioning on the first layer of a dream substrate transistor. Stylized components. As the discussion demonstrates, the memory is provided by a controlled transfer transistor logic element - a powerful tool to make the switch. Such open relationships are encountered in both PLD and FPGA devices. The high cost of configuration memory can be greatly reduced by the 3-dimensional integration of the configuration elements and the currently disclosed alternative modularity concepts of the suffix and the disclosed content by reference. These advances allow for a highly economical, reliable, low-dissipated power, high performance, high level of integration and ease of conversion to ASIC and FPGA packages. In one aspect, the less expensive memory components allow more memory to be used due to programmability. This enhances the ability to build large logical blocks (i.e., coarse grain advantages) while maintaining the logical fit of smaller components (i.e., fine particle advantages). In addition, larger particles require less connectivity: adjacent cells and distant cells, which further simplifies the interconnect structure. Therefore, a 3D programmable architecture is used to achieve better programmable logic and better programmable interconnects. A 3D SRAM program integration reduces the cost of reprogrammability of such interconnect structures. As such, any other 3D memory technology will offer the same cost advantages. This 3D technology can be a stylized fuse link in which the stylization is achieved by a laser gun. It can be achieved by magnetic memory or ferroelectric suffix. A method is also shown for mapping programmable elements to a particular application hardwire component, wherein the line delays are unaffected by the change. This conversion allows for further reduction in the cost of the user, thus providing an alternative technique in designing an ASIC through the original FPGA device and reaching 134972.doc -75-200931806 to an FpGA logic density close to the ASIC logic density. DETAILED DESCRIPTION OF THE INVENTION The present invention is described in detail with respect to the specific embodiments of the present invention. i, by the skilled person, the implementation of the changes and other modifications without taxation of the scope and spirit of the invention as defined in the appended claims. [Simple description of the map]

Figure 1 shows an exemplary interconnect structure using a logic element. Figure 2 shows an exemplary logic element. Figure 3A shows an exemplary fuse link junction-to-point connection. Figure 3B shows an exemplary anti-fuse point-to-point connection. Figure 3C shows an exemplary transfer gate point-to-point connection. Figure 3D shows an exemplary floating transfer gate point-to-point connection. Figure 4A shows an exemplary configuration for a 6T SRAM device. Circle 4B shows an exemplary programmable transfer gate switch with SRAM memory control. Figure 4C shows the symbols used for the switches in Figure 4B. Figure 5A shows an exemplary 2:1 mux controlled by a memory bit. Figure 5B shows an exemplary 4:1 MUX controlled by 2 memory bits. Figure 5C shows an exemplary 3:1 MUX controlled by 3 memory bits. Figure 6A shows a first embodiment of a 3D programmable logic device. Figure 6B shows a second embodiment of a 3D programmable logic device. 134972.doc -76· 200931806 Figure 6C shows a top view of Figure 6A where the top memory layer has been removed. Figure 7A shows a top view of a 2d FPGA stripped down from the top to the polysilicon layer. Figure 7B shows a programmable logic block in accordance with one of the present inventions. Figure 7C shows a memory array configured in accordance with one of the present inventions. Figure 7D shows a memory cell used in the memory array shown in Figure 7C. Figure 8 shows a top metal layer in accordance with the present invention. Figure 9A shows a cross-sectional view of the top metal and RAM configuration in 3D Fpga. Figure 9B shows a cross-sectional view of the top metal and ROM configuration in the 3E) FPGA. Figure 10A shows a 3D view of the substrate circuitry, the intermediate metal layer, and the top configuration memory. Figure 10B shows a unit cell that has been replicated to construct Figure 10A. Figure 11A shows an IP block positioned between two programmable logic blocks. Figure 11B shows an array of configuration memory for stylizing the programmable elements in Figure ha. Figure 11C shows a 3D view of Figures ha and 11B of the overlapping configuration. Figure 12A shows a plurality of IP blocks with a plurality of programmable logic block locations. Figure 12B shows an array of configuration memory configured to program the Figure 12A. 134972.doc • 77- 200931806 Figure 12C shows the 3D configuration of Figures 12A and 12B. Figure 13A shows a 3D FPGA/PLD in which logic is programmed by vertical memory. Figure 13B shows an enlarged view of a portion of Figure 13A. - [Major component symbol description] 101 to 104 Logic elements 201 to 205 Element 310 Conductive fuse link ❿ 320 Capacitor anti-fuse element 330 Transfer gate device 340 Floating transfer gate device 401 NMOS transistor/device 402 NMOS transistor / device 403 inverter 404 inverter 410 pass gate / NMOS transistor ❹ 450 component / configuration circuit 460 cross shadow circle ' 511 pass gate 512 pass gate 531 pass gate 532 pass gate 533 pass gate Pole 550 configuration circuit 134972.doc -78- 200931806 561 memory element 562 memory element 571 memory element " 572 memory element, 573 memory element 601 semiconductor wafer area / wafer 602 pad area / pad 603 circuit block /3D configuration circuit 604 604 metal bus line 605 metal bus line 606 metal line 607 metal line 608 programmable logic block array 609 programmable routing area 610 intellectual property (IP) core / IP circuit block 701 To 706 ❹ column 707a, 707b SRAM unit 711 programmable circuit / LUT / circuit block / LUT circuit ' 712 programmable input MU X 713 Programmable Routing Circuitry 714 Programmable Register 715 Programmable Input MUX 716 Programmable Input MUX 717 Programmable Output MUX 134972.doc -79- 200931806 718 Programmable Output MUX 721 Memory Unit 731 Inverter - 732 Access Transistor - 733 Transistor 801 Metal Short Post 802 Metal Wire 803 Metal Unit Cell / Zone 804 Second Size 805 First Size 901 Metal Area / Pad Area / Metal Short Post Layer 902 Metal Short Column/metal short layer 903 metal wire/metal short column array/metal short column layer 904 metal short column/metal short column layer 905 metal wire/metal short column array/metal short column layer 906 metal short column/metal short column layer 907 907 Metal Wire/Metal Short Post Array/Metal Short Post 908 Metal Area/Mat Area/Metal Short Post Layer* 912 Top Configuration Memory Module Layer 913 Metal Area 915 Channel 916 Memory Unit 917 Metal Line 931 Circumference塾 area 134972.doc -80- 200931806 ❹

932 Metal Short Column / Metal Short Column Area 933 Metal Wire 934 Metal Short Column 935 Metal Wire 940 Entire Area 941 Metal Area / Pad Area 942 to 945 Metal Line / Line 946 Metal Area / Pad Area 1001 Module Layer / Geometry 1002 Mode Group layer / 1003 module layer / second metal unit 1004 module layer / first metal unit 1005 module layer / memory unit 1006 unit unit area / unit unit 1011 module layer / substrate area 1012 to 1015 module layer 1016 Metal Layer / Module Layer / Metal Unit 1017 Module Layer / Memory Unit 1101 First Programmable Logic Tile / Programmable 1101a Programmable Logic Unit 1102 IP Block / Intellectual Property (IP) Core 1102a First Area / Programmable component 1102b second central region/fixed circuit region 1102c third region/programmable component device 134972.doc -81 · 200931806 1103 second programmable logic tile/programmable component 1111 area/configuration bit Meta/memory array 1111a Configuration memory unit '1112 area - 1113 area/configuration bit 1201 Programmable tile 1202 IP block 1202a Area ❹ 1202b Field 1202c Area 1203 Programmable Tile 1204 IP Block 1204a Area 1204b Area 1204c Area/Programmable Logic Block 1205 IP Block ❹ 1205a Area 1205b Area* 1205c Area/Programmable Logic Block 1205d Area 1205e Area 1206 IP Block 1206a Area 1206b Area 134972.doc -82- 200931806 1206c Area 1207 1208 Programmable Tile/Programmable Logic Block/First Array IP Block* 1208a Area 1208b Area 1208c Area 1209 Programmable Tile 1211 ❹ 1212 Configuring memory array area 1213 Configuring memory array 1217 Configuring memory array 1219 Configuring memory array 1303a Programmable area 1303a-1 Logic block 1303a-2 Logic block 1303a 3 A One logical block/can Stylized Logic Block Array Area Ir 1304 Programmable IP Block/Intelligent Property (IP) Core 1304a Programmable Circuit Area 1304b Fixed Circuit Area/Programmable Circuit Area 1305 I/O Unit 1305a Fixed Circuit Area 1305b Fixed Circuit area 1305c programmable circuit area 1313a configuration memory array 1349 72.doc -83- 200931806 1313a-1 Configuration Memory Unit A Node B Node BL Access Line BS Access Line GA Access Line GB Access Line I〇 to I3 Input 0 Output So to s2 Memory Element Output So ' Output control signal ❹ I34972.doc -84-

Claims (1)

200931806 X. Patent application: h A two-dimensional programmable logic device (PLD) comprising: - a programmable logic block 'having a complex geometry in a predetermined layout * 疋 in the logical block Configurable components; and . . . configure each of the memory cells of the - Array of δ hexamed cells. ^ _ _ α to 4 or other configurable elements - or more to program the logic block to a user specification, wherein the first array substantially conforms to the predetermined layout geometry and the first array is substantially Located above or below the logical block. 2. The device of claim 1, further comprising: an input/output (I/O) unit having a plurality of configurable components positioned therein - a first 1/0 region and a second 1/ a second array of one of the configuration memory cells having a plurality of configuration memory cells, each of the second array memory cells being coupled to the first I/O region One or more of the configurable elements to program the 1/() unit to a user specification, wherein the second array and the I/O area substantially conform to the predetermined layout geometry and the second array • The column is positioned substantially above or below the first I/O area. [3] The apparatus of claim 2, wherein the first and second memory arrays are combined to form a contiguous array of one of the configuration memory cells, and wherein the contiguous array is substantially associated with the second 丨/O The areas do not overlap. 4) The apparatus of claim 1, further comprising: a programmable intellectual property (IP) block having a first 〇 > region and a plurality of configurable components positioned within an area a second I/p 134972.doc 200931806 region; and a third array of one of the configuration memory cells having a plurality of configuration memory cells each of the third array memory cells One or more of the configurable elements in the first Ip region to program the IP block to a user specification, wherein the third array and the IP region substantially conform to the predetermined layout geometry Moreover, the third array is positioned substantially above or below the first IP region. 5. The device of claim 4, wherein the first and third memory arrays are combined to form an adjacent array of one of the configuration memory cells, and wherein the adjacent array system does not substantially overlap the second IP region. 6. The apparatus of claim 5, wherein one or more of the power bus and a ground bus are positioned above the second zone. 7. The device of claim 1, wherein the memory unit comprises one of: a random access memory (RAM) component and a read only memory (R〇M) component. 8. The device of claim 7 wherein the R〇m component comprises one of: a metal line of the handle σ to the power supply voltage and a metal line that is coupled to a ground supply voltage. 9. The device of claim 1, wherein the memory unit comprises at least the following item of electric wire bonding, a laser wire bonding key, an anti-fuse capacitor, and a static random access memory (SRAM) unit. a dynamic random access memory (DRAM) cell, a metal optional link, an erasable programmable read only memory (EPROM) cell, and an electronic erasable programmable read only memory (EEPROM) cell , a flash memory unit, a 134972.doc 200931806 carbon nano [- electrochemical unit, a motor unit, a resistance modulation element, a mechanical diaphragm 'an optical unit, an electromagnetic unit and a ferroelectric unit. 10. The device of claim 1, wherein one or more of the interconnect and routing signals are positioned above or below the array of memory cells. 11. A three-dimensional programmable logic device (pld) comprising: a plurality of I/O cells, each of the 1/〇 cells comprising: a fixed circuit region; and a programmable circuit region having a configuration a plurality of programmable elements of the 1/0 single element; and a core of intellectual property (IP), each IP core comprising: a fixed circuit area; and a programmable circuit area having a group a plurality of programmable elements of the IP core; and a programmable logic block array region comprising: a plurality of substantially identical programmable logic blocks replicated to form the array, each of the logic The block further includes a plurality of programmable elements; and a programmable area including the positionable programmable component of the programmable logic block array region, the one or more of the IP core programmable circuit regions And one or more of the programmable circuit regions of the I/O unit; and a configuration memory array including one or more of the programmable elements coupled to the programmable region a memory unit that stylizes the programmable region, wherein: the memory array is substantially positioned above or below the programmable region; and 134972.doc 200931806 the memory array and The stylized area layout geometry is essentially the same. 12. The device of claim 11, wherein the one of the programmable regions comprises one of the following: a programmable logic component and a programmable routing component. 13. A device as claimed in claim U, At least one of the power bus and a ground bus is positioned above the ip core fixed circuit area. 14. The apparatus of claim n, wherein the configuration memory unit comprises one of: a random access memory (RAM) component and a read only memory (ROM) component. 15. The device of claim 14, wherein the R〇M component comprises a metal line coupled to a power supply voltage and a metal line coupled to a ground supply voltage, **. 16. The device of claim 14, wherein the 11 8 1 component comprises at least one of the following: an electrical fuse link, a laser fuse link, an anti-solvent capacitor, an SRAM cell, a DRAM Unit, a metal optional link, an EPROM unit, an EEPROM unit, a flash memory unit, a carbon nanotube, an electrochemical unit, a motor unit, a resistor 70, a mechanical diaphragm, an optical unit , an electromagnetic unit and a ferroelectric unit. 1 7. A device as claimed, wherein one or more interconnects and signal routing paths are positioned above or below the array of memory cells. 18. A three-dimensional programmable logic device (pLD) comprising: a plurality of assigned programmable elements positioned in a substrate area 134972.doc -4 - 200931806; and one of the configuration memory cells Adjacent to the array, a plurality of the memory cells are coupled to the plurality of programmable elements to configure the programmable elements, wherein: ^ the memory array is substantially positioned above or below the substrate area; And the memory array and the substrate area layout geometry are substantially similar. The device of claim 18, further comprising an adjacent array of metal cells, each metal cell having a configuration memory cell size and a metal stub coupled to a configuration memory cell and the 20. The device of claim 19, wherein the two or more metal units further comprise metal, wires adjacent to the metal stub extending from one end of the unit to the opposite end of the unit , wherein two or more adjacent gold elements form a continuous metal line. The device of claim 19, wherein the metal cell array is positioned below the invisible cell array and above the substrate region. The device of the monthly item 18 includes a plurality of multifunctional I/O pads, each of which is coupled to the first and second buffers, wherein the first and third, the packet 3 are coupled to the Configuring one or more of the programmable elements of the memory unit. The setting of one or two long items 22, wherein the multi-function 1/〇 pad-or multi-into = the following - or more: - power supply pad, - ground supply clock pad - device configuration pad, An input pad and an output port. 134972.doc