200931548 六、發明說明： 【發明所屬之技術領域】 本發明係關於半導體元件裝载用基板之製造方法，詳言 之，係關於在由金屬製薄板構成的基材上形成多層鍍敷層而 構成的半導體元件裝載用基板之製造方法，在組裝步驟中， 基材與鍍敷層間之密接性優異’組裝完成後，該基材與鍍敷 層的剝離極為容易的半導體元件裝載用基板之製造方法。 ❹ 【先前技術】 半導體裝置的小塑•薄型化係逐年有進展，在密封樹脂的 背面具有與外部間之連接部（端子部）的半導體裝置正增加 中。此種半導體裝置的焊墊部或端子部，一般係使用藉由對 銅系合金或鐵錄合金施行姓刻加工或壓製加工，而形成既定 圖案的引線框架。然而’此種引線框架主要係使用板厚 0. 125〜0· 20腿的金屬性薄板’此將成為妨礙半導體裴置薄 Ο 型化的要因之一。 所以’近年有開發出取代該弓丨線框架，改為使用在由金屬 製薄板構成的基材表面上’形成厚度〇. lmm以下的鑛敷層， 並將該鍍敷層當作焊墊部或端子部用的半導體元件裝載用 基板，使用該半導體元件裝載用基板進行半導體裝置組裝的 產品在市場上已有上市。利用該鍍敷層在基材上形成焊墊部 或端子部的半導體元件裝载用基板一例，有提案：預先選擇 由可蝕刻金屬材料構成的基材，而獲得在該基材上形成有由 097137883 3 200931548 鍵金層鍛錄層、鑛金層構成之焊塾部及端子部的半導體元 件裝載用基板’在上述焊墊部上裝載半導體元件，同時將該 半導體元件與上述端子部利用連線焊接（wire bonding)相 .連結’並輯絲封粒裝步賴，再僅對基材施㈣刻而 去除的方法（例如參照專利文獻υ。 再者，針對將·歸的域製薄域由從韻密封體上 施行拉剝而去除，在密封樹脂的背面上具有利用鑛敷層形成 ❹連接部的半導體元件裝载用基板，亦有多數的提案。然而， 於此種半導航縣_基板，成為歸齡職薄板、與 所生成的錄敷層間之剝離性差，例如基材係使用銅系合金的 情況’因為無法利關械手段㈣地拉剝，因而在樹脂密封 後將屬於金屬製薄板的銅系合金去除之手段，便必需採行蚀 刻處理，此將成為製造步驟趨於複雜的要因，且經濟性亦 差。此外，將會有所形成的焊墊部或端子部會殘留於經拉剝 =去的金屬製薄板上之問題發生’為能改善此剝離性，亦有 提案在金屬性薄板表面上預先施行鼓風（Mast)處理而設置 凹凸後’再施行贿處理时糾物參科敎獻2)。 但’因施行對金屬性薄板設置凹凸的表面處理，將產生基材 發生-曲的新問題’且追加表面處理步驟與剝離處理步驟， 而殘留製造步驟更繁雜的問題。 另一方面’當成為基材的金屬製薄板係採用不錄鋼，並在 樹脂密封後將該不銹鋼製薄板拉剝時，一般而言，將因為形 097137883 4 200931548 成端子的錢敷層對不銹鋼之密接性不足，而有密封樹月旨會 、堯入不銹鋼製薄板與鑛敷層間的問題發生，且在樹脂密封 後成為焊塾部或端子部的錢敷層再與密封樹脂進行密接、， 俾不會發生從费封樹月旨上之浮起狀態或剝離情況，係屬重要 •事項❿提升3彡密封樹脂與It敷層之密接性的手段，有揭示 將鍍敷層的上端部周緣呈屋詹狀伸出的方法（例如參照專利 )仁疋，依照此方法，由於形成使鍍敷層懸吊於抗 ©#劑高度以上’因而為能呈屋綠伸出的長度控制並非= 易，會有與鄰接端子部相連接的顧慮。？文善密封樹脂、與所 生成锻敷層間之密接性的其他手段，有揭示：使用端子部剖 面形狀呈「工」字狀之基板的半導體裝置及其製造方法（例 >參照專利文獻4)。更具體而言，在金職雙面上依既定 圖案形成導電部’再隔著接著劑層貼附於基材上之後，以導 電部為钮刻遮罩並對金屬羯施行蚀刻處理，藉此便製造剖面 ❿形狀呈「J1」字狀的半導體元件裝載絲板之方法，但將追 加新的製造步驟，結果將導致製造步驟繁雜化，就成本面而 言亦構成問題。 [專利文獻1]曰本專利特開昭59—208756號公報 [專利文獻2]日本專利特開平1〇_5〇885號公報 [專利文獻3]曰本專利特開2〇〇3_174121號公報 [專利文獻4]日本專利特開2〇〇4_253674號公報 【發明内容】 097137883 5 200931548 (發明所欲解決之問題） 如此的話’就基材係使用金屬製薄板，並在樹脂密封後藉 由將該金屬製薄板拉剝而去除便獲得的上述半導體元件裝 載用基板，必需在組裝步驟中，鍍敷層不會從金屬製薄板上[Technical Field] The present invention relates to a method for producing a substrate for mounting a semiconductor element, and more particularly to a method of forming a multilayer plating layer on a substrate made of a metal thin plate. In the method of manufacturing a substrate for mounting a semiconductor element, the adhesion between the substrate and the plating layer is excellent in the assembly step. After the assembly is completed, the substrate for mounting the semiconductor element and the substrate are extremely easy to be peeled off. .先前 [Prior Art] The small-sized and thin-filmed semiconductor devices have been progressing year by year, and semiconductor devices having a connection portion (terminal portion) to the outside of the sealing resin are increasing. In the pad portion or the terminal portion of such a semiconductor device, a lead frame in which a predetermined pattern is formed by subjecting a copper-based alloy or a ferrous alloy to a predetermined pattern or press processing is generally used. However, such a lead frame mainly uses a metallic thin plate having a thickness of 0.125 to 0·20 legs, which is one of the factors that hinder the thinning of the semiconductor device. Therefore, in recent years, it has been developed to replace the frame of the bow line, and instead use a layer of a thickness of 〇.1 mm or less on the surface of a substrate made of a metal sheet, and use the layer as a pad. The semiconductor element mounting substrate for the terminal portion and the semiconductor device mounting substrate using the semiconductor element mounting substrate are commercially available. An example of a semiconductor element mounting substrate in which a pad portion or a terminal portion is formed on a substrate by using the plating layer, and it is proposed to select a substrate made of an etchable metal material in advance to obtain a substrate formed on the substrate. 097137883 3 200931548 A gold-plated forging layer, a solder joint portion formed of a gold-plated layer, and a semiconductor element mounting substrate of a terminal portion. A semiconductor element is mounted on the pad portion, and the semiconductor element is connected to the terminal portion. Wire bonding phase. The method of joining and arranging the wire to seal the particles and then removing only the substrate (for example, refer to the patent document υ. There is a large number of proposals for the semiconductor element mounting substrate which is formed by removing the stripe from the rhyme sealing body and having a tantalum joint portion formed by the mineral deposit on the back surface of the sealing resin. However, in this semi-navigation county_substrate The peeling property between the sheet of the aged age and the formed coating layer is poor. For example, when the base material is made of a copper-based alloy, it cannot be pulled by the mechanical means (four), so after the resin is sealed. The method of removing the copper-based alloy belonging to the metal thin plate requires an etching treatment, which is a factor that tends to be complicated in the manufacturing process, and is also economically inferior. Further, a pad portion or a terminal which will be formed will be formed. The problem that the part will remain on the metal sheet which has been peeled off = to improve the peelability, and there is also a proposal to perform a blast (Mast) treatment on the surface of the metallic sheet to provide a bump. When handling, the object of correction is given to the department 2). However, the surface treatment for providing irregularities on the metallic thin plate causes a new problem of occurrence of a substrate, and a surface treatment step and a peeling treatment step are added, and the remaining manufacturing steps are more complicated. On the other hand, when the metal thin plate that becomes the substrate is made of non-recorded steel and the stainless steel thin plate is peeled off after the resin is sealed, generally, the shape of the 097137883 4 200931548 terminal is applied to the stainless steel. The adhesion is insufficient, and there is a problem of sealing the tree and the problem between the stainless steel sheet and the mineral deposit layer, and the money coating layer which becomes the solder joint portion or the terminal portion after the resin sealing is adhered to the sealing resin.俾 俾 俾 俾 俾 俾 俾 俾 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费 费According to this method, the length of the coating can be suspended above the height of There is a concern that it is connected to the adjacent terminal portion. ? A semiconductor device using a substrate having a cross-sectional shape of a terminal portion and a method for producing the same, and a method for producing the same, (Example > Patent Document 4) . More specifically, after the conductive portion is formed on the double-sided side of the gold work and attached to the substrate via the adhesive layer, the conductive portion is used as a button mask and the metal ruthenium is etched. A method of loading a silk plate with a semiconductor element having a "J1" shape in cross section is produced. However, a new manufacturing step is added, resulting in a complicated manufacturing process and a problem in terms of cost. [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei 59-208756 [Patent Document 2] Japanese Patent Laid-Open Publication No. Hei No. Hei No. Hei. Patent Document 4] Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. In the above-described substrate for mounting a semiconductor element obtained by stripping and removing a metal thin plate, it is necessary that the plating layer does not pass from the metal thin plate in the assembly step.
剝離，此外，密封樹脂將在不會繞入金屬製薄板與鍍數層間 之情況下進行密接，並且將金屬製薄板拉剝後，在經拉剝的 金屬製薄板上不會殘留將成為焊墊部或端子部的鍍數層，與 密封樹脂密接且不會發生從密封樹脂上的浮起狀態與剝離 狀況之事，係屬重要課題。即，金屬製薄板與鍍敷層在截至 組裝步驟完成為止前均牢固地密接，當施行金屬製薄板的拉 剝時，將要求該金屬製薄板與鍍敷層可輕易地剝離之相反功 能’而本發明係將基材拉剝的方&巾所使㈣半導體元件裝 載用基板之製造方法，其目的在於合併解決上述問題，將提 供在組裝步财基材與魏層不會_，此外，密封樹脂將 在不會繞人基材與魏層間的情況下，牢固地維持其密接 性’經組裝完成後，該基材與賴層將極容易娜，在所去 除之基材侧上並無鍍敷層_’而與密封樹脂密接並不會發 生從該贿_旨上的浮祕態與_狀關半導體元件裝 載用基板之製造方法。 (解決問題之手段） 、為能解決上述問題的本發明半導體元件裝制基板之製 造方法，主要係包括有下述特徵構成要件的半導料件裝載 097137883 6 200931548 用基板之製造方法，該等特徵構成要件係··在由金屬製薄板 構成的基材雙面上貼附抗蝕劑，同時藉由以其中一面的抗餘 劑為鑛敷用遮罩而形成既定抗餘劑圖案的步驊；對從上述抗 蝕劑圖案中露出的基材上既定位置處，施行蝕刻加工的步 驟；在經施行蝕刻加工的上述基材上，形成由下側、中間及 上側等3層以上所構成之鑛敷層的步驟；將基材雙面上所貼 附的上述抗蚀劑剝離之步驟；以及對上述中間鍍敷層施行蝕 ❹刻加工，而變為較狹窄於上下鍍敷層的步驟。 再者，本發明的上述半導體元件裝載用基板之製造方法 中，較佳態樣為上述金屬製薄板係板厚〇 的科 鋼。 再者，本發明的上述半導體元件褒載用基板之製造方法 中，對基材上既定位置所施行的上述餘刻加卫，係深度 3〜10以m範圍内。 ❹ 本發明的上述半導體元件裝載用基板之製造方法，尚可取 代對基材上既定位置所施行之上_^加I，改為使用強酸 性浴而先形成鍍金層。 本發明的上述半導體元件裝載用基板之製造方法，更進一 述Γ⑽敷層，從其側面朝中心方向依單侧2〜1〇_ 其面積― 再者，本發明的上述半導體轉裝_基板之製造方法 097137883 7 200931548 中，上述下側艘敷層係鍍金及/或鍍鎳，中間鍍敷層係鑪銅 及/或鍍鎳，上侧鍍敷層係鍍鎳、鍍金、鍍銀、鍍鈀威该等 的合金鑛敷。 • 再者，本發明的上述半導體元件裝載用基板之製造方·法 中，上述上侧鍍敷層的厚度係形成厚達5wm以上。 再者，於中間鍍敷層含有未施行從側面朝中心方向之蝕刻 加工的鍍敷層，而在較上下鍍敷層為狹窄的中間鍍敷層中具 ❹ 有凸部。 (發明效果） 當使用依照本發明之製造方法所製得半導體元件裝載用 基板’進行半導體裝置組裝時，藉由使在基板上所生成的鑛 敷層係上續敷層具有5_以上的厚度，且中間鍵敷層形 成較狹窄於上下的職層，密封樹脂與錄層便呈現優異密 接性，在將基材拉剝後，該鑛敷層不會發生從密封樹脂上之 ©浮綠態與剝離情況’且，最先在基材上形成的鍍敷層特 卿代通常所使用的弱酸性〜中性浴，改為利用強酸性浴形 成錄金層，藉此便提升與基板間的寐姑^ 幻在接性，密封樹脂不會繞 入於基材與鑛敷層間。此外，藉由祖 柯田對基材上既定位置依 3〜ΙΟ/zm深度施行侧加工’而錢部分處形成職層，便 可更加防止密封樹脂繞人於基材與錢數層間。如此的話，依 照本發明方法所獲得的半導體元件较 叫用悉敬’儘管其製造 方法係狀簡略㈣’所生成職以密關的密接性 097137883 8 200931548 仍優異，將基材拉剝後，在所拉剝的基材側不會殘留將成為 焊墊部或端子部的鍍敷層，當使用為半導體元件裝載用基板 時將可達極優異的效果。 【實施方式】 以下’針對本發明根據所附圖式及實施例進行更進一步之 詳=說明’惟本發㈣不僅侷限於此，舉凡在不脫逸本2 主旨範疇内均可自由地設計變更。 ❹ Ο 圖1所示係根據本發明一實施例所獲得的半導體元件裝 載用基板’（a)係在基板上施行3層紐層的狀態之重要部 分剖視圖’⑹係形成5層鑛敷層的狀態之重要部分剖視 圖’（〇係由7層魏層’且中間紐層具有凸部的複數鐘 敷層構成的狀態之重要部分剖視圖。 圖2所示係在基板上形成複數組鑛敷層的狀態，⑷係重 要部分的平面圖’ (b)係⑷的其中一部分之放大平面圖。 圖3所㈣根據本發明的半導體元件㈣ 情在絲上軸3層錄層料魏步_進行說 綱Γ見圖，分別表示以下狀態之重要部分剖視圖：⑷係 形成圖案的狀態，（b)係對基材施行_口工的 纏、=)係在基材上施行3層練層的狀態，⑷係將抗钱 離的㈣，（e)係對㈣錄層施行㈣加工的狀 態。 圖4所示係根據本發明的半導體元件裝载用基板之製造 097137883 9 200931548 方法中，經樹脂密封後的基板狀態，（a)係依實施例1所獲 得基板的重要部分放大刮視圖，（b)係同樣的依實施例2所 獲得基板的重要部分放大剖視圖。 圖5所示係根據本發明的半導體元件裝載用基板之製造 方法中，說明本發明鍍敷層的示意剖視圖，（a)係利用3種 鍍敷層之5層構造的示意剖視圖，（b)係利用3種鍍敷層之 7層構造的示意剖視圖。 ❹ 本發明半導體元件裝載用基板之製造方法的較佳實施形 態，將依照步驟順序進行說明，由金屬製薄板構成的基材係 以由板厚0. 05〜0. 5mm，最好為〇. 1〜〇. 3mm的不銹鋼（SUS430) 所構成板材採用為基材，在該基材雙面上貼附著由感光性乾 膜構成的抗餘劑’然後，施行以其中一面的抗蝕劑為鍍敷遮 罩之處理’而在基材上製作既定圖案。然後，使用鐵液（ir〇n liquor) ’對基材的鍍敷區域施行蝕刻加工，當該 ^ 餘刻處理較淺於3私《!時，密封樹脂會繞入基材與鍍敷層 間，而當較深於10的蝕刻加工時，在將基材拉剝後，於 基材側會殘留將成為焊墊部或端子部的鍍敷層，因而最好依 3〜10 // m深度施行钮刻加工。 • 在經蝕刻加工過的上述基材上，首先施行一般的弱酸性〜 中陡浴之鍵金後’在其上施行鑛鎳，更在其上依照鍵銅、鑛 錄鑛金的順序重疊鑛敷層而生成，藉此便形成由鑛金與鍍 鎳構成下側鍍敷層、由鍍鋼構成中間鏡敷層、及由鍍錄與鍵 097137883 200931548 金構成上側鍵敷層所構成5層的鑛敷層，或者形成中間鍛敷 層係由依序施行錢銅與鍍鎳的層所構成7層以上的鐘敷層。 接著，將在基材雙φ上預先貼_抗㈣襲，僅對屬於 -巾間鍍敷層的賴層部分施行單侧2〜1G // m #刻加工，便形 ’ 成目5所示示意㈣的錢敷層。當該侧面餘刻加工較淺於 2/ζιη時’在與樹脂間之密接性將嫌不足，反之，當較深於 1〇_時’上繼敷層將部分性下降，導致有其形狀出現崩 ©潰的顧慮，因而最好在單侧2〜1〇/zm範圍内施行蚀刻加工。 另外如上述，必需利用對中間鑛敷層施行蝕刻加工，而將 上側錢敷層形成5/zm以上的厚度。 再者，本發明的半導體元件裝載用基板中 ，因為上述下側 鍍敷層的基材面側係屬於將半導體裝置連接於母板等的部 分’因而必需屬於可焊接的，另—方面，上侧鑛敷層的 最上層係屬於連線焊接的部分，因而可進行連線焊接的鍍敷 ❹便成為必要條件。為能滿足如上述條件，本發明的基板上之 錄敷層’係可從基材侧起依序將下侧鑛敷層設為鑛金或鏡 趣*將中間鑛敷層δ史為錢鋼或鑛鎳、將上側鍵敷層設為鑛纪 或鍍金等，且下侧、中間及上側的各層係可由單獨或複數鍍 敷層而形成。 [實施例1] 成為基材11的金屬製薄板係採用板厚0.2丽的不銹鋼 (SUS430) ’經施行脫脂•酸洗淨處理後，將厚度〇 〇25丽 097137883 11 200931548 感光f生乾膜抗姓劑12利用層壓輥（laminate Γ〇ι 1)貼附於其 材11雙面上之後，將鍍敷遮罩用玻璃遮罩覆蓋於基材u 其中一面的乾膜抗蝕劑12上，更從其上方施行紫外光照 射，藉以曝光並施行顯影處理，並利用乾膜抗蝕劑12製得 既定圖案。 f 再者，此時的圖案係形成鍍敷層的鍍敷區域4〇，如圖2 所示，準備3咖四方形的焊墊部41與其周邊所配置16個 ❹〇. 5麵四方形的端子部42，並將此種鍍敷區域4〇在寬4〇_ 基材的中央附近依6x6個一組的方式排列複數組而製得。 接著，對基材上的鍍敷區域4〇施行鍍敷前處理後，利用 pHO.l〜1.0的強酸性浴施行約〇. li(/m的鍍金，並在其上面 施行約10 # m的鑛鎳’更在其上面施行約1〇以m的鑛鋼更 在其上面施行約5//m的鍍鎳，在其上面利用弱酸性〜中性浴 施行約0. lem的鍍金，便形成從基材侧起依序由薄鍍金層 © 與1〇鍍鎳層構成的下侧鍍敷層21、由1〇以瓜鍍銅層構 成的中間鑛敷層22、由5 a m鑛鎳層與0·1/ζιη鑛金層構成 的上側鍍敷層23，而在基材上實質的形成3層鍍敷層（因為 鐘金層較薄因而未計數）。 • 其次，將在基材11雙面上預先貼附的乾膜抗蝕劑12剝 離，經施行水洗與乾燥後，利用鐵液對屬於中間鑛敷層的鑛 銅層，從其侧面朝向中心部分施行單側約7 /z m的钮刻加 工。藉由該等一連串的加工步驟，如上述，在基材上形成鑛 097137883 12 200931548 金層31與鍍鎳層q ㈣IM的下侧鑛敷層21、鑛銅層33的中_ 敷層，屬財間1 與鑛金層35的上側鑛敷層23之鍍 狹窄約_，而;數广鑛銅層33係較上下鍵敷層單侧 件裝载用基板。㈣Ub)重要部分剖面所示的半導體元 體元件得的半導體元件裝載用基板，將半導 蔣主道触-^日日（dleb〇nd)用糊膏裝載於焊墊部54上， 肝千导體70件5〗 ,, N 的電極與端子部52施行連線焊接53後， 如圖4(a)所示，侬 说 密封齡π 組而㈣的方式，施行使用 曰 的樹脂密封（參照樹脂密封後的半導體元件裝 載用基板50)，她…么 ㈣騎裝 冱樹知硬化後，將屬於基材11的不銹鋼從 Ο 、m日密封的部分上拉剝，詳細觀察所拉剝的不錄鋼侧，其 果句…、殘留錢敷層的部分，此外，在經樹脂密封的部分且 鄰接不_的錄金侧，亦無發現密封樹脂55繞人的痕跡， 或者從密輯脂55上發⑽敷層浮起純_ 切 到其係緊密地保持。 [實施例2] 示使用在如同實施例丨基材表面上利用乾膜抗蚀劑形成 既定圖案的基材11，首先對基材11的鑛敷區域40利用鐵 液施行深度^左右的_加卫，並在該部分上形成银刻 2 13之外，其餘均利用實質如同實施⑴相同的手段而獲 得半導體元件聚顧基板。使用所獲得之半導體元件裝載用 097137883 13 200931548 基板，將半導體元件51使用勘晶用糊膏裝載於焊墊部54 上’將半導體元件51的電極與端子部52施行連線焊接後， 如圖4(b)所*’依3减為—組而密封的方式施行樹脂密 •封（參照樹脂密封後的半導體元件裝載用基板5G)，經樹脂 •硬化後，將屬於基材11的不_從崎職封的部分上^ 剝，詳細觀察所拉_不_侧表面，其結果均無殘留鍛敷 層的部分，此外，在經樹脂輯的部分且鄰接賴鋼的鑛金 ❹側’亦無發現密封樹脂繞人的痕跡’或者從樹脂上發生鍛敷 層浮起或剝離的狀況，確認到其係緊密地保持。 [實施例3] 使用將實施例1的不銹鋼改為鋼合金，依同樣的乾膜⑽ 劑製作既定圖案的基材U，首先對基材n的鍍敷區域4〇 利用鐵液施行深度7# m左右的蝕刻加工，經施行鍍敷前處 理後，利用中性浴施行約3/zm鍍金，在其上面施行約6//m ❹鍍鎳，更在其上面施行約6/im鍍銀，而在基材上形成整體 約15# m的鑛敷層，然後將基材表面上所殘留的乾膜抗姓劑 剝離’利用選擇性蝕刻對鍍鎳層施行約5；αιη蝕刻加工，便 獲得本實施例的半導體元件裝載用基板。使用所獲得半導體 元件裝载用基板，如同實施例1施行樹脂密封，經樹脂硬化 後’對屬於基材11的銅合金利用餘刻液施行溶解處理，殘 留含有所形成鍍敷層的樹脂。於該樹脂側的鍍敷層而連接於 銅合金的鍍金部分，均無發現密封樹脂繞入的痕跡，亦無發 097137883 14 200931548 現從樹脂發生錄層料或_他況，賴财係依緊密 狀態保持。 [實施例4] 使用如同實施例1利用兹腹；> 〜用乾膜k蝕劑製作既定圖案的基材 π，首先對基材11的錢敷區域 • 又救40施行鍍敷前處理後，利用 pHO. 1〜1. 0的強酸性浴施行約〇 他灯？g ϋ. 1 am鍍金，在其上面施行Exfoliation, in addition, the sealing resin will be adhered without being wound between the metal thin plate and the plating layer, and after the metal thin plate is peeled off, it will not remain as a bonding pad on the peeled metal thin plate. The number of plating layers of the portion or the terminal portion is in close contact with the sealing resin, and the floating state and the peeling state from the sealing resin do not occur, which is an important issue. That is, the metal thin plate and the plating layer are firmly adhered to each other until the assembly step is completed, and when the metal thin plate is stretched, the opposite function of the metal thin plate and the plating layer can be easily peeled off. The present invention relates to a method for producing a substrate for mounting a semiconductor element by stripping a substrate with a substrate, and an object of the invention is to solve the above problems in combination, and to provide a substrate and a layer in the assembly step, and further, The sealing resin will firmly maintain its adhesion without going around the human substrate and the Wei layer. After the assembly is completed, the substrate and the layer will be extremely easy, and there is no substrate side removed. The plating layer _' is in close contact with the sealing resin, and does not cause a floating state of the brittleness and a method of manufacturing the semiconductor element mounting substrate. (Means for Solving the Problem) The method for manufacturing a semiconductor device package substrate of the present invention which can solve the above problems mainly includes a method of manufacturing a substrate for a semiconductor material having a feature of the following: 097137883 6 200931548; The characteristic component is a step of attaching a resist to both sides of a substrate made of a metal thin plate, and forming a predetermined anti-reagent pattern by using an anti-surplus agent on one side as a mask for mineral coating. a step of performing an etching process on a predetermined position on the substrate exposed from the resist pattern; and forming, on the substrate subjected to the etching process, three or more layers including a lower side, a middle side, and an upper side a step of depositing the deposit; a step of peeling off the resist attached to both sides of the substrate; and a step of etching the intermediate plating layer to be narrower than the upper and lower plating layers. Further, in the method for producing a substrate for mounting a semiconductor element of the present invention, it is preferable that the metal thin plate has a thick steel plate. Further, in the method for producing a substrate for mounting a semiconductor device according to the present invention, the above-described residual force applied to a predetermined position on the substrate is in the range of 3 to 10 m in depth. In the method for producing a substrate for mounting a semiconductor element of the present invention, it is also possible to replace the predetermined position on the substrate with the addition of a strong acid bath to form a gold plating layer. In the method for manufacturing a substrate for mounting a semiconductor element according to the present invention, the ruthenium (10) cladding layer is further unilaterally 2 to 1 〇 from the side surface thereof toward the center direction. Further, the semiconductor transposing substrate of the present invention In the manufacturing method 097137883 7 200931548, the lower side coating is gold-plated and/or nickel-plated, the intermediate plating layer is furnace copper and/or nickel plating, and the upper plating layer is nickel-plated, gold-plated, silver-plated, palladium-plated. The alloy deposits such as Wei. Further, in the method of manufacturing the substrate for mounting a semiconductor element of the present invention, the thickness of the upper plating layer is formed to a thickness of 5 wm or more. Further, the intermediate plating layer contains a plating layer which is not subjected to etching from the side surface in the center direction, and has a convex portion in the intermediate plating layer which is narrower than the upper and lower plating layers. (Effect of the Invention) When the semiconductor device mounting substrate 'made by the manufacturing method of the present invention is used for semiconductor device assembly, the deposited layer formed on the substrate has a thickness of 5 Å or more. And the intermediate bond layer is formed to be narrower than the upper and lower layers, and the sealing resin and the recording layer exhibit excellent adhesion. After the substrate is peeled off, the mineral layer does not occur from the sealing resin on the floating green state. And the peeling situation', and the first weakly acidic to neutral bath used in the plating layer formed on the substrate first, the strong gold bath is used to form the gold layer, thereby enhancing the space between the substrate and the substrate.寐 ^ ^ phantom connection, the sealing resin will not wrap between the substrate and the mineral layer. In addition, since Zu Ketian performs side processing on the predetermined position on the substrate at a depth of 3 to ΙΟ/zm and forms a layer at the money portion, the sealing resin can be further prevented from being wound around the substrate and the money layer. In this case, the semiconductor device obtained by the method of the present invention is more excellent than the 097137883 8 200931548 which is closely related to the work performed by the singularity of the manufacturing method, although the manufacturing method is simple (4). A plating layer to be a pad portion or a terminal portion is not left on the side of the substrate to be peeled off, and an extremely excellent effect can be obtained when used as a substrate for mounting a semiconductor element. [Embodiment] Hereinafter, the present invention is further described in detail with reference to the accompanying drawings and embodiments. The present invention is not limited thereto, and can be freely designed and changed without departing from the scope of the present invention. . Ο Ο FIG. 1 is a cross-sectional view of an important part of a substrate for mounting a semiconductor element obtained in accordance with an embodiment of the present invention, in which a layer of a three-layer layer is applied to a substrate (6) is formed by forming a five-layer mineral layer. A cross-sectional view of an important part of the state of the cross-sectional view of the important part of the state (the 〇 is composed of 7 layers of the Wei layer) and the intermediate layer has a plurality of complex layers of the convex portion. Figure 2 shows the formation of a complex array of mineral deposits on the substrate. State, (4) is a plan view of the important part's (b) an enlarged plan view of a part of the system (4). Fig. 3 (4) The semiconductor element according to the present invention (4) In the case of the upper layer of the wire, the layer of the layer is recorded. The figure shows a cross-sectional view of an important part of the following state: (4) a state in which a pattern is formed, (b) a tangling of the substrate, and a state in which three layers are layered on the substrate, and (4) (4), (e) is the state of processing (4) processing (4). Fig. 4 is a view showing the state of the substrate after resin sealing in the method of manufacturing the substrate for mounting a semiconductor element according to the present invention in the method of 097137883 9 200931548, and (a) an enlarged view of an important portion of the substrate obtained in the first embodiment, ( b) is an enlarged cross-sectional view of an important part of the substrate obtained in the same manner as in Example 2. Fig. 5 is a schematic cross-sectional view showing a plating layer of the present invention in a method of manufacturing a substrate for mounting a semiconductor element according to the present invention, and (a) is a schematic cross-sectional view showing a five-layer structure of three kinds of plating layers, (b) A schematic cross-sectional view of a seven-layer structure using three types of plating layers. 5mm,优选为〇. mm. 5mm, preferably 〇. 。. 5mm, preferably 〇. 1~〇. 3mm stainless steel (SUS430) The plate material is made of a base material, and an anti-reagent made of a photosensitive dry film is attached to both sides of the substrate. Then, a resist is applied on one side of the substrate. A masking process is applied to create a predetermined pattern on the substrate. Then, using ir〇n liquor ' to etch the plating area of the substrate, when the process is shallower than 3 private, the sealing resin wraps between the substrate and the plating layer. When the etching process is deeper than 10, after the substrate is peeled off, a plating layer which will become a pad portion or a terminal portion remains on the substrate side, and thus it is preferably performed at a depth of 3 to 10 // m. Button processing. • On the etched substrate, firstly perform the general weak acid ~ medium steep bath bond gold, then perform the mineral nickel on it, and further overlap the ore according to the order of bond copper and mineral gold. It is formed by coating, thereby forming a lower plating layer composed of gold and nickel plating, a middle mirror coating layer made of plated steel, and a 5-layer layer composed of a plating layer and a key layer of 097137883 200931548 gold. The mineral deposit layer or the intermediate forging layer is composed of a layer of seven or more layers of a layer of money copper and nickel plating. Next, the substrate double φ is pre-applied with _ anti-(four) attack, and only the delaminated portion belonging to the inter-sheet plating layer is subjected to one-side 2~1G // m # engraving processing, and the shape is shown in Figure 5 Indicate the (4) money layer. When the side machining is shallower than 2/ζιη, the adhesion between the resin and the resin will be insufficient. On the contrary, when it is deeper than 1〇, the successor coating will partially decrease, resulting in its shape. It is preferable to perform etching processing in a range of 2 to 1 Å/zm on one side. Further, as described above, it is necessary to form an etching process on the intermediate ore layer to form a thickness of 5/zm or more. Further, in the semiconductor element mounting substrate of the present invention, since the substrate surface side of the lower plating layer belongs to a portion in which a semiconductor device is connected to a mother board or the like, it is necessary to be solderable, and on the other hand, The uppermost layer of the side ore layer is part of the wire joint welding, so plating plating which can be connected by wire welding becomes a necessary condition. In order to satisfy the above conditions, the recording layer on the substrate of the present invention can sequentially set the lower ore layer from the side of the substrate to a gold or a mirror. * The history of the intermediate layer is δ steel. Or mineral nickel, the upper key layer is made of ore or gold plating, and each layer of the lower side, the middle side and the upper side may be formed by a single or multiple plating layers. [Example 1] A metal thin plate to be a substrate 11 was made of stainless steel (SUS430) having a thickness of 0.2 Å. After degreasing and pickling treatment, the thickness was 〇〇25 097137883 11 200931548. After the surname agent 12 is attached to both sides of the material 11 by laminating rolls (laminate Γ〇 1 ), the plating mask is covered with a glass mask on the dry film resist 12 on one side of the substrate u. Further, ultraviolet light irradiation is performed from above, whereby exposure is performed and development processing is performed, and a predetermined pattern is obtained by using the dry film resist 12. f Further, the pattern at this time forms a plating region 4〇 of the plating layer, and as shown in FIG. 2, the pad portion 41 of the three squares is prepared and 16 ❹〇. 5 faces and squares are arranged. The terminal portion 42 is obtained by arranging a plurality of arrays of the plating regions 4 in the vicinity of the center of the substrate 4×6. Next, after the plating treatment is performed on the plating region 4 on the substrate, a strong acid bath of pHO.l to 1.0 is used to perform gold plating of about li.li (/m, and about 10 #m is applied thereon). The smelting of the smelting of the smelting of the smelting of the smelting of the smelting of the smelting From the substrate side, the lower plating layer 21 consisting of a thin gold plating layer and a 1 〇 nickel plating layer, an intermediate mineral layer 22 composed of a ruthenium copper plating layer, and a 5 nm nickel layer and The upper plating layer 23 composed of the 0·1/ζιη gold layer is formed, and the three layers of the plating layer are substantially formed on the substrate (because the gold layer is thin, it is not counted). The dry film resist 12 which is pre-attached on the surface is peeled off, and after being washed and dried by water, the mineral copper layer belonging to the intermediate mineral deposit layer is applied by iron liquid, and a button of about 7 /zm on one side is applied from the side surface toward the center portion. Engraving processing. By the series of processing steps, as described above, the underlying mineral layer of the ore 097137883 12 200931548 gold layer 31 and the nickel plating layer q (tetra) IM is formed on the substrate. 21. The middle _ coating of the ore layer 33 belongs to the stenosis of the upper side of the gold layer 35 and the slab of the upper layer of the gold layer 35, while the number of the copper layer 33 of the guangdong mine is higher than that of the upper and lower layers. (4) Ub) The semiconductor element mounting substrate obtained by the semiconductor element device shown in the cross section of the important portion is mounted on the pad portion 54 with a paste for the semiconductor main contact. 70 pieces of liver-thick conductors, and the electrodes of N and the terminal portion 52 are subjected to the wire bonding 53, as shown in Fig. 4(a), the sealing is π group and (4), and the resin sealing using 曰 is performed. (Refer to the semiconductor element mounting substrate 50 after resin sealing), (4) After riding the eucalyptus, the stainless steel belonging to the substrate 11 is pulled and peeled off from the sealed portion of the Ο and m days, and the peeling is observed in detail. The part that does not record the steel side, the fruit of the ..., the part of the residual money coating, in addition, in the portion of the gold-sealed portion that is sealed by the resin, the trace of the sealing resin 55 is not found, or from the secret The fat 55 is raised (10) and the layer is floated purely _ until it is tightly held. [Example 2] It is shown that the substrate 11 having a predetermined pattern formed by using a dry film resist on the surface of the substrate of the embodiment is used, and first, the mineralized region 40 of the substrate 11 is subjected to a depth of about _ plus In addition to forming the silver inscriptions on the portion, the rest of the substrate is obtained by using the same means as in the implementation of (1). Using the obtained semiconductor element mounting 097137883 13 200931548 substrate, the semiconductor element 51 is mounted on the pad portion 54 using the paste for investigation. 'The electrode of the semiconductor element 51 is soldered to the terminal portion 52, as shown in FIG. (b) The resin is sealed and sealed (refer to the semiconductor element mounting substrate 5G after the resin sealing), and the resin 11 is cured, and the substrate 11 is not cured. On the part of the Sasaki seal, peeling, and observing the _ _ side surface in detail, the result is that there is no part of the residual forging layer, and in addition, in the part of the resin and adjacent to the side of the mine It was found that the sealing resin wraps around the person's or that the forging layer floats or peels off from the resin, and it is confirmed that it is closely held. [Example 3] Using the stainless steel of Example 1 as a steel alloy, a substrate U having a predetermined pattern was produced by the same dry film (10) agent, and first, the plating region 4 of the substrate n was subjected to a depth of 7# using molten iron. The etching process of about m is performed by pre-plating treatment, and about 3/zm gold plating is performed by a neutral bath, about 6//m ❹ nickel plating is performed thereon, and about 6/im silver plating is performed thereon. On the substrate, an overall mineral coating layer of about 15# m is formed on the substrate, and then the dry film anti-surname agent remaining on the surface of the substrate is stripped. The nickel plating layer is subjected to selective etching by about 5; αιη etching process is obtained. The substrate for mounting a semiconductor element of the present embodiment. Using the obtained substrate for mounting a semiconductor element, as in Example 1, resin sealing was performed, and the resin was cured, and the copper alloy belonging to the substrate 11 was subjected to a dissolution treatment using a residual liquid to leave a resin containing the plating layer formed. The plating layer on the resin side was connected to the gold-plated part of the copper alloy, and no trace of the sealing resin was found. No 097137883 14 200931548 is now recorded from the resin or _ other conditions. Lai Cai is closely related. The status is maintained. [Example 4] Using the substrate as in Example 1; > Using a dry film k-etching agent to form a substrate π of a predetermined pattern, first applying a pre-plating treatment to the surface of the substrate 11 , using the strong acid bath of pHO. 1~1. 0 to perform about 〇 灯? g ϋ. 1 am gold plated, performed on it
約5//m鍍鎳，在其上面施行約R 他盯n b&m鍍銅，更在其上面施行 ❹約5//m鍍鎳，更在其上面施行芍 ^ ^ β 5# m鍍銅，更在其上面施 行約鑛錄，在其上面利用弱酸性〜中性浴施行約〇.⑽ 鍍金’藉以獲得鍍敷層從基材側起，形成鍍金層Μ與鐘鎳 層32的下侧鑛敷層21、中間錢敷層22為鑛銅層33a、鍍錄 層33b及鑛銅層33㈣3層、以及其上面的鐘錦層料與鐘 金層35之上侧鑛敷層23之半導體元件裝載用基板。 Μ ’將乾膜抗__，_驗侧㈣賴層施行深 ❹度6/zm左右的則加玉，而形成圖丨⑹所示重要部分剖 面。便用該所獲得半導體元件裝載用基板，如同實施例i 施行樹脂密封，經樹脂硬化後，將屬於基材n的不銹鋼從 樹脂始、封的部分上拉剝。觀察所拉剝的不銹鋼側，其結果均 無鍍敷層殘留的部分’並且，在經樹脂密封的部分且鄰接不 錄鋼的鍍金層侧，亦無發現密封樹脂繞入的痕跡，亦無發現 從密封樹脂上發生鍍敷層浮起或剝離的狀況，確認到其係依 緊禮、狀態保持。此外，經利用回焊（ref low)施行焊料接合 097137883 200931548 後，利用破壞試驗測定密封樹脂與鍍敷金屬端子的固1$ 度，較實施例1、2、3情況獲得更高的強度。 另一方面，若更進一步將中間鐘敷層多層化’步驟將變為 繁雜，為使生產性不會降低，便將各鍍敷層變薄，密封樹月旨 . 便難以繞入蝕刻加工的部分，因為保持之效果將降低，因而 最好考慮層數最多亦僅為本實施例的層數。 依此的話，當將所形成鍍敷層的總厚度變厚時，有將中間 © 鍍敷層變厚的方法、將上下鍍敷層變厚的方法等，藉由在中 間鍍敷層中含有未施行蝕刻加工的鍍敷層，利用上下錢敷層 與中間鍍敷層中的凸部形狀，便可提升密封樹脂所保持的效 果。 本發明半導體元件裝載用基板之製造方法，在基材上所形 成3層以上的鍍敷層，除上述實施例之外，尚可從基材側起 依序形成例如：鍍金、鍍銅、鍍金（或金合金鍍敷）；或鍍金、 〇 錢把、鑛鎳、鍍鈀、鑛金（或金合金鍍敷）；或鍍金、鍍鈀、 鍍鎳、鍍金、鍍銀（或銀合金鍍敷）；或鍍金、鍍鈀、鍍鎳、 鍍鈀（或鈀合金鍍敷）等適當的組合。 (產業上之可利用性） ，依照本發明方法所獲得的半導體元件裝制基板，儘管其 製造方法屬於簡略的步驟，所生成的鑛敷層與密封樹脂間之 密接性仍優異，將基材拉剝後，在所拉剝的基材侧不會殘留 將成為焊墊部或端子部的鍵敷層，當使用為半導體元件裝載 097137883 200931548 而期待在該產業領域中可 用基板時將可達極優異的效果，因 被廣泛地使用。 【圖式簡單說明] 圖1為根據本發明―银 基板，其中，⑷係在基 部分剖視圖，層職層的狀態之重要 θ德層的狀態之重要部分剖視 Ο 勒恳谌⑽㈣ 々且中間鍍敷層具有凸部的複數鍍 敷層構成的n重要部分剖視圖。 圖2為在基板上根據抗賴圖案形成複數組鑛敷層的狀 3 ’八，（a)係其重要部分的平面圖，⑹係⑷的其中一 部分之放大平面圖。 、圖3為根據本發明的半導體元件裝制基板之製造方 法’針對在基板上形成3層鑛敷層的手段，依步驟別進行說 曰月的剖視圖，其中，分別表示以下狀態之重要部分剖視圖⑷ ❹係·抗_形案的狀態，⑻鑛基材施㈣刻加工 的狀態’（c〇係在基材上施行3層錄層的狀態，⑷係將抗 餘劑圖案_的狀態’（e)係對中間鎌層施行侧加工的 • 狀態。 圖4為根據本發明的半導體元件裝載用基板之製造方法 中，經樹脂密封後的基板狀態，其中，（a)係依實施例1所 獲得基板的重要部分放大剖視圖，（b)係同樣的使用依實施 例2、3所獲得基板的重要部分放大剖視圖。 097137883 17 200931548 圖5為根據本發明的半導體元件裝載用基板之製造方法 中，說明本發明鍍敷層的示意剖視圖，其中，（a)係利用3 種鍍敷層之5層構造的示意剖視圖，（b)係利用3種鍍敷層 之7層構造的示意剖視圖。 【主要元件符號說明】About 5//m nickel plating, on which R is placed on the n b&m copper plating, and more than 5//m nickel plating is applied thereon, and 芍^^β 5# m plating is applied thereon. Copper, on which a mineral record is applied, on which a weakly acidic to neutral bath is applied. (10) Gold plating is used to obtain a plating layer from the side of the substrate to form a gold-plated layer and a nickel layer 32. The side mineral layer 21 and the intermediate money layer 22 are a copper layer 33a, a plating layer 33b, a layer 33 of a copper layer 33, and a semiconductor layer on the upper side of the clock layer and the upper layer of the layer III of the gold layer 35. A substrate for component mounting. Μ ‘The dry film is resistant to __, _ test side (4) lye layer is applied with a depth of about 6/zm, and jade is added to form a section of the important part shown in Fig. 6 (6). The substrate for mounting a semiconductor element obtained in this manner was subjected to resin sealing as in Example i, and after hardening by the resin, the stainless steel belonging to the substrate n was peeled off from the portion where the resin was sealed. The stainless steel side of the peeled steel was observed, and as a result, there was no remaining portion of the plating layer'. Also, on the side of the gold-plated layer which was sealed by the resin and adjacent to the non-recorded steel, no trace of the sealing resin was found, and no When the plating layer was floated or peeled off from the sealing resin, it was confirmed that the coating layer was held tightly and in a state. Further, after solder bonding 097137883 200931548 was performed by reflow soldering (ref low), the solid state of the sealing resin and the plated metal terminal was measured by a breaking test, and higher strength was obtained than in the cases of Examples 1, 2, and 3. On the other hand, if the intermediate layer is further layered, the steps will become complicated, and in order to prevent the productivity from being lowered, the plating layers will be thinned, and the sealing process will be difficult. In part, since the effect of the retention will be lowered, it is preferable to consider the number of layers at most and only the number of layers of this embodiment. In this case, when the total thickness of the formed plating layer is increased, there is a method of thickening the intermediate plating layer, a method of thickening the upper and lower plating layers, and the like, and the intermediate plating layer is contained therein. The plating layer which is not subjected to the etching process can improve the effect of the sealing resin by the shape of the convex portion in the upper and lower money coating layers and the intermediate plating layer. In the method for producing a substrate for mounting a semiconductor element of the present invention, three or more plating layers are formed on a substrate, and in addition to the above embodiments, gold plating, copper plating, gold plating may be sequentially formed from the substrate side. (or gold alloy plating); or gold plating, enamel, nickel, palladium, gold (or gold alloy plating); or gold plating, palladium plating, nickel plating, gold plating, silver plating (or silver alloy plating) ); or a suitable combination of gold plating, palladium plating, nickel plating, palladium plating (or palladium alloy plating). (Industrial Applicability) The substrate for mounting a semiconductor element obtained by the method of the present invention, although the manufacturing method thereof is a simple step, the adhesion between the formed mineral layer and the sealing resin is excellent, and the substrate is excellent. After the peeling, the bonding layer which will become the pad portion or the terminal portion does not remain on the side of the stretched substrate, and when it is used for the semiconductor device to be loaded with 097137883 200931548, it is expected that the substrate can be used in the industrial field. Excellent results are widely used. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a "silver substrate" according to the present invention, wherein (4) is a cross-sectional view of a base portion, and an important part of the state of the layer of the layer is an important part of the state of the θ layer (Ο) (10) (4) A cross-sectional view of an important part of n in which a plating layer has a plurality of plating layers having convex portions. Fig. 2 is a plan view showing the formation of a complex array of ore layers on the substrate according to the resist pattern, (a) is a plan view of an important portion thereof, and (6) is an enlarged plan view of a part of the system (4). FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor element-mounted substrate according to the present invention, in which a three-layered ore layer is formed on a substrate, and a step-by-step view showing an important portion of the following state, respectively. (4) The state of the ❹ · 抗 抗 , , , , ( 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿e) a state in which the intermediate layer is subjected to side processing. Fig. 4 is a state of the substrate after resin sealing in the method of manufacturing a substrate for mounting a semiconductor element according to the present invention, wherein (a) is according to the first embodiment An enlarged cross-sectional view of an important part of the substrate is obtained, and (b) is an enlarged cross-sectional view of an important part of the substrate obtained by the second and third embodiments. 097137883 17 200931548 FIG. 5 is a manufacturing method of a substrate for mounting a semiconductor element according to the present invention. A schematic cross-sectional view of a plating layer of the present invention, wherein (a) is a schematic cross-sectional view of a five-layer structure using three kinds of plating layers, and (b) is a schematic cross-sectional view of a seven-layer structure using three kinds of plating layers. Main reference numerals DESCRIPTION
11 基材 12 乾膜抗蝕劑 13 蝕刻部 21 下侧鍍敷層 22 中間鍍敷層 23 上侧鏟敷層 31 ' 35 鍍金層 32、33b、34 鍍鎳層 33 、 33a 鏟銅層 40 鍍敷區域 41 焊墊部 42 端子部 50 經樹脂密封後的半導體元件裝載用基板 51 半導體元件 52 端子部 53 連線焊接 54 焊墊部 55 密封樹脂 097137883 1811 substrate 12 dry film resist 13 etching portion 21 lower plating layer 22 intermediate plating layer 23 upper side shovel layer 31 ' 35 gold plating layer 32, 33b, 34 nickel plating layer 33, 33a shovel copper layer 40 plating Application area 41 Pad portion 42 Terminal portion 50 Resin-sealed semiconductor element mounting substrate 51 Semiconductor element 52 Terminal portion 53 Wire bonding 54 Pad portion 55 Sealing resin 097137883 18