200931228 九、發明說明： 【發明所屬之技術領域】 本發明涉及一種供電控制電路，特別涉及一種電腦主 機板上CPU供電控制電路。 【先前技術】 隨著科技之進步，CPU之主頻越來越高，另外，還 有用戶為獲取更高之CPU處理速度，採用超頻技術，這 樣CPU經常工作於高溫環境下，此溫度超過了 CPU安全 ❹工作溫度範圍，長時間之高溫工作會使CPU出現老化加 快、穩定性差等問題，更嚴重還會造成CPU被燒毁。對 此問題之解決措施，比較常見係買一個散熱性能好之風 扇，但這也不能完全保證CPU之安全，同時用戶於安裝 使用過程中之一些不規範操作，比如風扇沒有放好、沒 放，或者風扇老化、滑絲等，會致使CPU散熱效果不理 想，進而可能導致CPU被燒毁。 Ο 【發明内容】 鑒於以上内容，有必要提供一種於CPU之工作溫度 超過安全溫度範圍時，立即停止為CPU供電之供電控制 電路。 一種供電控制電路，用於控制是否為一電腦之CPU 供電，其包括一溫度偵測電路、一供電電路及一放電電 路，該供電電路分別與該溫度偵測電路、該CPU及該放 電電路相連，該放電電路與該溫度偵測電路及該CPU相 連，該溫度偵測電路與該CPU相連，用於偵測CPU工作 溫度，並於CPU之工作溫度超過安全範圍時，發出溫度 7 200931228 過高訊號，該供電電路接收到該溫度過高訊號後停止工 作，該放電電路接收到此溫度過高訊號後，為該供電電路 放電，從而停止向該CPU供電。 此供電控制電路，可藉由溫度偵測電路偵測CPU之 溫度，當偵測到之溫度超過某一設定溫度時，使供電電路 停止工作並藉由放電電路放電，從而給CPU斷電，確保 CPU工作於安全溫度範圍内，防止其燒毁。 【實施方式】 ❹ 請參閱圖1，本發明供電控制電路之較佳實施方式包 括一開關10、一溫度偵測電路20、一供電電路30及一放 電電路40，用於控制是否為一中央處理器（CPU) 50供 電。開關10與溫度偵測電路20相連。供電電路30與溫 度偵測電路20、CPU 50及放電電路40相連。放電電路 40與溫度偵測電路20及CPU 50相連。溫度偵測電路20 與CPU 50相連。 再參閱圖2，開關10包括一 NMOS場效電晶體 ® Q1。溫度偵測電路20包括一溫度偵測晶片U1、一電容 C1、一電容C2、複數電阻Rl、R2及R3。其中，溫度偵 測晶片U1為WINBOND公司之型號為W83L785TS-S之 晶片。NMOS場效電晶體Q1之閘極與基本輸入輸出系統 (BIOS)之輸入輸出端GPIO相連，汲極與電源VCC相 連，源極與溫度偵測晶片U1之電壓控制端VDD相連。 電容C1、電容C2與電阻R1並聯接于NMOS場效電晶體 Q1之源極及地之間。溫度偵測晶片 U1之溫度偵測端 CPUT與CPU之溫度輸出端Temp相連。溫度偵測晶片 8 200931228 U1之參考端Vref藉由電阻R2及電阻R3後接地，比較 端Offset/Fault—limit連接於電阻R2及電阻R3之間，接 地端GND接地。 再參閱圖3，供電電路30包括一電壓調節模組 (Voltage Regulator Module，VRM)晶片、NM0S 場效電 晶體Q2及Q3、一電感L1及一電容C3。其中，VRM晶 片為INTERSIL公司之型號為ISL6312CRZ之晶片。VRM 晶片之輸入引腳EN連接到溫度偵測晶片U1之溫度判定 ❹輸出端Temp_fault。VRM晶片之第一輸出引腳UGATE1 連接到NM0S場效電晶體Q2之閘極，NMOS場效電晶體 Q2之没極連接到電源Vin，NM0S場效電晶體Q2之源極 及NM0S場效電晶體Q3之汲極及VRM晶片之第一相引 腳PHASE1相連，NM0S場效電晶體Q3之閘極連接到 VRM晶片之第二輸出引腳LGATE1，NM0S場效電晶體 Q3之源極接地。電感L1之一端與VRM晶片之第一相引 腳PHASE1相連，另一端藉由電容C3後接地，還連接 ❹CPU之供電端VCCP。此VRM晶片中，第一相引腳 PHASE1、第一輸出引腳UGATE1及第二輸出引.腳 LGATE1為一第一組引腳，該VRM晶片可包括多組此引 腳，每組引腳與CPU之供電端VCCP之間連接之電子元 件及與電子元件之連接方式同第一組引腳，每組引腳與 CPU之供電端VCCP之間連接之電子元件之作用均是保 證供電電路30給CPU供電之電壓保持穩定，引腳組越多 CPU供電之電壓越穩定。 再參閱圖4，放電電路40包括一電容C4、電阻R4 9 200931228 .及R5、一三極體Q4及一 NMOS場效電晶體Q5。其中， 三極體Q4為NPN三極體。放電電路40中之電阻R4 — .端與溫度债測晶片U1之溫度判定輸出端Temp_fault相 連，電阻R4之另一端藉由電容C4後接地，三極體Q4之 •基極連接於電阻R4及電容C4之間，集極藉由電阻R5與 '電源VCC相連，射極接地。NMOS場效電晶體Q5之源 極接地，閘極連接到三極體Q4之集極，汲極連接到CPU 之供電端VCCP。 ❹ 當用戶開機後，若用戶不想對CPU進行保護，即 CPU溫度過高後不會斷電，用戶得進入BIOS將此功能失 效掉，BIOS將會使輸入輸出端GPIO為低電平，從而使 NMOS場效電晶體Q1截止，電源VCC不給溫度偵測晶 片U1供電，從而使溫度偵測晶片U1停止工作，供電電 路30及放電電路40均失效，這樣於BIOS中可實現對 CPU是否進行保護之有效控制。 反之，默認BIOS中設置之此功能有效，此時BIOS ©之輸入輸出端GPIO為高電平，NMOS場效電晶體Q1導 通，電源VCC供電給溫度偵測晶片U1使溫度偵測晶片 U1開始工作。CPU傳輸溫度值到溫度偵測端CPUT，溫 度偵測晶片U1接收到此溫度訊號後，將此溫度與其内部 設定之CPU溫度安全值做一個比較，判斷當前溫度是否 於安全範圍内，若於安全範圍内則繼續進行偵測比較，若 超出CPU溫度安全值則溫度判定輸出端Temp_fault發出 溫度過南訊號’此溫度過南訊號為低電平訊號。 VRM晶片之輸入引腳EN接收到溫度判定輸出端 200931228200931228 IX. Description of the Invention: [Technical Field] The present invention relates to a power supply control circuit, and more particularly to a CPU power supply control circuit on a computer main board. [Prior Art] With the advancement of technology, the CPU frequency is getting higher and higher. In addition, users also use the overclocking technology to obtain higher CPU processing speed, so that the CPU often works in high temperature environment, and the temperature exceeds the temperature. CPU safety ❹ operating temperature range, long-term high temperature work will cause the CPU to aging faster, poor stability and other issues, more serious will cause the CPU to be burned. The solution to this problem is more common to buy a fan with good heat dissipation performance, but this does not completely guarantee the safety of the CPU. At the same time, some irregular operations of the user during installation and use, such as the fan is not placed, not put, Or the fan aging, slipping, etc., will cause the CPU to dissipate heat, which may cause the CPU to be burned. Ο [Summary] In view of the above, it is necessary to provide a power supply control circuit that immediately stops powering the CPU when the operating temperature of the CPU exceeds the safe temperature range. A power supply control circuit for controlling whether a CPU of a computer is powered, comprising a temperature detecting circuit, a power supply circuit and a discharging circuit, wherein the power supply circuit is respectively connected to the temperature detecting circuit, the CPU and the discharging circuit The discharge circuit is connected to the temperature detecting circuit and the CPU, and the temperature detecting circuit is connected to the CPU for detecting the operating temperature of the CPU, and when the working temperature of the CPU exceeds the safe range, the temperature is 7 200931228 is too high. The signal, the power supply circuit stops working after receiving the temperature over-high signal, and the discharge circuit discharges the power supply circuit after receiving the over-temperature signal, thereby stopping power supply to the CPU. The power supply control circuit can detect the temperature of the CPU by the temperature detecting circuit, and when the detected temperature exceeds a certain set temperature, the power supply circuit stops working and discharges through the discharging circuit, thereby powering off the CPU, ensuring The CPU operates within a safe temperature range to prevent it from burning out. [Embodiment] Referring to FIG. 1, a preferred embodiment of the power supply control circuit of the present invention includes a switch 10, a temperature detecting circuit 20, a power supply circuit 30, and a discharging circuit 40 for controlling whether it is a central processing. (CPU) 50 power supply. The switch 10 is connected to the temperature detecting circuit 20. The power supply circuit 30 is connected to the temperature detecting circuit 20, the CPU 50, and the discharging circuit 40. The discharge circuit 40 is connected to the temperature detecting circuit 20 and the CPU 50. The temperature detecting circuit 20 is connected to the CPU 50. Referring again to Figure 2, switch 10 includes an NMOS field effect transistor ® Q1. The temperature detecting circuit 20 includes a temperature detecting chip U1, a capacitor C1, a capacitor C2, and a plurality of resistors R1, R2 and R3. Among them, the temperature detecting wafer U1 is a wafer of the type W83L785TS-S of WINBOND. The gate of the NMOS field effect transistor Q1 is connected to the input/output terminal GPIO of the basic input/output system (BIOS), the drain is connected to the power supply VCC, and the source is connected to the voltage control terminal VDD of the temperature detecting chip U1. The capacitor C1, the capacitor C2 and the resistor R1 are coupled between the source of the NMOS field effect transistor Q1 and the ground. Temperature detection chip The temperature detection terminal of U1 is connected to the temperature output terminal Temp of the CPU. Temperature detection chip 8 200931228 The reference terminal Vref of U1 is grounded by resistor R2 and resistor R3. The comparison terminal Offset/Fault_limit is connected between resistor R2 and resistor R3, and the ground terminal GND is grounded. Referring to FIG. 3, the power supply circuit 30 includes a voltage regulator module (VRM) chip, NM0S field effect transistors Q2 and Q3, an inductor L1, and a capacitor C3. Among them, the VRM wafer is a wafer of the type ISL6312CRZ of INTERSIL Corporation. The input pin EN of the VRM chip is connected to the temperature determination ❹ output Temp_fault of the temperature detecting wafer U1. The first output pin UGATE1 of the VRM chip is connected to the gate of the NM0S field effect transistor Q2, the NMOS field effect transistor Q2 is connected to the power source Vin, the source of the NM0S field effect transistor Q2 and the NM0S field effect transistor. The drain of Q3 is connected to the first phase pin PHASE1 of the VRM chip, the gate of the NM0S field effect transistor Q3 is connected to the second output pin LGATE1 of the VRM chip, and the source of the NM0S field effect transistor Q3 is grounded. One end of the inductor L1 is connected to the first phase pin PHASE1 of the VRM chip, and the other end is grounded by the capacitor C3, and is also connected to the power supply terminal VCCP of the CPU. In the VRM chip, the first phase pin PHASE1, the first output pin UGATE1, and the second output pin LGATE1 are a first set of pins, and the VRM chip can include multiple sets of the pins, each set of pins and The electronic components connected to the power supply terminal VCCP of the CPU and the connection mode with the electronic components are the same as the first group of pins, and the functions of the electronic components connected between each set of pins and the power supply terminal VCCP of the CPU are to ensure that the power supply circuit 30 gives The voltage supplied by the CPU remains stable, and the more the pin group, the more stable the voltage of the CPU power supply. Referring to FIG. 4, the discharge circuit 40 includes a capacitor C4, a resistor R4 9 200931228, and R5, a triode Q4, and an NMOS field effect transistor Q5. Among them, the triode Q4 is an NPN triode. The resistor R4 in the discharge circuit 40 is connected to the temperature determination output Temp_fault of the temperature debt measurement chip U1, the other end of the resistor R4 is grounded by the capacitor C4, and the base of the triode Q4 is connected to the resistor R4 and the capacitor. Between C4, the collector is connected to the 'power supply VCC' through the resistor R5, and the emitter is grounded. The source of the NMOS field effect transistor Q5 is grounded, the gate is connected to the collector of the transistor Q4, and the drain is connected to the power supply terminal VCCP of the CPU. ❹ When the user turns on the computer, if the user does not want to protect the CPU, that is, the CPU will not power off after the CPU temperature is too high, the user has to enter the BIOS to disable this function, the BIOS will make the input and output GPIO low, thus making When the NMOS field effect transistor Q1 is turned off, the power supply VCC does not supply power to the temperature detecting chip U1, so that the temperature detecting chip U1 stops working, and the power supply circuit 30 and the discharging circuit 40 are disabled, so that the CPU can be protected in the BIOS. Effective control. On the contrary, the function set in the default BIOS is valid. At this time, the input and output GPIO of the BIOS © is high level, the NMOS field effect transistor Q1 is turned on, and the power supply VCC is supplied to the temperature detecting chip U1 to make the temperature detecting chip U1 start working. . The CPU transmits the temperature value to the temperature detecting end CPUT. After receiving the temperature signal, the temperature detecting chip U1 compares the temperature with the CPU temperature safety value set internally to determine whether the current temperature is within the safe range. In the range, the detection comparison is continued. If the CPU temperature safety value is exceeded, the temperature determination output Temp_fault sends a temperature over the south signal 'this temperature is too low for the south signal. The input pin EN of the VRM chip receives the temperature determination output terminal 200931228
Temp_fault發出之低電平訊號使VRM晶片停止工作。當 VRM晶片停止工作之瞬間，電感L1及電容C3有儲存電 量，此時，放電電路40會立即使CPU之供電端VCCP之 電壓歸零，停止向CPU供電。放電電路40接收到溫度偵 測晶片U1之溫度判定輸出端Temp_fault發出之低電平訊 —號後，三極體Q4截止，電源VCC將NMOS場效電晶體 Q5之閘極拉至高電平，NMOS場效電晶體Q5導通，使 CPU之供電端VCCP電壓拉至低電平，使電感L1及電容 ❹C3之電量放掉，停止向CPU供電端VCCP供電，CPU停 止工作。 如是藉由溫度偵測晶片Ul、VRM晶片及放電電路 40，若CPU溫度超過安全範圍，CPU會立即斷電，用戶 就不必擔心CPU被燒毁，即使用戶開機後忘記放CPU風 扇也沒有關係，對CPU進行了充分之保護。 綜上所述，本發明符合發明專利要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 Ο 熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾 或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1係本發明供電控制電路之較佳實施方式之模組 圖。 圖2係圖1中開關、溫度偵測電路及CPU連接之電 路圖。 圖3係圖1中供電電路之電路圖。 圖4係圖1中放電電路之電路圖。 11 200931228 【主要元件符號說明】 開關 10 溫度偵測電路 20 供電電路 30 放電電路 40 CPU 50 電阻 Rl~ R5 電容 C1〜C4 電源 VCC、Vin 二極體 Q4 NMOS場效電晶體 Ql、Q2 電感 L1 溫度债測晶片 U1The low level signal from Temp_fault stops the VRM die. When the VRM chip stops working, the inductor L1 and the capacitor C3 have stored power. At this time, the discharge circuit 40 immediately resets the voltage of the CPU's power supply terminal VCCP to zero, and stops supplying power to the CPU. After the discharge circuit 40 receives the low level signal issued by the temperature determination output terminal Temp_fault of the temperature detecting chip U1, the triode Q4 is turned off, and the power supply VCC pulls the gate of the NMOS field effect transistor Q5 to the high level, NMOS The field effect transistor Q5 is turned on, so that the VCCP voltage of the power supply terminal of the CPU is pulled to a low level, so that the power of the inductor L1 and the capacitor ❹C3 is discharged, and the power supply to the CPU of the CPU is stopped, and the CPU stops working. If the temperature of the CPU is over the safe range, the CPU will immediately power off the CPU, and the user does not have to worry about the CPU being burned. Even if the user forgets to put the CPU fan after booting, it does not matter. The CPU is fully protected. In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a preferred embodiment of a power supply control circuit of the present invention. Figure 2 is a circuit diagram of the switch, temperature detecting circuit and CPU connection of Figure 1. Figure 3 is a circuit diagram of the power supply circuit of Figure 1. 4 is a circuit diagram of the discharge circuit of FIG. 1. 11 200931228 [Main component symbol description] Switch 10 Temperature detection circuit 20 Power supply circuit 30 Discharge circuit 40 CPU 50 Resistor Rl~ R5 Capacitor C1~C4 Power supply VCC, Vin Diode Q4 NMOS field effect transistor Ql, Q2 Inductance L1 Temperature Debt measurement chip U1