200931049 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種主機板測試裝置，特別係關於一種 可對電腦主機板進行迴圈開關機測試之主機板測試裝置。 【先前技術】 電腦生產薇商在對電腦之品質驗證過程中，電腦主機 板之DC Power 0n/0ff測試，即直流開關機測試是一個重要 ❹之驗證項目。習知之測試方法是測試人員定期手動按下電 腦電源按鍵使得電腦主機板上電’而手動按下電腦電源按 鍵之實質是給電腦主機板上之輸入輸出控制器一個低電平 訊號，而放開電腦電源按鍵後該輸入輸出控制器又被置回 高電平，由此完成電腦開機。在電腦開機後執行測試程式， 當開機達到-定之時間後測試人員手動操作電腦軟關機。 而當關閉電腦一段時間後又重新按電腦電源按鍵，如此循 環往復進行開關機操作，直至測試次數達到預定之次數後 〇停止測試。為了完成此項測試，需要花費大量之人力，增 加了生產成本。 【發明内容】 雲於上述内容，有必要提供-種低成本之主機板測試 裝置，可自動對電腦主機板進行迴圈開關機測試。 一種主機板測試裝置，包括： 一輸出端， 生一脈波訊 一脈波訊號發生電路，其包括一輪入端和 該輸入端接收一待機電壓訊號，並在輪出端產 號； 200931049 端和一：出：制::二：包:-第-輪入端、-第二輸入 、_ k弟一輸入端接收來自脈波訊號發生電路 * 、訊號並根據該脈波訊號在第一控制電路之輪出 •匕-第-控制訊號至一電腦主機板上之輸入輸二 控制電：:出Γ11在接收到低電平之第-控制訊號後 端和制電路，其包括一第—輸入端、一第二輸入 ❹電壓Ί第二控制電路之第—輸人端接收該待機 丰㈣該第二控制電路之第二輸人端接收該主機板之 =電：訊：’電腦在軟關機後該第二控制電路之輸出端 第—控制訊號至第—控制電路之第二輸人端，使得 控制電路之第一輸入端在接收Μιϋ # $ 可再次_。 *純龍Μ之脈波訊號後 相較習知技術’該主機板測試裝置可不需測試人 J 電腦主機板上電和關機，透過脈波訊 ί機==出給輪八輸出控制器之高低電平訊號可對 易於實現。 -電路間早、成本較低、 【實施方式】 包括請h本發明主機板測試裝置之較佳實施方式 =-脈波訊號發生電路10、一第一控制電 一控制電路30。 示 該脈波訊號發生電路10包括—555計時器ui、一 —電阻R1、-第二電阻R2、—第—電容ci卜第二電= 200931049 C2 ’該555計時器υΐ包括一電源端11、—低觸發端 一清零端13、一控制端14、一高觸發端15、一放電端 一輸出端17和一接地端18 ’該電源端U间、、主& 丨J ’月令k 13相 連後連接一待測電腦主機板之5V STBY畲嚴 _ , - i ! 孩低觸發 端12和高觸發端15相連後經第一電容Cl接地，並透； 第一電阻R1和第二電阻R2連接該5V一STBY電壓，該=200931049 IX. Description of the Invention: [Technical Field] The present invention relates to a motherboard testing device, and more particularly to a motherboard testing device capable of performing a loop switching machine test on a computer motherboard. [Prior Art] Computer production of Weishang in the quality verification process of the computer, the DC Power 0n/0ff test of the computer main board, that is, the DC switch test is an important verification project. The test method of the conventional test is that the tester manually presses the power button of the computer to make the computer main board power on- and the manual pressing of the power button of the computer is to give a low level signal to the input and output controllers on the computer motherboard, and let go. After the computer power button is pressed, the input/output controller is set back to a high level, thereby completing the computer booting. After the computer is turned on, the test program is executed. When the power is turned on, the tester manually operates the computer to softly shut down. When the computer is turned off for a while, press the power button again, and then cycle the machine until the number of tests reaches a predetermined number of times. In order to complete this test, it takes a lot of manpower and increases production costs. SUMMARY OF THE INVENTION In the above content, it is necessary to provide a low-cost motherboard test device that can automatically perform a loop switch test on a computer motherboard. A motherboard testing device includes: an output terminal, a pulse-wave-to-pulse signal generating circuit, comprising a wheel-in terminal and the input terminal receiving a standby voltage signal, and producing a signal at the wheel end; 200931049 One: out: system:: two: package: - first - round input, - second input, _ k brother one input receives the pulse signal generation circuit *, the signal and according to the pulse signal in the first control circuit The wheel-out-first-control signal to the input and output control of a computer motherboard: the output terminal 11 receives the low-level control signal back-end and the circuit, which includes a first input terminal a second input voltage Ί the second control circuit of the first control circuit receives the standby Feng (four) the second control circuit of the second input terminal receives the motherboard = electricity: message: 'the computer after the soft shutdown The output of the second control circuit is first to the second input end of the first control circuit, so that the first input of the control circuit is receiving Μιϋ #$. *Pure dragon's pulse signal is better than the conventional technology' The motherboard test device can be used without the tester J computer power on and off, through the pulse wave machine == the output of the wheel eight output controller Level signals are easy to implement. - The circuit is early and the cost is low. [Embodiment] A preferred embodiment of the motherboard test apparatus of the present invention is included. - The pulse signal generating circuit 10 and a first control circuit A control circuit 30. The pulse signal generating circuit 10 includes a -555 timer ui, a resistor R1, a second resistor R2, a capacitor ci, a second capacitor = 200931049 C2 'the 555 timer υΐ includes a power terminal 11, - low trigger terminal - clear terminal 13, a control terminal 14, a high trigger terminal 15, a discharge terminal - an output terminal 17 and a ground terminal 18 ' between the power terminals U, main & 丨 J 'monthly k 13 connected and connected to a 5V STBY of the computer motherboard to be tested ,, - i ! The low trigger terminal 12 is connected to the high trigger terminal 15 and grounded through the first capacitor C1; and the first resistor R1 and the second resistor R2 connects the 5V to STBY voltage, which =
〇 電端16同第一電阻R1和第二電阻R2之間之連接節點相 連，該控制端14透過第二電容C2接地。 該第一控制電路20包括一第一場效電晶體、一第 二場效電晶體Q2、一二極體D1、一第三電阻R3和一第 三電容C3’該第一場效電晶體Q1之閘極連接該555計時 器U1之輸出端17，該第一場效電晶體Q1之源極連接該 電腦主機板上之輸入輸出控制器，該第—場效電晶體Qi 之汲極同第二場效電晶體q2之源極相連，該第二場效電 晶體Q2之閘極經第三電容接地，並透過第三電阻同該二 極體D1之陰極相連，該第二場效電晶體Q2之汲極接地， 該二極體D1之陽極接收該電腦主機板之一 5V_SYS電壓。 該第一控制電路30包括一比較器U2' —電晶體T1、 第四電阻R4、一第五電阻R5、一第六電阻R6和一第七 電阻R7，該比較器U2之同相輸入端經第四電阻r4連接 該5V_STBY電壓，並透過第五電阻R5接地，該比較器 U2之反相輸入端接收該5v_SYS電壓，該比較器u2之輸 出端透過第六電阻R6連接該電晶體τι之基極，該電晶體 T1之集極透過第七電阻R7連接該第二場效電晶體Q2之 200931049 .閘極，該電晶體T1之射極接地。其中第一場效電晶體Q1 和第二場效電晶體Q2均為P溝道MOS型場效電晶體，電 晶體T1為NPN型電晶體。該5V_STBY電壓為5V待機 電壓，5V_SYS電壓為5V系統電壓。 使用本發明主機板測試裝置對待測電腦主機板進行測 試時，先將主機板之電源供應器接入市電並閉合其開關， 待測主機板即輸出該5V_STBY電壓。該5 V_STBY電壓透 秦過第一電阻R1和第二電阻R2給該第一電容C1充電，在 〇 第一電容C1上之電壓充至5V_STBY電壓之三分之二前， 該555計時器U1之輸出端17 —直輸出高電平訊號。當第 一電容C1上之電壓充至5V_STBY電壓之三分之二時，該 第一電容C1透過第二電阻R2向該555計時器U1之放電 端16放電，此時該555計時器U1之輸出端17輸出低電 平。該第一電容C1不斷之充放電在該555計時器U1之輸 出端17產生高低電平之脈波訊號。當該555計時器U1之 ❹輸出端17輸出低電平時，此時由於5 V_SYS電壓還未輸 出，第二場效電晶體Q2之閘極為低電平而導通，使得該 第一場效電晶體Q1也導通，第一場效電晶體Q1的源極為 低電平，此時相當於測試人員手動按下了電源按鍵。該輸 入輸出控制器接收到低電平訊號時輸出各組系統電壓使得 待測主機板上電，5V_SYS電壓透過二極體D1及第三電阻 R3給該第三電容C3充電，在第三電容C3上的電壓充至 第二場效電晶體Q2之截止電壓後，第二場效電晶體Q2截 止，使得該第一場效電晶體Q1也截止，第一場效電晶體 200931049 Q1之源極為高電平，此時相當於測試人員又放開了電源按 鍵，由此完成了電腦自動開機。 在電腦開機達到一預設時間後該輸入輸出控制器發出 關機訊號使電腦軟關機，此時5V_SYS電壓關閉，作 -5V—STBY電壓仍然輸出。該比較器U2之輸出端輸出高電 平使得該電晶體T1導通，該第三電容C3透過第七電阻 R7放電。當第三電容C3上之電壓放至第二場效電晶體㈨ ❾之導通電壓時，第二場效電晶體Q2再次導通，當該 計時器U1之輸出端17再次輸出低電平時該第一場效電晶 體也可再次導通，電腦也可再次開機。由此透過該555 計時器U1之輸出端17不斷輸出之高低電平脈波訊號實現 了對待測主機板之迴圈開關機測試。 該主機板測試裝置可自動對電腦主機板進行迴圈開關 機測試，具有結構簡單、實用性強、成本較低等優點。 綜上所述，本發明符合發明專利要件，差依法提出專 ❿利申請。$，以上所述者僅為本發明之具體實施方式，舉 凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1係本發明主機板測試裝置之較佳實施方式之電路 圖。 【主要元件符號說明】 :波訊號發生電路10 帛一控制電路20 第二控制電路30 555計時g m 200931049 比較器 U2 電晶體 T1 第一場效電晶體 Q1 第二場效電晶體 Q2 二極體 D1 電阻 R1 〜R7 電容 C1-C3 11The electric terminal 16 is connected to the connection node between the first resistor R1 and the second resistor R2, and the control terminal 14 is grounded through the second capacitor C2. The first control circuit 20 includes a first field effect transistor, a second field effect transistor Q2, a diode D1, a third resistor R3, and a third capacitor C3'. The first field effect transistor Q1 The gate of the first field effect transistor Q1 is connected to the input and output controller of the computer motherboard, and the gate of the first field effect transistor Qi is the same as the first end. The source of the second field effect transistor q2 is connected, the gate of the second field effect transistor Q2 is grounded via a third capacitor, and is connected to the cathode of the diode D1 through a third resistor, the second field effect transistor The anode of Q2 is grounded, and the anode of the diode D1 receives a voltage of 5V_SYS of one of the computer boards. The first control circuit 30 includes a comparator U2' - a transistor T1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7. The non-inverting input of the comparator U2 is The fourth resistor r4 is connected to the 5V_STBY voltage, and is grounded through the fifth resistor R5. The inverting input terminal of the comparator U2 receives the 5v_SYS voltage, and the output end of the comparator u2 is connected to the base of the transistor τ1 through the sixth resistor R6. The collector of the transistor T1 is connected to the 200931049. gate of the second field effect transistor Q2 through the seventh resistor R7, and the emitter of the transistor T1 is grounded. The first field effect transistor Q1 and the second field effect transistor Q2 are both P-channel MOS type field effect transistors, and the transistor T1 is an NPN type transistor. The 5V_STBY voltage is 5V standby voltage and the 5V_SYS voltage is 5V system voltage. When testing the computer motherboard to be tested by using the motherboard test device of the present invention, first connect the power supply of the motherboard to the mains and close its switch, and the motherboard to be tested outputs the 5V_STBY voltage. The 5 V_STBY voltage passes through the first resistor R1 and the second resistor R2 to charge the first capacitor C1. Before the voltage on the first capacitor C1 is charged to two-thirds of the 5V_STBY voltage, the 555 timer U1 The output terminal 17 outputs a high level signal directly. When the voltage on the first capacitor C1 is charged to two-thirds of the voltage of the 5V_STBY, the first capacitor C1 is discharged to the discharge terminal 16 of the 555 timer U1 through the second resistor R2, and the output of the 555 timer U1 is output. Terminal 17 outputs a low level. The first capacitor C1 is continuously charged and discharged to generate a high and low pulse signal at the output terminal 17 of the 555 timer U1. When the output terminal 17 of the 555 timer U1 outputs a low level, at this time, since the 5 V_SYS voltage is not yet output, the gate of the second field effect transistor Q2 is turned to a low level, and the first field effect transistor is turned on. Q1 is also turned on, and the source of the first field effect transistor Q1 is extremely low, which is equivalent to the tester manually pressing the power button. When the input/output controller receives the low level signal, the system voltage is outputted so that the main body of the test is powered, and the 5V_SYS voltage is charged to the third capacitor C3 through the diode D1 and the third resistor R3, and the third capacitor C3 is charged. After the voltage on the second field effect transistor Q2 is turned off, the second field effect transistor Q2 is turned off, so that the first field effect transistor Q1 is also turned off, and the source of the first field effect transistor 200931049 Q1 is extremely high. The level is equivalent to the tester releasing the power button again, thus completing the automatic booting of the computer. After the computer is turned on for a preset time, the input/output controller sends a shutdown signal to make the computer softly shut down. At this time, the 5V_SYS voltage is turned off, and the -5V-STBY voltage is still output. The output terminal of the comparator U2 outputs a high level such that the transistor T1 is turned on, and the third capacitor C3 is discharged through the seventh resistor R7. When the voltage on the third capacitor C3 is placed on the turn-on voltage of the second field effect transistor (9), the second field effect transistor Q2 is turned on again, and when the output terminal 17 of the timer U1 outputs a low level again, the first The field effect transistor can also be turned on again, and the computer can be turned on again. Therefore, the high-low pulse signal continuously outputted from the output terminal 17 of the 555 timer U1 realizes the loop switch test of the motherboard to be tested. The motherboard test device can automatically perform loopback switch test on the computer motherboard, which has the advantages of simple structure, strong practicability and low cost. In summary, the present invention complies with the requirements of the invention patent, and the application for the special profit is made according to the law. The above description is only for the specific embodiments of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a preferred embodiment of a motherboard test apparatus of the present invention. [Main component symbol description]: Wave signal generation circuit 10 First control circuit 20 Second control circuit 30 555 timing gm 200931049 Comparator U2 Transistor T1 First field effect transistor Q1 Second field effect transistor Q2 Dipole D1 Resistor R1 ~ R7 Capacitor C1-C3 11