200931042 九、發明說明： 【發明所屬之技術領域】 * 本發明係關於一種測試裝置，特別係關於一種用於測 ， 試電腦主機板電壓裕度之測試裝置。 【先前技術】 電腦主機板之工作電壓主要包括3.3V_SYS、 12V_SYS、5V一SYS、-5V—SYS、-12V一SYS 及 5V—STBY， ❹以及PWROK控制訊號。這些電壓與控制訊號主要由機箱 電源提供’透過24pin連接器輸入到電腦主機板上，作為 主機板之輸入電源。 由於機箱電源為獨立配置設備，對於主機板設計與生 產廠商來說，其設計與生產之主機板流入市場後會遇到各 種各樣之機箱電源，為使機箱電源與電腦主機板相匹配， 需事先確定主機板電壓之裕度，即主機板電壓允許之上、 下限範圍。 ❹【發明内容】 馨於以上内容，有必要提供一種可方便測試主機板電 壓裕度之測試裝置。 一裡1： /金裕度測試裝置 -第二、一第三裕度測試電路、一第_、一第二、一第二 訊號產生電路及1於連接待測主機板之連接器，該第: 裕度測忒電路包括一第一直流可調 關，該第二裕度測試電路包括 ，、及一第-控制知 一 a栝第二直流可調電源及一每 -控制開_ ’該第三裕度測試電 ^ 匕祜一第二直流可調Ί 200931042 Ο :及：第三控制開關’該第一、第二、第三直流可調電源 過該第-、第二、第三控制開關與該連接器之—第 一二一第二、一第三電源引腳相連，該第一訊號產生電路 之輸入端與該第三直流可調電源相連，該第二訊號產生電 路之輸入端與該第二裕度測試電路及該第—訊號產生電路 輸出端相連’該第二訊號產生電路之輸入 度測試電路之輸出端相連，該第―、第二、第三訊號= 電路之輸出端分別接至該連接器之一第四、一第五、一第 六電源引腳’該控制電路之輸入端與該連接器之電源開機 ㈣引腳相連，輸出端分別與該第-、第二、第三裕度測 試電路相連，遠控制電路透過電源開機訊號引腳接收到待 測主機板之電源開機訊號後，驅使該第一、第二、第三控 制開關導通，使該第一、第二、第三直流可調電源供電給 該連接叩之第-、第二、第三、第四、第五、第六電源 腳。 Ο,該電壓裕度測試裝置應用該直流可調電源直接連接至 該待測主機板之電源電路上，並透過調節該直流可調電源 之電壓調節開關即可方便、快捷的得出該待測主機板之電 壓裕度。 【實施方式】200931042 IX. Description of the invention: [Technical field to which the invention pertains] * The present invention relates to a test apparatus, and more particularly to a test apparatus for measuring and testing the voltage margin of a computer motherboard. [Prior Art] The working voltage of the computer main board mainly includes 3.3V_SYS, 12V_SYS, 5V-SYS, -5V-SYS, -12V-SYS and 5V-STBY, ❹ and PWROK control signals. These voltage and control signals are primarily supplied by the chassis power supply's input to the computer's motherboard through the 24-pin connector as the input power to the motherboard. Since the chassis power supply is an independent configuration device, for the motherboard design and manufacturer, the design and production of the motherboard will encounter various chassis power supplies after entering the market. In order to match the chassis power supply with the computer motherboard, The margin of the motherboard voltage is determined in advance, that is, the upper and lower limits of the motherboard voltage are allowed. ❹ [Summary of the Invention] In the above content, it is necessary to provide a test device that can easily test the voltage margin of the motherboard. Yili 1: / Jin Yudu test device - second, a third margin test circuit, a _, a second, a second signal generation circuit and a connector connected to the motherboard to be tested, the first: The measuring circuit includes a first DC adjustable switch, the second margin testing circuit includes, and a first control unit, a second DC adjustable power supply, and a per-control open_'the third The margin test circuit ^ 匕祜 a second DC adjustable Ί 200931042 Ο : and: the third control switch 'the first, second, third DC adjustable power supply through the first, second, third control switch and The first two one second and one third power supply pin are connected to the connector, and the input end of the first signal generating circuit is connected to the third DC adjustable power supply, and the input end of the second signal generating circuit and the The second margin test circuit and the output end of the first signal generating circuit are connected to an output end of the input signal test circuit of the second signal generating circuit, and the output ends of the first, second, and third signals=circuits are respectively connected To the fourth, fifth, and sixth power pins of the connector The input end of the control circuit is connected to the power-on (four) pin of the connector, and the output end is respectively connected to the first, second, and third margin test circuits, and the far control circuit is received by the power-on signal pin to be tested. After the power-on signal of the motherboard, the first, second, and third control switches are driven to be turned on, so that the first, second, and third DC adjustable power supplies are powered to the first, second, and third terminals of the connection , fourth, fifth, and sixth power supply feet. Ο, the voltage margin test device applies the DC adjustable power supply directly to the power circuit of the motherboard to be tested, and can conveniently and quickly obtain the test to be tested by adjusting the voltage adjustment switch of the DC adjustable power supply. The voltage margin of the motherboard. [Embodiment]
請參閱圖1，本發明電壓裕度測試裝置用於測試電腦 主機板之電壓裕度，其較佳實施方式包括一 3.3V裕度測試 電路10、一 5V裕度測試電路2〇、一 12ν裕度測試電路 30、一控制電路40、一 5ν一STBY產生電路5〇、一 pWR〇K 200931042 產生電路60，一-12V產生電路70、一連接器80及一指示 電路90 ’該3.3V、5V、12V裕度測試電路1〇、20、30分 • 別用於測試待測主機板之3.3V、5V及12V電壓裕度，該 • 5V一STBY、PWROK、-12V 產生電路 50、60 及 70 分別用 於產生待測主機板所需要之5V_STBY、PWROK及-12V電 壓訊號。 請一併參閱圖2及圖6,該5 V_STBY產生電路50包 ❹括一型號為7805之三端穩壓器U1及電容Cl、C2，本實 施方式中，該三端穩壓器U1為一固定輸出為5V之7805 型三端穩壓器’其接地端GND接地，輸入端VIN接至一 直流可調電源C，並透過電容C1接地，該三端穩壓器U1 之輸出端VOUT作為該5V_STBY產生電路50之輸出端， 接至該連接器80之+5 V_AUX電源引腳，並透過該電容C2 接地。 請一併參閱圖3及圖6，該3.3V裕度測試電路1〇包 ©括一直流可調電源A、一第一控制開關及兩電容C3、C4， 該第一控制開關為一 N通道M〇s型場效應電晶體（nM0S 電晶體）Q1 ’該NM0S電晶體之汲極接至該直流可調 電源A ’並透過該電容C3接地，源極接至該連接器8〇之 +3.3V電源弓丨腳’並透過該電容C4接地。 該5 V裕度測試電路2〇包括一直流可調電源b、一第 二控制開關及兩電容C5、C6，該第二控制開關為一 NMOS 電晶體Q2 ’該NM〇s電晶體q2之汲極作為該裕度測 試電路20之輪入端’接至該直流可調電源b，並透過該電 200931042 容C5接地，源極作為該5 V裕度測試電路20之輸出端， 接至該連接器80之+5V電源引腳，並透過該電容C6接地。 ' 該12V裕度測試電路30包括一直流可調電源C、一 • 第三控制開關、兩電容C7、C8及電阻R5，該第三控制開 關為一 P通道MOS型場效應電晶體（PMOS電晶體）Q3， 該PMOS電晶體Q3之源極接至該直流可調電源C，並透 過該電容C7接地，汲極接至該連接器80之+ 12V電源引 _ 腳，並透過該電容C8接地，該PMOS電晶體Q3之閘極透 〇 過該電阻R5接至該直流可調電源C。 該控制電路40用於控制該NMOS電晶體Ql、Q2及 該PMOS電晶體Q3之工作狀態，其包括電晶體ΤΙ、T2、 T3、T4及電阻Rl、R2、R3、R4，該電晶體T1之基極透 過電阻R1接至電源開機訊號端PS_ONJ，集極接至該電晶 體T2之基極，該電晶體T2之基極透過電阻R2接至該 5V—STBY產生電路50之輸出端，集極接至該電晶體T3 Q 之基極，該電晶體T3之基極透過電阻R3接至直流可調電 源C，集極接至該電晶體T4之基極。該電晶體T4之基極 透過電阻R4接至直流可調電源C，並分別連接該NMOS 電晶體Ql、Q2之閘極，該電晶體T4之集極與該PMOS 電晶體Q3之閘極相連，該電晶體ΤΙ、T2、T3、T4之射 極均接地。 請一併參閱圖4及圖6，該PWROK產生電路60包括 運算放大器U2、U3、電阻R6、R7、R8、R9、電容C9及 一二極體D1，該運算放大器U2之正相輸入端透過電阻 200931042 R6接至該5 V裕度測試電路20之輸出端，並透過該電容 C9接地，該運算放大器U2之反相輸入端透過電阻R7接 - 至該5V_STBY產生電路50之輸出端，並透過該電阻R8 • 接地，該運算放大器U2之輸出端透過電阻R9接至該連接 器80之+5V電源引腳，該運算放大器U3之正相輸入端接 至該運算放大器U2之反相輸入端，該運算放大器U3之反 相輸入端接至該連接器80之電源開機訊號引腳PS_ONJ， ^ 該運算放大器U3之輸出端與該二極體D1之負極相連，該 〇 二極體D1之正極接至該運算放大器U2之正相輸入端，該 運算放大器U2之輸出端作為該PWROK產生電路60之輸 出端，還接至該連接器80之PWROK電源引腳，該運算放 大器U2、U3之電源端均連接該連接器80之+5V電源引 腳，該運算放大器U2、U3之接地端均接地。 請一併參閱圖5及圖6,該-12V產生電路70包括一計 時器 U4、電阻 R10、Rll、R12、電容 CIO、Cll、C12、 ❹ C13及二極體D2、D3，該計時器U4優選555計時器，其 接地端GND接地，電源端VCC及重定端/R均接至該12V 裕度測試電路30之輸出端，為該-12V產生電路70提供一 12V工作電壓，該計時器U4之電源端VCC及重定端/R之 連接節點透過串聯連接之電阻RIO、R11及電容C10接地， 該計時器U4之控制端CO透過電容C11接地，放電端D 接至該電阻R10、R11之連接節點，觸發端/TR及閾值電 壓端TH均接至該電阻R11及電容C10之連接節點，輸出 端OUT透過該電容C12連接該二極體D2之陰極及二極體 200931042 D3之陽極，該二極體D3之陰極接地，二極體D2之陽極 透過該電阻R12接地，並透過該電容C13接地，該二極體 • D2之陽極作為該-12V產生電路70之輸出端連接至該連接 • 器80之-12V電源引腳，該二極體D2、D3為肖特基二極 體，其正負端壓降非常小，約為0.2V。 當利用該電壓裕度測試裝置對電腦主機板之電壓裕度 進行測試前，將該連接器80與該待測主機板之電源連接器 A相連，調節該直流可調電源A之輸出電壓為3.3V，調節該 〇 直流可調電源B之輸出電壓為5 V，並調節該直流可調電 源C之輸出電壓為12V，該直流可調電源C輸出12V電 壓，透過該電容C1之濾波、該三端穩壓器U1之穩壓，及 該電容C2之濾波後，產生電腦開機之必備電壓訊號，即 穩定之5V_STBY電壓訊號給電腦主機板。 按下該待測主機板之開機按鈕後，該連接器80之電源 開機訊號引腳PS_ONJ變為低電平，電晶體T1截止，電晶 ©體T2導通，電晶體T3截止，電晶體T3之集極為高電平， 進而該NMOS電晶體Q1及Q2均導通，使該直流可調電 源A、B分別與該連接器80上之+ 3.3V電源引腳及+5V電 源引腳電性相連，該電晶體T4之基極為高電平而導通， 該PMOS電晶體Q3導通，使該直流可調電源C與該連接 器80上之+ 12V電源引腳電性相連，此時，相當於該直流 可調電源A直接給待測主機板上之3.3V電源電路供電， 該直流可調電源B直接給待測主機板上之5V電源電路供 電，該直流可調電源C直接給待測主機板上之12V電源電 11 200931042 路供電。 當電壓裕度測試裝置之系統上電以後，由於電容C9 - 之起始電壓為0V，該運算放大器U2之正相輸入端之電壓 • 亦為0，而該5V_STBY產生電路50輸出之5V_STBY電 壓透過電阻R7及R8之分壓後，為該運算放大器U2之反 相輸入端提供一參考電壓，則此時該運算放大器U2之反 相輸入端之電壓大於其正相輸入端之電壓，因此該運算放 _ 大器U2之輸出端為低電平，隨著5 V裕度測試電路20輸 ❹ 出之5V電壓不斷的透過電阻R6為電容C9充電，當電容 C9上之電壓，即該運算放大器U2之正相輸入端之電壓大 於其反相輸入端之電壓時，該運算放大器U2之輸出端輸 出高電平，即該PWROK產生電路60輸出一高電平之 PWROK訊號至電腦主機板，該高電平PWROK訊號在該 3.3V、5V、12V裕度測試電路20、30、40輸出正常後才 輸出，其輸出具有一定之延時，以確保主電壓有足夠之穩 Q 定時間，透過調節電阻R6、電容C9之參數即可調節該 PWROK訊號輸出之延時時間。 該直流可調電源C提供之12V工作電壓透過電阻 R10、R11向該電容C10充電，當該電容C10上之電壓達 到12V工作電壓之三分之二，即8V時，該計時器U4内 部之觸發器被重定，該計時器U4輸出低電平脈波訊號， 其内部之放電電晶體導通，該計時器U4之觸發端連接其 放電電晶體之集極，該放電電晶體之射極接地，因此電容 C10透過電阻R11放電，當該電容C10上之電壓為12V工 12 0 200931042 、 一 炙—，即4V時，該計時器U4内部之觸發器 被置位’該计時器U4輪出電壓值為i2v之高電平脈波訊 號’該计時器U4内部之放電電晶體截止，12V工作電壓 又透過電阻RIO、！？！·！ i 丄 σ R11向該電容CIO充電，如此循環。當 省计時二U4輸出兩電平脈波訊號時，電容匚12連接運算 $大益V4之一端之電壓為12〜，另一端電壓為w，計時 益U4輸出之12V電壓給電容⑴充電，二極體D2反向 ❹ ❹ 截止’：極體D3導通’電容C12與二極體D3組成充電 回路θ該冲4器U4輸出脈波訊號跳變為低電平時，二Referring to FIG. 1, the voltage margin testing device of the present invention is used to test the voltage margin of a computer motherboard. The preferred embodiment includes a 3.3V margin test circuit 10, a 5V margin test circuit, and a 12V margin. Degree test circuit 30, a control circuit 40, a 5ν-STBY generating circuit 5, a pWR〇K 200931042 generating circuit 60, a -12V generating circuit 70, a connector 80 and an indicating circuit 90' 3.3V, 5V 12V margin test circuit 1〇, 20, 30 points • Do not test the 3.3V, 5V and 12V voltage margin of the motherboard to be tested, the 5V-STBY, PWROK, -12V generating circuits 50, 60 and 70 They are used to generate the 5V_STBY, PWROK and -12V voltage signals required by the motherboard to be tested. Referring to FIG. 2 and FIG. 6 together, the 5 V_STBY generating circuit 50 includes a three-terminal regulator U1 of the type 7805 and capacitors C1 and C2. In the embodiment, the three-terminal regulator U1 is one. The 7805 type three-terminal regulator with a fixed output of 5V has its ground terminal GND grounded, the input terminal VIN is connected to the constant current adjustable power supply C, and is grounded through the capacitor C1. The output terminal VOUT of the three-terminal regulator U1 serves as the The output of the 5V_STBY generating circuit 50 is connected to the +5 V_AUX power supply pin of the connector 80 and grounded through the capacitor C2. Please refer to FIG. 3 and FIG. 6 together. The 3.3V margin test circuit 1 includes a DC power supply A, a first control switch, and two capacitors C3 and C4. The first control switch is an N channel. M〇s type field effect transistor (nM0S transistor) Q1 'The drain of the NM0S transistor is connected to the DC adjustable power supply A' and grounded through the capacitor C3, and the source is connected to the connector 8〇+3.3 The V power supply pin is 'grounded' and grounded through the capacitor C4. The 5 V margin test circuit 2 includes a DC current adjustable power supply b, a second control switch, and two capacitors C5 and C6. The second control switch is an NMOS transistor Q2 'the NM〇s transistor q2 The pole is connected to the DC adjustable power supply b as the turn-in terminal of the margin test circuit 20, and is grounded through the power 200931042, and the source is used as the output end of the 5 V margin test circuit 20, and is connected to the connection. The +5V power supply pin of the device 80 is grounded through the capacitor C6. The 12V margin test circuit 30 includes a DC current adjustable power supply C, a third control switch, two capacitors C7, C8, and a resistor R5. The third control switch is a P-channel MOS type field effect transistor (PMOS). Crystal) Q3, the source of the PMOS transistor Q3 is connected to the DC adjustable power supply C, and is grounded through the capacitor C7, the drain is connected to the +12V power supply pin of the connector 80, and grounded through the capacitor C8 The gate of the PMOS transistor Q3 is connected to the DC adjustable power supply C through the resistor R5. The control circuit 40 is configured to control the working states of the NMOS transistors Q1, Q2 and the PMOS transistor Q3, and includes transistors ΤΙ, T2, T3, T4 and resistors R1, R2, R3, R4, and the transistor T1 The base is connected to the power-on signal terminal PS_ONJ through the resistor R1, and the collector is connected to the base of the transistor T2. The base of the transistor T2 is connected to the output terminal of the 5V-STBY generating circuit 50 through the resistor R2. The base of the transistor T3 is connected to the DC adjustable power supply C through the resistor R3, and the collector is connected to the base of the transistor T4. The base of the transistor T4 is connected to the DC adjustable power supply C through the resistor R4, and is respectively connected to the gates of the NMOS transistors Q1 and Q2. The collector of the transistor T4 is connected to the gate of the PMOS transistor Q3. The emitters of the transistors T, T2, T3, and T4 are all grounded. Referring to FIG. 4 and FIG. 6 together, the PWROK generating circuit 60 includes operational amplifiers U2 and U3, resistors R6, R7, R8, and R9, a capacitor C9, and a diode D1. The positive phase input terminal of the operational amplifier U2 is transmitted through The resistor 200931042 R6 is connected to the output terminal of the 5 V margin test circuit 20, and is grounded through the capacitor C9. The inverting input terminal of the operational amplifier U2 is connected to the output terminal of the 5V_STBY generating circuit 50 through the resistor R7. The resistor R8 is grounded, the output terminal of the operational amplifier U2 is connected to the +5V power supply pin of the connector 80 through the resistor R9, and the non-inverting input terminal of the operational amplifier U3 is connected to the inverting input terminal of the operational amplifier U2. The inverting input terminal of the operational amplifier U3 is connected to the power-on signal pin PS_ONJ of the connector 80, and the output terminal of the operational amplifier U3 is connected to the negative pole of the diode D1, and the anode of the diode diode D1 is connected. To the non-inverting input terminal of the operational amplifier U2, the output terminal of the operational amplifier U2 serves as the output end of the PWROK generating circuit 60, and is also connected to the PWROK power supply pin of the connector 80, and the power terminals of the operational amplifiers U2 and U3. Connected to Connector 80 of the + 5V power pin, the operational amplifier U2, U3 of the ground terminal are grounded. Referring to FIG. 5 and FIG. 6 together, the -12V generating circuit 70 includes a timer U4, resistors R10, R11, and R12, capacitors CIO, C11, C12, ❹ C13, and diodes D2 and D3. The timer U4 Preferably, the 555 timer has a ground terminal GND connected to the ground, and the power terminal VCC and the re-set terminal /R are both connected to the output end of the 12V margin test circuit 30 to provide a 12V operating voltage for the -12V generating circuit 70. The timer U4 The connection terminal of the power supply terminal VCC and the re-set terminal/R is grounded through the series connected resistors RIO, R11 and capacitor C10. The control terminal CO of the timer U4 is grounded through the capacitor C11, and the discharge terminal D is connected to the connection of the resistors R10 and R11. The node, the trigger terminal /TR and the threshold voltage terminal TH are connected to the connection node of the resistor R11 and the capacitor C10, and the output terminal OUT is connected to the cathode of the diode D2 and the anode of the diode 200931042 D3 through the capacitor C12. The cathode of the body D3 is grounded, the anode of the diode D2 is grounded through the resistor R12, and grounded through the capacitor C13, and the anode of the diode•D2 is connected to the connector of the output of the -12V generating circuit 70. 80 -12V power supply pin, the diode D2, D3 is Schott The base diode has a very small voltage drop at the positive and negative terminals of about 0.2V. Before using the voltage margin test device to test the voltage margin of the computer motherboard, the connector 80 is connected to the power connector A of the motherboard to be tested, and the output voltage of the DC adjustable power supply A is adjusted to 3.3. V, adjusting the output voltage of the 〇DC adjustable power supply B to 5 V, and adjusting the output voltage of the DC adjustable power supply C to 12V, the DC adjustable power supply C outputting 12V voltage, filtering through the capacitor C1, the third The voltage regulator of the terminal regulator U1, and the filtering of the capacitor C2, generate the necessary voltage signal for the computer to boot, that is, the stable 5V_STBY voltage signal is given to the computer motherboard. After pressing the power button of the motherboard to be tested, the power-on signal pin PS_ONJ of the connector 80 becomes a low level, the transistor T1 is turned off, the transistor T2 is turned on, the transistor T3 is turned off, and the transistor T3 is turned off. The set is extremely high, and the NMOS transistors Q1 and Q2 are both turned on, so that the DC adjustable power supplies A and B are electrically connected to the +3.3V power pin and the +5V power pin of the connector 80, respectively. The base of the transistor T4 is extremely high and turned on, and the PMOS transistor Q3 is turned on, so that the DC adjustable power supply C is electrically connected to the +12V power supply pin of the connector 80. At this time, it is equivalent to the DC. The adjustable power supply A directly supplies power to the 3.3V power supply circuit on the motherboard to be tested. The DC adjustable power supply B directly supplies power to the 5V power supply circuit on the motherboard to be tested. The DC adjustable power supply C is directly sent to the motherboard to be tested. 12V power supply 11 200931042 road power supply. After the system of the voltage margin test device is powered on, since the starting voltage of the capacitor C9 - is 0V, the voltage of the non-inverting input terminal of the operational amplifier U2 is also 0, and the 5V_STBY voltage of the output of the 5V_STBY generating circuit 50 is transmitted. After the voltages of the resistors R7 and R8 are divided, a reference voltage is supplied to the inverting input terminal of the operational amplifier U2, and then the voltage of the inverting input terminal of the operational amplifier U2 is greater than the voltage of the non-inverting input terminal, so the operation The output of the amplifier U2 is low, and the 5V voltage of the 5 V margin test circuit 20 is continuously charged through the resistor R6 to charge the capacitor C9. When the voltage on the capacitor C9 is the operational amplifier U2 When the voltage of the positive phase input terminal is greater than the voltage of the inverting input terminal, the output terminal of the operational amplifier U2 outputs a high level, that is, the PWROK generating circuit 60 outputs a high level PWROK signal to the computer motherboard, which is high. The level PWROK signal is output after the output of the 3.3V, 5V, 12V margin test circuits 20, 30, 40 is normal, and the output has a certain delay to ensure that the main voltage has a sufficient stable settling time, through the adjustment resistor R6 , The parameter of capacitor C9 can adjust the delay time of the PWROK signal output. The 12V working voltage provided by the DC adjustable power supply C is charged to the capacitor C10 through the resistors R10 and R11. When the voltage on the capacitor C10 reaches two-thirds of the working voltage of 12V, that is, 8V, the trigger inside the timer U4 The timer is reset, the timer U4 outputs a low-level pulse signal, and the internal discharge transistor is turned on. The trigger end of the timer U4 is connected to the collector of the discharge transistor, and the emitter of the discharge transistor is grounded, so the capacitor C10 is discharged through the resistor R11. When the voltage on the capacitor C10 is 12V, 12 0 200931042, one turn, that is, 4V, the trigger inside the timer U4 is set. The high-level pulse signal of i2v 'The discharge transistor inside the timer U4 is cut off, and the 12V working voltage is transmitted through the resistor RIO,! ? ! ·! i 丄 σ R11 charges the capacitor CIO, and so on. When the provincial time two U4 output two-level pulse wave signal, the capacitance 匚12 is connected to the operation. The voltage of one end of the big benefit V4 is 12~, the voltage of the other end is w, and the voltage of the 12V of the timing benefit U4 is charged to the capacitor (1). Polar body D2 reverse ❹ 截止 Cutoff ': Pole body D3 conduction' Capacitor C12 and diode D3 form a charging circuit θ. When the U4 output pulse signal jumps to a low level, the second
極體D3截止，該钟拉笼TT/I 灰冲時15 U4之輸出端相當於接地，則雷袞 ⑽接運算放大器U4之-端之電壓為0V，由於電容C12 兩端電壓不能突變，此時電容C12之電壓經電容C13、電 阻 R12，使二極體 τί 9 t i ,«· 正向導通’組成放電回路，使電容 =2連接一極體D2之—端之電壓約為謂，由於二極體 之電壓極小’二極體D2正極之電壓亦約為-12V，即該 心產生電路7G輸出—約·l2v之電壓至該待測主機板: 對二可調電源A、B'C之電壓調節開關， ^该3.3V裕度測試電路1Q來說，如果向下調竿一 電壓，如2.67V時，将、別±地4〔丄卞也 呆 ' 機板由正吊工作轉為不工作， 主機板3.3V電壓裕度之下限;如果向 轅二=莖如3.63¥時，待測主機板由正常工作 轉為不工作，那麼該點·為待測主機板33 上：，從而可得出之待測主機板3 Μ—分別調節該直流可調電源B及C之電壓；二 13 200931042 開關即可測試出待測主機板5V及12V電壓裕度，測試方 法與測試3.3V電壓裕度之方法相同，不再贅述。如果待測 • 主機板還有其他規格輸入電壓需要測試，可透過增加對應 . 規格輸入電壓之裕度測試電路即可實現，本實施方式僅以 3.3V、5V及12V三種規格之輸入電屋裕度之測試加以舉 例說明。 當電壓裕度測試裝置之系統斷電以後，該連接器80 _ 之電源開機訊號引腳PS ONJ變為高電平，電晶體T1導 ❹ 一 通，使該NMOS電晶體Ql、 Q2及該PMOS電晶體Q3 均截止，該直流可調電源A、B、C停止給待測主機板上之 3.3 V、5 V及12 V電源電路供電。因該電源開機訊號引腳 PS—ONJ為高電平，其電平值為5V，該運算放大器U3之 反相輸入端之電壓大於其正相輸入端之電壓，該運算放大 器U3之輸出端輸出低電平，二極體D1導通，電容C9透 過二極體D1快速放電，使該運算放大器U2之正相輸入端 φ 之電壓快速降低，小於該運算放大器U2之反相輸入端之The pole body D3 is cut off, and the output of the terminal 15 U4 is equivalent to the ground when the TT/I is rushed. The voltage of the Thunder (10) connected to the terminal of the operational amplifier U4 is 0V. Since the voltage across the capacitor C12 cannot be changed, this When the voltage of the capacitor C12 passes through the capacitor C13 and the resistor R12, the diode τί 9 ti , «· forward conduction constitutes a discharge loop, so that the voltage of the capacitor = 2 is connected to the end of the pole D2 is about The voltage of the polar body is extremely small. The voltage of the positive electrode of the diode D2 is also about -12V, that is, the output of the core generating circuit 7G is about - the voltage of about l2v to the motherboard to be tested: the two adjustable power supplies A, B'C Voltage adjustment switch, ^ The 3.3V margin test circuit 1Q, if the voltage is down-regulated, such as 2.67V, it will be turned on, and the board will be changed from positive to no. , the lower limit of the 3.3V voltage margin of the motherboard; if the motherboard to be tested is changed from normal operation to inoperative when the second = stem is 3.63, then the point is on the motherboard 33 to be tested: The motherboard to be tested is 3 Μ—the voltage of the DC adjustable power supply B and C is adjusted separately; 2 13 200931042 The switch can be tested 5V and 12V motherboard test voltage margin, the same method of testing method of testing the voltage margin 3.3V, is omitted. If the test board has other specifications, the input voltage needs to be tested, and it can be realized by adding the corresponding standard input voltage margin test circuit. In this embodiment, only the input specifications of 3.3V, 5V and 12V are available. The test of degree is given as an example. After the system of the voltage margin test device is powered off, the power-on signal pin PS ONJ of the connector 80 _ is turned to a high level, and the transistor T1 is turned on, so that the NMOS transistors Q1, Q2 and the PMOS are electrically connected. The crystal Q3 is turned off, and the DC adjustable power supplies A, B, and C stop supplying power to the 3.3 V, 5 V, and 12 V power supply circuits on the motherboard to be tested. Because the power-on signal pin PS_ONJ is at a high level, its level value is 5V, the voltage of the inverting input terminal of the operational amplifier U3 is greater than the voltage of the non-inverting input terminal thereof, and the output of the operational amplifier U3 is output. Low level, the diode D1 is turned on, and the capacitor C9 is rapidly discharged through the diode D1, so that the voltage of the positive phase input terminal φ of the operational amplifier U2 is rapidly lowered, which is smaller than the inverting input terminal of the operational amplifier U2.
電壓，該運算放大器U2之輸出端輸出低電平，從而PWROK 訊號從高電平快速變為低電平；由於該12V裕度測試電路 30無電壓輸出，該-12V產生電路70無工作電壓，無法產 生-12V電壓給該待測主機板。Voltage, the output of the operational amplifier U2 outputs a low level, so that the PWROK signal rapidly changes from a high level to a low level; since the 12V margin test circuit 30 has no voltage output, the -12V generating circuit 70 has no operating voltage. Unable to generate -12V voltage to the board to be tested.
該指示電路90用於檢測該3.3V裕度測試電路10、5V 裕度測試電路20、12V裕度測試電路30、控制電路40、 5V_STBY產生電路50、PWROK產生電路60，-12V產生 電路70是否有輸入、輸出電壓，在該3.3V裕度測試電路 14 200931042 w裕度賴電路2G、12V裕度賴 路40、5V_STBY產生電路5〇、_〇κ產 = 入、輸出端分職-電阻之—端，其中每—電=== 接一發光二極體之陽極，每— =之另—端 ❹ ❹ ^體=極透過另一電阻接至該心產生電路％之輸 ％極接地，若上述各電路之輸入、輸出 ^吊，職叙發光二㈣發光，若上㈣ = :;輸:端之電壓不正常，則對應之發光二極 里^電路方便在測試待測主機板電壓之裕度過程中出現 八吊時，及時查找原因。 提二Π ’本發明確已符合發明專利之要件，差依法 ，出，利申I惟，以上所述者僅為本發明之較佳實施方 i枯蔽發明之範圍並不以上述實施方式為限，舉凡熟悉本 :、β之人士，在爰依本發明之精神所作之等效修飾或變 匕，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1係本發明電壓裕度測試裝置較佳實施方式之電路 模組圖。 5V及12V裕度測試電路及控制 圖2係圖1中3.3V、 電路之電路圖。 圖3係圖i中5V_STBY產生電路之電路圖。 圖4係圖χ中PWR〇K產生電路之電路圖。 圖4係圖χ中12v產生電路之電路圖。 圖6係圖1中連接器之電路圖。 15 200931042The indicating circuit 90 is configured to detect whether the 3.3V margin test circuit 10, the 5V margin test circuit 20, the 12V margin test circuit 30, the control circuit 40, the 5V_STBY generating circuit 50, the PWROK generating circuit 60, and the -12V generating circuit 70 are There are input and output voltages, in the 3.3V margin test circuit 14 200931042 w 度 赖 赖 2G, 12V 裕 赖 40 40, 5V_STBY generating circuit 5 〇, _ 〇 产 production = input and output split-resistance —End, where each—electricity=== is connected to the anode of a light-emitting diode, and each of the other ends of the light-emitting diode is connected to the core of the core generating circuit by the other resistor. The input and output of each of the above circuits are hoisted, and the illuminating two (four) illuminating, if the upper (four) = :; input: the voltage of the terminal is not normal, then the corresponding illuminating diode is convenient to test the voltage of the motherboard to be tested. When there are eight cranes in the process, find the cause in time.提二Π 'The invention has indeed met the requirements of the invention patent, the difference is according to the law, the out, Li Shen I, the above is only the preferred embodiment of the invention i is not covered by the above embodiment The equivalent modifications or variations made by those who are familiar with this:, β, in the spirit of the present invention should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit block diagram of a preferred embodiment of a voltage margin test apparatus of the present invention. 5V and 12V margin test circuit and control Figure 2 is a circuit diagram of 3.3V, circuit in Figure 1. Figure 3 is a circuit diagram of the 5V_STBY generation circuit in Figure i. Figure 4 is a circuit diagram of the PWR〇K generating circuit in Figure 。. Figure 4 is a circuit diagram of the 12v generating circuit in Figure 。. Figure 6 is a circuit diagram of the connector of Figure 1. 15 200931042
【主要元件符號說明】 3.3V裕度測試電路 10 直流可調電源 5 V裕度測試電路 20 三端穩壓器 12V裕度測試電路 30 運算放大器 控制電路 40 計時器 5V_STBY產生電路 50 NMOS電晶體 PWROK產生電路 60 PMOS電晶體 -12V產生電路 70 電晶體 連接器 80 二極體 指不電路 90 電阻 電源開機訊號端 PS ONJ電容 A、B、C U1 U2、U3 U4[Main component symbol description] 3.3V margin test circuit 10 DC adjustable power supply 5 V margin test circuit 20 Three-terminal regulator 12V margin test circuit 30 Operational amplifier control circuit 40 Timer 5V_STBY generation circuit 50 NMOS transistor PWROK Generation circuit 60 PMOS transistor-12V generation circuit 70 transistor connector 80 diode finger circuit 90 resistance power supply signal terminal PS ONJ capacitor A, B, C U1 U2, U3 U4
Ql、Q2 Q3 T1-T4 D1 〜D3 R1〜R12 C1-C13Ql, Q2 Q3 T1-T4 D1 ~ D3 R1 ~ R12 C1-C13
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