200926386 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於封裝晶片之承載帶及晶片封褒結構；特 別是一種具有共用測試墊區之承載帶及晶片封裝結構。 【先前技術】 隨著工業的進步，各種液晶螢幕、具折疊功能之電子產品已被 廣泛使用於曰常生活中。其中，由於可撓性電路板具有厚度薄、 ❹引腳間距小、且腳數高等優點，當液晶螢幕為了節省空間，或是 電子產品為了達到折疊之魏時，可撓性電路板便成為不可或缺 的元件。 般而。，可撓性電路板係利用晶片封裝技術，將半導體晶片 接合於其上。其中，捲帶自動接合封裝（TapeAut。刪ieB〇IJng, ❿ AB)技術係將日日片固定於承載帶上，並以晶片的凸塊或鲜塾， 與承載帶的金屬引線層對位加壓接合，為目前最常見的晶片封裝 技術之-。其又可分成捲帶承載封裝〜心心㈣喂τ 及薄膜覆晶封裝⑽ip_0n.Film，c〇F)二種封裝型式。， 包人二Co為習知之晶片封裝結構1之示意圖，晶片封裝結構1 3，承載:承«1G具有複數定位孔⑴複數測試塾⑶、 131 、第一引腳部分141及筮_?|、 ⑴係沿-輸送方向X，分佈^刀142。其中，複數定位孔 承載帶H)，或用以定位承栽帶1〇载帶1〇之二側邊’用以輸送該 承載㈣上或連結—電性測：之位置，以便將晶片21接合至 為知楚 裝置（圖未不）進行電性測試。 便說明，如弟1圖所示，在承载帶H)上定義-封裝區域121 200926386 以及分別位於封裝區域121二側之二測試墊區i3、i3，，其中封 裝區域m係設置於承载帶10二侧邊之定㈣⑴之間，並沿輸 达方向X分佈，晶片21係設置於封裝區域i2i内，而測試墊⑶、 131’係分別設置於第一測試塾區13及第二測試墊區13，上。而第 引腳4刀141自封裝區域121延伸至第一測試塾區^與測試塾 ⑶電性連結，而第二引腳部分142自封裝區域i2i延伸至第二測 试墊區13’與測試墊131，電性連結。 幹==係;接合於承栽帶10之封裝區域121’並以輸入端與 ==與第，部分⑷及第二引腳部分142 !^、'、口 ’該晶片封裝結構1。如此一來，晶片之輸入 電性連結至第-測：= 部：141及第二_分142 測試塾⑶，。完成封裝晶片21 131及第二測試墊區13,之 一 、日日 於承載帶〗〇之封裝區域121令後， ===探針同時電性連結測試…測試塾 更了對曰曰片21進行電性測試。 由:二圖可以清楚看出，習知的晶片封裝結構^ 131係分別配置於各晶 · ^ 第-測試塾區13及第二測^。^片21之電性職完成後， 區域⑵上的晶片2卜 °° 13皆需裁切錯，僅留下封裝 可想見地，若第分141及第二引腳部分142。 愈大，裁切去除的部分愈多，3此^^_13,所使用之區域 此外，之…_ i，於費： 將電性_置之探針’順序，地對測試塾⑶及:：】： 200926386 =電性連接之動作，此電性測試需要將探針反覆 化費大量製程時間，使得生產㈣效率不佳。 導致 晶=構提供一種可減少裁切量及提升測試效率之承載帶及 … 料此一業界丞待解決的問題。 【發明内容】 ❻ ❹ 二之:目的在於提供一種用於封裝晶片之承載帶及晶片封 :二=之二晶片封裝結構可共用一測試塾區，以減少測試 除= Γ面積比例。由於測試塾區最終將被裁切去 f χ明之承載帶及晶片封裝結構於測試完成後進行裁切時， :降低因為裁切測試塾區所導致承載帶之浪費,進而二 2發月之另—目的在於提供—種用於封裝晶片之承載帶及晶片 2構’由於相鄰之m«結構可_制之測試墊區盘 一電性娜試裝置電性遠技 片進行電性測試，至少可減試裝置可同時或單獨對二晶 率。料進而即令電性測試之作業時間，提升生產檢測效 域、二封’二::月所提供之承載帶至少包含有二傳輸區 等傳輸區域分別定義H區、複數測試塾及一金屬線路層。該 佈;該二=該等傳輸區域之間，沿該輸送方向分 於其上；該金又2Γ等封裝區域之間’供該等測試塾設置 、屬線路層係分佈於料封裝區域上。其t，該等封 200926386 裝區域包含-第m域及—第二縣輯，㈣金 2少包含-自該第-封裝區域延伸至該測試墊區之第 ^、以及-自該第二封裝區域延伸至該測試塾區之第二。 为。其特徵為該第1㈣分與該第二㈣部分 塾 區内’對應連接共同之料職墊。 哀轉 本發明更提供一種晶片封梦έ士播 更包含一第一曰，及Γ 使用上述之承載帶，且 ❹ ❷ 帛S曰片及一第二晶片’分別設置於該承載帶上之令第 區域及該第二封裝區域，該第_晶片與該第1腳部^電 1接’而該第二晶片與該第二引腳部分電性連接。藉此， ^片及該第二晶片透過該第—引腳部分及該第二引聊部分同 1 連結《應之該等測試塾，進而使該第—晶片與該第二晶片夺 由0亥等測試墊，_連接至電性測試裝置，進行電性測試。曰 下 為讓本發明之上述目的、技術特徵、和優點能更明顯易懂 文係以較佳實施例配合所附圖式進行詳細說明。 . 【實施方式】 本發明之一實施例揭露一種用於封裝晶片之承載帶3,適可，儿 輸送方向X延伸，如第2圖所示，承載帶3至少包二 域31、二封裝區域321及322、—測試塾區33、設置 輪區 33上之複數測試墊331及—金屬線路層。 、“忒墊區 於本實施财，承載帶3之二傳魅域31，分較義於 3之-側邊且沿輸送方向X延伸，更明確而古 载▼ 成有沿該輸送方向X順序配置，且鄰設料“域31上形 數定位孔311。承載帶3係藉由定位孔311進行傳輸^邊2 8 200926386 當承載帶3定位至一位置時，適可以進行晶片封裝，而之後定位 於另一位置進行裁切。 為方便說明，封裝區域321及322可區分為第一封裝區域321 及第二封裝區域322,定義於於二傳輸區域31之間。須說明的是， 承載帶3上的複數封裝區域係延輸送方向X順序分佈，本實施例 僅針對其中二相鄰之封裝區域作為例示，非用以限定本發明。其 中，第一封裝區域321及第二封裝區域322各包含一晶片接合區 321a及322a，用以供晶片設置。 不同於先前技術中測試墊區係單獨對應於封裝區域，故相鄰之 二封裝區域之間必定存在有二測試塾區1本實施例之第一封裝區 域321及第二封裝區域322之間僅設置有一共用之測試墊區33。 由於設置於承載帶3上之各測試墊區33，於晶片封裝於各晶片接 合區321a及322a並進行完封裝測試後，皆須裁切去除，故本實 施例採用共用之測試墊區33,可大幅降低測試墊區33之數目及面 積，可顯著降低封裝承載帶不必要之浪費，進而降低封裝成本。 φ 此外，金屬線路層係分佈於第一封裝區域321及第二封裝區域 322上，並且延伸至測試墊區33中，為方便說明，金屬線路層可 定義包含第一引腳部分34卜第二引腳部分342、第三引腳部分343 及第四引腳部分344。於本實施例中，第一引腳部分341係自第一 封裝區域321延伸至測試墊區33中，而第二引腳部分342係自第 二封裝區域322延伸至測試墊區33中，且第一引腳部分341與第 二引腳部分342，於該測試墊區33内，分別連接對應之測試墊 331。藉此，第一封裝區域321及第二封裝區域322之間僅需使用 200926386 一共用之測試墊區33，便可供後續之電性測試。 較佳地’於本發明之第一引腳部分341與第二引腳部分342係 具有相同數量之引腳，因此第一引腳部分341之各引腳與第二引 腳部分342之各引腳恰可分別連接至對應之測試墊331，更方便於 電性測試之進行。 此外’第三引腳部分343係相對於第一引腳部分341，設置於第 一封裝區域321中之晶片接合區321a之另一侧，並自第一封裝區 φ 域321延伸至另一與其他封裝區域（圖未示）共用之測試墊區； 而第四引腳部分344係相對於第二引腳部分342設置於第二封裝 區域322中之晶片接合區322a之另一側，並自第二封裝區域322 延伸至另一與其他封裝區域（圖未示）共用之測試墊區。 而為與晶片接合及連接測試墊331，第一引腳部分341包含一第 一内引腳341a及一第一外引腳341b，第二引腳部分342包含一第 二内引腳342a及一第二外引腳342b。第一内引腳341a與第二内 引腳342a係分別延伸於晶片接合區321a及322a内，用以分別與 ® 晶片之凸塊進行接合。而第一外引腳341b與第二外引腳342b係 * Λ 分別自第一封裝區域321及第二封裝區域322延伸至測試墊區33 内’並電性連接於對應之測試墊33卜封裝於各封裝區域321、322 中之各晶片’便藉由各晶片之複數凸塊電性連結該内引腳341a及 342a ’並透過外引腳341b、342b電性連結測試墊區33中之測試 墊331 ’以便後續透過測試墊331進行電性測試。同樣地，前述之 第三引腳部分343及第四引腳部分344亦分別包含内、外引腳， 在此不另賛述。 200926386 請參考第3圖，所示為本發明之第二實施例所揭露之晶片封裝 結構4之示意圖，此晶片封裝結構4包含如上所述之承載帶]，^ 更將第一晶片41及第二晶片42接合於承載帶3上。第一晶片y 及第二晶片42係分別設置於承載帶3上之第一封裝區域切及第 二封裝區域322中之晶片接合區321a、322a (如第2圖中所示）。 第一引腳部分341包含第一内引腳341a及第一外引腳34^，第二 引腳部分342包含第二内引腳342a及第二外引腳鳩，第一㈣ ❹腳341a與第二内引腳342a係分別於晶片接合區32u、322a内， 分別與第-晶片41及第二晶片42之凸塊電性連接第一外引聊 34lb與第二外引腳3.則分別自第一封裝區域321及第二封裝區 域322延伸至測試墊區33内，並電性連接至對應之測試塾如。 承載帶3之其他詳細結構如同上述之承載帶3之結構，在此不贊 ❹ 測試塾區33上之測試塾33卜於第—晶片41及第二晶片C 別接合至第-封裝區域321及第二封裝區域322完成封裝後， 外接-電性測試裝置（圖.未示），以對第—晶片4】及第二晶片 進仃-電性測試。而因第—引聊部分341與第二引腳部分如 ^相同之測試墊331，因此對封裝於第—封裝區域321及第二 、匚域322 t之不同晶片進行電性測試時，僅需進行一次測試: 電!·生連接至電性測試裝置之動作’故可節省電性測試之作業E 間，使生產效率顯著提升。 言，第—引腳部分341係透過第—内引腳地連接於; 之—輸人端，而第二引腳部分342係透過第二内引* 200926386 342a連接於第二晶片42之一輸入端，承載帶之第三引腳部分343 及第四引腳部分344則分別連接於第一晶片41之一輸出端及第二 晶片42之一輸出端。如此一來，測試墊331將可同時與第一晶片 41及第二晶片42之輸入端電性連接。當電性測試裝置之探針（圖 未示）與測試墊331電性連接，便可同時或分別地透過第一引腳 部分341與第二引腳部分342，對第一晶片41及第二晶片42，進 行一電性測試。較佳地，第一引腳部分341與第二引腳部分342 可具有相同數量之引腳，並且連結於與第一引腳部分341或第二 引腳部分342相同數量之測試墊331，電性測試裝置僅需進行一次 對測試墊331電性連結之動作，便可以同時或分別測試第一晶片 41及第二晶片42，電性測試裝置不需頻繁地執行插拔動作。 或者，第一引腳部分341係可連接於第一晶片41之輸出端，而 第二引腳部分342係可連接於第二晶片42之輸出端，而第三引腳 部分343連接於第一晶片41之輸入端，第四引腳部分344連接於 第二晶片42之輸入端。如此一來，測試墊331將可同時與第一晶 ❹ f 41及第二晶片42之輸出端電性連接，其他的結構則與前述實 施態樣相同，在此不贅述。 於本發明之上述實施例中，第一晶片41與第二晶片42實質上 可為相同之晶片，或者為不同之晶片，皆可實施本發明之概念。 僅需設計將第一引腳部分341及第二引腳部分342延伸至共用之 測試墊區33，並同時連接相對應之測試墊331。舉例而言，若第 一晶片41與第二晶片42為相同之二晶片，則僅需將相同之此二 晶片對稱設置於承載帶3上，晶片相互相鄰之一側便可具有相同 12 200926386 之數量之輸人端或輸出端’因此可以輕易地使用相同弓丨腳數量之 第-引腳部分341及第二引腳部分342，同時電性連結於相同 之測試墊3M。但若第—晶片41不同於第二晶^，亦可透則 腳及測試狄設計，同樣可達財發日歧料^賴墊區之目 的。 ❹ 藉由上述之承載帶3之結構，承載帶3可節省先前技術中相鄰 的封裝區域間需設置二測試塾區所佔用之承載帶面積，使承載帶3 於電性測試後，需要裁切去除之部分減少，可更充分地利用承载 帶’進而節省材料成本。而與晶片接合後，本發明之晶片封裝結 構4可透過共用之測試塾區33連結電性測試裝置，進而分別或同 時進行電性職，電性測試裝置較不需執行頻繁的插拔動作，更 可以節省電性測試之作業時間，顯著加速生產效率，降低生產成 本。 上述之實施例僅用來例舉本發明之實施態樣，以及闊釋本發明 :技術龍’並判來限制本發明之保護料。任何熟悉此技術 了輕易几成之改變或均等性之安排均屬於本發明所主張之範 圍’本發明之權利保護範圍應以申請專利範圍為準。 【圖式簡單說明】 第1圖係習知晶片封裝結構之示意圖； 第2圖係本發明承載帶之示意圖；以及 第3圖係本發明晶片《結構之示意圖。 【主要元件符號說明】 13 200926386BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier tape and a wafer package structure for packaging a wafer; in particular, a carrier tape having a shared test pad region and a chip package structure. [Prior Art] With the advancement of the industry, various liquid crystal screens and electronic products with folding functions have been widely used in ordinary life. Among them, since the flexible circuit board has the advantages of thin thickness, small pin pitch, and high number of feet, when the liquid crystal screen is used to save space, or the electronic product is in order to achieve the folding, the flexible circuit board becomes impossible. Or missing components. As usual. The flexible circuit board is bonded to the semiconductor wafer by wafer packaging technology. Among them, the tape automatic bonding package (TapeAut. IEB〇IJng, ❿ AB) technology system is fixed on the carrier tape, and the bumps or fresh enamel of the wafer are aligned with the metal wire layer of the carrier tape. Pressure bonding is the most common wafer packaging technology available today. It can be divided into two types of package: tape carrier package ~ core (four) feed τ and film flip chip package (10) ip_0n.Film, c〇F). , Bao Ren 2 Co is a schematic diagram of a conventional chip package structure 1 , a chip package structure 13 , carrying: a «1G has a plurality of positioning holes (1) a plurality of tests 塾 (3), 131, a first pin portion 141 and 筮 _? | (1) The knives 142 are distributed along the - conveying direction X. Wherein, the plurality of positioning holes carry the tape H), or the two sides of the carrier tape 1 定位 carrier tape 1 ′ are used to transport the bearing (4) or the connection-electrical measurement position to bond the wafer 21 Conduct electrical tests for the device (not shown). It is to be noted that, as shown in FIG. 1 , a package region 121 200926386 and two test pad regions i3 and i3 respectively located on two sides of the package region 121 are defined on the carrier tape H), wherein the package region m is disposed on the carrier tape 10 The two sides are defined between (4) and (1) and distributed along the direction of the transmission X. The wafer 21 is disposed in the package area i2i, and the test pads (3) and 131' are respectively disposed in the first test area 13 and the second test pad area. 13, on. The first pin 4 141 extends from the package region 121 to the first test region and is electrically connected to the test port (3), and the second pin portion 142 extends from the package region i2i to the second test pad region 13' and the test. Pad 131 is electrically connected. The die package structure 1 is bonded to the package region 121' of the carrier tape 10 and has an input terminal and a =, a portion, a portion (4) and a second pin portion 142, ^, ', and a port. In this way, the input of the chip is electrically connected to the first measurement: = part: 141 and the second_minute 142 test 塾 (3). After the packaged wafer 21 131 and the second test pad area 13 are completed, one of them is placed on the package area 121 of the carrier tape, and the === probe is simultaneously electrically connected to the test. Conduct an electrical test. It can be clearly seen from the two figures that the conventional chip package structure 131 is disposed in each of the crystals, the first test cell 13 and the second test. After the electrical job of the film 21 is completed, the wafer 2 on the region (2) needs to be cut, leaving only the package, conceivably, if the first portion 141 and the second pin portion 142. The larger the cut, the more parts are removed, 3 ^^_13, the area used, in addition, ..._ i, Yu Fei: The electric probe _ the probe 'sequence, the ground test 塾 (3) and :: 】: 200926386 = electrical connection action, this electrical test needs to repetitively probe the probe for a large amount of process time, making production (four) inefficient. This has led to the development of a carrier tape that can reduce the amount of cutting and improve the efficiency of testing, and this is an urgent problem to be solved in the industry. SUMMARY OF THE INVENTION [Abstract] The purpose of the present invention is to provide a carrier tape and a wafer package for packaging wafers. The two = two chip package structures can share a test area to reduce the test area ratio. Since the test area will eventually be cut to the carrier tape and the chip package structure is cut after the test is completed: reduce the waste of the carrier tape caused by the cutting test area, and then another two or two months - the purpose is to provide a carrier tape for the package of the wafer and the structure of the wafer 2" due to the adjacent m « structure of the test pad area disk - an electrical test device electrical telephoto film for electrical testing, at least The de-testing device can simultaneously or separately control the crystallinity. In turn, the operation time of the electrical test is increased, and the production inspection efficiency is improved. The carrier tape provided by the second package: the second transmission zone includes at least two transmission zones, respectively, defining an H zone, a plurality of test ports, and a metal circuit layer. . The cloth is divided between the transmission areas and the transport direction; the gold is placed between the package areas for the test 塾, and the genus line layer is distributed on the material package area. The t, the 200926386 loading area includes - the mth domain and the second county series, and (4) the gold 2 contains - from the first - package area to the first and the second of the test pad area The area extends to the second of the test area. for. It is characterized in that the first (four) point and the second (four) part of the area are correspondingly connected to each other. The invention further provides a wafer sealer, the babysitter, and a first one, and the use of the above-mentioned carrier tape, and the ❹ 帛 曰 曰 and a second wafer ′ are respectively disposed on the carrier tape In the first region and the second package region, the first wafer is electrically connected to the first leg portion and the second wafer is electrically connected to the second pin portion. Thereby, the ^ chip and the second chip are connected to the first pin portion and the second chat portion by the same test piece, so that the first chip and the second chip are captured by 0 Wait for the test pad, _ connected to the electrical test device for electrical testing. The above objects, technical features, and advantages of the present invention will become more apparent from the following description. [Embodiment] An embodiment of the present invention discloses a carrier tape 3 for packaging a wafer, which is suitable for extending in a transport direction X. As shown in FIG. 2, the carrier tape 3 includes at least two domains 31 and two package regions. 321 and 322, a test area 33, a plurality of test pads 331 on the wheel area 33, and a metal circuit layer. "The pad area is in this implementation, the carrying band 3 is transmitted to the enchantment field 31, which is divided into 3 sides - and extends along the conveying direction X, more clearly and the ancient load ▼ has a sequence along the conveying direction X Configured, and adjacent to the material "domain 31 on the number of positioning holes 311. The carrier tape 3 is transported by the positioning hole 311. When the carrier tape 3 is positioned to a position, the chip package can be performed and then positioned at another position for cutting. For convenience of description, the package areas 321 and 322 can be divided into a first package area 321 and a second package area 322, which are defined between the two transmission areas 31. It should be noted that the plurality of package regions on the carrier tape 3 are sequentially distributed in the transport direction X. This embodiment is only for the purpose of exemplifying two adjacent package regions, and is not intended to limit the present invention. The first package region 321 and the second package region 322 each include a die bond region 321a and 322a for the wafer to be disposed. Different from the prior art, the test pad area separately corresponds to the package area, so there must be two test areas between the adjacent two package areas. Only the first package area 321 and the second package area 322 of the embodiment are only between A shared test pad area 33 is provided. Since the test pad regions 33 are disposed on the carrier tape 3, after the wafers are packaged in the die bonding regions 321a and 322a and after the package test is performed, the chips are cut and removed. Therefore, the shared test pad region 33 is used in this embodiment. The number and area of the test pad areas 33 can be greatly reduced, and the unnecessary waste of the package carrier tape can be significantly reduced, thereby reducing the packaging cost. In addition, the metal circuit layer is distributed on the first package region 321 and the second package region 322 and extends into the test pad region 33. For convenience of description, the metal circuit layer may be defined to include the first pin portion 34 and the second portion. A pin portion 342, a third pin portion 343, and a fourth pin portion 344. In the present embodiment, the first lead portion 341 extends from the first package region 321 into the test pad region 33, and the second pin portion 342 extends from the second package region 322 into the test pad region 33, and The first pin portion 341 and the second pin portion 342 are respectively connected to the corresponding test pads 331 in the test pad region 33. Therefore, only the test pad area 33 shared by 200926386 needs to be used between the first package area 321 and the second package area 322 for subsequent electrical testing. Preferably, the first pin portion 341 and the second pin portion 342 of the present invention have the same number of pins, so each pin of the first pin portion 341 and the second pin portion 342 are referenced. The feet can be respectively connected to the corresponding test pads 331, which is more convenient for the electrical test. Further, the 'third lead portion 343 is disposed on the other side of the wafer bonding region 321a in the first package region 321 with respect to the first lead portion 341, and extends from the first package region φ field 321 to another a test pad region shared by other package regions (not shown); and a fourth pin portion 344 is disposed on the other side of the die bond region 322a in the second package region 322 with respect to the second pin portion 342, and The second package area 322 extends to another test pad area that is shared with other package areas (not shown). The first pin portion 341 includes a first inner lead 341a and a first outer lead 341b, and the second lead portion 342 includes a second inner lead 342a and a first die portion 341b. The second outer lead 342b. The first inner lead 341a and the second inner lead 342a extend in the die bond regions 321a and 322a, respectively, for engaging the bumps of the ® wafer. The first outer lead 341b and the second outer lead 342b are respectively extended from the first package area 321 and the second package area 322 into the test pad area 33 and electrically connected to the corresponding test pad 33. Each of the wafers in each of the package regions 321 and 322 is electrically connected to the inner leads 341a and 342a' by a plurality of bumps of the respective wafers and electrically connected to the test pad region 33 through the outer leads 341b and 342b. Pad 331' for subsequent electrical testing through test pad 331. Similarly, the third pin portion 343 and the fourth pin portion 344 also include inner and outer pins, respectively, which are not separately described herein. 200926386 Please refer to FIG. 3, which is a schematic diagram of a wafer package structure 4 according to a second embodiment of the present invention. The chip package structure 4 includes the carrier tape as described above, and the first wafer 41 and the The two wafers 42 are bonded to the carrier tape 3. The first wafer y and the second wafer 42 are respectively disposed on the carrier tape 3 and the first package region is cut into the die bond regions 321a, 322a in the second package region 322 (as shown in Fig. 2). The first pin portion 341 includes a first inner pin 341a and a first outer pin 34^, and the second pin portion 342 includes a second inner pin 342a and a second outer pin 鸠, the first (four) leg 341a and The second inner leads 342a are respectively disposed in the die bond regions 32u and 322a, and are electrically connected to the bumps of the first wafer 41 and the second wafer 42 respectively. The first external chat 34lb and the second outer pin 3. respectively The first package area 321 and the second package area 322 extend from the test pad area 33 and are electrically connected to corresponding test items. The other detailed structure of the carrier tape 3 is similar to the structure of the carrier tape 3 described above. It is not appreciated that the test 塾 33 on the test pad 33 is bonded to the first package region 321 and the first wafer 41 and the second wafer C. After the second package region 322 is packaged, an external-electrical test device (not shown) is used to test the first wafer 4 and the second wafer. Because the first-the chat portion 341 and the second lead portion are the same test pad 331, when the electrical test is performed on different wafers packaged in the first package region 321 and the second and second regions 322 t, only Carry out a test: electricity! · Health connection to the electrical test device's operation, so it can save the electrical test work E, so that the production efficiency is significantly improved. In other words, the first-pin portion 341 is connected to the input terminal through the first inner lead, and the second lead portion 342 is connected to the input of the second wafer 42 through the second inner lead *200926386 342a. The third pin portion 343 and the fourth pin portion 344 of the carrier tape are respectively connected to one output end of the first wafer 41 and one output end of the second wafer 42. In this way, the test pad 331 can be electrically connected to the input ends of the first wafer 41 and the second wafer 42 at the same time. When the probe (not shown) of the electrical test device is electrically connected to the test pad 331, the first lead portion 341 and the second lead portion 342 can be simultaneously or separately transmitted to the first wafer 41 and the second chip. The wafer 42 is subjected to an electrical test. Preferably, the first pin portion 341 and the second pin portion 342 may have the same number of pins and are connected to the same number of test pads 331 as the first pin portion 341 or the second pin portion 342, The sex testing device only needs to perform the action of electrically connecting the test pads 331 once, so that the first wafer 41 and the second wafer 42 can be tested simultaneously or separately, and the electrical testing device does not need to perform the insertion and removal operations frequently. Alternatively, the first lead portion 341 can be connected to the output end of the first wafer 41, and the second lead portion 342 can be connected to the output end of the second wafer 42, and the third lead portion 343 is connected to the first At the input end of the wafer 41, the fourth pin portion 344 is connected to the input end of the second wafer 42. As a result, the test pads 331 can be electrically connected to the output ends of the first wafer f 41 and the second wafer 42 at the same time. Other structures are the same as the foregoing embodiments, and are not described herein. In the above embodiments of the present invention, the first wafer 41 and the second wafer 42 may be substantially the same wafer, or different wafers, and the concept of the present invention may be implemented. It is only necessary to design the first lead portion 341 and the second lead portion 342 to extend to the shared test pad region 33, and simultaneously connect the corresponding test pads 331. For example, if the first wafer 41 and the second wafer 42 are the same two wafers, only the same two wafers need to be symmetrically disposed on the carrier tape 3, and one side of the wafer adjacent to each other can have the same 12 200926386 The number of input terminals or outputs ' can therefore easily use the same number of pin-pin portions 341 and second pin portions 342, while being electrically connected to the same test pad 3M. However, if the first wafer 41 is different from the second crystal, it can also pass through the foot and test the Di design, and it can also reach the purpose of the diverging area of the financial day.承载 With the structure of the above-mentioned carrier tape 3, the carrier tape 3 can save the area of the carrier tape occupied by the two test zones between adjacent package areas in the prior art, and the carrier tape 3 needs to be cut after the electrical test. The reduction of the part of the cut is made, and the carrier tape can be more fully utilized, thereby saving material costs. After being bonded to the wafer, the chip package structure 4 of the present invention can be connected to the electrical test device through the shared test area 33, and the electrical test device can be performed separately or simultaneously, and the electrical test device does not need to perform frequent plugging and unplugging actions. It can save the working time of electrical testing, significantly accelerate production efficiency and reduce production costs. The above-described embodiments are only intended to illustrate the embodiments of the present invention, and to broadly disclose the present invention, and to limit the protective material of the present invention. Any arrangement that is susceptible to variations or equivalences of the technology is within the scope of the invention. The scope of the invention should be determined by the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a conventional wafer package structure; Fig. 2 is a schematic view showing a carrier tape of the present invention; and Fig. 3 is a schematic view showing a structure of the wafer of the present invention. [Main component symbol description] 13 200926386
1 晶片封裝結構 10 111 定位孔 121 13 第一測試墊區 135 131 測試墊 131， 141 第一引腳部分 142 21 晶片 3 31 傳輸區域 311 321 第一封裝區域 321a 322 第二封裝區域 322a 33 測試墊區 331 341 第一引腳部分 341a 341b 第一外引腳 342 342a 第二内引腳 342b 343 第三引腳部分 344 4 晶片封裝結構 41 42 第二晶片 X 承載帶 封裝區域 第二測試墊區 測試墊 第二引腳部分 承載帶 定位孔 晶片接合區 晶片接合區 測試墊 第一内引腳 第二引腳部分 第二外引腳 第四引腳部分 第一晶片 輸送方向 141 chip package structure 10 111 locating hole 121 13 first test pad area 135 131 test pad 131, 141 first pin portion 142 21 wafer 3 31 transfer area 311 321 first package area 321a 322 second package area 322a 33 test pad Area 331 341 first pin portion 341a 341b first outer pin 342 342a second inner pin 342b 343 third pin portion 344 4 chip package structure 41 42 second wafer X carrier tape package area second test pad area test Pad second pin portion carrier tape positioning hole wafer bonding region wafer bonding region test pad first inner pin second pin portion second outer pin fourth pin portion first wafer transfer direction 14