TW200921796A - Semiconductor device and method of manufacturing thereof - Google Patents

Abstract

A method of fabricating a semiconductor device for improving gate-induced drain-leakage, comprising: providing a substrate; defining an active region in the substrate; forming a gate stack in the active region; conformally forming at least one offset spacer on a side and a surface of the gate stack and extending to a surface of the substrate for improving gate-induced drain-leakage; and carrying out an ion implant process with the offset spacer as a buffer layer to form doped regions in the substrate adjacent the offset spacers side of the gate stack and under the offset spacer.

Description

200921796 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a manufacturer thereof, and relates to a method for improving gate leakage current induced by a gate. Manufacturing method [prior art] With the miniaturization of integrated circuits

n 卞V gold oxygen + /it (metal-oxide-semiconductor, MOS) becomes more and more small, @金-氧-half field effect transistor (MOSFET) size, including ^ reduction pole length and gate oxide layer The method of thickness, etc. - Mu County Shaohao | 1Q1 The direction in which the inventors of related fields are actively studying. _ In the deep submicron technology, the MOS component is shortened with effective closed core. Due to the following miniaturization, the von von current of the second & degree of the M〇s opening is increased: (1) due to the threshold voltage (threshold voltage) The decrease causes the threshold leakage to increase exponentially. (2) The tunneling leakage caused by the direct penetration of the gate edge (3) due to the thickness reduction of the gate oxide layer. The gate-induced drain leakage (Gate-Induced Drain-Leakage, GIDL) increases exponentially (4) due to lightly doped-drain (LDD) or pocket-doping (pocket-doping) The increase in doping concentration causes the band-to-band-tunneling leakage of the valence band to the conduction band to increase exponentially. In the development of low-power dynamic memory components, the physical size reduction of the transistor means that the leakage current must be more precisely controlled without reducing the supply voltage. In particular, it has been reported that embedding

Client's Docket No.: 96-029 TT^ Docket No:0492-A41274-TW/fmal/hhchiang/ 200921796 Buried-channel PMOS single-gate (singie_gate) component, the main source of leakage current is the gate The induced buckling leakage current. Therefore, if a low leakage current is required in the standby mode, the gate leakage current caused by the gate is a bottleneck that needs to be broken. The main cause of the gate leakage induced by the gate is that during the formation of the M〇S device, after the formation of the gate structure, the ion implantation process is performed to form a lightly doped source and a drain (lightly doped source/drain). , LDD) region or pocket region, and the doping ions will diffuse below the gate structure, causing a strong electric field formed by a partial overlap between the gate and the gate-to-drain. . Conventional processes use modulated ion cloths to straighten process parameters such as implanted ion species, implant energy, or implant dose to avoid the formation of overlapping regions between gate-to-drain. However, with the miniaturization of components and the more stringent requirements for electrical properties, the conventional process can provide limited space for improvement. It is therefore an object of the present invention to provide an improved method for forming a metal oxide half component to overcome the prior art. Insufficient. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a semiconductor device, and more particularly to a metal oxide capable of improving gate induced drain leakage (GIDL). A manufacturing method of a semiconductor (M0S) device, comprising: providing a substrate; defining an active region in the substrate; forming a gate stack structure on the surface of the active region; forming at least one spacer layer on a sidewall and a surface of the gate stack structure Upper and extending onto the surface of the substrate; and using the isolation layer as a buffer layer, performing an ion implantation process to abut the sidewall of the gate stack structure

Client's Docket No.: 96-029 TT5s Docket No: 0492-A41274-TW/fmal/hhchiang/ 6 200921796 The underlying substrate is formed adjacent to the spacer layer and located in the spacer layer. [Embodiment] Embodiments of the present invention provide a method of manufacturing a semiconductor package, and in particular, a manufacturing method capable of improving the gate-induced drain leakage current of a gate. The system, the method of making and the manner of use of the respective embodiments are as follows, and are illustrated with reference to the drawings. .^ where 'graph and description 相同 The same component number used in 曰 denotes a phase-to-phase, day j or cheek-like component. In the drawings, for clarity and convenience of explanation, there is a thickness or an unrealistic situation. While the following description is particularly directed to the various elements of the device of the present invention, or the integration thereof, it is noted that the above-described elements are not particularly limited to the ones shown: those obtained by those skilled in the art. Form 2 If the material layer is located on another material layer or substrate, it may be directly on its surface or otherwise interposed with other intervening layers. 1 to 6 are cross-sectional views showing a process of a semiconductor device according to a preferred embodiment of the present invention, showing a manner of forming a MOS. Referring to Figure 1, first, a substrate 12 is provided. Substrate 12 can be a crucible substrate. In a consistent embodiment of the invention, the substrate 12 can be a (100) orientation (orientati〇n) and a P-type wafer wafer rotated at a 45 degree angle. In other embodiments, silicon germane (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI) may be utilized. , or other commonly used semiconductor substrates as the substrate 12. Next in the substrate 12

Client's Docket No.: 96-029 TTs Docket No: 0492-A41274-TW/final/hhchiang/ 200921796 The isolation structure l4 is formed to define the active-quasi-shallow trench isolation (STI) process formation, =. The isolation structure 14 can be formed by a marking method, and then the following steps are performed in a chemical process: using silver in the trench, the dielectric material can be filled by a chemical deposition process, and other isolation structures 14 can be used, for example. The process is flattened. In addition, the oxidation process forms a defined active region. In the ~ Xu storm oxide (that is, using the local row doping process of yttrium to form N or p type: in the example, the region can be entered in the active region to form the ~: impurity region of the MOSFET component as the active charge carrier Referring to FIG. 2, a gate structure 20 is formed to define a gate structure, and then a comprehensive multilayer deposition process is performed in the active region, which can be performed by conventional techniques, including an isotropic etching step. Formed by - ♦ photolithographic patterning and non-multilayer structure, including in the gate structure, the gate structure 20 can be an electrical layer 22, and formed in the gate dielectric layer 2 The gate of the lowest level is in the preferred embodiment, the gate electrode layer 24 on the gate structure θ·22. The gate top electrode layer 26 上 on the gate electrode layer; For example, the material of cerium oxide, cerium oxynitride or nitriding stone s 22 includes, for example, the combination of the above. The gate dielectric swarf is a ytterbium, a high dielectric constant dielectric or a cerium, including cerium oxide siA1 ηθ For the following - or a plurality of materials, 3), oxidation (Post 2), nitrogen oxidation, and strontium sulfate (cerebral palsy 4), oxidative error ((10)), nitrogen oxidization (Zr〇N), shixi secret (ZrSi〇4), yttrium oxide (γ2〇3), yttrium oxide (La2〇3), cerium oxide (Ce 〇 2), titanium oxide (Τι〇2), oxidation button (Ding & 2〇5) and their connections. In the practice of the present invention, the gate dielectric layer 22 is formed by a thermal oxidation method of a ruthenium oxide layer formed on the surface of the substrate. The gate electrode layer 24 may be doped polysilicon or polycrystalline

Client's Docket No.: 96-029 TT s Docket No: 0492-A41274-TW/fmal/hhchiang/ 8 200921796 In other embodiments, the gate electrode layer 24 may be made of one or more metals, metal tellurides, metals A nitride or a conductive metal oxide is formed. In a preferred embodiment, the gate electrode layer 24 includes a polysilicon. The above-mentioned metals include, for example, molybdenum, tungSten, titanium, tantalum, platinum, and hafnium as part of the gate top electrode layer 26. Further, the above metal nitrides include, but are not limited to, molybdenum nitride 'tungSten nitride, titanium nitride, and tantalum nitride. In addition, the genus of the genus of the genus includes, but is not limited to, nickel silicic, cobalt silicide, tungsten silidde, titanium silicide, and shi yihua. (tantalum silicide), platinum silicide, and erbium siHcide. Conductive metal oxides include, but are not limited to, ruthenium 〇xide and indium tin oxide. In a preferred embodiment of the invention, the gate top electrode layer 26 is comprised of tungsten germanium. According to a preferred embodiment of the present invention, after forming the gate structure 20 of the multilayer structure, the n2 is referred to as "Carder Gas" and the pock and the 〇2 (oxygen) are brought together into the high temperature furnace tube to the gate structure. The doping process of the sidewall of the gate dielectric layer 2〇6 (constituted by yttrium oxide) and the gate electrode layer (composed of the polycrystalline germanium material), and the oxide layer of the anti-deer phosphorus (not shown) . Heart ^ Please refer to Fig. 3, and then on the active region including the gate structure 2 and the surface of the substrate n, and extend to the isolation structure 14 to form a spacer 30. In a preferred embodiment of the invention, the spacer layer 3 is made of tetra-ethyl-ortho-silicate (TEOS).

Client's Docket N〇.:96-029 TT's Docket No:0492-A41274-TW/final/hhchiang/ 9 200921796 Using low pressure chemical vapor deposition (LPCVD) at temperatures between about 700 and 750° C, formed under pressure of 1 to 10 torr. In other embodiments, the spacer layer 30 can be formed by various techniques such as chemical vapor deposition, plasma chemical vapor deposition, physical vapor deposition, and deposition methods developed in the future. The spacer layer 30 may be composed of the following materials or a combination of the following materials: cerium oxynitride (SiON), tantalum nitride (Si3N4), oxidation button (Ta205), aluminum oxide (Al2〇3), polyethylene. Oxide (PE0X), tetraethyl phthalate 1 (TEOS) is an oxide of a substrate, a nitrided oxide, an oxide containing hafnium, and an oxygen-containing oxide. Oxide comprising tantalum, oxide comprising aluminum, oxide containing nitrogen or other dielectric material. It is particularly important to note that the thickness of the spacer layer 30 can be varied as required by the characteristics of the device, or can be formed by a multilayer structure formed by different deposition methods (including doping processes), as will be explained in more detail later. f In an embodiment of the invention, the thickness of the spacer layer 30 is between about 50 A (or 5 nm) to 250 A (or 25 nm). In addition, the spacer layer 30 formed by the deposition of the present invention does not need to be subjected to the etching process by the engraving process, thereby making it easier to control the within-wafer device uniformity. Referring to FIG. 4, after the spacer layer 30 is formed, the gate structure 3 and the spacer layer 30 around it are used as an implantation mask to perform an ion implantation process to implant dopant ions around the gate structure 20. In the substrate 12 on the side of the spacer layer 3, in one embodiment, it can be annealed after the ion implantation process.

Clients Docket No.:96-029 TT's Docket No:0492-A41274-TW/final/hhchiang/ 10 200921796 Cheng to make the push-ion ion expansion and open y / _ _ _ _ _ _ _ _ _ _ _ _ _ /drain, LDD) area 42. The ldd region 42 is also referred to as the source/drain extension region. In other embodiments, the implant process may be performed at an oblique angle to extend beyond the LDD region 42 to form a pocket region (not shown) below the gate structure. The process conditions used in the implant process, such as the implanted ion species, implant energy and dose, or implant angle, are modulated as the characteristics of the device are required. Since the spacer layer 30, which is reduced around the gate structure 20, has a suitable thickness, it can be used to form an LDD (four) 42 erroneous doping in the implantation process or the annealing process to provide a buffer region U-distribution to avoid dopant ion diffusion. The gate-to-drain (4) overlap region of the shallow surface of the substrate 12 under the pole structure 20 is increased to increase the gate leakage current induced by the gate in the device. With the different characteristics of the components, the thickness of the spacer layer 30 can be modulated by the difference in the possible diffusion of the dopant ions, depending on the conditions used in the implantation process. Also because of the spacer layer 3 having an appropriate thickness as a modulation parameter of the device process, the spacer layer 3 on the surface of the substrate 12 can also serve as a buffer layer, so that it is possible to use a higher energy or dose than the general doping process. The ion implantation conditions form the LDD region 42 so as not to cause the doped region to be excessively distant from the surface of the substrate 12 to lose its effect. In an embodiment of the invention, the thickness of the spacer layer 30 is between about 5 〇 a (or 5 nm) to 25 〇 (or 25 nm). In an embodiment, the doping process is performed at an energy of about 2 〇 KeV to 40 KeV to form the LDD region 42. Please refer to Figure 5 to Figure 6. Then, sidewall spacers 32 as shown in FIG. 5 are formed on the spacer layer 30 on both sides of the gate structure 2A, for example.

Client^ Docket No.: 96-029 TT5s Docket No:0492-A41274-TW/fmal/hhchiang/ 11 200921796 5 Enclosed to y is gasification 矽 (ie Si〇2), bismuth oxynitride (ie or 矽:矽(SlN) material 'This also includes the method of forming a multi-layered spacer by utilizing the conventional technique: 1 and 'the product and the back process' and then the sidewall spacer 32. Bamboo & said: $ @ ^ As a deployment mask, a self-aligned second ion implant is privately placed next to the sidewall spacer 32 as shown in Fig. 6 and spaced apart

A source/drain region 44 is formed in the substrate 12 under layer 3. This completes the fabrication of a MOS transistor. The method for forming a semiconductor device disclosed in the embodiments of the present invention is to deposit a spacer layer having a suitable thickness on the periphery m of the gate structure and the substrate without performing an etchback process through the etching process, thereby being easily etched. Control the uniformity of the components in the wafer. The spacer layer formed on the surface of the substrate can serve as a buffer layer, so that the LDD region can be formed using ion implantation conditions with higher energy or dose than the general doping process, so that the doped region is not excessively far from the substrate surface and loses its effect. . The isolation layer formed around the gate structure enables the dopant ions implanted for forming the LDD region to provide a buffer region for diffusion during the implantation process or the annealing process to prevent the dopant ions from diffusing below the gate structure. The overlap between the gate and the gate-to-drain on the shallow surface of the substrate improves the immersed leakage current induced by the gate in the device. The above method of forming a semiconductor device can be applied to various MOS transistors including surface channel (surface_channei) NM0S transistors, buried-channel P]V [〇S transistors, and dynamic random access memory (dynamic Random-access memory, DRAM) Fabrication of components. Although the present invention has been disclosed above in the preferred embodiment, it is not intended to be used

Client's Docket No.: 96-029 TT7s Docket No:0492-A41274-TW/final/hhchiang/ 200921796 How to be familiar with this artist's work without departing from the essence of the present invention. The protection perimeter is subject to the scope defined in the patent scope. [Simple description of the drawing] Figure 1 shows the isolation structure formed in the substrate to customize the cross-section of the process; ~ Figure 2 shows the process profile of forming a dummy structure in the active region, and Figure 3 shows the structure including the gate structure. And the active area on the surface of the substrate, and extending to the process of forming a blanket-separation layer on the isolation structure; Figure 4 shows the gate structure and the spacer layer around it as a coating mask for material curing The process section of the base (4) of the edge of the partition and the edge of the partition is formed into a lightly mixed series; the fifth figure shows the process profile of the sidewall spacer formed on the spacer layer on both sides of the gate structure. Figure 6 shows a cross-sectional view of the process of forming a source/drain region in the substrate under the spacer layer next to the sidewall spacer. [Main component symbol description] U substrate; 丨4 isolation structure; 20 gate structure; 22 gate dielectric layer; 24 gate electrode layer; 26 gate top electrode layer; 30 spacer layer, 32 sidewall spacer; Doped source and drain regions; 44 source/drain regions.

Client's Docket No.:96-029 XT's Docket No:0492-A41274-TW/final/hhchiang/ 13

Claims (1)

200921796 X. Patent Application Range: 1. A method for fabricating a semiconductor device for improving gate-induced drain leakage current, comprising the steps of: providing a substrate; defining an active region in the substrate; forming a surface on the active region a gate stack structure; forming at least one spacer layer on sidewalls and surfaces of the gate stack structure and extending onto a surface of the substrate; and: performing an ion implantation process to adjacent the gate stack structure A doped region is formed in the substrate below the spacer layer. 2. The method of fabricating a semiconductor device according to claim 1, wherein the spacer material comprises tetraethoxydecane. 3. The method of fabricating a semiconductor device according to claim 1, wherein the spacer layer material comprises bismuth oxynitride, tantalum nitride, oxidized button, aluminum oxide, polyethylene oxide, and tetraethyl decanoate. The oxide of the substrate, the nitrided oxide layer, the oxide-containing oxide, the cerium-containing oxide, the cerium-containing oxide, the nitrogen-containing oxide, or a combination thereof. 4. The method of fabricating a semiconductor device according to claim 2, wherein the spacer layer has a thickness of about 50 Å (or 5 nm) to 250 A (or 25 nm). 5. The method of fabricating a semiconductor device according to claim 4, wherein the spacer layer is formed by a low pressure chemical vapor deposition process. 6. The manufacturer of the semiconductor device described in the fifth paragraph of the patent application is called Client's Docket No.: 96-029 TT5s Docket No: 0492-A41274-TW/fmal/hhchiang/ 14 200921796 :========== The low method is carried out, and the manufacturing method of the semiconductor device described in claim 5 is determined by the gas phase sinking force = the force is between about 1 and the reading device is carried out, and the red (four) device is set up. The manufacturing method, wherein the doped region comprises a lightly doped region and/or a pocket-shaped alternating region The manufacturing method of the semiconductor package described in claim 8 wherein the impurity region comprises a germanium-type doped region. The manufacturing method of the semiconductor package described in the above-mentioned patent application, wherein the doped region comprises a p-type doped region. The manufacturing process of the semiconductor device described in the second paragraph of the patent scope / the energy of about 2G KeV to 4Q Kev is performed to improve the gate-induced semiconductor device manufacturing method. The following steps: providing a substrate; defining an active region in the substrate; forming a gate stack structure on the surface of the active region; forming at least one spacer layer on the sidewall of the gate stack structure and extending to the surface of the substrate And using the isolation layer as a buffer layer, performing a first ion implantation process to form a first doped region in the substrate adjacent to the spacer of the __# structure sidewall; Client's Docket No.: 96-029 TT5s Docket N〇: 〇 492-A41274-TW/fmayiilichiang/ 15 200921796 Forming a sidewall spacer next to the isolation layer of the sidewall of the gate stack structure; and implementing a second ion implantation The process is such that a second doped region is formed in the substrate adjacent to the sidewall spacer adjacent to the sidewall of the gate stack structure and under the spacer layer. 13. The method of fabricating a semiconductor device according to claim 12, wherein the spacer material comprises tetraethoxydecane. 14. The method of fabricating a semiconductor device according to claim 12, wherein the spacer layer material comprises bismuth oxynitride, cerium nitride, cerium oxide, aluminum oxide, polyethylene oxide, tetraethyl cerate. The oxide of the substrate, the ruthenium oxide layer, the oxide-containing oxide, the group oxide, the oxide containing the oxide, the nitrogen oxide, or a combination thereof. 15. The method of fabricating a semiconductor device according to claim 13 or claim 14, wherein the spacer layer has a thickness of about 50 (or 5 nm) to 250 A (or 25 nm). 16. The method of fabricating a semiconductor device according to claim 15, wherein the spacer layer is formed by a low pressure chemical vapor deposition process. 17. The method of fabricating a semiconductor device according to claim 16, wherein the low pressure chemical vapor deposition process is carried out at a temperature of about 700 to 750 °C. 18. The method of fabricating a semiconductor device according to claim 16, wherein the low pressure chemical vapor deposition process is carried out at a pressure of between about 1 and 10 torr. 19. The manufacture of a semiconductor device as described in claim 12, Client's Docket No.: 96-029 TT^ Docket No: 0492-A41274-TW/fmal/hhchiang/16 200921796 / ” The method of fabricating a semiconductor device according to claim 19, wherein the first doped region comprises an N-type doped region. The method of fabricating a semiconductor device according to claim 19, wherein the first doped region comprises a p-type doped region. 22. The semiconductor device of claim 12, wherein: The method for fabricating a semiconductor device according to claim 12, wherein the second doped region comprises a source region and/or a drain The method of manufacturing a semiconductor device according to the invention of claim 23, wherein the second doped region comprises an N-type doped region. The semiconductor device method described in claim 23, wherein The two doped regions include a P-type doped region. Body apparatus, comprising: a substrate; a gate stack structure over the substrate; a spacer layer on the sidewalls and surfaces of the gate stack structure and extending onto the surface of the substrate; a first doped region adjacent to the gate stack The spacer sidewall of the structure sidewall is located in the substrate below the spacer layer; the sidewall spacer is located adjacent to the isolation sidewall of the gate stack structure; and @ a second doped region adjacent to the gate stack structure Client's Docket N〇.: 96-029 TT5s Docket No: 0492-A41274-TW/fmayhhchiang/ 17 200921796: The child is located in the substrate below the spacer layer. β 27. As described in claim 26, the spacer layer material contains tetraethoxy I. The semiconductor device described in claim 26, wherein the semiconductor device comprises: bismuth oxynitride, tantalum nitride, oxidized group, aluminum oxide, layer, and oxide The base oxide is a substrate oxide, nitriding oxidation or a group thereof containing (tetra) monooxide, nitrogen oxide, f 29 = the thickness of the semiconductor spacer layer according to claim 27 or claim 28 The semiconductor device of claim 26, wherein the human germanium region comprises a lightly doped region and/or a pocket doped region. In the semiconductor device described in the third aspect of the patent, the doped region of the basin includes an N-type doped region. The semiconductor device according to the third aspect of the invention, wherein the Μ 払 doping region comprises a Ρ type doped region. The semiconductor device of claim 26, wherein the doped region comprises a source region and/or a drain region. This is the semiconductor device described in item 5% of the patent application, in which. / Brother - 4 hetero regions include N-doped regions. 35. The semiconductor package of claim 33, wherein the preparation region comprises a P-type doped region. , Client's Docket N〇.;96-029 TT'sD〇cketNo:0492-A41274-TW/fmayhhch1ang/ 18