200919520 κυ-υ/4-ι w z4170twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種保險絲的結構與製作方法，且特 別是有關於一種晶片保險絲的結構與製作方法。 【先前技術】 圖1繪不一種習用晶片保險絲的剖面示意圖。請參照 圖1，晶片保險絲10已揭露於台灣專利公告號第1242876 號。晶片保險絲10具有基板（substrate ) 11、隔熱層（thermal insulating layer) 12、第一導電層（conductive layer) 14、 緩衝層 15(buffer layer)、第二導電層 16、保護層（protective layer) 17、二個背面電極（back electrode) 18 以及二個端 面電極（end electrode) 19。 隔熱層12配置於基板11的表面11&上。第一導電層 覆蓋基板11與隔熱層12。緩衝層15配置於第一導電層 14上，而第二導電層16配置於緩衝層15上。保護層17 覆盍第二導電層16、緩衝層15以及部分第一導電層14。 二個背面電極18配置於基板11的表面lib上。二個端面 電極19为別配置於基板11的兩端面（end surface) 11 c， 且各個端面電極19電性連接第一導電層14與這些背面電 極18的其中之一。 基板11的材質為氧化鋁（八丨2〇3)。隔熱層12的材質 莖石=膠（SilieGnrubber)。第—導電層14的材質為銅。 一導電層16的材質為錫，且第一導電層14的熔點大於 200919520 z4170twf.doc/n 第一導電層16的熔點。緩衝層15的材質為氮化鈦（TiN)、 鈦鎢合金（την)、氮化石夕（SiN)、坤化銘（A1As)、硫 化鎘（CdS)及鎳（Ni)中的一種。背面電極18的材質為 銀或銅。 、當晶片保險絲10工作時，隨著電流增加或是工作時 間增長，晶片保險絲10的溫度隨之攀高，使第二導電層 16熔融擴散至第一導電層14中。隨著第二導電層16擴^ 至=-導電層14的量增加，被擴散的第—導電層14的炫 點Ik之降低且其阻抗隨之增加。此外，流過被擴散的第一 導電層Μ的電流所產生的熱量將持續增加，使得第一導電 層14溶斷而斷路，進而保護其他電路元件。因此，晶片保 險絲10的功用是當溫度或電流超過臨界值時，立即中斷電 路工作，以保護其他電路元件。 隔熱層12的功用在於，當晶片保險絲1〇運作時，由 於隔熱層12的熱傳導率（heatc〇nductivity)比基板u的 熱傳導率為低’所以流過被擴散的第_導電層14的電流所 產生的熱量將迅速增加而不易消散。 缓衝層b的功用在於控制第二導電層16擴散至第— V電層14的擴散啟動機制。若晶片保險絲1〇不具有緩衝 層15/則第二導電層16料在甚低於臨界值下熔融並擴 散至第—導電層14 ’而致使被擴散之第-導電層14的炫 點不當降低，導致W保險絲易燒毁而壽命縮短。然而， 晶片保險絲1G所具有的緩衝層15的材質點較高，又 將會使晶片保險絲1〇不易麟。另外，第—導電層“與 200919520 κυ-υ 1 w Z4170twf.doc/n 隔熱層12之間常有附著性不佳的問題存在。有鑑於此，選 擇適當材質的緩衝層以及改善第一導電層與隔熱層之間的 附著性是值得努力的課題。 【發明内容】 本發明提供一種晶片保險絲的製作方法，可提升第一 導電層與隔熱層之間的附著性。 ^本發明提供一種晶片保險絲的製作方法，可有效控制 第一導電層擴散至第一導電層的擴散啟動機制。 本發明提供一種晶片保險絲，其第一導電層與隔熱層 之間的附著性較佳。 沒本，明提供一種晶片保險絲，可有效控制第二導電層 擴政至第一導電層的擴散啟動機制。 本發明提出-種晶片保險絲的製作方法，其包括下列 =驟。首先’形成-隔熱層於—基板之—第—表面上，並 二、層之退離基板的—第二表面為—粗链面。接著，形 八電層於第二表面上。然後，形成—保護層於部 i之外T“層上’而且* —導電層的其他部分暴露於保護 列程本發明一實施例所述’形成隔熱層的步驟包括下 鋼i層與p:e:之;先，提供-背膠銅箱’其具有- 表面上，使得‘ 壓合#於基板之第— 蒋，丨、^、田骖體層配置於第一表面上。接著， 矛、八》銅fl層’使得膠體層作為隔熱層。隔熱層的 200919520 JKU-u /4-1 w z4170twf.doc/n 至少部分第二表面暴露於外，而且隔熱層的第二表面為粗 链面。 依照本發明一實施例所述，形成隔熱層的步驟包括藉 由塗佈（coating)的方式形成隔熱材料層於基板之第—表 面上’接著粗糙化隔熱材料層，以形成隔熱層，並使得隔 熱層之第二表面為粗糙面。 依本發明一實施例所述’晶片保險絲的製作方法在 形成保護層之前，更包括形成一緩衝層於部分第一導電層 上及形成一第二導電層於缓衝層上。缓衝層的材質可為金 鉑合金、金鈷合金或純金。 依知、本發明一實施例所述，第二表面的中心線平均粗 糙度（center-line average roughness’Ra)可大於或等於 3〇〇〇 埃（angstrom，A)且小於或等於5000埃。 依照本發明一實施例所述，晶片保險絲的製作方法更 包括下列程序。首先，形成兩背面電極於基板之一第三表 面上，而且第二表面相對於第一表面。接著，形成兩端面 電極於基板之彼此相對之兩端面上。各端面連接第一表面 與第二表面，且各端面電極電性連接第一導電層與這些背 面電極之'~。 依照本發明一實施例所述，隔熱層的材質包括環氧樹 脂。 —本發明提出一種晶片保險絲包括一基板、一隔熱層、 :第一導電層、一第二導電層以及一保護層。隔熱層配置 於基板之第一表面上，而且隔熱層之遠離基板的第二表面 200919520 KU-υ/^-ι w z4170twf.doc/n 為一粗較面 第一導電層阶里## . 於部分第-導電層上，以於::=。保護層配置 保護層之外。 尤且弟―導電層的其他部分暴露於 w = ΐ發明一實施例所述，晶片保險絲更包括-第二 Τ二®緩衝層’第二導電層配置於部分第-導電芦 衝層的材質為金鉑合金、全叙 緩 蓋缓衝層及第二導電層。I金或、純金，縣護層更覆 依照本發明-實施例所述，第二表面的中心線平均粗 糙度可大於或等於3_埃且小於或等於5_埃。 依照本發明一實施例所述，隔熱層於第-表面所形成 的一正投影可與第一表面重合。 依照本發明一實施例所述，晶片保險絲更包括兩背面 電極以及兩端面電極。兩背面電極配置於基板之—第三表 面上而且第二表面相對於第一表面。兩端面電極配置於 基板之彼此相對之兩端面上，而且各端面連接第一表面與 第二表面。各端面電極電性連接第一導電層與這些背面電 依照本發明一實施例所述，隔熱層的材質包括環氧樹 脂。 依照本發明一實施例所述，晶片保險絲更包括一銅落 層，其配置於隔熱層的第二表面上。銅箔層暴露部分第二 表面’而且第一導電層配置於第二表面與銅箔層上。 依照本發明一實施例所述，隔熱層的玻璃轉換溫度 200919520 κυ-υ/4-ι w z4170twf.doc/n (glass transition temperature )可大於攝氏 l5〇 度。 依照本發明一實施例所述，隔熱層的熱傳導率可介於 0.1 W/mK 與 1 W/mK 之間。 依照本發明一實施例所述，保護層更包括一第—保護 層及一第二保護層。第一保護層的材質包括環氧樹脂第 二保護層的材質包括聚醯亞胺，且第一保護層配置於第一 導電層與第二保護層之間。 ' 本發明提出一種晶片保險絲包括一基板、一隔熱層、 一第一導電層、一緩衝層 '一第二導電層以及一保護'層曰。 隔熱層配置於基板之第-表面上。第—導電層配置於隔轨 層上。缓衝層配置於部分第—導電層上，而且緩衝層的材 質為金翻合金、金齡金或純金。第二導電層配置於緩衝 層上。保護層配置於部分第—導電層上以覆蓋第二導電層 與緩衝層，且第-㈣層的其他部分暴露於紐層之外曰。 附菩述2發明之實施例之第一導電層與隔熱層的 Γΐί;二1發明之實施例之緩衝層可有效控制 弟—導電層擴散至弟—導電層的擴散啟動機制。另外’本 ，明2實施例之隔熱層所覆蓋的範圍較 故隔熱效果較佳。 …1寻V午1& 為讓本發明之上述特徵和優點能更明 舉實施例’並配合所附圖式’作詳細說明如下。 【實施方式】 [第一實施例] 200919520 KJj-u/4-丄 w z4170twf.doc/n 圖2繪示本發明第一實施例之晶片保險絲的剖面示音、 圖。請參照圖2，本實施例之晶片保險絲200包括一基板 21〇、一隔熱層220a、一第一導電層230、一第二導電層 240以及一保護層250。 隔熱層220a配置於基板210之一表面212上，而且 隔熱層220a之遠離基板210的一表面222為一粗糙面。第 一導電層230配置於表面222上，而第二導電層24〇則配 置於部份的第一導電層230上，且第二導電層240的溶點 可低於第一導電層230的熔點。保護層250配置於部份的 第一導電層230上且覆蓋第二導電層240，而且第一導電 層230的其他部分暴露於保護層250之外。 由於隔熱層220a之表面222為粗糙面，因此第一導 電層230與表面222之間附著性較佳，故第一導電層230 較不易脫落。在本實施例中，隔熱層220a之表面222的中 心線平均粗糙度例如大於或等於3〇〇〇埃且小於或等於 5000 埃。 在本實施例中’隔熱層220a於基板210之表面212 所形成的一正投影（orthogonal projection)可與表面212 重合（coincide)。換言之，隔熱層220a可完全覆蓋基板 210之表面212。此外，隔熱層220a具有耐燃、玻璃轉換 恤度南及熱傳導率低的優點。詳言之，本實施例之隔熱層 220a的玻璃轉換溫度可大於攝氏15〇度，其熱傳導率可介 於0.1 W/mK與1 W/mK之間，且其固化溫度（curing temprature)可介於攝氏15〇度與250度之間。因此，與習 200919520 κυ-υ/4-ι w z4170twf.doc/n 知技術相較’本實施例之隔熱層220a所覆蓋的範圍較大且 熱傳導率低，故隔熱效果較好。此外，保護層250的功用 在於可避免第一導電層230與第二導電層240熔斷時賤出 而污染其他電路元件（未繪示）。 在本實施例中’基板210之材質包括玻璃或氧化紹， 且隔熱層220a之材質包括ί衣氧樹脂（epoxy resin)。第一 導電層230的材質例如為銅或銅錫合金。第二導電層240 的材質例如為錫。保護層250的材質例如為焊罩（s〇lder mask )的材料或包括聚酸亞胺（p〇iyimjde )與環氧樹脂 (epoxy resin)。詳言之，保護層250具有第一保護層（圖 未示）及第二保護層（圖未示），且第一保護層的材質可 由環氧樹脂組成’第二保護層的材質可由聚醯亞胺組成。 第一保護層配置於第一導電層230上，且第二保護層配置 於第一保護層上。在本實施例中，第一保護層設置於第二 導電層240與第二保護層之間。由於第二保護層的彈性較 佳’當第一導電層230與第二導電層240熔斷時，第一保 C) 護層會先熔掉，但第二保護層會產生形變使其仍包覆著第 二導電層240，故可避免第二導電層240熔斷時，材質例 如為錫的第二導電層240濺出而污染其他電路元件。 在本實施例中’晶片保險絲200更包括一缓衝層26〇 , 其配置於第二導電層240與部份第一導電層23〇之間，緩 衝層260、第一導電層230及第二導電層240形成一保險 絲部。此外，保護層250更可覆蓋緩衝層260。緩衝層260 的材質可為金鉑合金、金銘合金或純金。在此必須說明的 12 200919520200919520 κυ-υ/4-ι w z4170twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a structure and a manufacturing method of a fuse, and more particularly to a structure and structure of a chip fuse Production Method. [Prior Art] Fig. 1 is a schematic cross-sectional view showing a conventional wafer fuse. Referring to Figure 1, the wafer fuse 10 has been disclosed in Taiwan Patent Publication No. 1242876. The wafer fuse 10 has a substrate 11, a thermal insulating layer 12, a first conductive layer 14, a buffer layer, a second conductive layer 16, and a protective layer. 17. Two back electrodes 18 and two end electrodes 19. The heat insulating layer 12 is disposed on the surface 11 & of the substrate 11. The first conductive layer covers the substrate 11 and the heat insulating layer 12. The buffer layer 15 is disposed on the first conductive layer 14, and the second conductive layer 16 is disposed on the buffer layer 15. The protective layer 17 covers the second conductive layer 16, the buffer layer 15, and a portion of the first conductive layer 14. The two back electrodes 18 are disposed on the surface lib of the substrate 11. The two end electrodes 19 are disposed on the end surfaces 11c of the substrate 11, and the end electrodes 19 are electrically connected to one of the first conductive layer 14 and the back electrodes 18. The material of the substrate 11 is alumina (eight 丨 2 〇 3). The material of the heat insulation layer 12 is stone (silica) (SilieGnrubber). The material of the first conductive layer 14 is copper. A conductive layer 16 is made of tin, and the first conductive layer 14 has a melting point greater than the melting point of the first conductive layer 16 of 200919520 z4170 twf.doc/n. The material of the buffer layer 15 is one of titanium nitride (TiN), titanium tungsten alloy (την), nitridox (SiN), Kunming Ming (A1As), cadmium sulfide (CdS), and nickel (Ni). The back electrode 18 is made of silver or copper. When the wafer fuse 10 is in operation, as the current increases or the operating time increases, the temperature of the wafer fuse 10 increases, causing the second conductive layer 16 to be melt-diffused into the first conductive layer 14. As the amount of the second conductive layer 16 expanded to the =-conductive layer 14 increases, the sleek point Ik of the diffused first conductive layer 14 decreases and its impedance increases. In addition, the heat generated by the current flowing through the diffused first conductive layer 持续 will continue to increase, causing the first conductive layer 14 to be broken and open, thereby protecting other circuit components. Therefore, the function of the wafer fuse 10 is to interrupt the circuit operation immediately when the temperature or current exceeds a critical value to protect other circuit components. The function of the heat insulating layer 12 is that when the wafer fuse 1 is operated, since the heat conductivity of the heat insulating layer 12 is lower than the heat conductivity of the substrate u, it flows through the diffused first conductive layer 14 The heat generated by the current will increase rapidly and not easily dissipate. The function of the buffer layer b is to control the diffusion initiation mechanism of the diffusion of the second conductive layer 16 to the first-V electrical layer 14. If the wafer fuse 1 does not have the buffer layer 15 / then the second conductive layer 16 is melted and diffused to the first conductive layer 14 ' at a value lower than the critical value, resulting in an improper reduction of the diffused first conductive layer 14 As a result, the W fuse is easily burned and the life is shortened. However, the wafer fuse 1G has a higher material point of the buffer layer 15, which in turn makes the wafer fuse 1 less prone. In addition, there is often a problem of poor adhesion between the first conductive layer and the 200919520 κυ-υ 1 w Z4170twf.doc/n thermal insulation layer 12. In view of this, a buffer layer of a suitable material is selected and the first conductive is improved. The adhesion between the layer and the heat insulating layer is a problem that is worthy of effort. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a wafer fuse that improves adhesion between a first conductive layer and a heat insulating layer. A method for fabricating a wafer fuse can effectively control a diffusion initiation mechanism of diffusion of a first conductive layer to a first conductive layer. The present invention provides a wafer fuse having better adhesion between a first conductive layer and a heat insulating layer. The present invention provides a wafer fuse that can effectively control the diffusion initiation mechanism of the second conductive layer to the first conductive layer. The present invention provides a method for fabricating a wafer fuse, which includes the following = step. First, 'formation-insulation The layer is on the surface of the substrate, and the second surface of the layer is separated from the substrate by a thick chain surface. Then, the eight layers are formed on the second surface. Then, the shape - the protective layer is outside the portion i "on the layer" and * the other portion of the conductive layer is exposed to the protective train. The step of forming the insulating layer according to an embodiment of the invention comprises the lower steel i layer and p:e: First, a back-coated copper box is provided which has a surface such that the 'pressing # is on the first of the substrate--the Jiang, 丨, ^, and Tian 骖 body layers are disposed on the first surface. Next, the spear, eight "copper fl layer" makes the colloid layer serve as a heat insulating layer. Insulation 200919520 JKU-u /4-1 w z4170twf.doc/n At least part of the second surface is exposed, and the second surface of the insulation layer is a thick chain surface. According to an embodiment of the invention, the step of forming the heat insulating layer comprises forming a layer of the heat insulating material on the first surface of the substrate by coating, and then roughening the heat insulating material layer to form heat insulation. The layer is such that the second surface of the insulating layer is a rough surface. According to an embodiment of the present invention, a method of fabricating a wafer fuse further includes forming a buffer layer on a portion of the first conductive layer and forming a second conductive layer on the buffer layer before forming the protective layer. The material of the buffer layer may be gold platinum alloy, gold cobalt alloy or pure gold. According to an embodiment of the invention, the center-line average roughness 'Ra' of the second surface may be greater than or equal to 3 angstroms (A) and less than or equal to 5000 angstroms. According to an embodiment of the invention, the method of fabricating the chip fuse further includes the following procedure. First, two back electrodes are formed on one of the third surfaces of the substrate, and the second surface is opposed to the first surface. Next, the both end surface electrodes are formed on both end faces of the substrate opposite to each other. Each end surface is connected to the first surface and the second surface, and each of the end surface electrodes is electrically connected to the first conductive layer and the back electrodes. According to an embodiment of the invention, the material of the heat insulating layer comprises an epoxy resin. The present invention provides a wafer fuse including a substrate, a heat insulating layer, a first conductive layer, a second conductive layer, and a protective layer. The heat insulation layer is disposed on the first surface of the substrate, and the second surface of the heat insulation layer away from the substrate is 200919520 KU-υ/^-ι w z4170twf.doc/n is a rough surface first conductive layer step ### On some of the first conductive layers, to ::=. The protective layer is configured outside the protective layer. In particular, the other portion of the conductive layer is exposed to w = 所述 according to an embodiment of the invention, the chip fuse further includes a second second buffer layer, and the second conductive layer is disposed on a portion of the first conductive reed layer. Gold platinum alloy, full-slip cover buffer layer and second conductive layer. I gold or pure gold, the county sheath is further covered. According to the invention - the embodiment, the center line average roughness of the second surface may be greater than or equal to 3 angstroms and less than or equal to 5 angstroms. In accordance with an embodiment of the invention, an orthographic projection formed by the insulating layer on the first surface may coincide with the first surface. According to an embodiment of the invention, the wafer fuse further includes two back electrodes and two end surface electrodes. The two back electrodes are disposed on a third surface of the substrate and the second surface is opposite the first surface. The two end electrodes are disposed on opposite end faces of the substrate, and the end faces are connected to the first surface and the second surface. Each of the end surface electrodes is electrically connected to the first conductive layer and the back surface. According to an embodiment of the invention, the material of the heat insulating layer comprises an epoxy resin. According to an embodiment of the invention, the wafer fuse further includes a copper drop layer disposed on the second surface of the heat insulating layer. The copper foil layer exposes a portion of the second surface' and the first conductive layer is disposed on the second surface and the copper foil layer. According to an embodiment of the invention, the glass transition temperature of the thermal insulation layer may be greater than 15 degrees Celsius by the temperature of the glass transition temperature of 200919520 κυ-υ/4-ι w z4170twf.doc/n (glass transition temperature). According to an embodiment of the invention, the thermal conductivity of the thermal insulation layer may be between 0.1 W/mK and 1 W/mK. According to an embodiment of the invention, the protective layer further includes a first protective layer and a second protective layer. The material of the first protective layer comprises a material of the second protective layer of the epoxy resin comprising a polyimide, and the first protective layer is disposed between the first conductive layer and the second protective layer. The present invention provides a wafer fuse including a substrate, a heat insulating layer, a first conductive layer, a buffer layer 'a second conductive layer, and a protective layer. The heat insulating layer is disposed on the first surface of the substrate. The first conductive layer is disposed on the barrier layer. The buffer layer is disposed on a portion of the first conductive layer, and the material of the buffer layer is gold alloy, gold age gold or pure gold. The second conductive layer is disposed on the buffer layer. The protective layer is disposed on a portion of the first conductive layer to cover the second conductive layer and the buffer layer, and the other portions of the first (four) layer are exposed to the outer layer. The first conductive layer and the heat insulating layer of the embodiment of the invention are attached to the invention. The buffer layer of the embodiment of the invention can effectively control the diffusion initiation mechanism of the diffusion of the conductive layer to the conductive layer. Further, the range covered by the heat insulating layer of the present invention is better than that of the heat insulating layer. The above-described features and advantages of the present invention will be described in more detail with reference to the accompanying drawings. [Embodiment] [First Embodiment] 200919520 KJj-u/4-丄 w z4170twf.doc/n FIG. 2 is a cross-sectional view and a view showing a wafer fuse according to a first embodiment of the present invention. Referring to FIG. 2, the wafer fuse 200 of the present embodiment includes a substrate 21, a thermal barrier 220a, a first conductive layer 230, a second conductive layer 240, and a protective layer 250. The heat insulating layer 220a is disposed on one surface 212 of the substrate 210, and a surface 222 of the heat insulating layer 220a away from the substrate 210 is a rough surface. The first conductive layer 230 is disposed on the surface 222, and the second conductive layer 24 is disposed on a portion of the first conductive layer 230, and the melting point of the second conductive layer 240 may be lower than the melting point of the first conductive layer 230. . The protective layer 250 is disposed on a portion of the first conductive layer 230 and covers the second conductive layer 240, and other portions of the first conductive layer 230 are exposed outside the protective layer 250. Since the surface 222 of the heat insulating layer 220a is a rough surface, the adhesion between the first conductive layer 230 and the surface 222 is better, so the first conductive layer 230 is less likely to fall off. In the present embodiment, the center line average roughness of the surface 222 of the heat insulating layer 220a is, for example, greater than or equal to 3 angstroms and less than or equal to 5000 angstroms. In the present embodiment, an orthogonal projection formed by the heat insulating layer 220a on the surface 212 of the substrate 210 may coincide with the surface 212. In other words, the insulating layer 220a can completely cover the surface 212 of the substrate 210. Further, the heat insulating layer 220a has the advantages of flame resistance, glass transition degree, and low heat conductivity. In detail, the glass transition temperature of the heat insulating layer 220a of the embodiment may be greater than 15 degrees Celsius, and the thermal conductivity may be between 0.1 W/mK and 1 W/mK, and the curing temprature may be Between 15 degrees Celsius and 250 degrees Celsius. Therefore, the heat insulating layer 220a of the present embodiment covers a larger range and has a lower thermal conductivity than the conventional technique of the present invention, so that the heat insulating effect is good. In addition, the function of the protective layer 250 is to prevent the first conductive layer 230 and the second conductive layer 240 from being blown out to contaminate other circuit components (not shown). In the present embodiment, the material of the substrate 210 includes glass or oxide, and the material of the heat insulating layer 220a includes an epoxy resin. The material of the first conductive layer 230 is, for example, copper or a copper-tin alloy. The material of the second conductive layer 240 is, for example, tin. The material of the protective layer 250 is, for example, a material of a solder mask or a polyimine and an epoxy resin. In detail, the protective layer 250 has a first protective layer (not shown) and a second protective layer (not shown), and the material of the first protective layer may be composed of epoxy resin. The composition of the imine. The first protective layer is disposed on the first conductive layer 230, and the second protective layer is disposed on the first protective layer. In this embodiment, the first protective layer is disposed between the second conductive layer 240 and the second protective layer. Since the elasticity of the second protective layer is better, when the first conductive layer 230 and the second conductive layer 240 are blown, the first protective layer C) is first melted, but the second protective layer is deformed so that it is still coated. The second conductive layer 240 is formed, so that when the second conductive layer 240 is blown, the second conductive layer 240 of a material such as tin is splashed to contaminate other circuit components. In the present embodiment, the wafer fuse 200 further includes a buffer layer 26 配置 disposed between the second conductive layer 240 and a portion of the first conductive layer 23 , the buffer layer 260 , the first conductive layer 230 , and the second The conductive layer 240 forms a fuse portion. In addition, the protective layer 250 may further cover the buffer layer 260. The material of the buffer layer 260 may be gold platinum alloy, gold alloy or pure gold. Must be explained here 12 200919520
KiJ-u/4-iw ^4170twf.doc/n 是，與習知技術相較，由於材# 金或純金的緩衝層260的熔‘彻如為金鉑合金、金鈷合 比較不會不易溶斷。舉例來說以晶片保險絲， 其溶點為14GG°C以上，而本發明用鎳為緩衝層 或純金為緩衝層260其熔點約為:c:合金 =权不易熔斷。換言之’材質例如為金鉑合金、金鈷 ;ί===效控制第二導電層24。擴散 二=的擴散敌動機制。此外，詳細的實驗數 晶片保險絲 第一種 第二種 3 3 「-0.60% 0.04% ) 0.582 0.074 雙呈安培） 阻值變化率 的平均熔斷時間 、，各種晶片保險絲在兩倍額定電流時經過多次試驗的 平均炫斷時間及耐脈波後的阻值變化率整理如表一。請參 考表―、圖1與圖2,第一種晶片保險絲10 (習知技術） 具有材質為銅的第一導電層14、材質為鎳的緩衝層15且 材質為錫的第二導電層16。第二種晶片保險絲2〇〇 (亦即 本發明之—可能的實施例）具有材 質為銅的第一導電層 材質為金的緩衝廣260且材質為錫的第二導電層 24〇 °由表一可知，第一種晶片保險絲10被施加兩倍額定 電流時’非常不容易熔斷，而第二種晶片保險絲200被施 加兩倍額定電流時，熔斷時間可以縮短，且阻值變化率小 13 200919520 κ^-υ/Η-iw z4170twf.doc/n 故其耐脈（pulse)波或突波（surge)的能力佳。 在本實施例中，晶片保險絲200更包括一銅箔層22〇b ，一電鍍種子層（seed layer) 290 ,電鍍種子層29〇的材 質可為鎳或鉻化鎳。銅箔層220b配置於隔熱層22〇a的部 f表面222上，且銅箔層220b暴露部分表面222，詳細地 說，銅箔層220b配置於隔熱層220a的表面222的兩側， 使表面222的中心部份暴露出來。銅箔層22〇b的厚度通常 广 大於第一導電層230的厚度。電鍍種子層290直接配置於 銅箔層220b與被銅箔層220b所暴露的隔熱層22〇a之表面 22^上，而且第一導電層23〇配置於電鍍種子層2卯上。 換言之’部分電鍍種子層29〇直接配置於隔熱層22加之表 面222上，另一部份電鍍種子層29〇間接配置於隔熱層 220a之表面222上’且第一導電層23〇間接配置於表面222 與銅^層220b上。由上述可知，本實施例之第一導電層 230疋藉由電鍍的方式形成。若第一導電層23〇是藉由濺 鍍的方式形成，則可省略電鍍種子層29〇的配置。換言之， ϋ 第一導電層230可直接配置於銅箔層22〇b與被^箱層 22〇b所暴露的隔熱層22〇a之表面222上，但是並未以圖 面繪示。在此必須說明的是，銅箔層220b與隔熱層220a 可藉由將一背膠銅箔（未繪示）預先壓合於基板21〇之表 面212上，接著再進行後續加工處理而形成，詳細的製作 過程可見後述。 在本貝把例中’日曰片保險絲2〇〇更包括兩背面電極270 以及兩端面電極280。兩背面電極27〇配置於基板21〇之 14 200919520 RD-074-iW 24170twf.d〇c/nKiJ-u/4-iw ^4170twf.doc/n is compared with the conventional technology, because the melting of the buffer layer 260 of gold or pure gold is completely as gold-platinum alloy, gold-cobalt is less soluble. Broken. For example, in the case of a wafer fuse, the melting point is 14 GG ° C or higher, and the present invention uses nickel as a buffer layer or pure gold as a buffer layer 260 having a melting point of about: c: alloy = weight is not easily blown. In other words, the material is, for example, gold platinum alloy, gold cobalt; ί=== effect control of the second conductive layer 24. Diffusion Two = the proliferation of the enemy mechanism. In addition, the detailed experimental number of chip fuses is the first type of second 3 3 "-0.60% 0.04%" 0.582 0.074 double amps) The average fusing time of the rate of change of resistance, and the multi-chip fuses pass at twice the rated current. The average rupture time of the sub-test and the resistance change rate after the pulse-resistant wave are as shown in Table 1. Please refer to the table, Figure 1 and Figure 2, the first type of chip fuse 10 (known technology) has the material of copper a conductive layer 14, a buffer layer 15 made of nickel and a second conductive layer 16 made of tin. The second type of wafer fuse 2 (that is, a possible embodiment of the invention) has a first material made of copper The second conductive layer of the conductive layer is made of gold and has a buffer width of 260 and is made of tin. As can be seen from Table 1, when the first type of chip fuse 10 is applied with twice the rated current, it is very difficult to fuse, and the second type of wafer When the fuse 200 is applied twice the rated current, the fusing time can be shortened, and the resistance change rate is small. 13 200919520 κ^-υ/Η-iw z4170twf.doc/n Therefore, its pulse or surge The ability is good. In this embodiment, The chip fuse 200 further includes a copper foil layer 22〇b, a plating seed layer 290, and the material of the plating seed layer 29〇 may be nickel or nickel chromium. The copper foil layer 220b is disposed on the heat insulation layer 22〇a. The portion f of the portion 222, and the copper foil layer 220b exposes a portion of the surface 222. In detail, the copper foil layer 220b is disposed on both sides of the surface 222 of the heat insulating layer 220a to expose the central portion of the surface 222. The thickness of the layer 22〇b is generally wider than the thickness of the first conductive layer 230. The plating seed layer 290 is directly disposed on the surface 22 of the copper foil layer 220b and the heat insulating layer 22〇a exposed by the copper foil layer 220b, and The first conductive layer 23〇 is disposed on the plating seed layer 2卯. In other words, the “partial plating seed layer 29” is directly disposed on the surface of the heat insulating layer 22 and the other portion of the plating seed layer 29〇 is indirectly disposed on the heat insulating layer. The first conductive layer 23 is disposed on the surface 222 and the copper layer 220b. The first conductive layer 230 of the present embodiment is formed by electroplating. Layer 23 is formed by sputtering, and plating seeds can be omitted. The configuration of the layer 29〇. In other words, the first conductive layer 230 can be directly disposed on the surface 222 of the copper foil layer 22〇b and the heat insulating layer 22〇a exposed by the box layer 22〇b, but It should be noted that the copper foil layer 220b and the heat insulating layer 220a may be pre-bonded to the surface 212 of the substrate 21 by a backing copper foil (not shown), and then performed. It is formed by subsequent processing, and the detailed production process can be described later. In the example of the present invention, the 曰 chip fuse 2 〇〇 further includes two back electrodes 270 and two end surface electrodes 280. The two back electrodes 27 are disposed on the substrate 21 2009 14 200919520 RD-074-iW 24170twf.d〇c/n
表面214上，而且表面214相對於表面212。兩端面電極 280配置於基板21〇之彼此相對的兩端面216上，而且各 端面216連接表面212與表面214 ,並且各端面電極28〇 電性連接第一導電層23 0、銅箔層220b與這些背面電極27〇 的其中之—。由於第一導電層230的厚度較薄，故可藉由 具有較大厚度之銅箔層220b的設置，增加端面電極28〇 其端面之電性連接面積，且可使量測阻值較為準確。 r' 以下對於晶片保險絲200的製作方法作說明。圖3A 至圖、3H %示圖2之晶片保險絲之製作流程的剖面示意 圖。首先，請參考圖3A與圖3B，形成隔熱層22〇a於基 板210之表面212上，而且隔熱層220a之遠離基板210 的表面222為一粗糖面。 在本實施例中，形成隔熱層220a的步驟包括下列程 序。首先，請參考圖3A，提供一背膠銅箔（resin c〇ated copper，RCC) 220，其具有一膠體層220c與一銅箔層 220b。必須說明的是’背膠銅箔22〇的銅箔層22肋之與膠 U 體層220c相接觸的表面已預先經過粗糙化，且膠體層220c 塗佈於銅箔層220b之粗糙化表面上，所以膠體層22〇c會 沿著銅箔層220b之粗糙化表面而形成粗糙面。接著，將背 膠銅箔220壓合於基板210的表面212上，使得銅箔層220b 藉由膠體層220c配置於表面212上。值得注意的是，膠體 層220c具有耐燃、玻璃轉換溫度高及熱傳導率低的優點。 接著’請參考圖3B，移除至少部分銅箔層220b使得 膠體層220c作為隔熱層220a，且隔熱層220a的至少部分 200919520 κι>υ /4- i w /4170twf.doc/n 表面222暴露於外。必須強調的是，如上所述，膠體層22〇c 會沿著銅箔層220b之粗糙化表面而形成粗糙面。因此，當 至少部分銅箔層220b被移除後，隔熱層220a之暴露於外 的表面222即為粗糙面。在本實施例中，銅箔層22%亦可 完全移除，端視設計者的需求而定。 ^在形成隔熱層22〇a之後，請參考圖3C，形成一第一 V電層230於表面222上。形成第一導電層23〇的方法例 如為電鍍或是濺鍍。在本實施例中，當形成第一導電層23〇 法為電鍍時，通常在電鍍第一導電層230之前會先在 ^洎層220b與被銅箔層22〇b所暴露的隔熱層22〇a之表面 上濺鍍電鍍種子層290。當形成第一導電層230的方法 錢時，可省略錢鑛電鑛種子層290的步驟。在此必須 ，的疋，第一導電層23〇的厚度通常小於銅箔層22〇b \ 一戈带者，請參考圖3D，可形成一緩衝層260於部分第 240 ^層2!°上。接著，請參照圖3E，形成第二導電層 -俾it分第—導電層23G上。之後’請參考圖沖，形成 24〇護層25Q於部分第—導電層⑽上以覆蓋第二導電層 之外而/弟—導電層230的其他部分暴露於保護層250 H本實施例中，保護層250可更覆蓋緩衝層260。 ’开）成保護層250的方法例如為印刷。 表面考圖3G ’可形成兩f面電極27G於基板210之 圖祀，可开表面214相對於表面212。之後，請參考 心成兩端面電極280於基板210之彼此相對之兩 16 200919520 κυ-υ/4-1 w ιΑ 170twf.doc/n 端面216上，而且各端面216連接表面212與表面214。 各端面電極280電性連接第一導電層230與這些背面電極 270的其中之一。一般而言，形成背面電極27〇與端面電 極280的方法例如為濺鐘。 [弟二實施例] 圖4纟會示本發明弟一實施例之晶片保險絲的剖面示意 圖。請參考圖4與圖2，本實施例之晶片保險絲4〇〇與第 一實施例之晶片保險絲200差異之處在於，晶片保險絲4〇〇 不具有晶片保險絲200之銅箔層220b。此外，本實施例之 晶片保險絲400的隔熱層420的製作方法除了可藉由第一 實施例所述之隔熱層220a的製作方法來達成之外，亦可藉 由其他方式達成，詳見下述。 圖5A至圖5B緣示圖4之隔熱層之製作流程的剖面示 意圖。首先，請參考圖5A，可藉由塗佈的方式在基板41〇 之表面412上形成隔熱材料層42〇a。接著，請參考圖5A 與圖5B，粗糙化隔熱材料層420a，以形成隔熱層420，使 得隔熱層420之表面422為一粗糙面。在本實施例t，可 藉由離子轟擊隔熱材料層420a的方式粗糙化隔熱材料層 420a。值得注意的是，上述隔熱層42〇的形成方法僅為舉 例說明並非用以限定本發明。請參考圖4，關於後續之電 鍍種子層490、第一導電層43〇、缓衝層44〇、第二導電層 450、保護層460、兩背面電極470以及兩端面電極48〇的 形成方式與位置可參考第一實施例所述，故於此不再贅述。 在此強調的是，若第一導電層43〇是藉由濺鍍的方式 17 200919520 κυ-υ/4-iw /4170twf.d〇c/n /成則可省略形成電鍍種子層490的步驟與電鍍種子芦 490的配置。 曰Surface 214, and surface 214 is opposite surface 212. The two end surface electrodes 280 are disposed on the opposite end faces 216 of the substrate 21, and the end faces 216 are connected to the surface 212 and the surface 214, and the end face electrodes 28 are electrically connected to the first conductive layer 230 and the copper foil layer 220b. These are the back electrodes 27〇. Since the thickness of the first conductive layer 230 is thin, the electrical connection area of the end surface of the end surface electrode 28 can be increased by the arrangement of the copper foil layer 220b having a large thickness, and the resistance value can be accurately determined. r' The following describes the method of fabricating the wafer fuse 200. 3A to 3F are schematic cross-sectional views showing the fabrication process of the wafer fuse of Fig. 2. First, referring to FIG. 3A and FIG. 3B, the heat insulating layer 22A is formed on the surface 212 of the substrate 210, and the surface 222 of the heat insulating layer 220a away from the substrate 210 is a rough sugar surface. In the present embodiment, the step of forming the heat insulating layer 220a includes the following procedure. First, referring to FIG. 3A, a resin crusted copper (RCC) 220 having a colloid layer 220c and a copper foil layer 220b is provided. It should be noted that the surface of the copper foil layer 22 of the backing copper foil 22 is in contact with the surface of the rubber U layer 220c, and the surface of the copper layer 220c is previously roughened, and the colloid layer 220c is coated on the roughened surface of the copper foil layer 220b. Therefore, the colloid layer 22〇c forms a rough surface along the roughened surface of the copper foil layer 220b. Next, the backing copper foil 220 is pressed onto the surface 212 of the substrate 210 such that the copper foil layer 220b is disposed on the surface 212 by the colloid layer 220c. It is to be noted that the colloid layer 220c has the advantages of flame resistance, high glass transition temperature, and low thermal conductivity. Next, referring to FIG. 3B, at least a portion of the copper foil layer 220b is removed such that the colloid layer 220c functions as the thermal insulation layer 220a, and at least a portion of the thermal insulation layer 220a is exposed to the surface 222 of the surface of the thermal insulation layer 220a. Outside. It must be emphasized that, as described above, the colloid layer 22〇c will form a rough surface along the roughened surface of the copper foil layer 220b. Therefore, when at least a portion of the copper foil layer 220b is removed, the exposed surface 222 of the insulating layer 220a is a rough surface. In this embodiment, 22% of the copper foil layer can also be completely removed, depending on the designer's needs. After forming the thermal barrier layer 22A, please refer to FIG. 3C to form a first V electrical layer 230 on the surface 222. The method of forming the first conductive layer 23 is, for example, electroplating or sputtering. In the present embodiment, when the first conductive layer 23 is formed by electroplating, the insulating layer 22 exposed by the copper layer 22b is usually first before the first conductive layer 230 is plated. A plating seed layer 290 is sputtered on the surface of 〇a. When the method of forming the first conductive layer 230 is made, the step of the gold ore seed layer 290 may be omitted. In this case, the thickness of the first conductive layer 23〇 is usually smaller than that of the copper foil layer 22〇b·1, please refer to FIG. 3D, and a buffer layer 260 can be formed on the portion 240×2 2°° . Next, referring to FIG. 3E, the second conductive layer - 俾it is formed on the first conductive layer 23G. Then, please refer to the figure punch, forming a 24 〇 layer 25Q on the part of the conductive layer (10) to cover the second conductive layer and the other part of the conductive layer 230 is exposed to the protective layer 250 H in this embodiment, The protective layer 250 may cover the buffer layer 260 more. The method of opening the protective layer 250 is, for example, printing. The surface test 3G' can form a top surface of the two f-surface electrodes 27G on the substrate 210, with the surface 214 being open relative to the surface 212. Thereafter, the core end electrodes 280 are opposite to each other on the substrate 210, and the end faces 216 are connected to the surface 212 and the surface 214. Each of the end surface electrodes 280 is electrically connected to one of the first conductive layer 230 and the back surface electrodes 270. In general, the method of forming the back surface electrode 27A and the end surface electrode 280 is, for example, a splash clock. [Brief Embodiment] Fig. 4A is a schematic cross-sectional view showing a wafer fuse of an embodiment of the present invention. Referring to FIG. 4 and FIG. 2, the wafer fuse 4 of the present embodiment is different from the wafer fuse 200 of the first embodiment in that the wafer fuse 4 does not have the copper foil layer 220b of the wafer fuse 200. In addition, the manufacturing method of the heat insulating layer 420 of the wafer fuse 400 of the present embodiment can be achieved by the method for manufacturing the heat insulating layer 220a according to the first embodiment, and can be achieved by other means. The following. 5A to 5B are cross-sectional views showing the flow of the heat insulating layer of Fig. 4. First, referring to Fig. 5A, a heat insulating material layer 42A can be formed on the surface 412 of the substrate 41 by coating. Next, referring to Figures 5A and 5B, the heat insulating material layer 420a is roughened to form the heat insulating layer 420 such that the surface 422 of the heat insulating layer 420 is a rough surface. In the present embodiment t, the heat insulating material layer 420a can be roughened by ion bombardment of the heat insulating material layer 420a. It should be noted that the method of forming the above-mentioned heat insulating layer 42A is merely illustrative and is not intended to limit the present invention. Referring to FIG. 4, the subsequent plating seed layer 490, the first conductive layer 43A, the buffer layer 44A, the second conductive layer 450, the protective layer 460, the two back electrodes 470, and the both end surface electrodes 48A are formed and The location can be referred to the first embodiment, and thus will not be described again. It is emphasized here that the step of forming the plating seed layer 490 may be omitted if the first conductive layer 43 is by sputtering 17 200919520 κυ-υ/4-iw /4170 twf.d〇c/n / The configuration of the electroplating seed re 490.曰
紅上所述，本發明之晶片保險絲及其製作方法至少呈 有以下的優點： A 、由於本發明之實施例之隔熱層其與第—導電層相 接，的表面為-粗糙面，因此第一導電層與隔熱層之間的 附著性較佳，且第一導電層將較不易脫落。 P 二、由於本發明之實施例之缓衝層的材質可為金鉑合 金、絲合金或純金且其熔雜低。a此，與f知技術相 t ’本發明之實施例之晶片保險絲比較不會不易炫斷。換 «之，材貝例如為金鉑合金、金銘合金或純金的緩衝層可 有效控制第二導電層擴散至第一導電層的擴散啟動機^。 二、由於本發明之實施例之隔熱層可完全覆蓋基板之 表面且熱傳導率低，所以，與習知技術相較，本發明之實 施例之隔熱效果較好。 雖然本發明已以實施例揭露如上，然其並非用以限定 U 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 * 【圖式簡單說明】 圖1緣示一種習用晶片保險絲的剖面示意圖。 圖2繪示本發明第一實施例之晶片保險絲的剖面示意 18 200919520 κυ-υ/4-ι w z4170twf.doc/n 圖。 圖3A至圖3H繪示圖2之晶片保險絲之製作流程的 剖面示意圖。 圖4繪示本發明第二實施例之晶片保險絲的剖面示意 圖。 圖5A至圖5B繪示圖4之隔熱層之製作流程的剖面示 意圖。 〃 【主要元件符號說明】 10 .晶片保險絲 11 :基板 11a、lib、11c :表面 12 隔熱層 14 第一導電層 15 緩衝層 16 第二導電層 17 保護層 18 背面電極 19 端面電極 200、400 .晶片保險絲 210、410 :基板 212、214、216、222、412、422 :表面 220 :背膠銅箔 220a、420 :隔熱層 19 200919520 / a w ζ·4170ίΛνί·(1〇€/ΐ1 220b :銅箔層 220c :膠體層 230、430 :第一導電層 240、450 :第二導電層 250、460 :保護層 260、440 :缓衝層 270、470 :背面電極 280、480 :端面電極 290、490 :電鍍種子層 420a ·隔熱材料層As described above, the wafer fuse of the present invention and the method of fabricating the same have at least the following advantages: A. Since the heat insulating layer of the embodiment of the present invention is in contact with the first conductive layer, the surface is a rough surface, The adhesion between the first conductive layer and the heat insulating layer is better, and the first conductive layer will be less likely to fall off. P. The material of the buffer layer of the embodiment of the present invention may be gold-platinum alloy, silk alloy or pure gold and its melting is low. Here, it is not easy to smash the wafer fuse of the embodiment of the present invention. In other words, the material such as gold platinum alloy, gold alloy or pure gold buffer layer can effectively control the diffusion of the second conductive layer to the first conductive layer. Second, since the heat insulating layer of the embodiment of the present invention can completely cover the surface of the substrate and has low thermal conductivity, the heat insulating effect of the embodiment of the present invention is better than that of the prior art. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. * [Simple Description of the Drawings] Fig. 1 is a schematic cross-sectional view showing a conventional wafer fuse. 2 is a cross-sectional view of a wafer fuse according to a first embodiment of the present invention. 18 200919520 κυ-υ/4-ι w z4170twf.doc/n. 3A to 3H are schematic cross-sectional views showing the fabrication process of the wafer fuse of FIG. 2. Fig. 4 is a cross-sectional view showing the wafer fuse of the second embodiment of the present invention. 5A to 5B are schematic cross-sectional views showing a manufacturing process of the heat insulating layer of Fig. 4. 〃 [Main component symbol description] 10. Chip fuse 11: substrate 11a, lib, 11c: surface 12 heat insulation layer 14 first conductive layer 15 buffer layer 16 second conductive layer 17 protective layer 18 back surface electrode 19 end surface electrodes 200, 400 Wafer Fuse 210, 410: Substrate 212, 214, 216, 222, 412, 422: Surface 220: Backing Copper Foil 220a, 420: Thermal Insulation Layer 19 200919520 / aw ζ·4170ίΛνί·(1〇€/ΐ1 220b: Copper foil layer 220c: colloid layer 230, 430: first conductive layer 240, 450: second conductive layer 250, 460: protective layer 260, 440: buffer layer 270, 470: back surface electrode 280, 480: end surface electrode 290, 490: plating seed layer 420a · insulation layer
2020