TW200919476A - Non-volatile storage with source bias all bit line sensing and the related method therefor - Google Patents

Abstract

A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

Description

200919476 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory. This application is related to the commonly assigned U.S. Patent Application Serial No.: "Method for Sensing Negative Threshold Voltages In Non-Volatile Storage Using Current Sensing" SAND-1233USl/SDD-1123), titled "Non-Volatile Storage With Current Sensing of

US Patent Application No. _ (File No. SAND-1233US2/SDD-1123), titled "Method for Current Sensing With Biasing Of Source And P-Well In Non-Volatile Storage, US Patent Application No. 5, Negative Threshold Voltages " Case No. (File No. SAND-1241US1/SDD-1126), titled "Non-Volatile Storage using Current Sensing With

Biasing Of Source And P-Well, US Patent Application No. _ (File No. SAND-1241US2/SDD-1126), entitled "Method for Source Bias All Bit Line Sensing in

Non-Volatile Storage, US Patent Application No. (File No. SAND-1242US0/SDD-1127), entitled "Non-Volatile Storage with Source Bias All Bit

Line Sensing, US Patent Application No. _ (File No. SAND-1242US1/SDD-1127), entitled "Method For Temperature Compensating Bit Line 132483.doc 200919476

During Sense Operations In Non-Volatile Storage" US Patent Application No. __ (File No. SAND-1243US1/SDD-1128), and titled "Non-Volatile Storage With Temperature Compensation For Bit Line During Sense Operations" US Patent Application No. _ (File No. SAND-1243US2/SDD-1128), each of which is filed with the present application, and each of which is incorporated by reference. This article. [Prior Art]

Semiconductor 3 memories have become increasingly popular in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Electrically erasable and programmable read-only memory (EEpR〇M) and flash memory are the most popular non-volatile semiconductor memory. In the case of flash memory (also type-type EEPROM), the contents of the entire memory array or a portion of the memory can be erased in one step in contrast to conventional EEPROMs having all features. Both the conventional EEPROM and the flash memory utilize a floating gate I floating gate (4) positioned above and insulated from the channel region in the semiconductor substrate between the source region and the (four) region. The control gate is provided on and insulated from the floating gate. The voltage (Vth) of the thus formed transistor is controlled by the amount of charge remaining on the flip gate. That is, the minimum amount of voltage applied to the control gate before the transistor is turned on to allow conduction between the source and the drain of the transistor is controlled by the charge level on the floating gate. - some EEPROM and flash, hidden | 'used to store two charges 132483.doc 200919476 car's annual gate, and therefore, memory, such as 舳 1 / , va body parts can be in two states (Example: Prepare one ~ broadcast μ - heart) between stylized / erased. Because the memory component can store a data 彳ίτ-ΐ f ;# 拄1 U β , bucket position 70, so this flash memory device is sometimes called a binary flash memory device called multi-level Flash memory is implemented by recognizing multiple/effective/programmed threshold voltage ranges. Each distinct L-limit voltage range corresponds to a set of encoded data bits in the 穿 body 隐 hidden device

Pre-existing value. For example, when each parent can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges, the component can store two data bits. . Usually, the stylized voltage vPGM# applied to the control gate during the stylization operation is applied as a series of pulses whose magnitude increases with time. In one possible method, the magnitude of the pulse is increased by a predetermined step with each successive pulse of 例·2-0.4 v. VpGM can be applied to the control gate of the flash memory component. During the period between the stylized pulses, a verification operation is performed. That is, the programmed level of each of a group of components that are programmed in parallel is read between successive stylized pulses to determine whether the programmed level is equal to or greater than the verify level to which the component is programmed. ◎ For multi-state flash memory device arrays, a verification step can be performed for each state of the component to determine if the component has reached its verification level associated with the data. For example, a multi-state memory element capable of storing data in four states may need to perform a verify operation for three comparison points. In addition, when programming an EEPROM or flash memory device (such as a NAND flash memory device in a NAND string), VpGM is typically applied to the control terminal and the bit line is grounded, thereby Electrons of the channels of the cells or memory components (eg, 'storage components') are injected into the floating gates. When electrons accumulate in the oceanic gate, the floating gate becomes negatively charged and the 6a voltage limit of the memory element rises so that the memory element is considered to be in a programmed state. Available under the heading "s〇urce Side Self B〇〇sting

Technique For Non-Volatile Memory, US Patent 6,859,397 and February 3, 2005, titled "Detecting

Further information on this stylization can be found in U.S. Patent Application Publication No. 2/5/24,939, the disclosure of which is incorporated herein in its entirety by reference. SUMMARY OF THE INVENTION The present invention provides a non-volatile storage device having the ability to sense stylized conditions of a non-volatile storage element using full-scale 7L line sensing.

In one embodiment, a non-volatile storage system includes a set of non-volatile storage elements configured as a string of octaves, wherein each of the NAND strings is associated with a respective bit line, The individual sensing components are associated with a respective discharge path. - or multiple (four) circuits communicate with the woven non-volatile storage elements. The or the control circuit: (1) during a first time period: (a) applying a source voltage to each of the NAND strings - source, (b) preventing each individual bit line Coupled to the respective sensing components and (〇) coupled to the parent bit tl line to the respective discharge path; and (2) during the first time period following the first time period '(a) continues Applying the source voltage to the source of the NAND string allows the parent-specific bit line to be coupled to the respective sensing component of 132483.doc 200919476.

In another embodiment, a non-volatile storage system includes a collection of non-volatile storage elements configured as NANDt, wherein each of the NAND strings and a respective bit line, a respective sensing component And a respective one or more control circuits associated with the respective discharge paths are in communication with the set of non-volatile storage elements. Or the control circuit: (4) applying a source voltage to one of each of the NAND strings such as hai, '(8) coupling each bit line to the respective discharge path, and (c) After coupling, a stylized condition of one of the selected non-volatile storage elements is determined based on the potential of each of the respective bit lines. In another embodiment, the non-volatile storage system includes: a first set of non-volatile storage elements associated with a bit line and a respective discharge path, and a second bit line and a a second set of one of the volatile storage elements associated with the discharge path; and one or more control circuits in communication with the first set and the second set of non-volatile storage elements. The control circuit or the like: (a) applying a source voltage to a source of the first set of storage elements '8) purely the κ line to the respective discharge paths such that a voltage is applied when the source voltage is applied The first set of storage elements are capacitively coupled to the potential of the second set of storage elements to be at least partially discharged, and (c) after the potential is at least partially discharged, one of the second set of elements is determined A stylized condition for one of the non-volatile storage elements is selected. [Embodiment] It has the ability to use all-synthesis conditions. The present invention provides a non-volatile storage device for bit line sensing to sense non-volatile storage elements. One example of a memory system suitable for use in practicing the present invention uses a NAND flash memory structure that includes a plurality of transistors arranged in series between two select gates. The series connected transistors and the select gates are referred to as NAND strings. Figure 1 is a top plan view showing a NAND string. Figure 2 shows the equivalent circuit of the NAND string. The NAND string depicted in Figures 1 and 2 includes four transistors 100, 102, 104, and 106 that are connected in series and sandwiched between a first select gate 120 and a second select gate 122. The gate 120 gate NAND string is connected to the bit line 126. The connection of the gate 122 gated NAND string to the source line 128 is selected. The selection gate 2 is controlled by applying an appropriate voltage to the control gate 丨 20CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 has a control gate 1 CG and a floating gate 100FG. The transistor 1〇2 includes a control gate 1〇2CC} and a floating gate 102FG. The transistor 1〇4 includes a control gate 1〇4CG and a floating gate 104FG. The transistor 1〇6 includes a control gate 1〇6C(} and a floating gate 106FG. The control gate i〇OCG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, and the control gate 1〇4CG Connected to word line WL1, and control gate 106CG is coupled to word line WL. These control gates may also be provided as part of the word it line. In the embodiment, transistor 1〇〇, 102 Each of 104, 106 and 106 is a storage element (also referred to as a memory unit). In other embodiments, the storage element may comprise a plurality of transistors or may be different from the storage elements depicted in Figures 1 and 2. The selection interval 12 is connected to the selection line SGD (drain selection gate). The selection gate 122 is connected to the selection line 132483.doc • 12-200919476 SGS (source selection gate). Figure 3 is a circuit diagram depicting three NAND strings. A typical architecture of a NAND-structured flash memory system would include several NAND strings. For example, three NAND strings 320, 340, and 3 60 are shown in a memory array with more NAND strings. Each of the strings includes two selection gates and four storage elements. Although for the sake of simplicity Four storage elements are illustrated, but modern NAND strings can have up to, for example, 32 or 64 storage elements. 1 : For example, NAND string 320 includes select gates 322 and 327 and storage elements 323-3 26, NAND string 340 Including select gates 342 and 347 and storage elements 343-3 46, NAND string 360 includes select gates 362 and 367 and storage elements 363-366. Each NAND string is selected by its gate (eg, select gates 3 27, 3 47 or 3 67) is connected to the source line. The selection line SGS is used to control the source side selection gate. The various NAND strings 320, 340 and 360 are connected by selecting the selection transistor in the gates 3 22, 3 42 and 3 62 Up to the respective bit lines, 321 , 341 and 361. The selected transistors are controlled by the drain select line SGD. In other embodiments, it is not necessary to use the select lines in common between the NAND strings; that is, Different NAND strings provide different select lines. Word line WL3 is connected to the control gates of storage elements 323, 343 and 363. Word line * WL2 is connected to the control gates of storage elements 324, 344 and 364. Word line WL1 Connected to the control gates of storage elements 325, 345, and 365. Word line WL0 is connected to The control gates of elements 326, 346, and 366 are stored. As can be seen, each bit line and each NAND string includes an array or set of rows of storage elements. The word lines (WL3, WL2, WL1, and WL0) comprise an array or Set 132483.doc -13 - 200919476. The list. Each word line is connected to one pole. Or the 'control gate' can be provided by the hold-by-make, the control gate WL2 of the parent-storage component. For example, there can be thousands of words on the :: meta line: = control open. Practice Digital data: = material. (10) Words, when storing one element in two ranges, it is said to be able to limit the power (Vth) to the flash memory - instance order, v ^ material Μ" and "〇". It is defined as logic "". The second TH is negative after erasing the storage element, and the logic is "〇". When the Vth after the v_ is positive and defined as the negative of the field and the reading is attempted, The storage component will be connected and rained to indicate that the logic "" is being stored (4)... When the cow will be turned on, the storage component will not be turned on, and the pattern will be read, for example, multiple digit data bits. If four information levels are stored, the number of :: (4) is assigned to the data value ||-,,," two =^ U1 and 00. The % after the erase operation in the NANE^ memory instance is negative and is defined as "11". Positive VTH values are used for status "1〇", 〇1" and "〇〇. The specific relationship between the data that is programmed into the storage element and the threshold voltage range of the component depends on the data encoding mechanism used by the storage component. For example, U.S. Patent No. 6,222,762 and U.S. Patent No. 5, the entire disclosure of which is incorporated herein by reference. Examples of NAND-type flash memory are provided in U.S. Patent Nos. 5,386,422, 5,522,580, 5,570,315, the disclosure of which are incorporated herein by reference. And its operation, each of which is incorporated herein by reference. When the flash storage component is programmed, a programmed voltage is applied to the control gate of the storage element and the bit line associated with the storage component is grounded. The electrons from the channel are injected into the floating gate. When electrons accumulate in the floating pole, the floating gate becomes negatively charged and the Vth of the storage element rises. To apply a programmed voltage to the control gate of the memory element being programmed, the stylized voltage is applied to the appropriate word line. As discussed above, one of the storage elements in each of the NAND strings shares the same word line. For example, when the storage element 324 of Figure 3 is programmed, a programmed voltage is also applied to the control gates of storage elements 344 and 364. 4 depicts a cross-sectional view of a NAND string formed on a substrate. This view is simplified and not to scale. The NAND string 400 includes a source side select gate 406, a drain side select gate 424, and eight storage elements 4A, 410, 412, 414, 416, 418, 420, and 422 formed on the substrate 490. A number of source/drain regions (one of which is source/drain region 430) are provided on either side of each of the storage elements and select gates 406 and 424. In one method, substrate 490 employs triple well technology that includes p-well region 492 within n-well region 494, which in turn is within p-type substrate region 496. The NAND string and its non-volatile storage elements can be formed at least partially on the p-well region. A source supply line 404 having a potential VsouRCE is provided in addition to the bit line 4 26 having a potential V B L . In one possible approach, a voltage can be applied to P well region 492 via terminal 402. The voltage can also be applied to the n-well region via the terminal 403 132483.doc -15- 200919476 494. During a read or verify operation (including an erase_verify operation) (the condition of the storage element, such as its threshold voltage) is determined during this period, Vcgr is provided on the selected word line associated with the selected storage element. . In addition, it can be recalled that the control gate of the storage element can be provided as part of the word line. For example, WL0, WL1, WL2, WL3, WL4, machine 5, machine 6 and WL7 may extend via control gates of storage elements 4〇8, 41〇' 412, 4l4, 4i6, 418, 420 and 422, respectively. . In a possible boosting mechanism, the read pass voltage Vread can be applied to the unselected word lines associated with the NAND string 4A. Other boosting mechanisms apply the ¥^ heart to some of the word lines and apply a lower voltage to the other word lines. Vsgs and VsGD are applied to select gates 406 and 424, respectively. Figures 5a through 5d depict the stylization of non-volatile storage elements. In one possible stylization technique, the lower, middle, and upper pages are stylized in the three steps depicted in Figures 5a, 5b, and 5c, respectively. Two Vth distributions 510 and 512 are provided when the lower page of the data is programmed after the erase operation. The minimum distribution 510 represents an erased state and has a negative Vth. Next, the first Vth knife cloth 520 and the second γΤΗ distribution 522 of FIG. 5b are respectively obtained from the first γΤΗ distribution 51〇 of FIG. 5a, and the third VTH distribution of FIG. 5b is obtained from the second VTH distribution 512 of FIG. 5a, respectively. 524 and fourth VTH distribution 526. From the first Vth distribution 52 of Figure 5b, the first VTH distribution and the second Vth distribution of Figure 5c representing the final erased state e and the first programmed state A, respectively, are obtained. From the second Vth distribution 522 of Figure 5b, the third VTH distribution of Figure 5c and the fourth Vth distribution 132483.doc -16.200919476, respectively, representing the second programmed state b and the second programmed state C are obtained. From the third Vth distribution 524 of Figure 5b, the fifth detonation distribution and the sixth VTH distribution of Figure 5c representing the fourth programmed state D and the fifth programmed state E, respectively, are obtained. From the fourth Vth distribution 526 of Fig. 5b, the seventh γη distribution and the eighth vTH distribution of Fig. 5c representing the sixth programmed state F and the seventh programmed state G, respectively, are obtained. In addition, the code words 1U, 011, 〇〇1, 1〇1, 1〇〇, 〇〇〇, 〇1〇, and no may be associated with the state E, respectively. States E and A are examples of negative threshold voltage states. Depending on the implementation, one or more states may be a negative threshold voltage state. Figure 5c also depicts a verify voltage for obtaining the indicated distribution. Specifically, the verification voltages vVE, VvA, VvB, Vvc, Vvd, Vv, and VVG are associated with the distributions E, A, B, c, D, and E, respectively, and are compared to a given period during the process 2 The threshold voltage of the distributed storage element and the associated verification voltage. The storage element receives the stylized pulses via the associated word line until the threshold voltage of the elements is verified to have exceeded the associated verification battery. Figure 5d depicts A read voltage for reading the programmed state of the storage element. After the storage element has been programmed, it can be read using the read voltages I, RB VRC, Vrd, Vre, VRF, and Vrg. One or more storage elements associated with the common sub-line and each read power, whether the threshold voltage of ** / 丄 70 of this I! exceeds the read voltage, and can be followed by the highest The voltage is read to determine the state of the storage element. The read voltages are provided between adjacent states. The stylized process of privacy is a possible example, as other parties are possible in the law of 1264.doc 200919476. Current sensing of the electric show 2 volatile storage In the setting (including the use of the excitation D semaphore storage device), Μ平 says ^., ,, is used to sense the negative threshold of the non-volatile storage element during the reading or inspection: The voltage state of the ~, the method has been used for voltage sensing, but it has been found that the need to complete: 1 In addition, due to bit line to bit line capacitance coupling and other effects 'electrical sensing is not suitable for simultaneous Sense of execution of adjacent storage element groups: then: full bit line sensing. - Possible solutions include: when using current sensing 'adjust the source voltage and ρ well pressure to a fixed positive during sensing The DC level, and the associated gate of the storage element is connected to a potential lower than the source and the pu well voltage via the associated word line of the sensed storage element. The component voltage and the ρ well voltage may also be different. This method of combining the source and the well's bias voltage to a fixed potential may use current sensing sensing—or multiple negative threshold voltage states. In addition, 'because current sensing avoids electricity ί.” Measuring many shortcomings, so it is compatible with the full bit line sense Figure 6a depicts one configuration of a NAND string and components for sensing. In a simplified example, 'NAND string 612 includes four storage elements that communicate with word lines WL0, WL1, WL2, and WL3, respectively. 'Additional storage elements and word lines can be used. Additionally, additional NAND strings are typically placed adjacent to each other in blocks or other sets of non-volatile storage elements (see, for example, Figure 14). The storage elements are coupled to the substrate. ρ well region. In addition to the sensing component 600, a bit line 610 having a voltage vBL is depicted. In detail, the BLS (bit line sensing) transistor 606 is bonded to the bit line 610 〇 BLS transistor 132483.doc -18· 200919476 Body 606 is a high voltage transistor and is turned on in response to control 608 during a sensing operation. The BLC (bit line control) transistor 6〇4 is a low electrical piezoelectric crystal that is turned on in response to control 608 to allow the bit line to communicate with the current sensing module 602. A capacitor in the current sensing module 6〇2 during a sensing operation (such as a reading or verifying operation) is charged in the operation. The BLC transistor 604 can be turned on to allow for pre-charging. Also during the sensing operation, for a storage element having a negative threshold voltage state, a positive voltage is applied to the word line of one or more of the storage elements involved in the operation. Since a negative charge pump is not required to provide a negative word line voltage, it is advantageous to use a positive voltage for the selected word line in sensing operations that sense negative threshold voltages. Incorporating a negative charge pump into many non-volatile storage systems may require extensive process research and modification. For example, 'assuming the selected word line is WL1. The voltage on WL1 is coupled to the control gate of the storage element on the word line as a control gate read voltage VCGR. Alternatively, a positive voltage VS0URCE can be applied to the source side of the NAND string 630 and a positive voltage Vp_WELL can be applied to the p-well. In an implementation, VS0URCE and VP-WELL are larger than VCGR. VS0URCE and Vp_WELL may be different from each other' or they may be coupled to the same DC voltage VDC. In addition, VDC>VCGR. As an example, the VDC can be in the range of about 〇·4 to 1.5 V, for example, '0·8 V. A higher VDC causes a more negative threshold voltage state to be sensed. For example, the first negative threshold voltage state vTH1 = -i.o v and the second negative threshold voltage state Vth2 = _0 5 V can be sensed using VDC = 1.5 V and VDC = 1.0 V, respectively. Vdc can be set to 'one bit' to make V"dc_Vth> 〇 V. Typically, to sense the negative threshold voltage, the word line and source voltages are set such that the gate-to-source voltage of the gate 132483.doc -19-200919476 is less than zero, that is, VGS<〇 V. If the gate-to-source voltage is greater than the threshold voltage of the storage element (i.e., VGS > VTH), then 70 of the selected stores are conducted. To sense the positive threshold voltage, the source and P wells can be held at the same voltage while the selected word line voltage is adjusted.

On the drain side of NAND string 630, BLS transistor 610 is turned on, for example, to conduct or turn it on. Additionally, a voltage VBLC is applied to the BLC transistor 604 for conduction. The pre-charge capacitor in current sensing module 6〇2 is discharged into the source via a bit line such that the source acts as a current sink. The precharge capacitor at the drain of the nand string can be precharged to a potential that exceeds the potential of the source such that when the selected storage element is in a conducting state, current flows through the selected non-volatile storage element and sinks into the source in. In particular, a relatively high current will flow if the selected storage element is at the conduction center due to the application of VCGR. If the selected storage element is in a non-conducting state, no current or relatively small current will flow. The electrical influenza module 602 can sense the unit/storage component current. In one possible method, the current sensing module determines a voltage drop that is related to the - fixed current by the relationship Δ V 1 t/C, where is the voltage drop, and 1 is the fixed current 't is predetermined. Time period and. It is the electric valley of pre-charging electricity in the current sensing module. See also Figure 6d, which depicts the voltage drop over time for different fixed current lines. A higher voltage drop indicates a higher current. At the end of a given discharge cycle, because of the W, the Δν of a given current can be determined. In one method Φ, makeup _ τ uses a P-mos transistor to determine the level of AV relative to the demarcation value. In another possible method, the cell current discriminator acts as a current bit by determining whether the conduction current is above or below the delimited current. 13243.doc • 20- 200919476 The discriminator or comparator. In contrast, voltage sensing does not include sensing the voltage drop associated with a fixed current. Alternatively, voltage sensing includes determining whether charge sharing occurs between the capacitors in the voltage sensing module and the capacitance of the bit lines. The current is not fixed or constant during sensing. When the selected storage element conducts, little or no charge sharing occurs, in which case the voltage of the capacitor in the voltage sensing module does not decrease significantly. When the selected storage element is not conducting, charge sharing occurs. Under this condition, the voltage of the capacitor in the voltage sensing module drops significantly. The electric "il sensing module 602 can therefore determine the selected storage element in a conducting or non-conducting state by the level of current. Typically, a higher current will flow when the selected storage element is in a conducting state, and a lower current will flow when the selected storage element is stored in a non-conducting state. When the selected storage element is in a non-conducting or conducting state, its threshold voltage is above or below a comparison level (such as verifying the level (see Figure 5c) or reading the level (see Figure 5d)). Figure 6b depicts the waveform associated with Figure 6a. Waveform 620 depicts vS0URCE and VP.WELL, VBL, and VBLC. The vS0URCE and VP-WELL are set to an elevated level at t1 during the sensing operation. In a method, such as when the sensing operation includes negatively controlling the electric dust, VsOURCE and Vp-WELL exceed VCGr. However, for example, when the sensing operation includes a positive threshold voltage, vS0URCE and VP-WELL do not have to exceed VCGR. vBL increases with VSOURCE between tl and t2. The pre-charge capacitor is discharged at t2', which in turn increases vBL. Thus, the drain potential associated with the selected non-volatile storage element (e.g., 132483.doc -21 - 200919476 V B L) is higher than the source potential associated with the selected non-volatile storage element (e.g., 'VS0URCE). The vBLC tracks the vBL, but is slightly higher due to the threshold voltage of the BLC transistor. In practice, after the rise, if the current flows in the NAND string, Vbl will drop slightly (not shown). For example, when VBLC = 2 V and the threshold voltage of the BLC transistor is } v, Vbl can rise to 1 v. When sensing, if current flows, Vbl can drop from 丨V to (e.g., 0·9 V). Wave Open > 622 depicts a voltage applied to the BLS transistor, which indicates that the electrical sa body is conducting between t0 and t5. Waveform 624 depicts a sense signal that is a control signal that indicates the time t after the electric grid begins to discharge in the current sensing module. Waveforms 626 and 628 depict the sense voltage of the selected bit line, which is associated with a fixed current. A determination can be made at t3 as to whether the voltage exceeds a certain level. It can be concluded that when the voltage drops below the delimiter level (e.g., line 628), the selected storage element conducts. If the voltage does not fall below the delimiter level (eg, line 626), the selected storage element is not conducting. Figure 6c depicts the sensing process associated with Figures 6a and 6b. Provide an overview of the sensing process. In this and other flow charts, the steps depicted are not necessarily taken as discrete steps and/or in the order described. At step 64, a sensing operation such as a read or verify operation is initiated. Step 642 includes opening the BLS transistor and the BLC transistor to precharge the bit line. Step 644 includes setting the word line voltage. Step 646 includes setting Vs 〇 URCE & VpwELL. Step 648 includes using current sensing to determine whether the storage element is conductive or non-conductive. If, at decision step 650, another sensing operation is to be performed, then control flow continues at step 64. Otherwise, the process ends at step 652. 132483.doc -22- 200919476 Multiple sensing operations can be performed continuously ^ 乍 For example, for each verification or reading operation. In a method φ .. π ^ , , the applied source voltage and the well voltage are applied in each sensing operation, but A _ m , ' 疋 予 予 。 。 。 。 。 。 。 。 。 。 。 Thus, in a first sensing operation, the control gate/character of the storage element: will, for example, be applied to the selected line' to apply the source voltage to the source. The P well voltage is applied to the p-well. Then, at the application of the first voltage and the source = Γ:, current sensing is used to determine whether the storage element is in conduction I or not. - The second sensing operation comprises applying a second source voltage to the control gate while applying the same source dust and the same day. A determination is then made as to whether the storage element is in a conducting state or a non-transducing heart. Although the same source voltage and P-well voltage are used, the continuous sensing operation can be similar to the selected word line voltage. ϋ In addition, T performs sensing on the same storage device as the plurality of storage elements associated with the common word 1 line and source. The plurality of storage elements can be in adjacent or non-adjacent strings. The full bit line sensing described in the first 4 includes simultaneous sensing of the stored items in the adjacent AND string. In this case, sensing includes determining whether each of the non-volatile storage elements is in a conductive state or a non-conducting state in a simultaneous sensing operation using motor sensing. Current sensing with source and sink bias voltages in non-volatile storage devices (including non-volatile storage devices using NAND memory design) 'current sensing can be used during read or verify operations The threshold voltage state of the non-volatile storage element is measured. However, this current sensing has caused a change in the source voltage or "jump", especially at ground voltage. The degree of bounce depends on the level of current through the storage element. This 132483.doc •23· 200919476, bounce can cause sensing errors. A method of controlling the source of the cell during the sensing period is to sense using at least two gates. This minimizes the effect of cell source bounce. For example, in the case of current sensing, the current in the NAND string of the selected storage element can be sensed at the # strobe from control. A relatively high or otherwise inaccurate bounce current may occur at the first gating, while a lower current is at the second gating (four), wherein the lower current more accurately represents the storage element 然而n, however, using additional gating Waiting for current stability requires additional current and sensing time. Referring to Figure 7a, the current and voltage as a function of time due to ground bounce during sensing operation are depicted. Another technique is to couple the source to the gate and drain of the storage element. However, this technique is cumbersome, requires additional circuitry, and has an impact on the grain size and power consumption of the memory chip. Moreover, this technique can not work well due to the Rc delay from the source to the gate of the storage member. Upper: The general approach to avoiding these shortcomings is to adjust the source and p wells to a certain fixed positive DC level during sensing, rather than ground. By keeping the source and p wells at a fixed DC level and avoiding bouncing in the source voltage, we can use only one strobe to sense the data. As a result, the sensing time and power consumption are reduced by v. In addition, a large amount of additional circuitry is not required, so the grain size is not adversely affected. It is also possible to ground the P well while adjusting the source voltage to a fixed positive DC level. Adjusting the source voltage to a fixed positive Dc level is easier than adjusting the source voltage to ground because the regulation circuit only needs to sense a positive voltage. The regulator is usually adjusted by the comparison of the monitoring level based on (for example, the source) with the internal reference voltage. 132483.doc -24- 200919476 =. When the right monitor level falls below the internal reference voltage, the voltage regulator can increase its turn-out. Similarly, if the monitor level is increased above the internal reference voltage, the voltage regulator can reduce its output. For example, an op amp can be used with a voltage regulator. However, if the reference voltage is grounded, the 'f voltage regulator typically cannot reduce its output below 〇v if the monitor level becomes greater than G V . In addition, the voltage regulator may not be able to distinguish the monitoring level below 〇 v. Therefore, adjusting the source voltage to a fixed positive DC level avoids ground bounce and reduces current consumption and sensing time. Referring to Figure 7b, there is depicted a decrease in current and voltage as the source voltage is adjusted to a fixed positive DC level during the sensing operation. Figure 7c depicts another configuration of a NAND string and components for sensing. This configuration corresponds to the configuration provided in Figure 6a, except that the voltage regulator 720 is depicted. As mentioned, the source voltage and the p-well voltage can be adjusted to a fixed positive DC level during the sensing operation. During a sensing operation of the storage element, such as a read or verify operation, a voltage is applied to the word line of one or more storage elements involved in the operation. For example, suppose the selected word line is WL丨. This voltage is coupled to the control gate of the storage element on the word line as a control gate read voltage VCGR. Alternatively, a fixed DC voltage can be applied as the source voltage VS0URCE & p well voltage VP-WELL to the source side of the string 612 and the p-well. In one implementation, when the threshold voltage is negative, Vcgr may be positive, and vS0URCE and vP-WELL may be greater than Vcgr. In one implementation, the vCGR may be greater than VsoURCE and Vp WELL when the threshold voltage is positive. Vs〇urce and Vp-WELL may be different from each other' or they may be coupled to the same DC voltage VDC. As an example of 132483.doc -25-200919476, V λ-t- 欣 DC can be adjusted by voltage regulator 720 to within about 0.4 to 1.2 ( (e.g., 〇.8 V). As discussed previously, accurate sensing can be achieved by using the gates due to the source and the voltage. In addition, I pump / J lamp full bit line sensing (in which the storage element associated with all bits is sensed) (see Figure (4). In detail, the voltage regulator can receive a reference voltage Vref, s〇urCE (which is used to adjust VS0URCE to a level greater than 0 V) and — reference voltage Vref'p.well (which is used to adjust the p-well voltage to a level greater than or equal to 〇v). The sensing process associated with Figures 7a through 7c is also depicted. The sensing operation, such as a 4-take or verify operation, begins at step 700. The steps include opening the BLS transistor and the BLC transistor and pre-charging the bit line. Step (4) 4 Including setting the word line voltage. Steps 7〇6 include adjusting V—and VP·− to a positive DC level. Step 7〇8 includes using current sensing to determine whether the selected storage element is conductive or non-conducting. In 71(), if there is another sensing operation, the control flow continues in step 7. Otherwise, the process ends in step 712. Additionally, as discussed earlier, the common word line and source can be paired with The associated plurality of storage elements simultaneously perform a sensation j. The multiple storage elements may be adjacent or In the adjacent NAND string, in this case, the sense (4) includes using current sensing to determine whether each of the non-volatile storage elements is in a conductive state or a non-conducting state in a simultaneous sensing operation. For each sensing operation The voltage is adjusted as discussed. Source Polarity Full Bit Line Sense Full Bit Line Sensing includes performing a sense of the stored elements in the adjacent NAND strings 1234.doc • 26 · 2009 19476 (see Figure 14). A potential sensing method uses DC snubber current to cause the charge on the fixed capacitance in the sensing module to be in a fixed period of time: to convert the threshold voltage value of the storage element into a digital data format. This requires a relatively large current sinking into the source side of the NAND string. Additionally, as previously discussed, to sense the negative threshold voltage value, a bias voltage can be applied to the source using the analog voltage level and P. Both wells avoid the need for a negative sub-wire voltage and a negative charge system. However, since full-bit line sensing is very sensitive to source bias 4, it is necessary to maintain analog voltage levels - relative Larger voltage The device and source voltages are evenly distributed into the array. This can increase the required device area. As discussed previously, another method of full bit line sensing uses voltage sensing because there is no DC to the source side. Current, so this method does not require a voltage regulator. However, due to the bit line-to-bit line coupling noise, this method cannot simultaneously successfully sense each bit line. Alternatively, given Time (for example, in parity sensing (see Figure 14)), only every other bit line is sensed. Therefore, from the sensing time, the performance is not optimal. In other words, depending on the proximity • Strings are very close and all-bit sensing is problematic. Capacitive coupling can occur, especially from the NAND string in which the selected storage element conducts to the coupling of the nand string in which the selected storage element is not conducting. The bit line voltage of the NAND string in which the selected storage element is not conducted is thereby increased, thereby interfering with the sensing operation. This capacitance is depicted by a capacitance 813 from a neighboring π line. Adjacent bit lines/NAND strings can be directly adjacent or non-contiguous. The capacitive coupling from adjacent bit lines/NAND strings is the strongest, but some electricity from non-adjacent bit lines/NAND strings can also occur. 132483.doc •27· 200919476 Also described is a capacitor 8 11 to ground. To overcome these problems, sensing can be performed using the mechanism as depicted in Figure 8a. Figure 8a depicts the configuration of the NAND string and components, including the current discharge Z-path. In a simplified example, NAND string 812 includes four storage elements that are in communication with word lines WL0, WL1, WL2, and WL3, respectively. In practice, β uses additional storage elements and word lines. In addition, the extra (four) side strings ^ blocks or other sets of non-volatile storage elements are usually arranged adjacent to each other. The it piece (4) will be stored to the ρ well area of the substrate. In addition to the sensing component 800, a bit line 81A having a voltage VBL is depicted. In particular, the initially opened or conductive BLS (Bit Line Sense) transistor 8〇6 is coupled to bit line 81A via sense node 814. The BLS transistor 8〇6 is a high voltage transistor and becomes conductive in response to control 808 during sensing operations. The initially non-conducting BLC (bit line control) transistor 8〇4 is a low voltage transistor that is turned on in response to control device 808 to allow bit line and voltage sensing module/circuit 8〇2 to pass through 5^ During a sensing operation, such as a read or verify operation, a pre-charge operation occurs in the 'voltage sensing module 8G2', in which the capacitor is charged. The BLC transistor 804 can be turned on to allow for pre-charging. / In addition, a relatively weak current pull-down device is introduced. In detail, way (4) 6 (which is part of the current discharge path of _ 〇 string 812) is interfaced to sense node 814 (which is in turn _ to bit line 810). A transistor in a conducting state (referred to as a GRS transistor 818) is provided such that the rear 816 is drained to the way #82() which is also part of the current discharge path. Parallel to paths 816, 820 provides - a current source 825 (e.g., an electric mirror) that provides current i to pull down the current on the paths to ground. In a real 2 132483.doc -28-200919476, a relatively weak pulldown with an iREF of about 150 nA is provided. However, the strength of current source 825 can vary depending on the particular implementation. In a possible configuration, current source 825 is common to multiple bit lines & NAND strings. In this case, transistor 824 couples current source 825 to a different NAND string. Path 822 carries a control signal for GRS transistor 818 that is local to a particular bit line and NAND string, while path 826 is a common ground path for a plurality of bit lines. During sensing, the bit line will be charged to a level based on the threshold voltage and body effect of the selected storage element. In the case of negative Vti, even if Vgcr = 〇 V, the storage element will still conduct. Vp_WELL can be set to 〇 V. The transistors 8 18 and 824 are made conductive to form a current discharge path and pull-down means for discharging any charge, the charge being coupled to one or more adjacent NAND strings due to capacitance 813 to adjacent bit lines To NANE^ 812. Therefore, any extra charge generated by the coupling noise of adjacent bit lines will eventually disappear. After a certain amount of time, all of the bit lines reach their DC level, and BLC transistor 804 is turned "on" to allow charge sharing between voltage sensing module 8〇2 and sense node 814, so that the selected memory is stored. Voltage sensing of the threshold voltage of the component can occur. For example, voltage sensing module 8〇2 can perform voltage sensing as part of a read or verify operation. Figure 8b depicts the configuration of the naNd string and components of Figure 8 & when voltage sensing occurs. Here, the BLC transistor 804 is turned on such that current flows from the voltage sensing module 8〇2 to the discharge path in addition to the current discharged from the NAND string 8 12 . Therefore, the GRS transistor remains in the conduction state, so that the discharge continues during the voltage sensing. 132483.doc •29- 200919476

Figure 8c depicts the waveforms associated with Figures 8a and 8b. Vsource ' is depicted at waveform 830 and the voltages on three adjacent bit lines BL0, BL1, and BL2 are depicted at waveforms 832, 834, and 836, respectively. The voltage VBLS on the BLS transistor is traced at waveform 838, and the voltage VBLC' on the BLC transistor is depicted at waveform 840 and the voltage Vgrs on the GRS transistor is depicted at waveform 842. The sensed voltages on BL0 and BL2 are depicted at waveform 844. The sensed voltage on BL1 when the selected storage element on BL1 is conducting is depicted at Waves & 846 and is sensed at waveform 848 when BL1 is selected when the selected storage element on BL1 is not conducting Voltage. As mentioned, during voltage sensing, when the selected storage element is not conducting, charge sharing between the voltage sensing module and the bit το line occurs. This charge sharing reduces the sensed voltage at the voltage sensing module. When the selected storage element conducts, little or no charge sharing between the voltage sensing module and the bit line occurs, so that the sensed voltage at the voltage sensing module remains high. Since the sensing did not occur, the sensed voltage for the other time was not depicted. At the same time, the VBLS is increased, causing the BLS transistor to conduct. At u, VS0URCE is applied as the common source voltage for one of the NAND strings. In this example, we assume that the selected bank # element associated with BL1 is not conducting when the selected storage element associated with BL0 and BL2 is being transmitted. (10) is adjacent to BU on one side, and BL2 is adjacent to Bu on the other side (see Fig. 14). Combined vs〇URCEtuf plus time, Vbl. And % will rise as depicted by waveforms 832 and 2, respectively, resulting in capacitive coupling to BL1, as depicted by the momentary increase. When it reaches t2, this face will disappear on the real f. The GRS transistor of the machine 1 is kept conducting at tl#t5 „ to allow the bit to be discharged: 132483.doc -30- 200919476 to discharge the surface-charged charge. At t3, by making the vBLC as depicted by waveform 840 Adding 61^ transistors, thereby allowing sensing of selected storage elements on BL1 to occur. Note that corresponding components associated with BL0, BL2, and other bit lines can be similarly controlled to allow for other Sensing occurs simultaneously on the bit line. For BL1, if the selected storage element is not conducting, the sensed voltage at the voltage sensing module will drop as depicted by waveform 846. On the other hand, if the selected storage element conducts The sense voltage will remain substantially high as depicted by waveform 844. The voltage sense components can use voltage breakpoints at a specified sense time 14 to determine whether the selected storage element is conductive or non-conductive. It is mentioned that if the sensed voltage exceeds the breakpoint, the indication storage element is turned on, and if the sensed voltage falls below the breakpoint, then the indication storage element is not conducting. VsojjRCE is lowered at t5 and the BLS transistor is not at t6 Conduction, And indicating the end of the sensing operation. In a possible method, the VP-WELL can be set to 〇V during the sensing. According to a specific sensing mechanism, the selected word line receives the VCGR, and the unselected word line can receive the reading. Passing voltage. Therefore, after applying the source voltage to t1, a predetermined delay of t3_tl is set to allow sufficient time or at least partial discharge of capacitive coupling from adjacent bit lines. Based on theory and / Or experimental testing, setting the appropriate delay as required for a particular implementation. After the delay, voltage sensing occurs. At the specified time t4', whether the storage element is in a conductive or non-conducting state and therefore has a higher than verification or The determination of the threshold voltage of the comparison level is read. Figure 8d depicts the sensing process associated with Figures 8a through 8C. The sensing operation begins at step 132483.doc 200919476 850 '. At step 852, the BLS transistor is turned on, At the same time, the BLC transistor remains non-conducting and pre-charges the bit line. At step 854,

* Also 疋 疋 line voltage. At step 856, vsvurce and vP_WELL (Vp*WELL = 〇 V) are set. At step 858, the bit line is discharged. At step 86, the BLC transistor is conducted to allow sensing to occur. At step 862, voltage sensing is used to make a determination as to whether the selected storage element is conductive or non-conductive. In 朿v 864, if there is another sensing operation, then control flow continues at step 850. Otherwise, the process ends at step 868. Further 'as previously discussed' may perform sensing simultaneously on the evening storage elements associated with the common word line and source. Multiple storage elements can be in adjacent or non-adjacent NAND strings. In this case, sensing includes determining whether each of the non-volatile storage elements is in a conductive state or a non-conducting state in a simultaneous sensing operation using current sensing. The delay before the BLC transistor is turned on can be set for each NAND string so that the NAND string can be discharged as needed before sensing occurs. Temperature Compensation Bit Line During Sensing Operation In the non-volatile storage device of the present invention, such as a NAND flash memory device, temperature changes cause various problems in reading and writing data. The memory device is subject to varying temperatures based on the environment in which it is located. For example, some current memory devices are rated for use between _4 〇 (5 (:: and +85). Devices in industrial, military, and even consumer applications can experience significant temperature changes. Temperature affects many electricity. Crystal parameters, the most important of which is the threshold voltage. In particular, temperature changes can cause read errors and widen the threshold voltage distribution of different states of the non-volatile storage element. The following will discuss 132483.doc • 32· 200919476 An improved technique for addressing temperature effects in non-volatile storage devices. Figure 9a depicts a NAND string and components for temperature compensated sensing. The same numbered components correspond to the components provided in Figure 8a. The current discharge path of Figure 8 & is depicted. However, the configuration of Figure 8a may be combined with the configuration of some of Figure 9a or other figures provided herein. Additionally, a temperature dependent circuit 900 is provided as control 8〇 Part 8 to provide a temperature compensated voltage to the BLC transistor 804. The BLC transistor 8〇4 has a node coupled to the voltage sensing module 802 and is consuming to the nanD string 8 12 or non-volatile Another node of the drain or bit line associated with the other set of 7L pieces. During a sensing operation, a voltage Vblc is applied to the Blc transistor 804, which will place the bits of the NAND string 8丨2 The line or drain side is coupled to the voltage sensing module 802. According to the method herein, Vblc is set based on the temperature to offset or compensate for the change of the VBL with temperature. Specifically, vBLC=vBL+vTH (independent of temperature) + Δν, where Δν is the voltage change due to temperature. Vbl also changes Δν due to temperature ^ Therefore, vBLC can be controlled such that it changes with temperature according to the change of Vbl. In detail, by using temperature dependent Circuit 900 can match Δν on the bit line to ΔV of VBLC. Current 1CELL flows in NAND string 812. The dashed line indicates charge sharing. The external voltage variation with temperature is illustrated, for example, ΔντΗ/t: The voltage of the volatile storage element decreases with increasing temperature. The change of the electrical C with respect to the degree of change can be expressed by a temperature coefficient of usually about mV / ^. / The presentity coefficient depends on various characteristics of the memory device. Set, such as doping, layout, and the like. In addition, it is desirable that the magnitude of the temperature coefficient increases as the memory size 132483.doc -33- 200919476 decreases. Often, various techniques for providing temperature compensated signals are known. For example, σ叮One or more are used in the temperature dependent circuit 900. Most of these techniques do not rely on obtaining actual temperature measurements. However, this method is also possible. For example, the title incorporated herein by reference is &quot A voltage generating circuit that outputs a read voltage to a non-volatile memory based on a temperature coefficient is described in US Pat. No. 6,8,1,454. The circuit uses a bandgap current comprising a temperature independent portion and a temperature dependent portion that increases with increasing temperature. The title of this article is incorporated by reference. " Non-Volatile Memory with Temperature_c〇mpensated

U.S. Patent No. 5, the disclosure of which is incorporated herein by reference. The title of this article, incorporated by reference, is "Multi_State eeprom

U.S. Patent No. 5,172,338, the disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all The unit provides a reference level that compares the measured current or voltage of the selected unit to the reference levels. Since the reference level is affected by temperature in the same manner as the value read from the data storage unit, temperature compensation is provided. Any of the techniques, as well as any other known techniques, can be used to provide a temperature compensated voltage to the bit line control line, as described herein. As discussed, 'Vblc is the voltage of the control signal or is provided to the BLC transistor 132483.doc • 34- 200919476 804's voltage' which allows the sensing component to sense the Vth of the selected storage element being subjected to an erase-verify or other sensing operation. Sensing via the selected storage: the bit line of the NAND string in which the piece is located Occurs. In the _ instance implementation,

VbLC = Vbl + Vth (BLC transistor). Therefore, the control is configured to increase Vblc with increasing temperature to track the increase in Vbl. Given a vTH, vBL will increase with temperature. ';:

Figure 9c illustrates the variation of VBLC and Vbl with temperature. How does the pattern V appear to increase with temperature to track the increase in VBL. Control songs that provide a specific change in temperature for VBLe may be threaded into control 8〇8 based on theoretical and experimental results' depending on the particular implementation. Typically, the bit line voltage increases as the % of the storage element decreases with higher temperatures. This means that the voltage sensing module 802 should be higher to sense a higher Vbl. Note that the Vth of the storage component dominates the vBL. However, the varying Vblc changes the voltage sensed by the voltage sensing module such that the voltage is temperature compensated. Additionally, it is noted that the variation in VTH of the BLC transistor 804 can be counteracted by providing a temperature dependent transistor similar to the BLC transistor 8〇4 in the temperature dependent circuit 900. Figure 9d depicts the waveforms associated with Figures 9 & to Figure 9c. Waveform 91 〇 depicts VS0URCE and Vp_WELL, which are set to an elevated level during the sensing operation. Waveforms 9U and 914 depict the increase in VBL due to the application of snaps (10) (3) and force. Waveform 912 depicts a higher level of VBL at a higher temperature than waveform 914. In practice, after the rise, when current flows in the NAND string, Vbl may drop slightly (not shown). Waveform 916 depicts the voltage applied to transistor BLS, which indicates that the transistor is turned "on". The waveforms 91 8 and 920 respectively depict the voltage applied to the transistor 132483.doc -35· 200919476 BLC at higher and lower temperatures. Note: • The waveforms provided are for a temperature compensation mechanism combined with the mechanisms of Figures 8a through 8d, where the opening of the germanium transistor is delayed to allow: electricity to occur prior to sensing. However, it is not required to use the temperature compensation mechanism' in this manner and it can be used in other implementations that do not involve delays in the discharge path and/or sensing. Waveform 922 depicts the sensed voltage in the voltage sensing module of the selected meta-line when the selected storage element is open, and waveform 924 depicts the sensed voltage when the selected storage element is not conducting. A determination is made at t2 as to whether the sensed voltage exceeds a breakpoint. It can be concluded that the selected storage element conducts when the sensed voltage exceeds the breakpoint, and the selected storage element does not conduct when the sensed voltage drops below the breakpoint. Figure 9e depicts the sensing process associated with Figures 9a through 9d. At step 93, a sensing operation, such as a read or verify operation, is initiated. The steps include conducting the BLS transistor and the coffee crystal, and pre-charging the bit line to set the temperature dependent VBLC. Step 934 includes setting the word line voltage, which is temperature dependent as appropriate. In one method, only the word line voltage is selected to be temperature dependent' while in other methods, some or all of the word line voltage is temperature dependent. The word line voltage can be reduced as the temperature increases due to the decrease in vTH (see Figure 9b). Step 936 includes setting VS0URCE and Vp_WELL. Step 938 includes using voltage sensing to determine whether the selected storage element is conductive or non-conductive. If it is determined at decision step 940 that another sensing operation will be performed, then control flow continues at step 930. Otherwise, the process ends at step 942. Note that 'because the sitter element on the drain side of the selected storage element is in a conducting state due to a sufficiently high voltage on the associated word line, nand 132483.doc -36 - 200919476 string no pole or bit line search a & , selects the drain of the storage element. Similarly, because the selection of the storage element is also selected, the storage element on the primary side is in a conducting state due to a sufficient voltage on the associated word line, so the source of the sacred string is stored with the 疋The source is connected. Therefore, the voltage of the pole or bit line of the nand string is basically the voltage of the drain of the selected storage element, and the source of the source of the NAND string is basically the voltage of the source of the selected storage element. The techniques described herein can be used with a single storage element so that the sensed storage elements are not necessarily in the nand string or other collection of storage elements. Additionally, as previously discussed, sensing can be performed simultaneously on a plurality of storage elements associated with a common word line and source. Moreover, from the perspective of control 808, the sensing process includes receiving information from temperature dependent circuit 900 and providing a temperature compensated voltage to the control gate of the BLC transistor in response to the information, the BLC transistor will be a nand string or a non-volatile storage element The other sets are coupled to the sensing circuit. Control may also set the word line, source and p-well voltages, and receive information from the voltage sensing module 8〇2 regarding the sensed stylized conditions of the selected storage element. Figure 9f depicts an erase-verify process. Step 95 includes erasing a set of storage elements. Step 952 includes initiating the softening of one or more of the storage elements to, for example, an erased state. Soft programming typically involves applying a voltage pulse to the selected word line to raise the threshold voltage of one or more of the storage elements on the selected word line. The voltage pulse can be a soft stylized pulse that is less in amplitude than the pulse used to program to a higher state (step 954). This type of programming can be used, for example, when the storage element is subjected to deep erasure to ensure that its threshold voltage is below IBC. Step 956 includes verifying the stylized condition of the storage element (e.g., relative to the state to be erased). For example, this verification can include performing step 932_938 of Figure 9e as discussed above. At decision step 958, if the soft programming is to continue (e.g., when the storage element has not reached the desired erase state), then control flow continues at step 954. Otherwise, the process ends at step 96. Additionally, an erase-verify operation can be performed simultaneously on a plurality of storage elements associated with a common word line and source. Figure l〇a illustrates the change in temperature of VSOURCdi|. In another method, VS0URCE is temperature compensated, for example, such that it increases with temperature. Typically, vwl = vsource + Vth (selected storage element), where Vwl is the voltage applied to the selected word line. As discussed, Vth decreases with temperature. Therefore, in the case where the vWL is fixed, the wVsgurce can be set to increase with temperature to avoid the temperature bias during sensing. In addition, in a possible implementation, a constraint can be set such that vS0URCE is only increased to a positive value. For example, if vs URCE = 0 V at baseline temperature and the temperature increases, Vs 〇 urce remains at 〇 V. If the temperature is lowered, vS0URCE is increased according to the temperature coefficient. On the other hand, if VSOURCE > 〇 V at the baseline temperature and the temperature increases, Vsource can be reduced to a value greater than or equal to 0 V (i.e., non-negative). If the temperature is lowered, then VS0URCE is added according to the temperature coefficient. Figure 10b depicts an example of a storage element array including different sets of NAND strings. Each row 'bit line 丨 006 along the memory array 1 轻 is lightly connected to the 汲 terminal 1026 of the drain select gate of the NAND string 1050. Along the column of nane^, the source line 1004 can be connected to the source selection gate of the NAND string. 132483.doc -38 - 200919476 Active Extreme Gift. Found in U.S. Patent No. 5, No. 3i5, No. and No. 046,935, 7

The instance of the architectural array and its operation take the ND to divide the storage element (four) column into a large number of (four) storage component blocks. As common to the flash PROM system, the block is the unit of erasure. Each block contains a minimum number of storage elements that are erased together. The parent-block is usually divided into many pages. The page is a stylized unit. In an example, individual pages may be divided into segments, and the segments may contain a minimum number of storage elements that are written once with the basic operation. - or multiple ί 枓 pages are usually stored in a storage element column. One page can store 2 sections. - The section includes user data and additional item information. Additional items = often include error correction codes that have been calculated from the user data for the segment). One part of the controller (described below) calculates the ECC when the data is programmed to the array order, and also checks the coffee when reading data from the array. Or: ECC and/or other additional items are stored on a different page than the user profile to which they belong or even in different blocks. The section of the user data is usually 512 bytes, which corresponds to the size of one of the sectors in the disk drive. The additional item data is usually an additional 16-20 bytes. A large number of pages form a block from, for example, 8 pages up to any number between ",", "solid" or more pages. In some embodiments, a column of NAND strings constitutes a block. In an embodiment: Erasing memory by causing P well to rise south to erase power (eg, 2G v) for a sufficient period of time while floating the source and bit lines and grounding the word lines of the selected block Body storage component. Due to the capacitance of 132483.doc -39· 200919476, the unselected word line, bit line, select line and common source (c-source) also rise to the significant part of the erase voltage. A strong electric field is thus applied to the tunnel oxide layer of the selected storage element, and the data of the selected storage element is erased as the electrons of the floating gate are emitted to the substrate side (usually by Fowler -Nordheim) tunneling mechanism. As the electron self-floating gate is transferred to the p-well region, the threshold voltage of the selected storage element is reduced. The entire memory array, individual block or another unit of the storage element can be wiped. except.

Figure 11 is a block diagram of a non-volatile cryptosystem using a single column/row decoder and a read/write circuit. The figure illustrates a "self-device 1196" having a read/write circuit for storing and storing a page in parallel, in accordance with an embodiment of the present invention. Memory device 1 丨 96 can include one or more memory dies 1198. The memory die includes a two-dimensional storage element, a car, a control circuit 111, and a read/write circuit. In some embodiments, storing an array of 1 pieces can be three dimensional. The memory array 1 ’ '7 ' is addressed by the 解码j decoder 丨 13G by the word line and via the line decimator by the bit line. The read/write circuit 1165 includes a plurality of sensing blocks 1100 = allowing parallel reading or stylization - storage of component pages. Typically, control benefit 115G is included in the same memory, 96 (e.g., removable memory card) as the or the memory die 1198. Commands and data are transferred between the host and controller 115A via line 120 and transferred between the controller and the memory die 1198 via line m8. (d) tgUH) cooperates with the read/write circuit (10) to perform a memory operation on the memory array 1000. The control circuit (1) G includes a state machine (1) 2, a 132483.doc 200919476 on-chip address decoder 1114 and a power control module 1116. Status Provides wafer level control of memory operations. The on-wafer address decoder 1114 provides an address interface between the address used by the host or memory controller to the hardware address used by the decoder U. The power control module Kawasaki 6 controls the power and voltage supplied to the word lines and bit lines during memory operation. In some implementations, certain components of Figure n can be combined. One or more of these components (except storage element array m_) # may be considered as management or control circuitry in various designs. For example, one or more of the management or control circuits can include control circuit 111, state machine (1) 2, decoder im/1160, power control (1) 6, sense block. Read/write circuit U65' controller 1150 or the like, or a combination thereof. Figure 12 is a block diagram of a non-volatile memory system using a dual column/row decoder and a read/write circuit. Here, another configuration of the memory device (10) shown in Fig. U is provided. The access to the memory array 1 by various peripheral circuits is performed on the opposite side of the array in a symmetrical manner such that the density of the access lines and circuits on each side is reduced by half. Therefore, the column decoder is divided into column decoders U30A and 1130B' and the row decoder is divided into a row decoder unit and 1160B. Similarly, the read/write circuit is divided into a read/write circuit u65A connected from the bottom of the array to the bit line, and a read/write circuit connected from the top of the array to the bit line. delete. In this way, the density of the read/write modules is substantially reduced by half. The device of Figure 12 may also include a cheat as described above for the device of Figure u. Figure 13 is a side view of the embodiment of the depiction block. : Individual Sensing 132483.doc 41 200919476 Block 1100 is divided into a core portion (referred to as sensing module 810) and a common portion 1190. In one embodiment, there will be a single sensing module 1180 for each bit line and a common portion 1190 for a collection of multiple sensing modules 1180. In one example, the sensing block will include a common portion 1190 and eight sensing modules 1180. Each of the sensing modules in the group will communicate with the associated common portion via the data bus 117. For other details, refer to the title "Non-Volatile" published on June 29, 2006.

Memory and Method with Shared Processing for an

U.S. Patent Application Publication No. 2006/014, the entire disclosure of which is incorporated herein by reference. The sensing module 186 includes a sensing circuit 117 that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. Sensing module 1180 also includes a bit line latch 1182 for setting the voltage conditions on the connected bit line. For example, latching in the pre-branch state of the bit line latch will cause the connected bit line to be pulled to indicate a stylized suppression state (e.g., vDD). The common portion U9G includes a set of processors 1192, f-fatch (10), and - an input/output interface 1196 that is interposed between the data latch 1194 set and the data bus. The processor (10) performs its function of determining (4) the information stored in the sensed storage component and storing the shaped data in the data latch to store the data in the set of the Beca latch U94. The data bit. It is also used for storage = data bits imported by the processor from the data bus (10). The data bits transferred during the operation of the data bit 132483.doc • 42· 200919476 The table is not intended to be programmed into the memory. Enter the information. 1/〇 interface I 〗 % Provides the interface between the data latch 1194 and the data bus 112 。. During reading or sensing, the operation of the system is controlled by state machine 1112, which controls the supply of different control gates to the addressed storage elements. As it steps through various predefined threshold voltages corresponding to the various memory states supported by the memory, the sensing module 118 can be tripped at one of the voltages and the output will be via the bus The ι 72 self-sensing module 1180 is provided to the processor 1192. At this time, the processor determines the state of the obtained memory by considering the tripping event of the sensing module and the information about the control applied from the state machine via the input line ιΐ93. The processor then occupies the binary encoding for the #memory state and stores the resulting data bits in the data compensator 1194. In another embodiment of the core portion, the bit line latch 1182 acts as a 镂. The tongue field and the male brother field dual use, both as a latch for latching the output of the sensing module 8' and as a bit line latch as described above. Processor 1192. In an embodiment, each I_, 2 will include an output line (not depicted) such that one of the output lines is logically ORed (4) to (10) In the second embodiment, the output line is reversed before being connected to the hardwired logic or line! The programmatic verification enables the stylized verification when the stylization process is completed to determine 6$仃&& 'Because the state machine that receives the hardwired logical OR has a bit when it has reached the desired level. For example, when the path is reached to its desired level, the logic zero of the bit is sent to the hardwired logic. Or line (or _ ^ _ rounded out the information GA - Bessie 1 is reversed). When all the bits 兀 ° information 1) 'like The state machine knows to terminate the program 132483.doc -43- 200919476. The purpose is to communicate with each of the eight test modules, so the state machine needs to read the hardwired logic or line eight times, or The logic is added to the processor 1192 to accumulate the result of the associated bit line such that the state machine only needs to read the hardwired logic or line once. Similarly, the global state machine can detect by correctly selecting the logic level. When the first bit changes its state and changes the algorithm accordingly. During stylization or verification, the data to be programmed is stored in the set of data latches 1194 from the data bus 1120. The state machine controlled program The operation includes a series of clamped voltage pulses applied to the control gates of the addressed storage elements. Each stylized pulse is followed by a readback (verification) to determine if the stored 7L pieces have been programmed to the desired memory. The state of the processor 1192 monitors the readback memory state relative to the desired memory state. When the two states coincide, the processor 1192 sets the bit line latch 1182 to cause the bit line to be pulled to indicate the program. State of suppression. Even if a stylized pulse appears on the control gate of the storage element, this inhibits further storage of the storage element coupled to the bit line. In other embodiments, the processor initially loads the bit 7L line latch. The device 1 i 82, and the sensing circuit sets it to a suppression value during the verification process. The data latch stack 1 194 contains a data latch stack corresponding to the sensing module. In one embodiment, each sense There are three data latches in the test module 在 8 在 in some implementations (but not required), the data latch is implemented as a shift register, so that the parallel data stored therein is converted into The serial data of the data sink 1120, and vice versa. In the preferred embodiment, all data latches corresponding to the read/write blocks of the m storage elements are 132483.doc -44 - 200919476 The links can be linked together to form a block shift register so that a data block can be input or output by serial transfer. In particular, the group of r read/write modules is configured such that each data latch in its data latch set sequentially shifts data into or out of the data bus. As with the data latches being part of the shift register for the entire read/write block. Additional information regarding the structure and/or operation of various embodiments of non-volatile storage devices can be found in: (丨) March 27, 2007 entitled "Non-Volatile Memory And Method With Reduced"

U.S. Patent No. 7,196,931 to Source Line Bias Errors; (7) U.S. Patent No. 7,023,730 entitled "Non_volatile Mem〇ry And Method with Improved Sensing", issued on April 4, 2006, on '(3) 2006 US Patent No. 7,046,568 entitled "Memory Sensing Circuit And Method For Low Voltage Operation", entitled "Compensating for Coupling During Read Operations of Non-", issued May 5, 2006. US Patent Application Publication No. 2006/0221692 to Volatile Memory " and (5) US Patent Application Publication No. 2006/0158947, entitled "Reference Sense Amplifier For Non-Volatile Memory", published on July 20, 2006. The entire disclosure of all of the above-identified patent documents is incorporated herein by reference. Figure 14 illustrates the organization of memory arrays as blocks for a full bit line memory architecture or for a parity memory architecture An example is described. An exemplary structure of a memory array 1 400 is described. As an example, the description is divided into 1,024 132483.doc -45· 2009 19476 blocks of NAND flash EEPROM. The data stored in each block can be erased simultaneously. In one embodiment, the block is the smallest unit of the simultaneously erased storage element. In this example, There are 8 rows corresponding to the bit lines BL〇, BL1, ..., BL8511 in each block. In an embodiment called the all-bit π line (ABL) architecture (architecture 141〇), Simultaneously select all of the bit lines of a block during read and program operations. The storage elements along the common word line and connected to either bit line can be programmed simultaneously.

In the example provided, 64 storage elements and two dummy storage elements are connected in series to form a -NAND string. There are 64 data word lines and two dummy word lines WL_d 〇 and WL dl, wherein each NAND string includes 64 data storage elements and two virtual (four) memory elements. In other embodiments, the NAND string can have more or less than 64 data storage elements and two dummy storage elements. The data memory unit stores user or system data. The dummy memory single is usually not used to store user data or system data. The terminals of the NAND string are connected to the dragon bit line via the drain select gate (connected to the selected idle pole line SGD), and the other terminal is connected via the source select gate (connected to the select gate source line SGS) To the common source. In an embodiment referred to as an odd-even architecture (Architecture i), the bit lines are divided into even bit lines (BLe) and odd bit lines (BL.). In this case, the storage elements along the common word line and connected to the odd bit lines are programmed at - time, while the other elements along the common word line and connected to the even bit lines are programmed at another time. The data can be programmed into different blocks and read from different blocks at the same time. In this example, > △ 丄丄, there are 8, 5 12 rows in the parent block, which are divided into even rows and odd rows. I32483.doc •46- 200919476 In the configuration of one of the acquisition and stylization operations, select 4,2· storage components at the same time. The selected storage elements have the same word line and the same type of bit line (e.g., even or odd). Therefore, 532 data bytes can be simultaneously read or programmed to form a logical page, and one block of memory can store at least eight logical pages (four word lines, each having odd pages and even numbers) page). For a multi-state storage element, when each storage element stores two data bits (where each of these two bits is stored in a different page), a [^•秘姑十,区The block stores sixteen logical pages. Blocks and pages of other sizes can also be used. For fox or parity architectures, the storage elements can be erased by raising the ρ well to erase power (e.g., ' 2G V) and grounding the word line of the selected block. The source line and the bit line are floating. The entire memory array, a single block, or another unit of a storage element that is part of a memory device can be erased. The floating idle pole of the electronic self-storage element transfers "the well region, making the VTH of the storage element become negative. Figure 15 depicts a set of instances of the threshold power distribution. The status of two data bits for each storage element (four) An example of distribution of storage element arrays is provided. The first-order electric dust distribution e is provided for the erased storage element. The three threshold voltage distributions A, B, and ^ for the programmed storage element are also described. The threshold voltage in the £ distribution is negative, and the threshold voltage in the A and MC distributions is positive. The mother-dissimilar threshold voltage range corresponds to a predetermined value of the data bit set. Stylized to the storage element The specific relationship between the data and the threshold voltage level of the storage element depends on the data encoding mechanism of the material element (4). 132483.doc -47- 200919476 For example, the full text is incorporated herein by reference. Various data encoding mechanisms for multi-state flash storage elements are described in U.S. Patent No. 6,222,762, issued toK.S. Pat. Assignment assigns a data value to a threshold voltage range such that if the threshold voltage of the floating gate is erroneously shifted to its neighboring entity state, only one bit will be affected. - The instance will be assigned "ii " To the threshold voltage range E (state E), assign "10" to the threshold power a range A (state A), and assign "〇〇, to the threshold power range B (state B), and Assigning "G1," to the threshold voltage range C (state C) H. In other embodiments, the Gray code is used. Although four states are shown, the present invention can also be applied to other multi-state structures, including Structures that include more or less than four states. - Three read reference voltages Vra, Vrb, and Vrc are also provided for self-storing 7L pieces of material. By testing the threshold voltage of a given storage element is Above or below the Vra' Vj^Vrc' system determines the state of the storage element (eg 'stylized conditions'). In addition, three verification reference voltages Vva, Vvb and Vvc are provided. When the storage element stores additional status Additional reading and reference values can be used. When the storage component is programmed to At state eight, the system will test whether their storage elements have a threshold voltage greater than or equal to Vva. When the storage element is programmed to state B, the system will test whether the storage element has a voltage greater than or equal to the limit. When the component is programmed to state C, the system will determine if the storage component has a threshold voltage greater than or equal to he. In an embodiment referred to as full sequence stylization, the storage component can be self-wipe 132483.doc • 48 - 200919476 In addition to the state E directly stylized to any of the stylized states A, b or c =. For example, 'the group of storage elements to be programmed can be erased first, so that all storage elements in the group are rubbed Except state E. Next, a series of stylized pulses, such as those depicted by the control gate voltage sequence of Figure 19.

Directly program the storage element to state A, B or c. When some of the storage elements are being programmed from state E to state A, the other storage elements are programmed from state E to state B and/or from state E to state c. When staging from state e to state c on selected word line WLi, the floating gate below WLi is compared to the voltage change from staging to state A or staging from state E to state 3 The amount of charge changes the most, so the amount of parasitic coupling to the adjacent floating closed-pole below WLi-Ι is maximized. When staging from state E to state 3, the amount of coupling to the adjacent floating gate is reduced, but still significant. When staging from state E to state A, the amount of coupling is even further reduced. Therefore, the amount of correction required to subsequently read each state of WLid will vary depending on the state of the adjacent storage elements on WLn. Figure 16 illustrates an example of a two-pass (pass_pass) technique for a stylized multi-state storage element that stores data for two different pages: a lower page and an upper page. Describe four states: state E (1丨), state Α (ι〇), state B (00), and state C (01). For the state £, both pages store "1". For state A, the lower page stores "〇 and the upper page stores 1'. For state B, both pages store "〇". For the bear c, the 'lower page is stored 1' and the upper page is stored, 〇,,. Note that although a particular bit pattern has been assigned to each of these states, it is also possible to assign different bit patterns. 132483.doc •49- 200919476 In the first pass, stylize φ . _ ^ , according to the logic to be programmed to the logical + bit to set the threshold voltage level for storing the stored parts of the lychee and branch. If the bit is logic 1, it does not change the limit, because it is in the proper state because it has been erased earlier. However, if - as indicated by arrow 1600, if the bit 7C to be programmed is logical ’ ', then the property will increase the threshold level of the 7G component to the state Α. This ends the first stylization. In the second pass of the stylization, according to the program to be programmed into the upper logic page

The bit is used to set the threshold voltage level of the storage element. If the upper logical page bit will store the logic "1 ", the order, 丨 丄,, _ 丨 does not be stylized, because the lower page bit is stylized and the storage element is in state E or A In one of the two states, both states carry the upper page bit open " ^ I only 甶1 。. The upper right page bit will be the logical "0", which will shift the threshold voltage. The first right pass causes the storage element to remain in the erased state E' then rides as arrow 162{), and in the second phase, the 7L piece is stored' so that the threshold voltage is increased to state c. If the storage element has been programmed to state A due to the first pass, then the arrow (10)' is programmed to store the component in the second pass, causing the threshold voltage to increase to state (4). The result of the second pass is to program the storage element to the state indicated to store the logic of the upper page "" without changing the information on the next four pages. In both Figures 15 and 16, the amount of coupling to the floating gate on the adjacent word line depends on the final state. In an embodiment, the system can be configured to perform a full sequence of writes when sufficient data is written to fill the entire page. If the data written is less than one full page, the stylization process can be programmed to program the next four pages with the received data. When subsequent data is received, the system will then program the upper 132483.doc •50· 200919476 page. In yet another embodiment, the system can begin writing in the mode of the programmed lower page, and if subsequently received enough data to fill the entire element line (or most), the system can switch to Full sequence stylized mode. Further details of this embodiment are disclosed in U.S. Patent Application Publication No. 2006/012639, the entire disclosure of which is incorporated herein to This is incorporated herein by reference. 17a-17c disclose another trick for staging non-volatile memory that is written to a particular page after writing to a neighboring storage element of a previous page for any particular storage element Specific storage elements to reduce the coupling effect of the floating gate to the floating gate. In an example implementation, the non-volatile storage element uses four data states to store two data bits per storage element. For example, assume that state E is an erased state and states A, B, and C are stylized. Status E stores data丨丨. State A stores data 01. State B stores data 1〇. Status (4) Storage information. The order is that two bits change between adjacent states A and B, so this is an example of non-Gray coding. You can also use the data to other codes of the entity data status. Each data element stores two data pages. For reference purposes, • These pages are referred to as the upper and lower pages; however, such pages may be given other petitions. H^ _ > test heart A ' The upper page stores the bit 〇 and the lower page stores the bit i. Referring to state B, the upper page storage bit is stored in the lower page. Referring to state c, both pages store bit information 0. Stylized % is a two-step process. In the first step, stylize the lower 132483.doc -51 - 200919476 page. If the lower page holds data 1, the state of the storage element remains as follows: If the = material is weighted to zero, the voltage threshold of the storage element is raised: the storage element is programmed to state B. Figure m thus shows the stylization of the storage element from state E to state B. State B, which is the transition state b; , therefore, the verification point is depicted as Vvb, which is lower than Vvb. - In the embodiment - after the storage element is programmed from state E to Βι, the adjacent storage element (WLn+1) in the NAND string will be programmed next to the page below the storage element. For example, returning to Figure 2, after the page below the stylized storage element 〇6, the page below the storage element 104 will be stylized. After the stylized storage element HM, if the storage element 104 has a threshold voltage from the state E to the state b, the floating gate-to-floating gate light combining effect will make the storage element (10) appear The voltage limit is increased. This will have the effect of widening the threshold voltage distribution of state B to the distribution of the threshold voltage distribution 175 被 of the trace of Figure 17b. This apparent widening of the threshold knife will be corrected when stylizing the upper page. ο Figure i7c depicts the process of stylizing the upper page. If the storage element is in the erased state E and the upper page remains at 1, the storage element will remain in the state if the storage element is in state E and its upper page data will be programmed to. (4) The threshold voltage of the storage device will rise. So that the storage element is in the shape = A. If the storage element is at the intermediate threshold voltage distribution and the upper page data will remain at 1, the storage element will be programmed to final state B. If the storage element is at the intermediate threshold voltage distribution 175 and the upper page data becomes data, the threshold voltage of the storage element will rise, causing the storage element to be in state C. The process depicted in Figures i7a through 17c reduces the floating gate to 132483.doc • 52· 200919476 The floating gate coupling library will be coded for a given storage: only the upper page of the adjacent storage element is coded - The example is <apparent threshold electric dust has an effect. Substitute state to state c, and when the upper page data of the upper part is 1, the self-distribution 1750 shifts ^^m] 7 surface data is 〇, and moves to state B. Although Figure 17a to Figure ι7 ^ ^ ^. 槌 for four data status and two data pages

An example of the face, but the concept is applicable to other implementations with more or less than four sorrows and different from two hundred products ^#^. For example, Figure 5a to Figure f

5d_ describes three pages: Example. The U-face, the intermediate page, and the upper page are flowcharts describing one embodiment of a method for staging non-volatile memory. In a glimpse of the mountain, the storage element is erased before the stylization (in blocks or other units). In step 18, the "data load" is issued by the controller and is received by the control circuit 1110. In step 1805, the address data representing the page address is input from the controller or host to the decoder 1114. In step 181, a stylized data page of the addressed page is input to a data buffer for stylization. The data is latched into the appropriate set of latches. In step 1815, the "programmed" command is issued by the controller to state machine 1112.

Triggered by the "programming" command, the data latched in step 108 will be stylized using the stepped stylized pulses of burst 19 of Figure 19 applied to the appropriate selected word line. To the selected storage element controlled by state machine 1112. In step 〇82, the programmed voltage VpGM is initialized to a start pulse (eg, 12 V or other value) and the programmed counter maintained by state machine 1112 ( PC) is initialized to 0. In step 1830, a first VPQM 132483.doc -53.200919476 pulse is applied to the selected word line to store the component. "The museum is in the direction of the selection of the cognac...the line phase "in the specific data latch, the corresponding bit = the piece should be the surface, if the logic" is stored in the indication of the opposite shore. Also - the data status The specific lock " condition should be kept in its current suppression stylization. Save 'quote' to connect the corresponding bit line to ~ to the post, verify the target limit of the selected storage element "has reached the appropriate test The selection of electricity has not yet reached two: the wide-ranging material has changed to logic. If the level of the material in the threshold is detected, "change (4) is stored in the data latch. In this way, the corresponding data pin m is stored in the bit line. The bit line of the logic "1" in the ‘,,, ‘ 盗. When all data vendors store logic short, M " master latch or type mechanism) know, emirate (via the hardwired logic described above, all selected storage elements have been pushed by program 1840; ^ θ 牡 少 仃 仃 仃 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有 所有It is programmed and verified. In step 1845, the "pass" status is reported. "If, in step 1840, it is determined that not all of the data latches store logic 1, then continue the stylization process. In step t, program The limit value PCmax is checked to verify that the stylized counter pc> one of the stylized limit values is "yes, however, other numbers can be used. If the stylized counter pc is not less than PCmax, the stylization process fails and is reported in step 1855. , failure state. If the stylized counter pC is less than pCmax, then increase the step size of the VPGM and increment the stylized counter PC in step 1 132483.doc -54· 200919476. The process then returns to step 1. 830 to apply the next VpGM pulse. Figure 19 depicts an example pulse train 1900 applied to the control gate of the non-volatile storage element during stylization, and switching of the boost mode that occurs during the burst. Pulse train 1900 includes application A series of stylized pulses 1905, 1910, 1915, 1920, 1925, 1930, 1935, 1940, 1945, 1950, etc. selected for use in the stylized word line. In one embodiment, the 'stylized pulse has a voltage VpGM, which starts at 12 V and increases in increments (eg, ' 〇 5 V) for each successive stylized pulse until it reaches a maximum of 2 〇 V. Between the stylized pulses is a verify pulse. In other words, the verification pulse set 1906 includes three verification pulses. In some embodiments, there may be one verification pulse for each state (eg, states A, B, and C) to which the material is programmed. In the example, there may be more or fewer verification pulses. The verification pulses in each set may have amplitudes of, for example, Vva, Vvb, and Vvc (Fig. 16) or Vvb, (Fig. 17a). As mentioned, Applied to word line The voltage that implements the boost mode is applied when stylization occurs (for example, before the stylized pulse and during the stylized pulse). In practice, the boost voltage of the boost mode can be slightly initiated before each stylized pulse. And removed after each stylized pulse. In addition, during the verification process that occurs, for example, between stylized pulses, no voltage is applied. Alternatively, it will typically be less than the boost voltage. Applied to the unselected word line. When comparing the threshold voltage of the currently programmed storage element to the verify level, the read voltage has a sufficient storage element to keep the previously programmed storage element in the NAND string open. Zhen 132483.doc -55- 200919476. The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention. Many modifications and variations are possible in light of the above teachings. The embodiments described are chosen to best explain the principles of the invention and the practice of the application in the The present invention is preferably utilized. It is intended that the scope of the invention be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a NAND string. 2 is an equivalent circuit diagram of the NAND string of FIG. 1. 3 is a block diagram of an array of NAND flash memory elements. Figure 4 depicts a cross-sectional view of a NAND string formed on a substrate. Figures 5a through 5d depict the stylization of non-volatile storage elements. Figure 6a depicts a configuration of a NAND string and one of the components for sensing. Figure 6b depicts the waveform associated with Figure 6a. Figure 6c depicts the sensing process associated with Figures 6a and 6b. Figure 6d depicts current sensing based on voltage changes. Figure 7a depicts the current and voltage as a function of time due to ground bounce during a sensing operation. Figure 7b depicts the change in current and voltage as the source voltage is adjusted to a fixed positive DC level during the sensing operation. Figure 7c depicts another group of NAND strings and components for sensing. Figure 7d depicts the sensing process associated with Figures 7a-7c. 132483.doc -56- 200919476 Figure 8a depicts one of the NAND strings and components configuration, including the current sink circuit. Figure 8b depicts the configuration of the NAND strings and components of Figure 8a when voltage sensing occurs. Figure 8c depicts the waveforms associated with Figures 8a and 8b. Figure 8d depicts the sensing process associated with Figures 8a-8c. Figure 9a depicts a NAND string and components for temperature compensated sensing. Figure 9b illustrates the variation of the threshold voltage with temperature.

Figure 9c illustrates the change in Vblc and Vbl with temperature. Figure 9d depicts the waveform associated with Figures 9a through 9c. Figure 9e depicts the sensing process associated with Figures 9a through 9d. Figure 9f depicts the erase & verify process. Figure 1 Oas children VS0URCdi|temperature changes. Figure (10) depicts a real array of storage elements for a different set of packets of the #NAND string. Figure U is a block diagram of a volatile memory system using a single column decoding 11/row decoder and a read/write circuit. Figure 12 is a block diagram of a non-volatile memory system using a dual column decoder / ^ ^ and a read/write circuit. Electrical Tower Figure 13 is a block diagram depicting an embodiment of a sensing block. Figure 14 depicts an example for parity and all-bit columns organized into blocks. The u-wood structure will be a collection of memory maps. A collection of instances. 15 depicts a single-pass stylized 1 6 depicting one of the multi-pass stylized threshold voltage distributions. One of the threshold voltage distributions is 132483.doc •57· 200919476 Figure 17a to Figure 17c show various threshold voltage distributions and are described for the program The process of non-volatile memory. Figure 18 is a flow chart depicting one embodiment of a process for programming non-volatile memory. Figure 19 depicts an example pulse train applied to the gate during stylization. Control of non-volatile storage components [Key component symbol description] 100 transistor

100CG 100FG102 102CG 102FG 104 104CG 104FG 106 106CG 106FG120 120CG122 122CG 126 Control gate floating gate transistor control gate floating gate transistor control gate floating gate transistor control gate floating gate first selection gate control gate Second select gate control gate bit line 132483.doc -58- 200919476 128 source line 320 NAND string 321 bit line 322 select gate 323 storage element 324 storage element '325 storage element 326 storage element 327 select gate 340 NAND string 341 bit line 342 select gate 343 storage element 344 storage element 345 storage element 346 storage element Cj 347 select gate 360 NAND string 361 bit line 362 select gate 363 storage element 364 storage element 365 storage element 366 storage element 132483.doc -59 - 200919476 367 Select Gate 400 NAND String 402 Terminal 403 Terminal 404 Source Supply Line 406 Source Side Select Gate 408 Storage Element 410 Storage Element 412 Storage Element 414 Storage Element 416 Storage Element 418 Storage Element 420 Storage Element 422 Storage Element 424 Side selection gate 426 bit line 430 source/> and polar region 490 substrate 492 p well region 494 η well region 496 Ρ type substrate region 510 Vth distribution 512 Vth distribution 520 first VTH distribution 132483.doc -60- 200919476 522 second Vth Distribution 524 third Vth distribution 526 fourth vTH distribution 600 sensing component 602 current sensing module 604 BLC (bit line control) transistor 606 BLS (bit line sensing) transistor 608 control device 610 bit line 612 NAND string 620 waveform 622 waveform 624 waveform 626 waveform 628 waveform 720 voltage regulator 800 sensing component 802 voltage sensing module / circuit 804 BLC (bit line control) transistor 806 BLS (bit line sensing) transistor 808 Control device 810 bit line 811 to grounded capacitor 812 NAND string 132483.doc -61 - 200919476 813 capacitance to adjacent bit line 814 sensing node 816 path 818 GRS transistor 820 path 822 path 824 transistor 825 current source 826 path 830 waveform 832 waveform 834 waveform 836 waveform 838 waveform 840 waveform 842 waveform 844 waveform 846 waveform 900 temperature dependent circuit 9 10 Waveform 912 Waveform 914 Waveform 916 Waveform 918 Waveform 132483.doc -62- 200919476 1 922 Waveform 924 Waveform 1000 Memory Array 1004 Source Line 1006 Bit Line 1026 汲 Extreme 1028 Source Terminal 1050 NAND String 1100 Sensing Block 1110 Control Circuit 1112 State Machine 1114 On-Chip Address Decoding 1116 Power Control Module 1118 Line 1120 Line/Data Bus 1130 Column Decoder 1130 Α Column Decoder 1130 Β Column Decoder 1150 Controller 1160 Line Decoder 1160 Α Row Decoder 1160 Β Decoding 1165 Buy/Write Circuit 1165ΑBuy/Write Circuit 132483.doc -63· 200919476 1165B Read/Write Circuit 1170 Sensing Circuit 1172 Data Bus 1180 Sensing Module 1182 Bit Line Latch 1190 Common Part 1192 Processor 1193 Input Line 1194 Data Latch 1196 Memory Device / 1/0 Interface 1198 Memory Die 1400 Parity Structure 1410 Full Bit Line (ABL) Architecture 1750 Threshold Voltage Distribution 1900 Burst 1905 Stylized Pulse 1910 stylized pulse 1915 stylized pulse 1920 stylized pulse 1925 Stylized Pulse 1930 Stylized Pulse 1935 Stylized Pulse 1940 Stylized Pulse 1945 Stylized Pulse 132483.doc -64- 200919476 1950 Stylized Pulse 1906 Verify Pulse Set BLO, BL1, BL2, BL3, BL4, BL5, BL8511 Bits Line BLeO, BLe 1, BLe2, BLe4255 Even bit line BLoO, BLo 1, BLo2, BLo4255 Odd bit line SGD Dip line selection line SGS Source selection line Vra, Vrb, Vrc Read reference voltage Vva, Vvb, Vvc Verification Reference voltage WL_dO, WL_dl dummy word line WLO word line WL1 word line WL2 word line WL3 word line 132483.doc 65-

Claims (1)

200919476 X. Patent Application Range: 1. A method for operating a non-volatile storage system, comprising: during a period of time: (a) applying a source voltage to each of a plurality of NAND strings a source, each of the plurality of strings is associated with a respective bit line, (b) preventing each individual bit line from being coupled to a respective sensing component, and (c) Coupling each bit line to a respective discharge path; and continuing to apply the source voltage to each of the plurality of NAND strings during a second time period subsequent to the first time period The source 'and each of the individual bit lines are coupled to the respective sensing component. 2. The method of claim 1, wherein the respective sensing components perform a voltage sense, and determine whether a charge sharing occurs between the respective bit lines of the β Xuanyuan and the respective sensing components. 3. The method of claim 1, wherein a respective transistor is coupled between each of the respective bit lines and the respective sensing components, and wherein the coupling of the step (c) comprises providing a control gate voltage To the respective transistors, the respective transistors are in a conducting state. 4. The method of claim 1, further comprising continuing to lightly connect each bit line to its respective discharge path during the second time period. 5. The method of claim 1, further comprising adjusting the discharge of each bit line via the respective discharge path. 6. The method of claim 1, further comprising adjusting a discharge of each bit line via the respective enemy power path using a current mirror. 7_ The method of claim 1 wherein the first time period has a predetermined duration of 132483.doc 200919476 time 'which is selected such that it is attributed to the hacker + —, the power of the next adjacent bit line The bit line noise of the valley light is discharged. & The method of claim 7, wherein the bit line noise is consumed by - or a plurality of selected non-volatile memory elements in a conductive state - or a plurality of adjacent bit lines An associated non-volatile storage element is in the non-conducting state of the NAND strings - one of the τ <«· bits. 9. A non-volatile storage system, comprising: a set of non-volatile storage elements configured as a plurality of NAND strings, each of the plurality of NAND strings and - each bit line, two senses The test component is associated with a respective discharge path; and one or more control circuits in communication with the set of non-volatile storage elements 'the one or more control circuits: (1) during the first time period: (4) applying one Source source voltage to each of the plurality of NAND strings (b) preventing each individual bit line from being coupled to the respective sensing component, and (1) consuming # respective bit line to the And (7) continuing to apply the source voltage to the source of each of the plurality of strings during a second period of time following a (four) interval, and causing each Each bit line is coupled to the respective sensing component. 10. The non-volatile storage system of claim 9, wherein the respective sensing components perform voltage sensing to determine whether charge sharing occurs between the respective bit lines and the respective sensing components. U.: The non-volatile storage system of claim 9, further comprising a respective electro-optical transistor 132483.doc 200919476 coupled between each individual bit line and the respective sensing component by providing Controlling the gate voltages of the respective transistors so that the respective 啻θ 本 ^ 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 々 . 12. The non-volatile storage system of claim 9, wherein the one or more control circuits continue to consume each bit line discharge path during the second time period. 〃 13. 14. The non-volatile storage of claim 9 is stored in the system, wherein the one or more control circuits regulate the discharge of each bit line via the respective discharge path. The non-volatile storage system of claim 9, wherein the one or more control circuits adjust the discharge of each of the bit lines via the respective discharge paths using a current mirror. 15. The non-volatile storage system of claim 9, wherein the first time period has a predetermined duration 'which is selected such that a bit line is attributed to capacitive coupling from one or more adjacent bit lines The noise is discharged. 16. The non-volatile storage system of claim 15, wherein the bit line (4) is coupled by one or more associated non-volatile storage elements in one or more adjacent bit lines in a conducting state. The selected non-volatile storage element is in one of the non-conducting state of one of the nand strings. 132483.doc