TW200915717A - Methods and apparatus for calibration of automatic gain control in broadcast tuners - Google Patents

Abstract

In one aspect, a calibration component configured to calibrate an automatic gain controller (AGC) for use in a tuner configured to isolate a selected channel from a multi-channel broadcast signal, the tuner implemented substantially on two chips, a first chip comprising a radio frequency (RF) integrated circuit adapted for RF processing and a second chip comprising a digital integrated circuit adapted for digital processing is provided. The calibration component comprises a calibration signal generator implemented on the RF integrated circuit, the calibration signal generator adapted to generate a generally known calibration signal, a power detector implemented on the RF integrated circuit and configured to detect, during calibration, at least one power characteristic of the calibration signal and to provide a power level signal indicative of the at least one detected power characteristic, a gain controller implemented on the digital integrated circuit, the gain controller adapted to generate at least one error signal based, at least in part, on a comparison between the power level signal provided by the power detector and a first reference signal, an offset signal generator implemented on the RF integrated circuit and configured to generate an offset signal based, at least in part, on the at least one error signal and a summing element implemented on the RF integrated circuit and adapted to combine the offset signal with the power level signal provided by the power detector to provide an adjusted power level signal.

Description

200915717 IX. DESCRIPTION OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to tuners, and more particularly to automatic gain control in a preamplifier stage in a television conditioner. [Prior Art] The negative signal 'especially the TV signal' is often received by a cable connected to a set-top box or by an antenna or a satellite dish! The land broadcast to be transmitted. In either case, the s-hole number is usually composed of several different information components transmitted in a specified frequency channel. This multi-channel signal is referred to herein as a "broadcast signal." In this regard, the information in the broadcast signal may be processed by a tuner to extract one or more of the channels from the broadcast signal. For example, the broadcast signal may include signals throughout the spectrum of the television signal, including the high frequency (VHF) band (ie, the 54 to 2i6 MHz TV carrier frequency) and the ultra high frequency (UHF) band (ie, 47〇 to, 890MHz frame-view carrier frequency The broadcast signal may also include other channel frequencies outside the frequency band (for example, in addition to the vhf band and the W band, the cable broadcast signal may also contain other specified signals Carrier frequency band. In general, these various frequency bands include several different channels. For example, the VHF band is divided into n channels (channels 2 to 13), and the UHF band is divided into 7 channels (channel to μ). Each channel is assigned a specific bandwidth in the broadcast frequency 200915717 according to the standard by which the broadcast signal is transmitted. For example, the US standard is for each band. Assigning a 6MHz bandwidth and specifying that the video and audio information components of the signal should be modulated in the channel for transmission. A tuner allows a user to One of the channels in the broadcast signal is selected to be isolated from the signal and provided to, for example, a television for viewing. The benefit may include a preamplifier to control the various components provided to the edge adjuster. Processing the gain of the broadcast signal of the component. For example, an automatic gain controller (AGC) may be arranged at the front end of the tuner to provide an adjustable gain to the broadcast signal in order to try to be used by the preamplifier The signal provided is maintained at a substantially constant level. It is clear that the AGC will operate to maintain signal power within the dynamic range acceptable to the downstream components of the tuner and to maximize signal strength while Maintaining a very low degree of signal distortion. [Invention] Certain embodiments of the present invention include an automatic gain controller (AGC) that is used in a tuner that is configured to use a selected channel and A multi-channel broadcast signal is isolated. The tuner is essentially carried by two wafers: a first wafer, including one adapted to be used a radio frequency (RF) processed RF integrated circuit; and a second chip including a digital integrated circuit adapted for digital processing. The automatic gain controller includes: a variable gain amplifier (VGA) And being implemented on the RF integrated circuit, the VGA is adapted to receive the broadcast signal and to apply a variable 200915717 gain to the broadcast signal based at least in part on a gain signal. Providing an amplified broadcast signal; a power detector configured to be implemented on the RF integrated circuit and configured to detect at least one power characteristic of the amplified broadcast signal and to provide a representation At least one power level signal having detected a power characteristic; and a gain controller implemented on the digital integrated circuit, the gain controller being adapted to be at least partially dependent on the power detection ???a comparison value between the power level signal and a reference signal provided by the detector to generate at least one error signal, wherein the gain signal is based at least in part on the gain controller The at least one error signal generated. Some embodiments include an automatic gain control benefit (AGC) that is used in a tuner that is adapted to isolate a selected channel from a multi-channel broadcast signal, the AGC being configured to use The operation is performed in a calibration mode adapted to correct the AGC and to operate in an operation mode adapted to apply a variable gain to a broadcast signal. The AGC includes a first control loop, including: a correction signal generator that is adapted to generate a correction signal; a power detector configured to detect an received input signal At least one power feature is used to provide a power level signal indicating the detected at least one power feature; an adding component for combining the power level signal and an offset signal to provide an adjusted The power level controller is a tiger; a gain controller includes a reference signal, and the gain controller is adapted to generate at least an error signal for indicating the reference signal and the adjusted power bit. a difference between the quasi-signals; and an offset signal generator that is adapted to provide the offset signal to the adder 200915717, the offset signal generator being configured to be at least partially The offset signal is adjusted according to the at least T error signal. The AGC further includes a first control loop including: a variable gain amplifier (VGA) adapted to receive the broadcast signal and to apply a variable gain to the gain signal according to a gain signal The broadcast signal uses 4 for the amplified broadcast signal; the power (four) device; the phase adder#; and the gain control benefit, wherein in the calibration mode, the first control loop is in operation and reaches The received input signal of the power detector is a correction signal, and the first control loop is operative to correct the offset signal so that it reflects the offset error of the AGC, and wherein 'in the operation mode The second control loop is in operation and the received input signal to the power detector is the amplified broadcast signal, and the second control loop operates to power the amplified broadcast signal. The level is maintained within a range of expectations. Some embodiments include a method of operating an automatic gain controller (AGC) in a tuner configured to isolate a selected channel from a multi-channel broadcast signal, the tuner Essentially being performed on two wafers: a first wafer comprising an RF integrated circuit adapted for radio frequency (RF) processing; and a first wafer comprising an adapted a digital integrated circuit for performing digital processing, the method comprising: applying a variable gain to the broadcast signal based on a gain signal on the RF integrated circuit to provide an amplified broadcast a signal; on the RF integrated circuit, detecting at least one power characteristic of the amplified broadcast signal, above the RF integrated circuit, 10 200915717: At least a first power level signal of the power characteristic; receiving the first power level signal on the two integrated circuit; above the digital circuit, at least partially according to the first power level The comparison value between the signal and the test signal generates an error signal; and in the lamp integrated circuit, the SI, A„, t to ^ey knife provides the gain signal according to the error signal. & As discussed above, a television tuner is a device for receiving a television signal from a broadcast or a broadcast source and rotating an interest frequency to reject all other channels. For example, the television tone spectrum; σ «receives a broadcast nickname, the broadcast signal has a plurality of channels transmitted in a plurality of individual frequency bands, and the television tone (4) may be isolated according to the user's channel selection One of the channels is used to cause it to be demodulated and processed for viewing. The details of how the information is aligned and modulated within a specified frequency band and the designation and composition of the frequency band itself may be For example, the standards supported by Japanese TV broadcasts are different from those of American TV broadcasts. In addition, information may be modulated by digital, analog, and sig. Many general concepts of isolating the channel and the broadcast signal are independent of the broadcast standard used at any particular geographic location. Figure 1 is a block diagram of a tuner in a conventional television receiver. The source n 0 will provide a broadcast signal 115 to the tuner i 20 〇 for example, 'the signal source, 110 may be a cable connected to a set-top box or a land broadcast source received by the 200915717 I-antenna-antenna And can provide digital tone:: analog modulation signal 115. Broadcast (four) 115 may be composed of a plurality of frequency groups, each channel will occupy one of the spectrum of the broadcast signal, see: frequency. For example The broadcast signal 115 may be composed of several electrical videos = 'at any given time. These television channels may only be of interest. As discussed above, # within a channel & The summation and information components are typically based on the broadcast standard used to transmit the signal. The peripheral device 120 can be a user-adjustable component that can be configured to select a channel from the broadcast signal. And substantially rejecting each of the other channels present in the broadcast signal. The tuner UOC or a separate component downstream of the tuner may further process the single channel signal and demodulate the information in the signal from the carrier. The demodulation may be one or any combination of a plurality of demodulation transformers. For example, the demodulation may support one or more digital modulation techniques, one or more analog modulation techniques, or two Then, the generated demodulation signal may be post-processed to create a signal 125 that can be displayed for viewing. For example, display 130 may be a plasma display, a liquid crystal display, a digital light projection display, a cathode ray tube display, or any other type of display capable of representing the signal for viewing. Figure 2 shows a more detailed view of the two alternative modes of operation of the tuner 12A shown in Figure 1. The tuner 120 may consist of a preamplifier crying stage 230 and a channel selection processing block 240. The preamplifier crying stage 230 may include a variable gain amplifier (ν〇Α) 250 and an automatic 12 200915717 gain controller (AGC) 260. The broadcast signal 115 may be received from a dual line or terrestrial broadcast source and amplified by the VGA 250 in accordance with a VGA gain that is controlled in a controlled manner by a gain of 1% 255. The value of gain signal 255 may depend on AGC 260, as described in further detail below. The channel in the broadcast signal may be selected in the channel selection processing block 240 and may be demodulated and post-processed.

For example, channel selection processing block 240 may include any of the ways and components shown in US Patent Publication No. 2006/0166633 (the '633 publication), which is hereby incorporated by reference in its entirety, or It is a component that includes any other name and arrangement that is adapted to select a Greek channel from a broadcast signal. It should be understood that a tuner may also include other components not shown in FIG. Other tuners that are adapted to receive and process different types of television signals (for example, the tuners described in U.S. Patent No. 7, s. 91,792 (the '792 patent), which is incorporated herein by reference. Its full incorporation) is equally applicable to aspects of the invention. The broadcast signal 115 may be received at the preamplifier 230 in a wide variety of conditions, which may be related to the type of signal being transmitted, the type of transmission medium, and the modulation of the spectrometer itself. Change technology and / or geographic location. For example, the broadcast signal 115 may be transmitted to the tuning 1 120 via a cable, or the 'broadcast signal i 15 may be broadcasted from the terrestrial source via wireless electromagnetic radiation and from an antenna, satellite ear, or the like. The device is provided to the tuner 12A. When transmitting through a cable, the broadcast signal 'broadcast signal 115' received from a terrestrial broadcast source (for example, a base station) may have a lower noise to 13 200915717 and a higher signal. strength. In addition, compared to the near-the broadcast source or the fish, the broadcast source is substantially unblocked (9) i2Q, located in a region away from the broadcast source or has a party-to-blocking tuning between the broadcast source and the broadcast source. The device may receive a relatively low signal power of 7,000 relative noise signals. 11 5 〇 To help process the signal 'tuners' with varying quality attributes (for example, different noise and signal strength characteristics) It may include a VGA 25A that will receive a variable gain control signal 255 from the AGC 260 to indicate the level of gain to be applied to the broadcast m 115. The purpose of the preamplifier stage 23 is to ensure that the broadcast component received by the front end component of the tuner (for example, channel selection processing block 240 and/or other downstream stages of the television receiving device) is sufficiently high. Noise ratio (SNR) and has very low distortion and falls within a very limited dynamic range. For example, the TV tuner may receive an input signal ranging from about 85 ζ 1 Β i i. If there is no preamplifier and automatic gain control, the tuner's downstream processing block will need to handle this very large dynamic range. The preamplification, and can be used to reduce the dynamic range requirement of the 11-week ritual by maintaining the signal level within a small range.

Figure 2a shows a tuner implementation in which the agC operates in response to a signal 丨25 following the channel selection processing block. That is, the AGC 260 will generate the gain control signal 255 after the channel selection processing block 24 is followed by the single channel selected by the pirate. As understood in the '633 publication, detecting the characteristics of the single channel signal typically has a non-stimulus effect that inactivates the sensitivity of the tuner. Specifically, the beta function of the AGC 14 200915717 loop may not be able to see most of the signal characteristics present in channels other than the selected channel. Accordingly, because this agc can't see a particular broadcast signal condition, the loop cannot = change the offset gain to compensate for the selected channel before it is negatively affected. ~ Figure 2b is derived from the one (four) line of the 633's modifier, in which the operation of the AGC is processed in the Occupy Ownership System to process the amplified broadcast signal. By pulling the detection mechanism of the AGC loop back to the broadcast signal, the characteristics of the signal that adversely affect the performance of the tuner (eg, the interference source) can be measured and properly resolved. The AGC 26〇 (via gain signal 255) controls the gain level on the VGA 250 to provide a convenient amplification of the broadcast signal U5. The generated amplified broadcast signal can then be provided to the channel selection processing block 24A. However, instead of analyzing the characteristics of the single-channel signal (ie, signal 125) as shown in FIG. 2a, the AGC control loop is formed. Instead, the system 260 is based on the characteristics of the amplified broadcast signal. To generate a gain control signal 255. ~ In Figure 2b, the AGC 260 receives the amplified broadcast signal directly from the variable gain amplifier 25A. However, the tuner is not limited in this respect. Some filtering or other processing may occur after amplification and before the singular AGC offloads the broadcast signal. For example, the broadcast signal may be low-pass filtered before or after amplification to remove any frequency noise outside the broadcast spectrum, thereby making the broadcast signal substantially intact. Or one or more channels in the broadcast signal may be excluded, and the important information or a large number of channels may be removed. Compared with the 15 200915717 best, it may analyze the broadcast signal immediately after amplification to ensure that the signal characteristics in any band that may damage the tuner performance will be detected before the dry processing filter removes the problem frequency. To. Applicants have found that 'tuner performance is typically optimized by employing a dual chip tuner design. Specifically, the Shenjing people invented that various tuner processing can be optimized using a special wafer design. For example, because of the availability of bipolar transistors, = frequency (RF) processing (for example, preamplification, channel selection, and other functions implemented on RF signals) may be appropriate. In the bipolar complementary metal oxide semiconductor (BiCMOS) method; and digital processing (for example, the digital portion of the channel selection, demodulation, post processing, etc.) may be more suitable for precision CMOS methods. Furthermore, the Shenjing people have discovered that the conventional tuner design may be susceptible to interference between the components of the modulation. For example, RF processing may interfere with analog to digital conversion if implemented on a common substrate, while digital processing may interfere with RF functionality.

Similarly, the Applicant has found that a particular portion of an AGC may be more suitable to be applied to one of the wafers and not suitable for execution on another wafer; and the applicant of the invention has correctly misdivided the AGC, which Agc is the best way. The method is used in a dual chip design to take advantage of the dual chip functions and/or to reduce interference between different processes. According to some embodiments, a spectrometer is substantially broken on two wafers, most of which are incorporated into the RF processing components of the tuner, and Most of the wafers 16 200915717 are incorporated into the tuner analog to digital processing components and digital to analog processing components, as described in further detail below. Accordingly, the agc components may be dispersed over the two wafers in accordance with the RF/digital processing separation distance. For example, an AGC of a tuner preamplifier stage may be classified as having the following two main components (which may be composed of a combination of a plurality of smaller components (1) a power to determine the broadcast signal The force rate level 'and the (7)_ control component, which is adapted to convert the power of f (four) to a control signal of a variable gain amplifier. In some embodiments, The detector may be implemented on the -th chip, as an RF process, and the control components are executed on a second chip (for example, as a digital bit) Dispersing the AGC control loop on both wafers can reduce or eliminate interference between the digital processing and can improve the optimization in the dual-chip architecture. For example, 'RF components may be Integrated on an optimized RF 4 wafer and digital components may be integrated on a wafer optimized for digital processing. 'in the environment' and not Interference with each other. Figure 3 shows a tuner that is implemented on two separate integrated circuits in accordance with some embodiments of the present invention. Some components of the tuner are divided into 2 '俾Executed on the [integrated circuit: part: smashed her on the second integrated circuit 3 1 。. For example, the channel selection processing block may be divided into the first integrated circuit 300 The above RF channel selection processing block 34a and the digital channel selection processing block 34b on the second integrated circuit 17 200915717 way 310. agc can also be performed on the two day and day films For example, the components constituting the AGC can be broadly classified into a power detector component hall and a gain controller component surface, wherein the power edge device is implemented in the first integrated body Above the circuit, the gain controller is then executed on the second integrated circuit 3 1 。. / In some embodiments, the first integrated circuit is adapted to仃RF processed RF integrated circuit, and the second integrated circuit will be adapted A digital integrated circuit for digital processing. The "rf integrated circuit" herein mainly includes an RF component and/or a processed integrated circuit and/or is fabricated in this manner to facilitate RF processing. Similarly, the term "digital integrated circuit" as used herein refers to an integrated circuit that mainly includes digital components and/or processing and/or an integrated body that is fabricated in this manner to facilitate digital processing. For example, 'a general RF pfe· I® a knife* RF processing and digital processing bi-wafer design may contain two wafers made in the same way, which will be implemented with RF A master Processing and digital-based processing, using two to prevent you and/or the two wafers from being produced in different ways to substantially assist and/or optimize individual processing environments. It should be understood that an RF integrated circuit may contain specific digital processing (or other non-RF analog processing), and the ❿-digital integrated circuit may contain specific processing and/or other # R" Aspects of the invention are not limited in this respect. Similarly, the words "RF" and "digit" are used to modify the tuner component (for example, the RF channel selection processing block) to represent the integrated circuit in which the component is implemented. Thus, a component labeled as RF or digital may contain an RF, digital, or analog aspect, as such terms are typically used to indicate a wafer on which the component is disposed. f For the tuner shown in FIG. 3, the broadcast signal 1 15 may be received by the first integrated circuit 300, wherein the preamplifier stage 330 operates to adjust the gain of the broadcast signal, The power level of the signal is maintained within a range of the imaginary range. Above the first integrated circuit 300, the broadcast signal 115 may be first amplified by the VGA 350 according to the value of the gain control signal 355 generated by the gain controller 36〇b. The amplified broadcaster number may then be provided to a power detector 3 60a. The power detector 360a may detect one or more power characteristics of the amplified broadcast signal and generate a detected power level signal 325 for indicating the detected power feature. The term "power characteristics" refers to any of the combinations of values, characteristics, or attributes of the signal used to indicate the power level of the chime. For example, a power feature may be a direct power measurement, such as a root mean square (RMS) value of the signal; or may be statistically related to the power, such as a wave seal of the signal. Other power characteristics include ^ ^ value Ή wave seal ratio (PER), peak average ratio! The detected power level signal 325 generated by the power detector can be provided to the second integrated circuit 丨vJ 10 for further execution, how to change the VGA's promotion, The power level is 徂 | | 从 从 从 从 从 从 将该 将该 将该 将该 将该 将该 将该 将该 将该 将该 将该 从 从 从 从 从 从 | | | | | | | | 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例Level 325 is determined by 19 200915717 A 'difference 345' will attempt to keep the amplified broadcast signal at the desired level to reduce the dynamic range of downstream processing components. Any variety of controls The mechanism can be used to form the gain controller 360b, which includes, but is not limited to, various conventional control methods, such as: proportional control, integral control, proportional_product# control, differential control, proportional-differential control, Integral. Differential control, proportional_integral, differential control, etc. 'Because the aspect of the invention is not limited in this respect. The gain controller 36〇b may provide an error signal 345 to the first integrated circuit 300, specifically to the gain mapper 39〇. The gain map 3 90 converts the error signal 345 into a gain control signal gw which tends to reduce the strength of the error. For example, the gain mapper 39 〇 γ can include - or a plurality of look-up tables for converting the error values into corresponding augmented signals; or a proportional gain function for appropriately scaling and adjusting the error values; Or it may contain any other machine f suitable for mapping the error value to the appropriate gain variation applied to the VGA 350. In some embodiments, gain mapper 390 may be implemented above product block circuit 31 instead of 300, as aspects of the present invention are not limited in this respect. In other embodiments, the error signal 345 is applied directly to the VGA 3 50 without the need for an intermediate gain mapper. The VGA 350 receives the gain control signal 355 and amplifies the broadcast number accordingly. As discussed above, the AGC control loop 330 includes a VGA 350, a power detector 360a, and a gain controller 36〇b that are configured to maintain the amplified broadcast signal 305 in the channel selection processing block. At the amplitude. The amplified broadcast signal 3〇5 may be provided by the 20 200915717 to the RF channel selection processing block 3 40a on the first integrated circuit 300. The channel selection processing block 340a may include a channel configured to be selected. The various RF processing components that are isolated from the broadcast signal by the channel may be processed by the digital channel selection processing block 340b over the second integrated circuit 310. The digital channel selection processing block 34B can include various digital processing configured to convert the received signal from the first integrated circuit 300 into a video signal and/or audio signal that can be presented to the user. Components are discussed in further detail below. 4 is a dual-wafer tuned frequency selective selection component according to some embodiments of the present invention. They are generally divided into an RF processing component and a digital processing component. For example, the RF channel selection processing block diagram illustrates one of the non-standard implementations of the RF channel selection processing block 340a shown in FIG. Similarly, the digital channel selection processing block 44 〇 b = the solution is shown in the digital channel selection processing block 3 shown in FIG. 3 : an exemplary implementation manner. The RF channel selection processing block 44A may be applied to the RF integrated circuit 400 that is generally optimized for RF processing, and the digital channel selection processing block 440b may be implemented. A second integrated circuit 410 is generally optimized for digital processing. The amplified broadcast signal 4〇5 corresponds to the amplified broadcast signal provided by the VGA 350 shown in FIG. The RF channel selection processing block 44A may be subjected to a behavioral_mixing stage comprising: - a first mixer f: a skin 427a; a second mixer, a vibrating 4i7b; j^ and an optional brother Passing filter 427b. The double conversion mixing stage operates to upconvert the frequency of the broadcast signal to 21 200915717, such that the selected channel is substantially centered on a first inter-order frequency; The number of channels of the signal is chopped; the frequency of the remaining channels is down-converted such that the selected frequency is substantially centered at a second intermediate frequency; and the channel located near the selected channel is further filtered as appropriate For example, 'the classics The large broadcast signal 405 may be input to the first mixer/oscillator pair 417a. The frequency of the oscillator may be changed by the frequency selector 470, which may be controlled by a user from a channel selected for viewing. The input may be accessed from the digital processing portion and/or an external connection. The first mixer/oscillator pair 4i7a will operate the amplified broadcast signal 4〇5 with a selected operation. The signal provided by the local oscillator at the frequency is heterodyned to shift the frequency of the broadcast signal such that the selected channel is substantially centered on a first intermediate frequency. For example, the first mixture The oscillator/oscillator pair may move the frequency such that the frequency component of the first intermediate frequency broadcast signal is above the frequency range of the amplified broadcast signal to avoid collision with the image frequency and avoid Resonance occurs. The first intermediate frequency signal may then be provided to a bandpass filter d having a predetermined conduction band centered at the first intermediate frequency to allow a peak frequency The signals in the range pass while substantially rejecting all other frequencies. For example, the band pass filter 4仏 may have a conduction band that is substantially suitable for passing a single channel in the broadcast signal. Or, for example, By narrowing the broadcast signal to two or more frequencies, the bandpass filter (4) passband allows more than one channel to pass. In some 22 200915717 some embodiments t 'bandpass filter 427a will Being cried, for example, an external SAW is so thin that it is straightforward, and it is intended to have a conduction band that is configured to narrow the signal to one or more channels while rejecting other frequencies. However, the 'H-skin can also be any type of band-pass filter' skin, because the evil of the present invention is not limited in this respect.帑逋 Filter --- Not the same as the oscillating oscillator pair 417b. The mixer/vibrator pair 41 7b may convert the frequency of the input signal based on the frequency of the signal provided by the local oscillation. 选定, the selected channel is substantially centered at a second intermediate frequency. In some embodiments, the second mixer/oscillator #4m will down-convert the frequencies such that the selected channel will be at the fundamental frequency of the tuner, and in other embodiments, The second mixer/oscillator pair 41 will downconvert the frequencies such that the selected channel is centered at a center frequency. ', ', the second mixer/vibrator pair 417b may be arranged according to the bandpass f wave 427a to allow a single channel or channels from the broadcast signal to pass Further filtered. For example, the output of the second mixer/invigorator 417b may be provided to a band (4) wave 427b to reject channels located near the selected channel. The signal 43 5 provided by the rf channel selection processing block 440a may basically only include the selected channel in the broadcast signal centered on the fundamental frequency of the television receiving device or the specific intermediate frequency thereof, or may include the A channel and one or more adjacent channels or a portion of a nearby channel. The RF channel selection processing block 44a will provide a signal 435 to the digital channel selection processing block 44b on the digital 23 200915717 integrated circuit 410. Digital channel selection processing block 440b may include a feedback loop that includes: a vga 430; an analog to digital converter 445; and a digital intermediate frequency (if) processing block 480. The output of the digital channel selection processing block 44b may be a video signal and/or audio signal 125 that may be displayed and/or provided to a promotional component for presentation to the user. One embodiment of the digital channel selection processing block may operate as follows. The signal 435 supplied to the digital channel selection processing block 4401 may be amplified by the VGA 430. The gain of the VGA is dependent on the gain control signal 455. The amplified signal may then be converted by a analog to digital converter 445 into a digital signal so that the remainder of the gain control process can be handled digitally. If the signal 435 is located at an intermediate frequency signal other than the fundamental frequency, then the digital IF processing 48 may down the frequency of the signal down to the base frequency and demodulate the selected channel. Digital IF processing 480 may also include post processing, which may include any of a number of processing components for performing techniques that may be based on the type and composition of signal 435. Post processing may include any number of processing and/or filtering, demodulation, video and audio processing, decoding and encoding, decompression, etc. of the following and/or combinations thereof. These processes are considered to be through an audio. And/or video presentation to prepare for the necessary processing of the signal to be presented to the user. Digital IF Processing 48〇 may also output a gain control signal that is input to the VGA 430. 45 5 ° Any of a variety of control mechanisms, including those described herein, can be used to generate the gain control signal 455. Digital IF processing 480 may also be 24 200915717 with the frequency selector. 470 communication, to control which channel is selected to be understood, - the channel selection component adapted to isolate a selected harmonic may contain various other components, or may be selected in other ways - Channel. For example, I replaces the double-conversion type front-end shown in Figure 1 with a single-conversion method. The components of the front-end: 4 are only constituents - generally divided into RF 4 and digital processing and = substantial bi-chip design. An example of some embodiments of components of a channel selection process that are dispersed over individual RF bust circuits and digital integrated circuits. In this regard, aspects of the present invention are not limited to use with any specially configured channel selection component, and other tuner configurations adapted to receive and process different types of television signals can be used. For example, any of the various bimorph designs described in the '792 patent may be suitable for the aspects of the present invention. As discussed above, the Applicant has found that 'the division of the AGC into RF processing components and digital processing components may be superior and will enhance the -substantial dual-wafer tuner design, some of which have been implemented in conjunction with Figure 3. Description. Figure 5 illustrates one of the implementations of an AGC control loop that is substantially implemented on two wafers, as described herein, in accordance with certain embodiments of the present invention. The dual-chip design may be due to power detection. The 560a is applied over the RF integrated body wafer 500 and the gain controller 56A is applied over the digital integrated wafer 51A to obtain benefits. The system shown in Figure 5 may be suitable for use in an exemplary assembly of a gain controller in accordance with aspects of the present invention. As discussed above, a VGA 550 may be implemented on the RF product 25 200915717 body circuit 500 for receiving a broadcast signal and adjusting the gain to maintain the power in the signal within an acceptable range. A power detector 560a may be implemented on the RF integrated circuit for detecting one or more power characteristics of the amplified broadcast signal and providing a signal indicating that the one or more detected The detected power level signal 525 of the power feature. The detected power level signal 525 may then be provided to the gain controller 56Gb' to convert the developed power to a gain adjustment value for the vga. The manner in which the gain controller 560b operates may be as follows. The detected power level signal 525 received from the power detector 560a may be converted into a voltage signal, for example, using a Δ to v RC amplification S 561. It should be understood that if the debt measurement power level signal 525 is originally a voltage signal, then the I to v amplifier 561 or other conversion elements may not be needed. In some embodiments in which ς to V conversion is used, the conversion element (for example, transimpedance amplifier 561) may be implemented on the digital integrated circuit 5 〇〇 the digital integrated circuit 510 because This issue is not restricted. Because the aspect of the invention is in this respect

Filtering is used to remove high frequency variations in the detected power level to improve the estimate of the signal gain. In some embodiments, a downsampling block may be included. The digital detected power signal 525 can be converted to a digital signal by a reference signal for indicating a power level in the broadcast signal. A low pass filter 26 200915717 5 5 5 may then be used for comparison. 5th, a reference signal (for example, the reference voltage νπ〇565 may be selected to represent a different power level, which is the power bit in the amplified broadcast signal that the agc tries to maintain as much as possible) The reference voltage may be selected according to the performance specifications of the downstream processing component (such as the channel selection processing block), or may be selected according to other design considerations of the spectrometer. Therefore, the digital power level signal is selected. It may be subtracted from the reference "565" by the summing element 567 (or vice versa) to generate an error signal 568. The error signal 568 operates as a detected power characteristic for estimating the broadcast signal. How far away from the value of the 'X AGC control loop is configured to drive the error signal tiger (10) to zero to maintain the power characteristics of the 5 Hz amplified broadcast signal at the level indicated by the reference signal 565 The error signal 鸠 may then be scaled by the multiply element 566 by the programmable variable parameter k to modify the closed loop system to control the VGA 55() for the broadcast. (1) A time constant of the reaction rate of the change in the power level. The scaled error signal may then be provided to the integrator state, which may be between the detected power level signal and the reference signal. In some embodiments, the controller will be configured such that when the gain of the broadcast signal is too high (for example, 'when the prepared power level signal is greater than the reference signal), The error signal will be positive and the integrator state: the input will increase; @ when the gain of the broadcast signal is too low (for example, 'When the detected power level signal is less than the reference signal), The error 27 200915717 signal will be negative and the output of the integrator 569 will drop. In other embodiments, the controller will be configured such that when the gain of the broadcast signal 115 is too high, the error signal will If the gain of the broadcast signal is too low, the error signal will be positive and the turn of the integrator 569 will increase. It should be understood that Provided by the switch to the adder element The signal symbol can be implemented as an embodiment. The integrator 569 provides an integrated error signal 545 to the gain mapper 590. As discussed above, the gain mapper 59 can be configured to integrate the The value of the error signal 545 is mapped to the gain value represented by the gain control nickname 5 5 5. Then, the gain control signal 5 5 5 may be supplied to the VGA 55 〇 for decreasing the absolute value of the error signal. The gain is adjusted in the direction. Accordingly, the AGc control code is operative to maintain the power level of the amplified broadcast signal, so that the near reference signal is approached. As discussed above, the gain map The device 59 can be implemented on any of the wafers; or, in some embodiments, the 70 can be used without the need. In addition, the AGC control loop may also include a digital to analog converter (DAC) for converting a signal from the gain controller from a digital signal to an analog signal before being supplied to the VGA. The DAC can be implemented on the <壬__ wafer and may be & according to the location where the 5 liters mapper (if provided) is implemented. should. In the case of Haiyuebai, the above-mentioned implementation of an AGC is only an example. The implementation of the method may also apply. Specifically, the % 仃 method described above clarifies how the AGc can be dispersed over two crystals in order to separate the main functions into a core component and a digital component. However, the manner of applying _, 匕, is equally applicable to the aspect of the present invention. In particular, γ 仁 疋 is not limited, and other modes of operation generally in accordance with one: 曰曰5 can be used, since the aspect of the invention is not limited in this respect. The AGC (especially the various components of the whip control loop) can easily determine the effects of errors. One of the common errors is called "shift error" in this paper. Offset errors can occur due to changes in environmental conditions (such as temperature and humidity), and more notably, due to variations in the specifications of the electronic components that make up the associated control loop. An offset is generally referred to as the difference between the actual value that the control loop is to be proud of and the desired value that the control loop intends to converge. In the AGC '$ may cause the control loop to converge to - too large or too small a power level' to expose downstream processing components to non-optimal power levels. In the prior art, various correction techniques are used to resolve the offset error at the time of manufacture. These correction techniques typically involve testing and fine tuning the Xiao AG. s component. However, such conventional correction techniques are very expensive. For example, the 'offset error may be estimated after manufacture but before sale' and the components of the AGC control loop are fine-tuned to compensate for the difference between the actual convergence value and the convergence value. These fine-tuning methods require a very large amount of resources and can substantially increase the cost of manufacturing. The applicant of the present invention has found that the automatic calibration standard that operates at the time of power-on can be used by the provincial department for testing and fine-tuning at the time of manufacture. According to some embodiments, the tuner includes a correction process that corrects the AGC to compensate for the offset error. This correction can be implemented automatically at startup or manually, to reduce the need for post-manufacturing testing and fine-tuning (and thus reduce the cost) in this regard. In some embodiments, the calibration process utilizes the same control, such as: raw, 丨, n, . 扪 control loops to improve the accuracy of the correction, as described in further detail below. Figure 6 illustrates a server having a correction process for correcting - AGC to compensate for offset errors, in accordance with some embodiments of the present invention. The tuner may be identical to the tuner shown in Figure 3. Specifically, the adjustment in Figure 6. The white chip can be a dual-chip design that is generally divided into RF processing components and digital processing components located on separate integrated circuits. However, the tuner 6 包含 also includes a component that is configured to perform a correction on the AGC 630: a calibration process for the industry to reduce the need for post-implementation manufacturing testing and fine-tuning in this regard. It is said that the tuner 60 includes a correction signal generator (7), a motion signal generator 671', and an addition amplifier 677. The line system table in Fig. 6 has not only the link that is active during the correction process but also does not function after the completion of the parent and until the correction process is restarted (for example, when the machine is turned on). The calibration operation is performed at least in part by a = fixed-offset signal, and the offset signal adjusts the measured power level signal supplied by the power controller _ = a predetermined amount to supplement the calibration operation. The offset error of the shift predicted during the period is as described in further detail below. 30 200915717 To correct the AGC, a correction signal having substantially known power may be generated by a correction signal generator 674 preferably located above the RF integrated circuit 6A. The power of the correction signal may correspond to the power level of the broadcast signal input to the channel selection processing block during the operation, and thus may be equal to the reference signal used by the gain controller (for example, The power of the correction signal may be equal to that shown in Figure $

Power of Vref 565). In this regard, if there is no offset error, then ▲ the difference between the output of the power detector and the reference signal (for example, the error signal 568 shown in the figure) should theoretically be equal to zero. . However, even if the actual power characteristic of the broadcast signal is equal to the reference signal, the offset error in the AGC (four) loop (for example, in the power controller and/or the components of the gain controller) may still be This will cause the actual error signal to become non-zero (for example, the fabricated power can deviate from its true value). J ; J ° 杈 杈 positive control loop will operate to adjust the offset signal, so that the error signal is arrogant to zero or close to zero with respect to the generated correction signal =. Once the error signal converges to zero or is close to, the offset signal will reflect the offset error, and the offset error will then be from the power detector during operation of the modulating device. The output signal is further detailed below the port. In one embodiment, the ★hai school positive signal includes a sine wave generated by the ring vibrator. Using a ring oscillator to utilize a relatively inexpensive component to produce a consistent and known voltage lifetime: two: a well-known looper can be implemented as the correction signal generator because the present invention is ώ/ΐβ d is not limited in this respect. In addition to the 31 200915717, other types of correction signals and correction signal generators can be used, as the aspect of the invention is not limited to use with any particular type or arrangement of signal and signal generators. . The processing can start when the tuner is started or turned on, or when it is restarted, or can be started manually at a certain time. When the correction process is initiated, the correction signal generator 674 provides a correction signal 675 to the multiplexer 673, which will select the correction signal 675 during calibration and select the amplified broadcast during normal operation. The output of the 605 will be provided to the power detector 66A, which will prepare one or more power characteristics of the received signal and provide a detected power level signal 625. . If the offset error is present, the detected power level signal 625 may be at least partially incorrect due to the variation of the operational characteristics of the components including the power detector. According to this, some part of the offset error may be caused by the power (four) detector 66〇a. The summing component 677 combines the detected power level signal (2) with the offset signal 672, and the offset signal is adjusted during the correction to compensate for the offset error, and can be set at the beginning. An internal value that may be zero or any other desired value used to initiate the adjusted power level signal 625 provided by the summing element 677 in the correction, which may then be provided to the digit product Gain control Θ 660b above the body power & 61〇. The adjusted power level signal may be converted to a number. The various methods described in Figure 5 or any other suitable control method(s) are processed. 32 200915717, two = gain controller _ may be calculated by the 2 = 2 (or the equivalent of the adjusted power level signal =: =:: match the power level in the correction signal) Referring to the coincidence error signal, the error signal may then be used to apply the error signal of the difference between the power level signal of any other control signal gate m and the reference number. Gain control: The difference signal is converted into a -gain signal or used in the control loop: 1; comparison:: system, control... in: two... system. The second control element is the same. The output of the 接着 may then be a generator, It is used to decide how to adjust the size of the offset 1 to the offset signal. The money is moved to reduce the error signal.

• It should be understood that the correction control circuit in Figure 6 is the same as the AG:' That is, the two control loops contain the phase: the rate and the same gain controller control element 2's control bubble, 兮p τ & Hita knife works on the same component (and thus " See:: the same or the actual phase and thus see the same offset error), School:: Accuracy. It should be understood that the system can also be, its way. However, no matter which control loop is implemented, the & AGC control loop used during the operation of the master is used; the components of the correction control loop used are exempted from a large amount of overlap, but this does not limit the present invention. The way. The system shown in Fig. 7 is identical to the calibration process shown in Fig. 6 - a tuner having 33 200915717 integrated correction processing. However, the correction control loop includes a state machine 771a and a digital to analog converter (DAC) 771b for illustrating one of the possible implementations of an offset signal generator in accordance with some embodiments of the present invention. The DAC 771b may receive a DAC code 71 and convert the DAC code 71 to an offset signal 772. The DAC code may be a digit value stored by the offset generator 771, which converts the digit value to its analog equivalent value for combining the output of the power detector. The DAC code may initially be set to a default value, which may be zero (for example, to initiate the correction and assume that the offset error is zero) or any other range of values that the DAC code can represent. The value of the choice. The state machine 771a may be adapted to at least partially rely on the gain control pro 7 7 0 b & the machine number 7 5 5 (for example, the integrated error signal) tends to cause the control loop The direction of convergence (i.e., tending to drive the error signal of the gain controller to zero) adjusts the dac code. It should be understood that the state machine 771a can be implemented in a variety of ways and can be replaced with a controller that is adapted to adjust the offset signal to reduce the error signal, as aspects of the present invention are aspects of this aspect. Not limited. Figure 8 illustrates a state machine for adjusting a dAc Malay approximation to an offset error in accordance with some embodiments of the present invention. The state opportunity of Figure 8 monitors the signal provided by the gain controller (e.g., the integrated error signal) at regular intervals and retains the three most recent values. The most recent value will be represented by vl, the second nearest value will be represented by v2, and the third nearest value will be represented by v3. In step 8〇〇, the values of vi and v2 34 200915717 are compared to determine if their values are equal. If the values of vl and v2 are not equal, then step 8〇5 may be implemented. In step 805, it will determine whether the gain is increasing (vl > v2) or decreasing (vl < v2). If the right increase is increasing, then the DAC code is assumed to be too small and the DAC code is incremented by one unit in step 8. If the gain is decreasing on the right then the Dac code is assumed to be too large and the DAC code is decremented by one unit in step 8丨5. In f step 820, it is determined if the current value of the DAC code is equal to the most s large or minimum value. If the DAC code is equal to the maximum or minimum, then the correction is complete and the state machine proceeds to step 87. The correction control loop is considered to converge. That is, if the DAC code has been incremented to a preset maximum value, or has been decremented to a predetermined minimum value, an individual maximum or minimum value is used as the DAC code to approximate one during the job. Offset error. If the DAC code is not equal to the maximum or minimum value, then the " state machine will wait for the next U value from the gain controller in step 825 to continue adjusting the DAC code. After receiving the next gain control value, it will determine in step 83 that the value of the gain control signal has changed direction. A change in direction indicates a zero crossing, and the zero-crossing DAC code reflects the offset error in a satisfactory manner. If vl > v2 and v2 < v3, or if vl < v2 and v2 > v3, the values have changed direction. If the value has changed direction of the store, then the defect has been completed and the state machine proceeds to step 870 to approximate the offset error using the witnessed DAC code. If the 35 200915717 value does not change direction (for example, v1<v2<v3 or vl>v2>v3), then the state machine will proceed to step 8〇5 to continue adjusting the DAC. The code attempts to converge the correction control loop (for example, attempting to reach step 870). If, at step 800, the value of V2 is equal, then it is determined in steps 835 and 840 whether vi is equal to the maximum or minimum possible value of the signal provided by the gain controller. If v丨 is not equal to the minimum or maximum value, then the correction is complete and the state machine proceeds to step 870. If vl is equal to the maximum value, then the DAC code is incremented by one unit in step 845; and if vl is equal to the minimum value, then the DAC code is decremented by one unit in step 850. After incrementing or decrementing the DAC code, it is determined in step 855 whether the current value of the DAC code is equal to the maximum or minimum value. If the DAC code is equal to the maximum or minimum value, then the correction is complete and the state machine proceeds to step 87. If the DAC code is not equal to the maximum or minimum value, then the hopper will wait for the next gain control value in step 860. After receiving the next gain control value, it will determine in step 865 whether the gain control values have changed (i.e., whether vl is not equal to if the gain control values have changed), then the correction is already Completion 'and the state machine proceeds to step 870. If the gain control values have not changed, then the state machine proceeds to step 835. The system described above, the state machine described above only It is an example of a state machine suitable for determining the 36 200915717 DAC code to compensate for the offset error. The state machine design of f匕 is also applicable and the aspect of the invention is not limited to this aspect. The offset signal generator does not necessarily need to use a state machine to generate any hardware or software components that are capable of generating an offset signal with an offset error to approximate an offset error, since the aspect of the present invention is The above embodiments of the present invention are not limited. The above embodiments of the present invention can be implemented in any of a number of ways. For example, hardware, software, or a combination of both can be utilized. I. I understand that the △ set of any component or component that uses a f to be used for the functions described above can be considered to be used to control the controller or the controller discussed above. The one or more controllers can be implemented in a variety of ways, such as by using proprietary hardware, circuitry, or by general purpose hard programming using microcode or software to implement the functions mentioned above. Body (for example, - or a plurality of processes (5) to _. ^ Various aspects of the invention may be used alone, in combination, or in a variety of arrangements not explicitly discussed in the foregoing examples of r The application of the present invention is not limited to the details or arrangements of the components illustrated in the foregoing description or the drawings. The invention may have other embodiments and may be implemented or implemented in various ways. The use of the ordinal words "first", "second", "third", ..., etc. in the scope to retouch a patent application component does not contain a patent I request = the authority, priority, order is higher than The meaning of the element does not contain the chronological meaning that the action of the method is implemented, but is only used as a mark to distinguish between a patent application component with a specific name and 37 200915717 another with the same name Twins (rather than used as ordinals) are divided into such patent application components. 乂 £ £ Similarly, the wording and terminology used in this document is used only for the purpose of the statement and should not be considered as limiting. The establishment of "... 逹. 儿明" - 1 thinking of the system. In this article "including", including

J contains

The use of J Guang, and its variants, covers the sounds listed later. A brief description of the personnel and its equivalents and additional items [, a simple description of the schema] The tuner in the conventional television receiver shown in FIG. 1; the μ diagram # 2b is not in accordance with some embodiments of the present invention. For example: an automatic gain controller (AGC) for white devices, the AGc is operated on a signal and an amplified broadcast signal; and, as shown in FIG. 3, according to some embodiments of the present invention - A portion of the server of the automatic device that is implemented in the two integrated circuits 4 is subjected to a channel selection process performed on two products according to some embodiments of the present invention. Exemplary Components; Figure 5 is an exemplary component of an AGC that is implemented over two A circuits in accordance with some embodiments of the present invention, and Figure 6 is used in accordance with some embodiments of the present invention. -AGC correction processing on top of an integrated circuit; an exemplary component of an offset signal generator for a correction process according to some embodiments of the present invention; and at 38 200915717 Figure 8 illustrates an offset signal generation in accordance with some embodiments of the present invention. A state machine. [Main component symbol description] 110 Signal source 115 Broadcast signal 120 Tuner 125 Display signal 130 Display 230 Preamplifier stage 240 Channel selection processing block 250 Variable gain amplifier 255 Gain control signal 260 Automatic gain controller 300 Integrated circuit 305 Amplified broadcast signal 3 10 Integrated circuit 325 Detected power level signal 330 Preamplifier stage 335 Signal 340a RF channel selection processing block 340b Digital channel selection processing block 345 Error signal 350 Variable gain amplifier 39 200915717 355 Gain control signal 360a power edger 360b gain controller 390 gain mapper 400 RF integrated circuit 405 amplified broadcast signal 410 digital integrated circuit 417a mixer/oscillator pair 417b mixer/oscillator pair 427a bandpass filter 427b Bandpass Filter 430 Variable Gain Amplifier 435 Signal 440a 440b 445 l 455 465 470 480 500 510 525 5255 RF Channel Selection Processing Block Digital Channel Selection Processing Block Analog to Digital Converter Gain Control Signal Signal Frequency Selector Digital IF Processing Block RF integrated circuit digital Body circuit detected power level signal digital detected power signal 40 200915717 545 integrated error signal 550 variable gain amplifier 555 gain control signal 5 60a power 1 side 560b gain controller 561 I to V transimpedance amplifier 562 Analog to Digital Converter 563 Low Pass Filter 565 Reference Signal 566 Multiplying Element 5 67 Adding Element 568 Error Signal 569 Integrator 590 Gain Mapper 60 Talker 600 RF Integrated Circuit 605 Amplified Broadcast Signal 610 Digital The integrated circuit 625 has detected the power level signal 625 'the adjusted power level signal 630 automatic gain control loop 635 signal 640a RF channel selection processing block 640b the digital channel selection processing block 41 200915717 650 variable gain amplifier 655 signal 660a power 660b gain controller 671 offset signal generator 672 offset signal 673 multiplexer 674 correction signal generator 675 correction signal 677 adding component 700 RF integrated circuit 705 signal 710 digital integrated circuit 725 'adjusted Power level signal 730 automatic gain control loop 735 signal 740a RF channel selection Select Processing Block 740b Digital Channel Selection Processing Block 750 Variable Gain Amplifier 755 Signal 760a Power Detector 760b Gain Controller 771 Offset Generator 771a State Machine 42 200915717 771b 71 772 773 774 777 Digital to Analog Converter DAC Code Offset Signal multiplexer correction signal generator adding element 43

Claims (1)

200915717 X. Patent Application Range: 1. A calibration component configured to correct an automatic gain controller (AGC) used in a tuner configured to broadcast a selected channel and a multi-channel The signal is isolated, the tuner is essentially implemented on two wafers, a first wafer, including an RF integrated circuit adapted for radio frequency (RF) processing; and a first-曰y In a day, including a digital integrated circuit adapted for digital processing, the correction component includes: a correction signal generator that is implemented on the RF integrated circuit, the correction A number is generated The device is adapted to generate a substantially known correction signal; a power detector is implemented on the RF integrated circuit and is configured to detect the correction signal during correction At least one power source is used to provide a power level signal indicating the at least one detected power characteristic; a gain controller is implemented on the digital integrated circuit, the gain control The device is adapted to generate at least one error signal based at least in part on a comparison value between the power level signal provided by the power detection TM and a first reference signal; - an offset signal generator, Executing on the RF integrated circuit and configured to generate an offset signal based at least in part on the at least _ error signal; and adding an element to be implemented on the RF integrated circuit And it is suitable for combining the offset signal and the power level signal provided by the power detector 44 200915717 for providing - by 2. as claimed in the patent scope! The school's calibration signal generates M j nn ^ , , , , where the correction is 3. The correction component 3. The calibration component of the application model (4) 2 includes a ring oscillator. Among them, the correction 4 · such as the scope of patent application 帛! Correction group #^ The components in the component will constitute a control loop. The control loop will be: used to drive the at least one error signal to zero or substantially zero. When the control loop has substantially converged, the The calibration component will complete the job. 5. The calibration component of claim 4, wherein the offset heart generator comprises a digital to analog converter (dac), and the & is configured to at least partially depend on the at least one error signal The offset signal is generated in a DAC code representing a digital value that will be corrected during the correction. The calibration component of claim 5, wherein the offset «generates the inclusion of - the storage component' to store a final DAC code (4) in the control loop has been received (four) to generate the bias The mobile number. 7_ The calibration component of claim 6 wherein the offset signal generator comprises a finite state machine (FSM) adapted to correct the DAC code based at least in part on the at least error signal . 8. The patent application scope "Beizhi correction component further includes a turns ratio to digital converter (ADC) which will be arranged between the power detector and the boost controller i The power level signal is converted into a digital power level signal for the gain controller to perform digital processing. 45 200915717 9. The calibration component of claim 8 of the patent, wherein the ADC is implemented on the digital integrated circuit. The aligning component of the eighth aspect of the patent, wherein the ADc is implemented on the RF integrated circuit. The calibration component of claim 8 , wherein the gain 1 3 adding component is configured to generate a first error signal according to a difference between the reference signal and the digital power level signal. 12. The correcting component of the u-worker of the patent application scope, wherein the control benefit includes a quarantine r〇 fM, a knife TM, for integrating the first error signal to provide an integrated error signal. 13. A combination of the calibration component of the patent application scope 6 and the AGC, the AGC comprising: an I-amplifier amplifier (VGA) that will be implemented in the RF integrated circuit; the VGA will be Adapted to receive the broadcast signal and used by the alpha knife to apply a variable gain to the broadcast signal according to the gain signal for providing an amplified broadcast signal; the power detector configured to be used to Detecting at least one power characteristic of the amplified broadcast signal after the correction and providing a power level signal 相^/additive element indicating the at least one detected power feature, which is configured to be combined From the final D from the code. The offset signal generated in the method for providing the adjusted power level signal, and the gain controller, which is adapted to be at least partially dependent on the The comparison between the adjusted power level signal and a second 46 200915717 reference signal generates at least one error signal, wherein the 1 gain signal is based at least in part on the + to error signal generated by the gain controller. 14 • A combination of claim 13 of the § § Scope of the patent, wherein the gain mapper is configured to map the integrated error signal to the gain signal. 15_ The combination of claim 14 wherein the gain map is implemented on the RF integrated circuit. 16_ The combination of claim 14 wherein the gain map is implemented on the digital integrated circuit. 1 7 · The combination of claim 16 of the patent application scope, wherein the first reference signal is the same as the second reference signal. 18. An automatic gain controller (AGC) for use in a -meter, the tuner is adapted to isolate a selected channel from a multi-channel broadcast signal, the AGC being configured to The operation mode is adapted to correct the AGC, and the operation mode is adapted to apply a variable gain to a broadcast signal, the AGC comprising: a first control loop comprising: a correction signal generator adapted to generate a correction signal; a power detector 'which is configured to detect at least one of the received round signals a power characteristic and for providing a power level signal indicating the at least one tested power characteristic; 47 200915717 a summing 7C piece for combining the power level signal and an offset signal for providing an adjustment a power level signal; a blood-increasing controller that includes a reference signal, the gain controller being adapted to generate at least an error signal for indicating between the reference signal and the adjusted signal a difference between the power level signals; and a ^-offset horn generator 'which is adapted to provide the offset signal to the adding component'. The offset signal generator is configured to be used at least The boring tool adjusts the offset signal during the correction mode according to the D-Hour v error signal; and a second control loop comprising: a variable-amplifier amplifier (VGA) adapted to receive The broadcast nickname is used to apply a variable gain to the broadcast signal according to the gain signal to provide an amplified broadcast signal; the power detector; the adding component; and the gain controller, \.+ where 'in the calibration mode, the first control loop is in operation and the received input signal sent to the power detector is a correction signal, and the first control loop operates to correct the bias Transmitting signal, such that it reflects the offset error of the AGC, wherein, in the operating mode, the second control loop is in operation and the received input signal sent to the power (four) detector is Widened The broadcast signal, (4) two control loops are used to maintain the power level of the (four) large broadcast signal within the range. 48 200915717 19. The AGC of claim 18, wherein the association is adapted to be used in conjunction with a tuner that is essentially implemented on two wafers: an H__ ay, brother a solar wafer comprising: an RF integrated circuit adapted for radio frequency (RF) processing; and a second wafer comprising a digital integrated circuit adapted for digital processing, and wherein亥 VGA, the correction signal generator, the power predator, and. The Hai offset 5 hole number generator is implemented on the RF integrated circuit, and wherein the 6 Haisheng touch controller is implemented on the digital integrated circuit. 20. The AGC of claim 18, wherein the offset signal generator comprises: a state machine configured to map the error signal to a value indicative of a s-think signal a digital to analog converter (dac) code, and a DAC, which is configured to convert the DA (: code into the offset signal. 21. The AGC of claim 18, further comprising a a multiplexer, the multiplexer being arranged to receive the correction signal and the amplified broadcast signal, the multiplexer being adapted to provide the correction signal to the calibration signal when in the calibration mode a power detector, and configured to provide the amplified broadcast signal to the power detector when in the operating mode. 22. The AGC of claim 21, wherein when the AGC is powered on, The AGC will automatically set the calibration mode. 23. For the AGC of the 22nd scope of the patent application, after the completion of the school 49 200915717, the “Yinghai AGC will be in the operation mode. Patent scope 21 The AGC of the item, wherein the gain control comprises an integrator for integrating the first error signal to provide an integrated error signal. 25. The AGC of claim 24, further comprising a gain map The device is configured to map the integrated error signal to the gain signal, such as the AGC of claim 25, wherein the gain is The mapper is implemented on the RF integrated circuit. /7. The AGC of claim 25, wherein the gain mapper is implemented on the digital integrated circuit. - 28. - Method For correcting an automatic gain controller (AGC) used in the -spectrum 'the spectrometer is configured to isolate the selected channel from a multi-channel broadcast signal, the (four) device being substantially implemented On top of two wafers: - a first wafer, including - an RF integrated circuit adapted for radio frequency (RF) processing; and a second wafer including a digital product adapted for digital processing Body circuit The method includes: generating a substantially known correction signal on the RF integrated circuit; detecting at least one power characteristic of the correction signal on the RF integrated circuit; providing a signal on the RF integrated circuit a first power level signal indicating the at least one power characteristic of the correction signal; receiving the first power level signal on the digital integrated circuit; and at least partially resting on the digital integrated circuit a comparison value between a power 50 200915717 bit signal and a first reference signal to generate a first error signal; and generating an offset signal based at least in part on the first error signal; and combining the offset signal with The first power level signal ' provided by the power detector is used to provide an adjusted first power level signal. 29. The method of claim 28, wherein generating the correction signal comprises using a "vibrator" to generate the substantially known correction signal. 3. The method of claim 29, wherein generating the correction signal comprises using a ring oscillator to generate the substantially known correction signal. 3. The method of claim 28, wherein the action in the calibration method is repeatedly performed on the adjusted first power level signal j until the first error signal is zero or substantially Zero or is judged to be non-# small so that the correction has been completed. ...3: The method of claim 31, wherein the offset signal representative generated during the calibration is stored for compensating for at least one offset during the operation of the AGC error. ^ > /3. The method of claim ", further comprising: converting the first-power level signal adjusted by the Haby to the --bit power level. The hole is used to integrate the digit The method of claim 33. The method of claim 33, wherein converting the power level signal is performed on the digital integrated circuit. 51 200915717 35 as claimed in claim 33 The method of claim 1, wherein converting the first power level signal is performed on the RF integrated circuit. 36. The method of claim 33, wherein the generating the first disease signal comprises determining The difference between the reference signal and the first digital power level signal. 37. The method of claim 28, further comprising operating the AGC after the calibration is completed, the operating the AGC comprising: The RF integrated circuit applies at least part of the gain signal to the broadcast signal to provide an amplified broadcast signal; and the amplified broadcast is detected on the RF integrated circuit. At least one power characteristic of the signal; providing a second power level signal indicating the at least one power feature on the far RF integrated circuit; adjusting the second power level according to the stored offset signal Providing an adjusted second power level signal; receiving the adjusted second power level signal on the digital integrated circuit; and at least partially adjusting the adjusted on the digital integrated circuit The comparison value between the second power level signal and a reference signal generates a second error signal; and the gain signal is provided based on the second error signal at least partially on the CMOS integrated circuit.