200910573 九、發明說明： 【發明所屬之技術領域】 種具金屬接點導孔之堆疊式半 種可堆豐之立體半導體封裝結 本發明係有關於一 、體封裝結構，尤指一 構及其製造方法。 【先前技術 仪’ w式電子裝置-向是在有限的尺寸下 ==與容量’這使得產業界不僅在晶粒層面上 ?，封褒層面上增加其整合度，亦即，可將各晶粒堆 :在：封，鼻上’或將良好的封裝結構堆叠在一 起，以獲得更好的性能及密度。 晶粒堆叠的方法主要受限於最終封裝結構之低良 的複雜度或是與製程相關的問題，使得 封裝結構中無法避免有些晶粒存在低良率。若這此低 良率晶粒未經預先檢測就包含在堆疊結構中 封裝結構的良率之低將會無法接受，因其會等於個別 =^良率測試的總合。另外，預先測試或燒錄裝置 的而要，加上其他技術性問題’例如不良的散埶路卜 以及可能存在的電子干擾（ΕΜΙ)，都使得晶粒堆叠更 加令人興趣缺缺。 •美國專利號 Νο.6,577,〇13 (，， Chip Size200910573 IX. Description of the invention: [Technical field of the invention] Stacked half-type stackable semiconductor package with metal contact holes The present invention relates to a body package structure, especially a structure and Production method. [Previous technical instrument 'w-type electronic device - the direction is limited size == and capacity' which makes the industry not only at the grain level, but also increases the degree of integration at the sealing level, that is, each crystal can be Granules: on: seal, nose' or stack good package structures for better performance and density. The method of die stacking is mainly limited by the low complexity or process-related problems of the final package structure, which makes it impossible to avoid the low yield of some grains in the package structure. If the low-yield die is included in the stacked structure without pre-detection, the yield of the package structure will be unacceptable because it will equal the sum of the individual =^ yield tests. In addition, the pre-testing or programming of the device, together with other technical problems such as poor divergence and possible electronic interference (ΕΜΙ), makes the die stack more interesting. • US Patent No. Νο.6,577,〇13 (,, Chip Size
Semiconductor Packages with Stacked Dies» issued on 加」0,2003 )的專财，描述一藉堆疊複數個晶粒以 200910573 =-：晶片大小之封裝結構’該複數個晶粒係相互 堆逢’使母-晶粒的終端焊點排成—列，而 (through S1liC0n Via)係穿過終端焊點（krm. pad )，使各焊點經由插入導孔的導 曰. 。….电綠路或疋接腳相 逆。除有興晶片堆疊相關的—般性問趨外，該財案 有一明顯缺點，即該垂直連接方法係以一特殊結構堆 疊相同的晶粒。這是因為導電焊點或線路必須插入 透各晶粒終端焊點之導孔以連接。亦即，若有—a 的晶粒放置於該堆疊結構中，其終端焊點就無法= 定垂直路徑上連接，造成終端焊點脫離，而不具所設 計之功能。再者，因大複數個晶粒表面的終端焊點= 當細微，為避免破壞焊點，在焊點周圍所鑽出之導孔 的實際尺寸必須夠小。而小的導孔將迫使以機器插人 的接腳細薄脆弱，基於其低產出及低製造良率^如此 將使批量生產不切實際，故成為一嚴重問題。 美國專利號 No. 6,908,785 (，，Multi-Chip Package (MCP) with a Conductive Bar and Method forSemiconductor Packages with Stacked Dies» issued on plus "0,2003" specialization, describing a package by stacking multiple dies with 200910573 =-: wafer size package structure 'The multiple die are stacked together' to make the mother- The terminal solder joints of the die are arranged in a row, and (through S1liC0n Via) is passed through the terminal solder joints (krm. pad) so that the solder joints pass through the guide holes inserted into the via holes. ....The electric green road or the shackle is reversed. In addition to the general nature of the wafer stacking, the financial scheme has the obvious disadvantage that the vertical joining method stacks the same grains in a special structure. This is because the conductive pads or wires must be inserted through the vias of the die termination pads to connect. That is, if the die of -a is placed in the stacked structure, the terminal solder joints cannot be connected in a vertical path, causing the terminal solder joints to be detached without functioning as designed. Furthermore, because of the large number of terminal solder joints on the surface of the die = when it is fine, in order to avoid damage to the solder joint, the actual size of the via hole drilled around the solder joint must be small enough. The small pilot holes will force the pins inserted by the machine to be thin and fragile, based on its low output and low manufacturing yield. This will make mass production impractical and therefore a serious problem. US Patent No. 6,908,785 (,, Multi-Chip Package (MCP) with a Conductive Bar and Method for
Mamifacturing the Same’’，issued on jun· 21，2005 )的 專利中，描述另一種晶片堆疊結構，具複數個焊點重 佈線（pad re-distribution line )於晶片表面，以重排原 有的終端焊點形成垂直連接。雖然該方法提供的堆疊 方法較有彈性，可緩和僅經由原有焊點垂直連接的嚴 格限制’但该裸晶堆疊方法仍然有一缺點，即必須在 200910573 晶粒邊界才可能進行垂直堆疊 點必須置於下方沒有 ，重新安置的焊 合广+ ^ '區域’這是為確伴導別不 會破壞電路*影響# ;保WL不 I經預先保留這此區域’否：：二但除非在設計上 ^否則在實際操作上並不可能 日密，藉堆疊多個封裳結構成品可以整合石夕 ㈣：：疋機迠以形成一多封裝結構模組。此種方法 封裝在各自的封裝結構中，再相互合 ， 稱』徒供。斗夕優點。例如，在將封裝社 = = = ^ ’每個㈣結構可作電子㈣’'赠 / 々人滿意’否則就加以淘汰。如此，最饮的 少封裝堆疊結構模組係可得到最好的良率。而在堆是 的封裝結構間以及模組的頂端插人—個散熱器，則ς 更有效率的冷卻堆疊封裝結構。封裝層級的堆爲 (package level stacking )也能夠讓rf晶粒具有電= 屏蔽功能’以降低對模組内其他晶粒的干擾。然而， 若在晶片上的封裝材料完全阻斷垂直連接通道，、則將 -封裝結構置放於另-封裝結構上的堆疊方法將受到 挑戰。因此’在層層堆疊之封裝結構中’頂端與底層 的封裝結構間具有垂直連接（z_axis c〇nnecti〇n)，京: 製造方便性、設計靈活度及成本的觀點而言，係為— 關鍵技術。 200910573 已有許多垂直連接的堆疊方法被提出來，包括週 邊焊接球連接（peripheral solder ball connection)，及 在底層封裝結構頂端包覆可撓式基板（flexible -substrate )等。在層層堆疊封裝結構中，使用週邊焊 接球會威重限制設計靈活度，且導致封裝結構的低良 率及大尺寸。而使用可撓式包覆基板一般而言有較佳 的設計靈活度，但折疊過程所需的製造基礎較不穩 固，除此之外，可撓式折疊需要兩層金屬軟板，材料 較為昂貴。再者，由於兩層金屬基板中電路路徑的限 制，可撓式折疊基板僅適用相對低的接腳數。 焊接球連接之限制係進一步詳述如第6及第7圖 所示。 第6圖為一傳統球閘陣列（baU grid array，bga ) 封裝結構剖面圖。B G A封裝結構6 〇 〇包含一半導 體晶片6 1 1及-連接板6 2 〇。該半導體晶片6丄 1的第-表面6 1 Q a上係具有複數個輪出入則工 1，配置有複數個積體電路（IC)。該連接板6 2 〇係 藉由黏著劑6 3 0，例如固晶膠（dieattachep〇xy)'，' 固定於半導體晶片611的第二表面61〇13上，且 連接板6 2 0具有-電介質基板6 2 1，該電介質基 板621的第一表面上係形成-提供線路接合端、; (wirebondfinger)6 2 4 的電路模板如 6 2 2。該電介質基板6 2丄的第二表面上係形成另 200910573 一配置有複數個傳導區（conductive land ) 6 2 5的電 路佈局623。每一電路佈局622、623係包含 一導電材料’例如銅’且以電鍍導孔6 2 6連接。阻 焊漆（solder mask) 6 2 7、6 2 8係分別塗佈於電 介質基板6 2丄及電路佈局6 2 2、6 2 3，使固接 點（bonding site)下方的金屬露出，以提供電子連接， 例如線路接合端線6 2 4與傳導區β 2 5分別與各線 路6 4 0及焊接球6 7 0連接。 半導體晶片6 1 1的輸出入點6 1 〇係以導電線 % 6 4 0與連接板6 2 0笫一表面上的線路接合端線 624電連接。為防止半導體晶片61丄及路線64 0與外界環境接觸，係用樹脂封裝材料6 5 〇封裝連 接板6 2 0之第一表面，以利操作。封裝《，複數個 焊接球6 7 0會回流而炫化在電路佈局6 2 3的傳導 墊6 2 5上，以提供電路板互連。 第7圖係傳統二層堆疊封裝結構（2_stacked package-on_package)模板剖面圖，其中，在一堆疊形 式之封裝結構間係藉焊接球7 7 5形成一垂直^接 U-interc〇nnect)。於該堆疊結構中，底層封裝結構係 如第6圖所示，在電介督其如 傳導巴，…Ϊ 表面具有複數個 傳導a些傳㈣位於封裝結構周邊，且未被 材，所封裝。另-封裝結構（即，，頂層，，封裝結構）堆 豐在底層封裝結構上，係與底層封裝結構之結構相 10 200910573 藉焊接球7 ，可達成二 似’只是焊接球僅安置在封裝結構周邊。 7 5回流至底層封裝結構上表面之 層堆叠封裝結構之垂直連接。 上面所述傳統堆疊封裝結構係 因I二妓版來說係介於G'5mm至^咖範圍内。 I球7 7 5直徑長度必須長到足以在回流時 、氏4BGA的固定墊（b〇nding 順利接觸亦 即丄焊接球7 7 5的直徑必須大於底層封裝結構的封 、一 八A叶诚砵1偟吓衣示一個大的焊接 球高度’限制了有限空間内可空納的球數。 以上所述之傳統堆疊封裝結構，由於焊接球的周 ，配置問題，迫使該堆疊封裝結構不得不比B GΑ的 標準尺寸大，如此則產生一個問題，即無法適用於各 種小型電子設備，例如記憶体模組、記憶卡、行動電 话、筆記型電腦及個人數位助理（PDA )。 美國專利號 N〇_ 6,900,〇74 (，，z-axis Connection 〇f Multiple Substrates by Partial Insertion of Bulges of a Pin”’ issued on April 6, 2004 )的專利中’描述一立體 電路模組，利用彎曲接腳（twist pin )電連接複數個具 隔離空間之電路板。該前案有一明顯缺陷，即接腳和 電錢導孔之間沒有金屬性（metallurgical )連接，故在 各種熱處理之下裝配電路板時，其物理性接觸並不穩 200910573 固。 而觀諸現行已知半導體晶片裝配的各種發展階段 ，限制’半導體晶片裝配的需求係在於節省成本，可 信賴’且可同時提供優良的機械與電子特性，以及對 一特定應用有效地使用一特別連結技術。 故’一般習用者係無法符合使用者於實際使 之所需。 【發明内容】 本發明之主要目的係提供—半導體封裝結構，且 -導孔及-插入之金屬接腳’適用於層模 組。 伏 =明之另一目的係提供—便利且節省成本之方 法以製造以上所述半導體封裝結構。 為達以上目的，本發明為—具 ==裝，複數個置放於連心 接點’與穿過母-焊接點及連接板的導電接腳， =接’其中’該導電接腳至少有一端置於半導體封 裝結構上’複數個半導體封裝結構係堆疊在—起.且 該對應的導電接腳露出之端點係連接在一起。， 本發明包含上述半導體封裝結 步驟係包含：提供-其上具㈣路佈 : 佈-焊接材料至該連接板之電路佈局上;連接！半； 12 200910573 體晶片至該連接拓，甘+ 第二相對表面，而該曰、㉟半導體晶片包含第—及 點；形成一接合點:：盘的第一表面係包含-輸出入 ^連接；以封裝程序電路佈局及該輸出入點電 面對第一方=^封裝晶片:其中，封裝材料包含一 面’而该第二方向係與第一方向相 ：：表 之外，並且，曰f延伸至晶片及連接板 -且日日片係嵌入封裝材料中，而在第一 上垂直延伸至連接板之外；一 ° 一邻八& ,成一導孔，穿透並去除 。刀’于裝材料、焊接材料與連接板 該導孔直徑相同或幾乎相同的金屬接腳插人導 接觸路出的焊接材料’藉使焊接材料回流以形成一連 接接點，電連接該電路佈局與所插入之金屬接腳。據 此’可獲得一全新的具金屬接點導孔之堆疊式半導俨 封裝結構。 ㈣ 【實施方式】 請參閱『第1Α圖』所示，係本發明第一實施例 之半導體封裝結構剖面圖。如圖所示：一堆疊半導体 封裝結構1 〇 〇係具有複數個金屬接腳’插I穿透該 半導體封裝結構1㈣，其中，該金屬接腳以焊錫魚 —電路佈局122、123互連，該半導體封裝結構 1 0 0包含一半導体晶片1 1 〇，該半導体晶片工工 〇之第一表面1 1 0 a係具有複數個輸出入點 13 200910573 1。一連接板1 20，包含一電介質基板i 2 i及位 於該電介質基板1 2 1各表面上之電路佈局1 2 2、 1 2 3。該連接板1 2 0係以黏著劑1 3 ◦，例如固 r晶膠（die attach epoxy)，固定在該半導体晶片工工〇 之第二表面1 1 〇 b上。 本發明可使用不同的基板’包括一層壓板、一彈 性聚亞醯氨耀帶（polyimide tape )或一陶瓷基板。該 電路佈局1 2 2係配置有線路接合端線（wire b〇nd finger) 1 2 4 ;而一傳導區丄2 5係在該電介質基板 1 2 1之第一表面1 2 i a上形成。另一電路佈局丄 2 3係在該電介質基板工2工之第二表面工2工]3上 形成。該傳導區125係具—下方焊點。阻焊漆12 7、128係分別塗佈在該電路佈局122、123 上’以露出下方連接處的㈣供電子連接。該連接板 之第-表面上的電路佈局係、朝向晶片橫向延伸至傳導 區1 2 5之外。In the patent of Mamifacturing the Same'', issued on jun 21, 2005, another wafer stack structure is described with a plurality of pad re-distribution lines on the wafer surface to rearrange the original terminals. The solder joints form a vertical connection. Although the method provided by the method is more flexible, it can alleviate the strict limitation of vertical connection only through the original solder joints. However, the bare crystal stacking method still has a disadvantage that it is necessary to perform vertical stacking points at the 200910573 grain boundary. There is no underneath, re-positioned welding is wide + ^ 'area' which is for the accompanying guide does not destroy the circuit * influence #; Bao WL does not reserve this area in advance 'No:: 2 but unless in design ^ Otherwise, it is not possible to be dense in practice. By stacking multiple finished products, you can integrate Shi Xi (4):: 疋 迠 to form a multi-package structure module. This method is packaged in the respective package structure, and then combined with each other. Doosan advantage. For example, in the package agency = = = ^ ’ each (four) structure can be electronic (four) ''gifts/satisfaction' or else eliminated. In this way, the best-selling, low-package stacking module provides the best yield. In the package structure between the stack and the top of the module, a heat sink is used to cool the stacked package structure more efficiently. The package level stacking also enables the rf die to have an electrical = shielding function to reduce interference with other dies in the module. However, if the encapsulation material on the wafer completely blocks the vertical connection vias, the stacking method of placing the package structure on the other package structure will be challenged. Therefore, in the package structure of the layer stack, there is a vertical connection (z_axis c〇nnecti〇n) between the top and bottom package structures. In terms of manufacturing convenience, design flexibility and cost, it is the key technology. 200910573 A number of vertical connection stacking methods have been proposed, including a peripheral solder ball connection, and a flexible-substrate on the top of the underlying package structure. In a layer-by-layer package structure, the use of perimeter solder balls limits the design flexibility and results in low yield and large size of the package structure. The use of a flexible coated substrate generally has better design flexibility, but the manufacturing process required for the folding process is less stable. In addition, the flexible folding requires two layers of metal flexible sheets, which are relatively expensive. . Furthermore, due to the limitation of the circuit path in the two-layer metal substrate, the flexible folded substrate is only suitable for a relatively low number of pins. The limitations of the solder ball connection are further detailed as shown in Figures 6 and 7. Figure 6 is a cross-sectional view of a conventional baU grid array (bga) package structure. The B G A package structure 6 〇 〇 comprises a half of the conductor chip 6 1 1 and a connection plate 6 2 〇. The first surface 6 1 Q a of the semiconductor wafer 6 丄 1 has a plurality of wheel-in and turn-in processes 1, and a plurality of integrated circuits (ICs) are disposed. The connecting plate 6 2 is fixed on the second surface 61〇13 of the semiconductor wafer 611 by an adhesive 600, such as a die attach adhesive, and the connecting plate 620 has a dielectric. The substrate 621, the first surface of the dielectric substrate 621 is formed to provide a line bonding end, and the circuit template of the wire bond is 6 2 2 . A second circuit surface 623 is formed on the second surface of the dielectric substrate 162. A circuit layout 623 is provided with a plurality of conductive land 6 2 5 . Each of the circuit layouts 622, 623 includes a conductive material 'e.g., copper' and is connected by plated vias 626. Solder mask 6 2 7 , 6 2 8 are respectively applied to the dielectric substrate 6 2 and the circuit layout 6 2 2, 6 2 3 to expose the metal under the bonding site to provide The electronic connection, for example, the line bonding end line 6 2 4 and the conduction area β 2 5 are respectively connected to the respective line 640 and the solder ball 607. The input/output point 6 1 of the semiconductor wafer 61 is electrically connected to the line bonding end line 624 on the surface of the connecting plate 6 2 0 by a conductive line % 6 4 0 . In order to prevent the semiconductor wafer 61 and the route 64 from coming into contact with the external environment, the first surface of the connecting plate 620 is packaged with a resin encapsulating material 6 5 以 for operation. The package ", a plurality of solder balls 670 will reflow and sleek on the conductive pads 6 2 5 of the circuit layout 6 2 3 to provide board interconnection. Figure 7 is a schematic cross-sectional view of a conventional two-layer stacked package structure (2_stacked package-on_package) in which a solder ball 7 7 5 is formed between a stacked package structure to form a vertical U-interc〇nnect. In the stacked structure, the underlying package structure is as shown in Fig. 6, and it has a plurality of conductions on the surface of the substrate, such as conduction, a (b) is located at the periphery of the package structure, and is not encapsulated. In addition, the package structure (ie, the top layer, the package structure) is stacked on the underlying package structure, and the structure of the underlying package structure is 10200910573. By soldering the ball 7, a two-like can be achieved. Only the solder ball is placed only in the package structure. Surroundings. 7 5 is reflowed to the vertical connection of the layer stack package structure on the upper surface of the underlying package structure. The conventional stacked package structure described above is in the range of G'5mm to 255 for the I 妓 version. I ball 7 7 5 diameter length must be long enough to reflow, 4BGA fixed pad (b〇nding smooth contact, that is, the diameter of the solder ball 7 7 5 must be larger than the bottom package structure of the seal, one eight A Ye Chengzhen 1偟 scare clothing shows a large solder ball height 'limits the number of balls that can be emptied in a limited space. The traditional stacked package structure described above, due to the circumference of the solder ball, configuration problems, forced the stacked package structure has to be better than B The standard size of the GΑ is large, which creates a problem that cannot be applied to a variety of small electronic devices such as memory modules, memory cards, mobile phones, notebook computers, and personal digital assistants (PDAs). _ 6,900,〇74 (,, z-axis Connection 〇f Multiple Substrates by Partial Insertion of Bulges of a Pin”' issued on April 6, 2004 ) describes a stereo circuit module using a bent pin (twist Pin) electrically connecting a plurality of circuit boards with isolated spaces. The prior case has a significant defect that there is no metallurgical connection between the pins and the money guiding holes, so When the board is assembled under heat treatment, its physical contact is not stable. In view of the various stages of development of the currently known semiconductor wafer assembly, the requirement for 'semiconductor wafer assembly is to save cost, be reliable' and simultaneously Providing excellent mechanical and electrical properties, as well as the effective use of a special joining technique for a particular application. Therefore, 'the general practitioners are unable to meet the needs of the user in practice. SUMMARY OF THE INVENTION The main object of the present invention is to provide - The semiconductor package structure, and the via holes and the -inserted metal pins are suitable for the layer module. Another purpose of the volts is to provide a convenient and cost effective method for fabricating the above described semiconductor package structure. The present invention is a device having a == mounting, a plurality of conductive pins disposed at the centering contact and through the mother-soldering point and the connecting plate, and wherein the conductive pin has at least one end disposed on the semiconductor a plurality of semiconductor package structures are stacked on the package structure, and the exposed ends of the corresponding conductive pins are connected together. The invention includes the above semiconductor package junction step comprising: providing - having a (four) road cloth: cloth-welding material to the circuit layout of the connection board; connecting! half; 12 200910573 body wafer to the connection extension, Gan + second relative a surface, and the 曰, 35 semiconductor wafer includes a first-and-point; forming a junction: the first surface of the disk includes an - output connection; the package circuit layout and the input-in point face the first party =^ package wafer: wherein the encapsulation material comprises a side 'and the second direction is opposite to the first direction:: and the 曰f extends to the wafer and the connection board - and the day-to-day film is embedded in the encapsulation material, On the first side, it extends vertically to the outside of the connecting plate; one° and one adjacent to the eighth & a through hole, penetrates and removes. The welding material of the knife's material, the welding material and the connecting plate having the same or almost the same diameter as the guiding hole of the connecting plate is inserted into the contact material by the contact material, so that the solder material is reflowed to form a connecting contact, and the circuit layout is electrically connected. With the inserted metal pin. According to this, a new stacked semi-conductive 封装 package structure with metal contact holes can be obtained. (4) [Embodiment] Please refer to FIG. 1 for a cross-sectional view showing a semiconductor package structure according to a first embodiment of the present invention. As shown in the figure: a stacked semiconductor package structure 1 has a plurality of metal pins 'inserts' through the semiconductor package structure 1 (4), wherein the metal pins are interconnected by solder fish-circuit layouts 122, 123, The semiconductor package structure 100 includes a semiconductor wafer 1 1 〇 having a plurality of input and output points 13 200910573 1 . A connection board 120 includes a dielectric substrate i 2 i and circuit layouts 1 2 2, 1 2 3 on the respective surfaces of the dielectric substrate 112. The connecting plate 120 is fixed to the second surface 1 1 〇 b of the semiconductor wafer tool by an adhesive 1 3 , for example, a die attach epoxy. The present invention can use a different substrate 'comprises a laminate, an elastic polyimide tape or a ceramic substrate. The circuit layout 1 2 2 is provided with a wire bond finger 1 2 4; and a conductive region 丄 25 is formed on the first surface 1 2 i a of the dielectric substrate 1 2 1 . Another circuit layout 丄 2 3 is formed on the second surface of the dielectric substrate. The conductive zone 125 is tied to the lower solder joint. Solder resists 12, 128 are applied to the circuit layouts 122, 123, respectively, to expose the (four) electron-donating connections at the lower connections. The circuit layout on the first surface of the web extends laterally beyond the wafer to the conductive region 1 2 5 .
該半導体晶片11〇與電路佈局122@係K t導体晶片110之輸出入點111與該電介質基相 1 2 1第一表面1 2 1 a之结饮社人 之線路接合端線1 2 4間# 線固接點1 4 0連接。 j 該半導体晶片1 1 〇及飧& . U及線固接點1 4 0係以樹脂 黏者劑（resin encapsulant)] u 1 3 U封裝，可以防護外 界物理性、化學性或機械性 又 饵鐵性的才貝害。該樹脂封裝材料 200910573 a 150係將該電介質基板121之 整體完全封裝。 請進一步參閱41β圖』所示，係本發明第一 實施例之4·導ft㈣結構邊緣導孔下 ;材=邊r複數個導孔180係穿透樹= 裝材科150、焊錫16Q及逹接板12〇。 當使用G.2職;的鑽頭時，導孔18〇的細緻程度 .麵。饭设導孔至晶粒邊緣的最小空 0.1mm，則各邊；e λα城《 尽荀 J谷邊尺寸的擴展因導孔i 8 〇而可 〇_4mm無論BGA封裝厚度為何。 及犀=方法’堆疊封裝結構的封裝面積（—Hnt)The semiconductor wafer 11 and the circuit layout 122@ is the output point 111 of the K t conductor wafer 110 and the dielectric base phase 1 2 1 the first surface 1 2 1 a #线固接点1 4 0 connection. j The semiconductor wafer 1 1 〇 and 飧 & U and the wire fixing point 1 40 are packaged in resin encapsulant u 1 3 U to protect the external physical, chemical or mechanical properties. The bait is irony. The resin encapsulating material 200910573 a 150 completely encapsulates the entire dielectric substrate 121. Please refer to the 41β diagram as shown in the figure, which is the edge guide hole of the 4th guide ft (four) structure of the first embodiment of the present invention; the material = the edge r, the plurality of guide holes 180 is the penetration tree = the loading section 150, the solder 16Q and the crucible The board is 12 〇. When using the drill bit of G.2; the fineness of the guide hole 18〇. The minimum space of the guide hole to the edge of the grain is 0.1mm, then each side; e λα城" The extension of the J-edge size can be 〇4mm regardless of the thickness of the BGA package. And rhinoceros = method 'package area of stacked package structure (-Hnt)
St可大幅縮減’且在絕大部分應用上都在可接 二：，如此可同時將數目眾多的金屬接腳置放於 圍繞晶片。製造方便性及設計靈活性 白有助於此項特性。 、兹複數個的金屬接腳1 9 0係置入導孔丄8 〇中， :孔1 8 0係具略小或幾乎等於金屬接腳的直徑，以 的機械接合。該金屬接腳1 9 0主㈣橫向 錫傳J固接點（―⑷160 (通常為焊 連接，而傳導固接點i 6 〇係自連接板丄2 〇 點〕2面與該電路佈局12 2電連接。該傳導固接 ' 6 0係在金屬接腳工9 〇、電路佈局χ 螃 固接點1 40及半導體晶片1 1 0之輸出入勢丄丄7 15 200910573 間提供電延續性（electrical continuity )。 例如，0.2mm的導孔穿透一厚度18μπι的封閉電 ，佈局1 2 2所露出的傳導區域是3.14χ2⑽χ 18㈣ 平，，此區域限定該導孔丄8 〇中的金屬接腳丄9 〇 至該電路佈局1 2 2間的最大接觸區域，且因其通常 太小，以致無法獲得任何可接受之可信任接觸點。 藉2在鑽出導孔i 8 0前熔點焊錫（通常約 ΙΟΟμηι呵）於電路佈局上，該電接觸區域在導孔1 8 〇内可大Ί»田增i 600% ’此接觸區域的擴大不僅降低接 觸電.，·且並增進封裝結構可信度，同時可在堆疊時提供 非常細緻的垂直連接（^-interconnect)。 ，、 該金屬接腳B0有二露出端，其具一終端表面 1 9 0 a與該封裝結構之第一表面同肖，而其他終端 表面1 9 0 b係與該封裝結構之第二表面同向。且唁 終端表面190a、19〇,分別在上下堆疊時作為 連接之用。 ^般常用的谭接球（s〇iderban)相較，金 腳1 9 0係強化z軸垂言 菊禪 神I直連接。一般而言，該金屬接 腳B0可視為預成形圓柱，較回流後可能變形 接球更為堅固。 請參閱『第2圖』所示，係本發明第二實施 半導體封裳結構剖面圖。如圖所示：一半導體封裝結 200910573 構2 0 〇的導電區與傳導固接點並不封裝入樹脂封裝 材料。 半導體封裝結構2 0 0含有半導體晶片2丄〇， 具有複數個輸出入點2 1 1，提供複數個積體電路 (IC)。一連接板2 2 0係藉由一黏著劑2 3 0，例如 固晶膠，固定於半導體晶片2 1 〇之第二表面2丄〇 b上。 3玄連接板2 2 0係具m基板2 2 ±。一配 置線路接合端線2 2 4的電路佈局2 2 2係在電介質 :板221之第一表面221a上形成，另一個電路 :=23 ’以及傳導區2 2 5在電介質基板221 一表面22lb上形成，在電路佈局222、2 別塗佈阻焊漆2 2 7、”8，露出固定位 置下方的金屬作為電子連接。 體晶2 1 路佈局2 2 3係藉由半導 第：表面” T輸出入點2 1 1、電介質基板2 2 1 ◦及另-電路佈局223之間的〜 :導孔28 2 4 0所連接。連 =口接點（而eb0⑷ 朝向曰接板第-表面之電路佈局2 2 3係 白曰曰“向延伸至傳導區2 2 5之外。 該封裝半導體晶片2 1 〇與線固接 —樹脂封裝材料2 5 〇 往2 4 〇知、以 係將該電介質基板22 7之第封裝材料2 50 」 表面2 2 1 a整體完 200910573 全封裝。 位於封裝結構邊緣之複數個導孔2 8 0係穿透該 樹脂封裝材料2 5 0、該連接板2 2 0、該傳導區2 25及傳導固接點260。複數個金屬接腳29〇係 放置在導孔2 8 0中，且具一較導孔2 8 0略小或是 幾乎相同之直徑。 該金屬接腳2 9 0主要係自橫向與該傳導固接點 2 6 0電連接；且該傳導固接點2 6 〇係自連接板2 2 0之第二表面與電路佈局2 2 3電連接。傳導固接 點260在金屬接腳290、電路佈局223、電錢 導孔2 2 6、電路佈局2 2 2、線固接點2 4 〇，以 及半導體晶片2 1 〇之輸出入點2 1 1間提供電延續 性。該金屬接腳2 g ◦之露出部分係位於該封裝結= 之第-表面2〇〇a及第二表面2〇〇b作為上 下方堆疊時終端之一部分。 主道躲^ 乐d圖』所示，係本發明第三實施例之 -封裝結構剖面圖。如圖所示：一半導體封裝結 構3 0 〇連接板之第一 材料所封裝，且丄：第一表面未被樹脂封裝 係覆晶封裝。+導體封裝結構3〇〇之連接方式 該半導體封裝 〇，其輪出入點3 複數個積體電路。 結構3 0 〇有一半導體晶片3 1 1 1上有複數個連接凸塊3 4 〇目、 連接板3 2 0以黏著劑，通常即 18 200910573 底部填充劑3 3 0，固定於該半導體晶片3丄〇之第 表面3 1 0 a。该連接凸塊3 4 0係由焊錫或金製 成。 r «亥連接板3 2 0具有一電介質基板3 2 1。一電 路佈局322係在該電介質基板321之第一表面3 2 1 a上形成且具固定焊點3 2 4。另—電路佈局3 2 3係在電介質基板3 2工之第二表面3 2工b上形 成，阻焊漆3 2 7、3 2 8係分別塗佈於該電路佈局 3 22、323 ’以露出固定焊點處之下方金屬供電 該半導體晶片3 1 〇與電路佈局3 2 2間之連接 係藉由該半導體晶片31〇之輸出入點 電介質基板3 2 1之第一袅而？ 9 Ί Ί9/«〇 213上的固定烊點 2 4及電路佈局3 2 2間的連接凸塊3 4 〇獲得。 ::接板第一表面之電路佈局322係朝向晶片橫向 邊緣的複數個導孔3 8 0係穿透連接板 焊錫）广325及傳導固接點360(通常為 :錫)。硬數個金屬接腳39〇係存 中：且具直徑與導孔3 8 0相同或幾彻。金屬 腳9 0主要係自橫向與傳導固接點3 6 〇電 接；而該傳導固接點3 6 〇 連 表面電連接至電路佈局32:自連接板32◦的第二 料J 2 3。該傳導固接點3 6 〇 200910573 在金屬接腳3 9 0、電路佈局3 2 3、導孔、盆他電 路佈局322、螺㈣接（即連接 ㈧ 導體晶片3⑽出入點311間提供電丰 :屬：腳390之露出端係位於封裝結構第一表 及第一表面，分別作為上下方堆叠時終端的一部分。 半導4圖』所示，係本發明第四實施例之 封裝結構剖面圖。如圖所示：一二層式堆疊之 +導體封裝結構4㈣係包含—頂端封裝結構400 二Π复ΓΓ頂：金屬接腳4 9 0 a;及-底層封裝 ^ 具複數個底部金屬接腳4 9 0 b，1 中，该複數個頂端金屬接腳4 g卩 金屬接腳4 9 0 b連接.係與複數個底部 η… 複數個底部金屬接腳4 9 〇b係與複數個頂端金屬接㈣g :與底部金屬接腳49〇a、49〇b係以 5相互連接。而該底層封 焊接球46〇或傳導區（=：14=;#'具複數個 •r先分配谭錫4 7 5至底層封裝結構 金屬接腳490a-端’再與頂端封裝結構 ^ 之金屬接腳4 9 0 a排成一列。為幫 的物理盥雷不、鱼拉 4幫助兩封裝結構間 屬接娜Γο 頂端金屬接腳4 9 0 3與底部金 屬接腳4 9 0 1)係藉由焊錫回流加以熔接。 、> :參閱『第5 Α〜5 Η圖』所示，係本發明製造 ,3封裝結構之各階段剖面圖。如圖所示：在第5 20 200910573 A圖中’連接板500係有_電介質基板5 2 1 — 具線路接合端線5 2 4之電路佈局5 2 2 ;及一在 電介質基板521之第一表面ς9ι μ , 乐衣面521a上的傳導區5 2 5。另-電路佈局5 2 3係在該電介質基板 之第二表面5 2 1匕上形成。阻烊漆5 ”、 係分別塗佈在電路佈局5 2 2、5 2 3上，露出 點之下方金屬形成電連接。 在第5Β圖中，一焊錫560在電路佈局522 之傳導d 5 2 5上溶化。該焊錫5 6 〇炫點在傳導區 υ 2 D上馮讓焊錫在<後的階段囚流。預先熔點的烊 錫提供-易於組裝的程序以協助—插人的金屬接腳與 一電路佈局間的電接觸。 、 在第5C圖巾’一半導體晶片51〇係藉黏著劑 5 3 0固接該連接板5 〇 〇。 在第5D圖中，該半導體晶片5 i 〇與電路佈局 5 2 2間之連接，係經半導體晶片5丄〇之輸出入點 5 1 1與電介質基板5 2 1第一表面5 2丄a上之線 路接合端線5 2 4間的線固接點5 4 0所形成 在第5 E圖中’該半導體晶片5 1 〇、線固接點 5 4 0、及焊錫5 6 〇係以樹脂封裝材料5 5 〇封裝。 在第5 F圖中’複數個導孔5 8 〇係沿著封裝結 構的邊緣形成’該些導孔5 8 0係穿透該樹脂封裝材 200910573 料5 5 0、焊錫5 6 〇及連接板5 2 〇 ^ 在第5 G圖中， 與導孔相近或幾乎相 複數個金屬接腳5 9 〇，其直徑 同，係分別插入該導孔5 § 〇。 之後圖中，該金屬接腳5 9〇係在焊錫回流 後鎖Y心位，其中，該烊錫5 6 :::::且自連接板5 2 0之第-表面與ΐ路： 接。該禪錫5 6 〇做為一傳導固接點，係 f屬接腳5 9 0、電路佈局5 2 2、線固接點5 〇…體晶片51〇之輸出入點511間以 延頊性。 製造半導體堆疊封裝結構可進一步包括自一串帶 中測試與切割（singulaiiGn)封裝結構成品， 例如早切或衝切；以及封裝以便進一步使用。 〜本發日m點為可枝製造半導体封裝結構及 郎名成本。 請裝、、、。構有利之處在於可在堆疊組裝前加以測 而！生此或可罪度未達要求的封裝結構可被除去， 故僅有測試後狀況良好的封裝結構會被使用在堆疊模 組中以極大化最終組裝良率，令人滿意。 本發明另一個優點係在印刷電路板（pcB)及連 :妾器工業（connector industdes )具良好的鑽孔及金屬 腳插入权序，並因此本發明之技術可在多層封裝結 22 200910573 構堆疊上具最低成本，毋需經過重大的修改，即可 接適用於半導體封裝 工業 本發明之優點尚有該金屬接腳為一獨立元件，μ 此可確保強徤的機械強度、一致性及垂直電連接。糟 本發明之優點尚有插入的金屬接腳與電路佈局 的接觸區域大幅增加’係由於導孔中所露出焊錫的^ 觸面積大’故而確保—可信賴的橫向連接。 本毛明之優點尚有封裝結構不需要 化學渥性電鍍，因其冗長、不易控制且不可信：： 其當樹脂封裝材料中包含填充料時。 本^之優點尚有封裝結構不需在導孔中充填焊 二 或是導電膠（_clUetiveadhesive)， =然本發明之程序仍具靈活度可在需要時使用這些技 本發明之優點尚有圍續θ y 提供一 B日片的複數個金屬接腳可 電；干擾T以限制RF晶片與其他相鄰晶片間的 电千干擾，而在一此梏π π , 外作為散熱片之用此種電子屏蔽狀態可額 板，優點尚有該封裝結構可適用於各式連接 子可：板’可撓屈材料或陶莞基板，板 卞了具有早一或複數個路怪 造垂直連接點以連接插人 u lng layer) ’可製 的金屬接脚與所設計的電 23 200910573 路。 惟以上所述者’僅為本發明之較佳實施例，當不 能以此限定本發明實施之範圍；故，凡依本發明申請 專利範圍及發明說明書内容所作之簡單的等效變化與 修飾’皆應仍屬本發明專利涵蓋之範圍内。 〃 24 200910573 【圖式簡單說明】 第1 A圖，係本發明笛 , 面圖第—實施狀半導體封裝結構剖 第！關，係本發明第—實施例之半導 緣導孔下視圖。 口構邊 結構剖面 第2圖’係本發明第二實施例之半導體封裝 圖。 第3圖’係本發明第三實 圖0 施例之半導體封裝結構剖 面 第4圖，係本發明第四實施例之半導體封裝結構剖面 圖。 第5A〜5 Η圖’係本發明製造半導體封裝結構之各 階段剖面圖。 第6圖’係傳統BGA半導体封裝結構剖面圖。 第7圖，係傳統具焊點球供BGa半導體堆疊封裝結 【主要元件符號：垂直連接之多封裝結構模組剖面圖。 半導體封裝結構1 〇 〇、2 0 0、3 〇 〇、4 〇 〇 半導体晶片110、210、310、51〇 第—表面ll〇a 第二表面ll〇b、210b 輸出入點1 1 1、2 1 1、3 1 25 200910573 連接板120、220、320、520 電介質基板121、221、321、521 第一表面 121a、221a、321a、52 p 第二表面 121b、221b、321b、52 電路佈局122、123、222、223、 322、323、522、523 線路接合端線1 24、224、524 傳導區125、225、325、525 阻焊漆127、128、227、228、 32 7、328、527、528 黏著劑130、230、530 線固接點1 4 0、2 4 0、5 4 0 樹脂封裝材料1 5 0、2 5 0、5 5 0 傳導固接點（焊錫）1 6 0、2 6 0、 3 6 0、5 6 0 導孔 180、280、580 金屬接腳190、290、390、590 終端表面190a、190b 第一表面2 0 0 a 第二表面2 0 0 b 第一表面31〇a 26 200910573 固定焊點3 2 4 底部填充劑3 3 0 連接凸塊3 4 0 頂端封裝結構4 0 0 a 底層封裝結構400b 焊錫4 7 5 焊接球4 6 0 頂端金屬接腳4 9 0 a 底部金屬接腳4 9 0 b 連接板5 0 0 27St can be greatly reduced' and can be connected in most applications: so that a large number of metal pins can be placed around the wafer at the same time. Manufacturing convenience and design flexibility White contributes to this feature. The plurality of metal pins 1 90 are placed in the via holes 丄 8 ,, and the holes 1 8 0 are mechanically bonded with a slightly smaller or almost equal diameter to the metal pins. The metal pin 1 90 main (four) transverse tin transfer J solid contact point (― (4) 160 (usually a welded connection, and the conductive fixed contact i 6 〇 is from the connection plate 丄 2 〇 point) 2 face and the circuit layout 12 2 Electrical connection. The conductive connection '60' provides electrical continuity between the metal pin 9 〇, the circuit layout 螃 the fixed contact point 140 and the semiconductor wafer 1 10 output 丄丄 7 15 200910573 (electrical For example, a 0.2 mm via hole penetrates a closed circuit having a thickness of 18 μm, and the conductive region exposed by the layout 1 2 2 is 3.14 χ 2 (10) χ 18 (four) flat, and this region defines the metal pin in the via hole 丄 8 〇 9 The maximum contact area between the circuit layout and the circuit layout is too small to be able to obtain any acceptable trusted contact points. ΙΟΟμηι呵) In the circuit layout, the electrical contact area can be larger in the via hole 18 〇»田增i 600% 'The expansion of this contact area not only reduces the contact electricity, but also enhances the reliability of the package structure. At the same time, it provides a very fine vertical connection when stacking (^-intercon The metal pin B0 has two exposed ends, and has a terminal surface 190a which is the same as the first surface of the package structure, and the other terminal surface 190b is the same as the package structure. The two surfaces are in the same direction, and the terminal surfaces 190a and 19〇 are used for connection when stacked up and down respectively. ^The commonly used tan ball (s〇iderban) is compared with the gold foot 1970 line to strengthen the z-axis. Chrysanthemum I is directly connected. In general, the metal pin B0 can be regarded as a pre-formed cylinder, which is more robust than the deformable ball after reflow. Please refer to FIG. 2, which is the second implementation semiconductor of the present invention. A cross-sectional view of the sealing structure. As shown in the figure: a semiconductor package junction 200910573 The conductive region and the conductive bonding point of the structure are not encapsulated in a resin package material. The semiconductor package structure 200 contains a semiconductor wafer 2 A plurality of input and output points 2 1 1 provide a plurality of integrated circuits (ICs). A connecting plate 2 2 0 is fixed to the second of the semiconductor wafer 2 by an adhesive 2 3 0, such as a solid crystal glue. Surface 2丄〇b. 3 Xuan connecting plate 2 2 0 with m substrate 2 2 ±. The circuit layout 2 2 2 of the line bonding end line 2 2 2 is formed on the first surface 221a of the dielectric: plate 221, another circuit: = 23 ', and the conductive region 2 25 is formed on a surface 22lb of the dielectric substrate 221, In the circuit layout 222, 2, the solder resist 2 2 7 and "8 are applied to expose the metal under the fixed position as an electronic connection. The body crystal 2 1 way layout 2 2 3 is by semi-conductive surface: surface" T output Point 2 1 1 , between the dielectric substrate 2 2 1 ◦ and the other circuit layout 223 : : vias 28 2 4 0 are connected. Connected to the mouth contact (and eb0 (4) towards the first surface of the splicing plate, the circuit layout 2 2 3 white 曰曰" extends beyond the conduction region 2 2 5 . The packaged semiconductor wafer 2 1 〇 and wire fixed - resin The encapsulation material 2 5 is known to be 2, and the surface of the encapsulation material 2 50 ′ of the dielectric substrate 22 7 is completely packaged in 200910573. The plurality of via holes located at the edge of the package structure are 2 0 0 The resin encapsulating material 250, the connecting plate 220, the conducting region 25 and the conductive fixing point 260 are penetrated. The plurality of metal pins 29 are placed in the guiding hole 280, and have a comparison The guiding hole 280 is slightly smaller or almost the same diameter. The metal pin 290 is mainly electrically connected from the lateral conductive junction 260; and the conductive fixing point is 6 〇 self-connecting plate The second surface of 2 2 0 is electrically connected to the circuit layout 2 2 3. The conductive fixed contact 260 is at the metal pin 290, the circuit layout 223, the money guiding hole 2 2 6 , the circuit layout 2 2 2, the wire fixing point 2 4 〇, and the semiconductor wafer 2 1 〇 the input point 2 1 1 provides electrical continuity. The exposed part of the metal pin 2 g 系 is located in the seal The first surface 2〇〇a and the second surface 2〇〇b of the mounting = are part of the terminal when stacked up and down. The main channel is shown in the figure of the third embodiment of the present invention. The cross-sectional view is as shown in the figure: a first semiconductor material of the semiconductor package structure is packaged, and the first surface is not encapsulated by a resin package. The connection pattern of the + conductor package structure is The semiconductor package has a plurality of integrated circuits at its turn-in and turn-in points. Structure 30 has a semiconductor wafer 3 1 1 1 having a plurality of connecting bumps 3 4, and connecting plates 3 2 0 with an adhesive, usually 18 200910573 The underfill agent 310 is fixed on the first surface of the semiconductor wafer 3 301. The connection bump 340 is made of solder or gold. r «Hail connection board 3 2 0 has a dielectric The substrate layout 322 is formed on the first surface 3 2 1 a of the dielectric substrate 321 and has a fixed solder joint 3 2 4 . The other circuit layout 3 2 3 is on the dielectric substrate 3 2 The two surfaces are formed on the 3 b b, and the solder resist 3 2 7 and 3 2 8 are respectively applied to the circuit layout 3 22 323' is electrically connected to the underlying metal at the fixed solder joint. The connection between the semiconductor wafer 3 1 〇 and the circuit layout 3 2 2 is performed by the first turn of the semiconductor wafer 31 and the input/output dielectric substrate 3 2 1 9 Ί Ί 9 / « 〇 213 fixed bump 2 4 and circuit layout 3 2 2 connection bump 3 4 〇 obtained. The circuit layout 322 of the first surface of the board is a plurality of vias 390 through the lateral edges of the wafer, a solder joint) solder 325, and a conductive bond 360 (usually: tin). A plurality of metal pins 39 are in the middle: and have the same or a few diameters as the guide holes 380. The metal leg 90 is primarily electrically connected from the lateral and conductive attachment points; and the conductive attachment point 3 6 is electrically connected to the circuit layout 32: the second material J 2 3 from the connection plate 32A. The conductive fixing point 3 6 〇200910573 provides electric power between the metal pin 390, the circuit layout 3 2 3, the via hole, the pot circuit layout 322, and the screw (four) connection (ie, the connection (8) conductor chip 3 (10) entry and exit point 311: Dependent: The exposed end of the foot 390 is located on the first surface and the first surface of the package structure, respectively as part of the terminal when stacked up and down. The semi-conductive diagram is a cross-sectional view of the package structure of the fourth embodiment of the present invention. As shown in the figure: a two-layer stacked + conductor package structure 4 (four) includes - top package structure 400 two domes: metal pins 4 9 0 a; and - the bottom package ^ with a plurality of bottom metal pins 4 In the case of 9 0 b,1, the plurality of top metal pins 4 g 卩 metal pins 4 9 0 b are connected. The system is connected with a plurality of bottom η... The plurality of bottom metal pins 4 9 〇b are connected with a plurality of top metal wires (4) g: and the bottom metal pins 49〇a, 49〇b are connected to each other by 5. The bottom layer seals the welding ball 46〇 or the conduction zone (=: 14=; #' has a plurality of •r first distributes Tan Tin 4 7 5 to the bottom package structure metal pin 490a-end 'and then the top package structure ^ metal pin 4 9 0 a Column. For the physical 盥 雷, fish pull 4 help the two package structure is connected to the Γ top metal pin 4 9 0 3 and the bottom metal pin 4 9 0 1) is welded by solder reflow. ; : Refer to the "5th Α to 5 Η 图", which is a cross-sectional view of each stage of the 3 package structure manufactured by the present invention. As shown in the figure: in the 5th 20 200910573 A picture, the connection plate 500 has a dielectric The substrate 5 2 1 - a circuit layout 5 2 2 with a line bonding end line 5 2 4; and a conductive region 5 2 5 on the first surface of the dielectric substrate 521 ς9 ι μ, the 面 surface 521a. 2 3 is formed on the second surface 5 2 1 of the dielectric substrate. The barrier paint 5 ′′ is applied to the circuit layout 5 2 2, 5 2 3 respectively, and the metal under the exposed point is electrically connected. In Fig. 5, a solder 560 is dissolved on the conduction d 5 2 5 of the circuit layout 522. The solder 5 〇 〇 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在烊锡 provides an easy-to-assemble program to assist in the electrical contact between the inserted metal pins and a circuit layout. A semiconductor wafer 51 is affixed to the connection plate 5 by an adhesive 530. In Figure 5D, the connection between the semiconductor wafer 5 i 〇 and the circuit layout 522 is via the semiconductor wafer 5 The input and output point 5 1 1 and the line bonding point 5 4 0 between the line bonding end line 5 2 4 on the first surface 5 2丄a of the dielectric substrate 5 2 1 are formed in the FIG. 5E 'the semiconductor wafer 5 1 〇, wire fixing point 504, and soldering 5 6 〇 are packaged in a resin encapsulating material of 5 5 。. In FIG. 5F, 'a plurality of via holes 58 8 are formed along the edge of the package structure'. The via holes 580 penetrate the resin package material 200910573 material 5 5 0, solder 5 6 〇 and the connection plate 5 2 〇^ In Fig. 5G, several metal pins 5 9 相 are similar to or nearly identical to the guide holes, and the diameters thereof are the same, and the guide holes 5 § 〇 are inserted respectively. In the following figure, the metal pin 5 9 is locked in the Y position after the solder is reflowed, wherein the bismuth tin 5 6 ::::: and the first surface of the connecting plate 520 is connected to the ΐ road. The Zen tin 5 6 〇 is used as a conductive fixed contact point, which is a f-pin 590, a circuit layout 5 2 2, a wire fixing point 5 〇... a body wafer 51 〇 between the input and exit points 511 to delay . Fabricating the semiconductor stacked package structure can further include testing and singulaiiGn package structure finishes from a string, such as early cutting or die cutting; and packaging for further use. ~ The m point of this issue is the manufacturing cost of the semiconductor package structure and the name of the Lang. Please install, ,,. The advantage is that it can be measured before stacking! Package structures that are unacceptable or less sinful can be removed, so only package structures that are in good condition after testing can be used in stacked modules to maximize final assembly yield, which is satisfactory. Another advantage of the present invention is that the printed circuit board (pcB) and the connector industdes have good drilling and metal foot insertion order, and thus the technique of the present invention can be stacked on the multilayer package junction 22 200910573. The lowest cost, without major modifications, can be applied to the semiconductor packaging industry. The advantages of the present invention are that the metal pin is a separate component, which ensures strong mechanical strength, uniformity and vertical power. connection. The advantage of the present invention is that the contact area of the inserted metal pin and the circuit layout is greatly increased 'because the contact area of the solder exposed in the via hole is large' to ensure a reliable lateral connection. The advantages of this product are that the package structure does not require chemically conductive plating because it is lengthy, uncontrollable and unreliable: it is when the resin packaging material contains filler. The advantage of this method is that the package structure does not need to be filled with solder or conductive glue (_clUetiveadhesive) in the via hole, and the program of the present invention is still flexible, and the advantages of the present invention can be used when necessary. θ y provides a plurality of metal pins of a B-day chip that can be electrically charged; interferes with T to limit the electrical interference between the RF chip and other adjacent chips, and is used as a heat sink for the electrons 在一 π π The shielding state can be used for the front plate. The advantage is that the package structure can be applied to various types of connectors: the plate can be flexed or the ceramic substrate, and the board has a vertical connection point of one or a plurality of roads to connect the plug. People u lng layer) 'can be made of metal pins with the designed electricity 23 200910573 road. However, the above description is only a preferred embodiment of the present invention, and the scope of the invention is not limited thereto; therefore, the simple equivalent changes and modifications made in accordance with the scope of the present invention and the contents of the description of the invention All should remain within the scope of the invention patent. 〃 24 200910573 [Simple description of the diagram] Figure 1A shows the cross section of the semiconductor package structure of the present invention. The lower side view of the semi-conductive edge guide hole of the first embodiment of the present invention. Port Structure Cross Section Fig. 2 is a semiconductor package diagram of a second embodiment of the present invention. Fig. 3 is a cross-sectional view showing a semiconductor package structure according to a fourth embodiment of the present invention, and Fig. 4 is a cross-sectional view showing a semiconductor package structure according to a fourth embodiment of the present invention. 5A to 5D are cross-sectional views showing the stages of manufacturing a semiconductor package structure of the present invention. Figure 6 is a cross-sectional view of a conventional BGA semiconductor package structure. Figure 7, is a traditional solder ball for BGa semiconductor stacked package junction [main component symbol: vertical connection of the multi-package structure module profile. Semiconductor package structure 1 〇〇, 2 0 0, 3 〇〇, 4 〇〇 semiconductor wafer 110, 210, 310, 51 〇 first surface 〇 第二 a second surface 〇 、 b, 210b input point 1 1 1 , 2 1 1 , 3 1 25 200910573 connecting plates 120, 220, 320, 520 dielectric substrate 121, 221, 321, 521 first surface 121a, 221a, 321a, 52 p second surface 121b, 221b, 321b, 52 circuit layout 122, 123, 222, 223, 322, 323, 522, 523 line joint end line 1 24, 224, 524 conductive area 125, 225, 325, 525 solder resist 127, 128, 227, 228, 32 7, 328, 527, 528 Adhesive 130, 230, 530 line fixing point 1 4 0, 2 4 0, 5 4 0 Resin encapsulation material 1 5 0, 2 5 0, 5 5 0 Conductive bonding point (solder) 1 6 0, 2 6 0, 3 6 0, 5 6 0 Guide holes 180, 280, 580 Metal pins 190, 290, 390, 590 Terminal surface 190a, 190b First surface 2 0 0 a Second surface 2 0 0 b First surface 31〇 a 26 200910573 Fixed solder joint 3 2 4 Underfill 3 3 0 Connection bump 3 4 0 Top package structure 4 0 0 a Underlying package structure 400b Solder 4 7 5 Solder ball 4 6 0 Top metal pin 4 9 0 a Bottom metal Web pin 4 9 0 b 50 027