TW200908007A - Memory and 1-bit error checking method thereof - Google Patents
Memory and 1-bit error checking method thereof Download PDFInfo
- Publication number
- TW200908007A TW200908007A TW96130066A TW96130066A TW200908007A TW 200908007 A TW200908007 A TW 200908007A TW 96130066 A TW96130066 A TW 96130066A TW 96130066 A TW96130066 A TW 96130066A TW 200908007 A TW200908007 A TW 200908007A
- Authority
- TW
- Taiwan
- Prior art keywords
- code
- data
- error
- bit
- new
- Prior art date
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
46PA 200908007 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種記憶體及其1位元讀取錯誤檢 測方法’且特別是有關於一種具有簡單硬體架構及節省“己 憶體空間之記憶體及其1位元讀取錯誤檢測方法。 σ 【先前技術】 記憶體係應用於現今之多種資料儲存之用途。其中, 確保儲存於記憶體中之資料之完整性是記憶體設計上復 重要的一環,傳統上通常使用錯誤修正碼(Error Correction Code,ECC)來達成此項要求。錯誤修正喝係 為一種能夠偵測並修正1位元錯誤(1 bit error)之資料 完整性檢測方法。 請參照第1A圖,其繪示乃傳統記憶體1位元讀取錯 誤檢測方法之流程圖。首先,於步驟1〇〇中,接收y位二 大小之至少一筆資料片段(data fragment),η為大於或等 於0之整數。接著,於步驟110中,依據此2Π位元大小之 至少一筆資料片段產生一 2η位元大小之錯誤修正碼 (error correction code),此錯誤修正碼係由錯誤修正 檢測演算法(ECC Algorithm)所產生,其中,為了避免j 位元錯誤發生在錯誤修正碼,故錯誤修正碼包括了錯誤修 正同位位元(ECC parity bit)及其補數。此錯誤修正碼係 屬於此至少一筆資料片段之管理位元(overhead bits)。 然後,於步驟120中,將至少一筆資料片段及錯誤修 20090800746PA 200908007 IX. Description of the Invention: [Technical Field] The present invention relates to a memory and a 1-bit read error detection method thereof, and particularly relates to a simple hardware architecture and saving "recall" Space memory and its 1-bit read error detection method. σ [Prior Art] The memory system is used in a variety of data storage applications today, in which the integrity of the data stored in the memory is ensured by the memory design. An important part of the loop is that the error correction code (ECC) is usually used to achieve this requirement. Error correction drink is a data integrity test that can detect and correct 1-bit error. Please refer to FIG. 1A, which is a flow chart of a conventional memory 1-bit read error detection method. First, in step 1〇〇, at least one data fragment of y bits and two sizes is received. , η is an integer greater than or equal to 0. Then, in step 110, a 2 η bit size is generated according to at least one data segment of the 2 Π bit size. Error correction code, which is generated by the error correction detection algorithm (ECC Algorithm). In order to avoid the j-bit error occurring in the error correction code, the error correction code includes the error correction parity. The bit error (ECC parity bit) and its complement. The error correction code belongs to the management bits of the at least one piece of data. Then, in step 120, at least one piece of data and error is repaired 200908007
6PA 正碼寫入於記情體夕士 讀取至少一筆資 1片’於f 130中’從記憶體 於步驟140中,依少取資料片段。接著, 修正碼,此新錯 少一筆讀取貝枓片段產生一新錯誤 °、t正碼亦由錯誤修正檢測演算法所產 射‘至少:2丄50中’依據錯誤修正職錯誤修正 片段。步驟κη: 料片段是否相同於至少一筆資料 誤修正碼= = 動作’若結果為。,則至二f斥或—〇Γ)的 -筆資料片段。叫—筆讀取資 料片段相同於至少 段,=驟St㈣片段相同於至少-筆資料片 憶體輸出此至少一筆判斷讀取操作係為正確,記 片段相異於至少=讀諸。若至少—筆讀取資料 體判斷讀取操作則於步驟no中,若記憶 ,筆讀取資料==少==_將 至少一筆讀取資料片段。 '《資枓片段,並輸出 ,為例::明至=之大小係為8位 正檢測演算法產生 ♦資^段係依據錯誤修 正同位位元ρι 之錯誤修正碼’包括錯誤修 同理,至少-筆及其補數ΡΓ,,*P4,。 修正碼1中,錯誤二正3亦產生6位元大小之新錯誤 錯誤修正同位位元P1、PUP4,以及錯The 6PA positive code is written in the syllabus. At least one piece of information is read in 'f 130' from the memory in step 140, and the data piece is taken less. Then, the correction code, this new error, reads a sample of the Bellows to generate a new error, and the positive code is also produced by the error correction detection algorithm, ‘At least: 2丄50, according to the error correction job correction piece. Step κη: Whether the fragment is identical to at least one piece of data Error correction code = = action ' If the result is . , then to the second refusal or - 〇Γ) - pen data fragment. The call-to-pen read data segment is identical to at least the segment, and the step St (four) segment is identical to at least the pen data slice. The memory output outputs the at least one judgment read operation is correct, and the record segment is different from at least = read. If at least the pen reading data body judges the reading operation, it is in step no. If it is memorized, the pen reading data == less ==_ will read at least one piece of data. '"Capital fragment, and output, for example:: Ming to = the size is 8 digits of the positive detection algorithm generated ♦ ^ ^ section based on the error correction of the same location ρι error correction code 'including error repair, At least - pen and its complement ΡΓ,, *P4,. In the correction code 1, the error two positive 3 also produces a new error of 6-bit size. The error correction parity bits P1, PUP4, and the error
346PA 200908007 誤修正同位位元之補數ΡΓ 、P2,及P4’之公式係如下 所述,㊉係代表,,互斥或,’。 (公式1) (公式2) (公式3) (公式4) (公式5) (公式6) P4 = D7 ㊉ D6 ㊉ D5 ㊉ D4 P2 = D7 ㊉ D6 ㊉ D3 ㊉ D2 P1 = D7 ㊉ D5 ㊉ D3 ㊉ D1 P4,=D3 ㊉ D2 ㊉ D10D〇 P2’ =D5 ㊉ D4 ㊉ D1®d〇 ΡΓ =D6 ㊉ Μ㊉ D2 ㊉ d〇 取操作1有;位元錯 备,亦即至少-筆㈣諸之錯誤修正料至卜筆讀取 =片段=錯贿正錢紅斥或㈣狀結果不全 麥脏纽^ , 筆讀取資料片段之錯誤位 置。將錯誤的位元反相,修正此錯誤。 上述之傳統記憶體讀取錯誤込 Δ1 .A、 测方法中,錯誤修正檢 測濟异法(ECC Algorithm)雖然能夠 « , ^ 1 ^ ^ 貝/IJ並修正 1 位元錯 誤仁對於5己隐體之1位疋讀取錯誤檢 小之錯誤修正碼將使得管理位元佔據太多:如位兀大 間’並使得記憶體之硬體架構無法簡化:之記憶體空 【發明内容】 本發明係有關於一種記愧體及其1 _ 測方法,利用較簡單之1位元讀取錯誤立元讀取錯誤檢 憶體具有簡單硬體架構’並節省印測方法’使得記 根據本發明,提出一種記憶體丨 几讀取錯誤檢 1,°匕憶體空間 測方346PA 200908007 The formula for the erroneous correction of the complement ΡΓ, P2, and P4' of the collocated bits is as follows, the ten series represents, mutually exclusive or, '. (Formula 1) (Formula 2) (Formula 3) (Formula 4) (Formula 4) (Formula 5) (Formula 6) P4 = D7 Ten D6 Ten D5 Ten D4 P2 = D7 Ten D6 Ten D3 Ten D2 P1 = D7 Ten D5 Ten D3 Ten D1 P4,=D3 Ten D2 Ten D10D〇P2' =D5 Ten D4 Ten D1®d〇ΡΓ=D6 Ten Μ10 D2 Ten d 〇Operation 1 has; bit erroneous, that is, at least-pen (four) error correction Expected to read the pen = fragment = wrong bribe money red repudiation or (four) results incomplete visceral New ^, the wrong location of the pen to read the data fragment. Incorrectly invert the wrong bit to correct this error. The above-mentioned conventional memory reading error 込Δ1.A, the measurement method, the error correction detection Equivalent Method (ECC Algorithm) can be « , ^ 1 ^ ^ Bay / IJ and correct 1 bit error kernel for 5 own hidden body The error correction code of the 1-bit 疋 read error detection will make the management bit occupy too much: if it is in a large space, and the hardware structure of the memory cannot be simplified: the memory is empty [invention] The present invention has With regard to a kind of recording body and its method, the error reading unit has a simple hardware structure and saves the printing method by using a simpler one-bit reading error reading element and making a printing method according to the present invention. Memory reading error reading 1, ° memory space test
46PA 200908007 法,包括,首先,接收至少一筆資料片段,至少一筆資料 片段之大小係為2η位元,η為大於或等於〇之整數。接^ =據至少-筆資料諸產生錯誤修正竭、同^檢查_ 資料碼,資料碼係相對應於錯誤修正碼。再來,將至少一 筆資料諸、錯誤修正碼、同位檢查碼及⑽碼寫入二記 憶體。然後,從記憶體讀取至少一筆資料片段馨 讀取資料片段,至少-筆讀取資料片段之大小係為2、筆 疒.Λ 70。接著,依據至少一筆讀取資料片段產生新錯誤修正 =新同位元檢查碼及新資料碼’新資料碼係相對應於新 =誤修正碼。再來,依據錯誤修正碼及新錯誤修正碼、同 、_檢查竭及新同位元檢查碼,以及資料石馬及新資料竭, 至少一筆讀取資料片段相對於至少一筆資料片段是, 於=1位it錯誤。之後’若至少-筆讀取資料片段相對 钱 筆資料片段不具有1位元錯誤,則輸出至少一答 哨取資科片段。 筆 及錯ί據本發明,提出一種記憶體,包括記憶單元陣列以 片^誤修正電路。記憶單元陣列接收並儲存至少一筆資料 少二:纪憶體從記憶單元陣列讀取至少一筆資料片段為至 資料ΐ?取資料片段’至少一筆資料片段及至少-筆讀取 錯鵠佟筏之大小係為2η位元,η為大於或等於〇之整數. 负元:疋電路依據至少一筆資料片段產生錯誤修正碼、同 俺辕查螞及資料碼,資料碼係相對應於錯誤修正嗎,且 蛉*ί少〜筆讀取資料片段產生新錯誤修正碼、新同位元 辱及_資料碼,新資料碼係相對應於新錯誤修正碼。 9The 46PA 200908007 method includes, firstly, receiving at least one piece of data, at least one piece of data having a size of 2η bits, and η being an integer greater than or equal to 〇. Connected = = according to at least - the pen data generated error correction, the same ^ check _ data code, the data code corresponds to the error correction code. Further, at least one of the data, the error correction code, the parity check code, and the (10) code are written into the two memory. Then, at least one piece of data is read from the memory to read the data piece, and at least the size of the piece of data read is 2, pen 疒.Λ 70. Then, a new error correction is generated according to at least one piece of read data = a new parity check code and a new data code 'new data code number corresponding to the new = error correction code. Then, based on the error correction code and the new error correction code, the same, the _ check exhaustion and the new parity check code, as well as the information stone horse and new data exhaustion, at least one reading data segment relative to at least one data segment is, at = 1 bit it error. Then, if at least the pen-reading data segment does not have a 1-bit error with respect to the money segment, at least one of the whistle-funding segments is output. According to the present invention, there is proposed a memory comprising a memory cell array and a chip correction circuit. The memory unit array receives and stores at least one piece of data: the memory element reads at least one piece of data from the memory unit array into the data frame, and takes the data piece 'at least one piece of data and at least one size of the pen reading error The system is 2η bits, and η is an integer greater than or equal to 〇. Negative element: The circuit generates an error correction code, a peer check data, and a data code according to at least one data segment, and the data code corresponds to the error correction, and蛉*ί少~ The pen reads the data fragment to generate a new error correction code, a new epoch humiliation and a _data code, and the new data code corresponds to the new error correction code. 9
346PA 200908007 其中’記憶體利用錯誤修正碼及新錯誤修正碼、同位元檢 查碼及新同位元檢查碼,以及資料碼及新貧料碼,判斷至 少一筆讀取資料片段相對於至少一筆資料片段是否具有1 位元錯誤。 為讓本發明之上述内容能更明顯易懂,下文特舉―較 佳實施例’並配合所附圖式,作詳細說明如下: 【實施方式】 本發明係為一種記憶體及其1位元讀取錯誤檢測方 法,利用僅具有錯誤修正同位位元(Ecc parity bit)戋其 補數之一之錯誤修正碼、丨位元大小之同位元檢查碼以及 1位元大小之資料碼,以較簡單之丨位元讀取錯誤檢測方 法來檢測記憶體所儲存之資料是否具有丨位元錯誤,使得 圯憶體具有簡單硬體架構,並節省記憶體空間。 請參照第2圖,其繪示乃依照本發明較佳實施例之記 憶體1位it讀取錯誤檢測方法之流程圖。此記憶體^位元 讀取錯誤檢測方法係應用於—記憶體。首先,於步驟· 中、,接收至少—筆資料片段,此至少-筆資料片段之大小 係為2"位7〇 ’ η為大於或等於G之整數。然後,於步驟21〇 中’依據至少-筆資料片段產生一錯誤修正碼、一同位元 心查媽及-資料碼’資料吗係相對應於錯誤修正碼。錯誤 ,正碼係由錯誤修正檢測演算法⑽AlgQrithm)所產 .,但此錯誤修正韻為錯誤修正同位位元(ECC parity ⑴或其補數之―,其大小為η位元。接下來舉至少-筆 200908007346PA 200908007 where 'the memory uses the error correction code and the new error correction code, the parity check code and the new parity check code, and the data code and the new poor material code to determine whether at least one piece of read data is relative to at least one piece of data. Has a 1-bit error. In order to make the above-mentioned contents of the present invention more comprehensible, the following detailed description of the preferred embodiment and the accompanying drawings will be described in detail as follows: [Embodiment] The present invention is a memory and its 1-bit The read error detection method uses an error correction code having only one of the complement correction bits (Ecc parity bit), one of its complements, a parity check code of the bit size, and a data code of one bit size. The simple bit reading error detection method is used to detect whether the data stored in the memory has a bit error, so that the memory has a simple hardware structure and saves memory space. Referring to Figure 2, there is shown a flow chart of a 1-bit it read error detection method in accordance with a preferred embodiment of the present invention. This memory ^ bit read error detection method is applied to - memory. First, in step ·, receive at least a pen data segment, the size of the at least pen data segment being 2" bit 7〇 ' η is an integer greater than or equal to G. Then, in step 21, "according to at least the data segment of the pen, an error correction code, a parity card, and a data code" are associated with the error correction code. Error, the positive code is produced by the error correction detection algorithm (10) AlgQrithm), but this error correction rhyme is the error correction parity bit (ECC parity (1) or its complement number, its size is η bit. Next, at least - pen 200908007
46PA 資料片段之大小係為8位元(D0-D7)為例做說明。其中, 錯誤修正同位位元El、E2及E4、錯誤修正同位位元之補 數E1 、E2’及E4’之公式係如下所述,㊉係代表,’石 斥或”。 (公式7) (公式8) (公式9) (公式10) (公式11) (公式12)The size of the 46PA data segment is 8 bits (D0-D7) as an example. Among them, the formulas for the error correction of the parity bits E1, E2, and E4, and the complements E1, E2', and E4' of the error-corrected parity bits are as follows, the ten-series representative, 'stone repulsion or'. (Formula 7) ( Equation 8) (Equation 9) (Equation 10) (Equation 11) (Equation 12)
E4 = D7 ㊉ D6 ㊉ D5 ㊉ D4 E2 = D7 ㊉ D6 ㊉ D3 ㊉ D2 E1 = D7 ㊉ D5 ㊉ D3 ㊉ D1 E4’ 二 D3 ㊉ D2 ㊉ D1 ㊉ DO E2’ ㊉ D4 ㊉ D1 ㊉ DOE4 = D7 Ten D6 Ten D5 Ten D4 E2 = D7 Ten D6 Ten D3 Ten D2 E1 = D7 Ten D5 Ten D3 Ten D1 E4' Two D3 Ten D2 Ten D1 Ten DO E2' Ten D4 Ten D1 Ten DO
ΕΓ =D6 ㊉ D4 ㊉ D2 ㊉ DO 同位元檢查碼(par i ty code)係由將至少一筆資料片 丰又之所有位元進行一互斥或(exclusive沉)的動作而產 ^ ’亦即當至少-筆資料片段具有偶數個i時 檢…筆貝枓片&具有奇數個1時’同位元 檢查竭為1。同位元檢查碼P或F之公式係如下所述 (公式 i3) PU P’㊉獅_D1_ 體心卜讀誤修正瑪之資料瑪來確保㈣ 為錯誤修正同=:::測完整性。當錯〜 瑕低位疋。當錯誤修 _叶片心 時’則資料竭係為至少一筆修正同位位70之補數 D戋IV 筆貝料片段之最高位元。資耝m 孑D之公式係如下所述。 貝枓碼 D = D0 (公式 14)ΕΓ =D6 十 D4 十 D2 十 DO The parity code (par i ty code) is produced by performing a mutually exclusive or (exclusive sinking) action on at least one piece of information. At least - the pen data fragment has an even number of i-times... Pens and tablets have an odd number of 1's and the homotopic check is 1. The formula of the parity check code P or F is as follows (Formula i3) PU P'Shishi_D1_ Body Mind Reading Miscorrected Ma's information Malay to ensure (4) Error correction with =::: Test integrity. When wrong ~ 瑕 low position 疋. When the error is repaired, the data is exhausted as at least one complement of the complement of the same position 70. D戋IV The highest bit of the pen piece. The formula for the asset m 孑D is as follows. Bellows code D = D0 (Formula 14)
146PA 200908007 DJ =D7 r^ ^ C公式15) 於步驟220中,將至少_筆次 同位檢查碼及資料碼寫入於 貝料片段、錯誤修正碼、 &〜記憶體。1击 碼、同位檢查碼及資料瑪係做 具中’錯誤修正 位元(overhead bit)而被窝:夕筆資料片段之管理 中,從記憶體讀取至少—鍪次, 热後’於步驟230 早Γ貝料片段兔 片段’此至少一筆讀取資料片ρ 馬至·^ 一筆讀取資料 於步驟240中’依據至少:=小:為2η位元。 錯誤修正碼、一新同位元檢查碼及二:::片段產生一新 係相對應於新錯誤修正喝。新伊=。啊貧料碼’新資料碼 測演算法所產生,其大小亦為a誤修正碼亦由錯誤修正檢 誤修正同位位元時,新錯誤^ _^錯誤修正碼為錯 錯誤修正碼為錯誤修正同位位3亦為錯誤同位位元。當 亦為錯誤修正同位位元之補數^之補數時,新錯誤修正碼 code)係由將至少一筆讀取 ^1位元檢查碼(Parity 斥或—Gr)的動作而產生n有位元進行-互 碼為錯誤修正同位位元時,則 =錯::正 資料片段之最低位元。當新 $係為至J一筆讀取 元之補數時’則資料碼係為;少:二多正同位位 位元。 聿嗔取資料片段之最高 於步驟250中,依據錯誤修正 位元檢查碼及新同位元檢查碼,以及碼、同 刺斷至少一筌蟢珩次如u 夂貝科碼及新資料碼, 否且有1位元#t组—μ 掌貝科片ί又疋 否…有凡料之後,於步驟260中,若至少一筆讀 12146PA 200908007 DJ = D7 r^ ^ C Equation 15) In step 220, at least the _ pen parity check code and data code are written in the batten segment, the error correction code, and the &~ memory. 1 Snap code, parity check code and data gram system are used in the 'error header bit' and the quilt: in the management of the eve data segment, read at least one time from the memory, after the heat 'in step 230 Early buckwheat segment rabbit segment 'This at least one reading piece of information ρ Ma to ^ ^ a reading data in step 240 'based at least: = small: 2n bits. The error correction code, a new parity check code, and the second::: fragment generate a new system corresponding to the new error correction drink. New Iraq =. Ah poor material code 'new data code measurement algorithm generated, its size is also a erroneous correction code is also corrected by error correction error correction of the same bit, new error ^ _ ^ error correction code is wrong error correction code for error correction The parity bit 3 is also the wrong parity bit. When the complement of the complement of the same bit is also corrected for the error, the new error correction code is generated by at least one operation of reading the ^1 bit check code (Parity or -Gr). When the element is performed - the mutual code is the error correcting the same bit, then = error:: the lowest bit of the positive data segment. When the new $ is the complement of a reading element to J, then the data code is; less: two more positive bits. The highest data fragment is captured in step 250, and the bit check code and the new parity check code are corrected according to the error, and the code is stabbed at least one time such as u 夂Beike code and new data code, And there is 1 bit #t组-μ 掌贝贝科片 疋又疋... After everything, in step 260, if at least one read 12
46PA 200908007 取資料片段相對於至少一筆資料片段不具有1位元錯誤, 則輸出至少一筆讀取資料片段。 於步驟250中,實質上係將錯誤修正碼及新錯誤修正 石焉、同位元檢查碼及新同位元檢查碼’以及資料碼及新資 料碼分別進行互斥或的動作來判斷至少一筆讀取資料片 段是否具有1位元錯誤。請參照表1,其為依照本發明較 佳實施例之記憶體1位元讀取錯誤檢測方法之查詢表。46PA 200908007 The data segment does not have a 1-bit error with respect to at least one piece of data, and at least one piece of read data is output. In step 250, substantially the error correction code and the new error correction stone, the parity check code and the new parity check code, and the data code and the new data code are mutually exclusive or mutually determined to determine at least one read. Whether the data fragment has a 1-bit error. Please refer to Table 1, which is a look-up table of a memory 1-bit read error detection method in accordance with a preferred embodiment of the present invention.
E P D 0 0 X 0 1 0 0 1 1 1 0 X 1 1 X 表1 上述之表1中,” E”為錯誤修正碼及新錯誤修正碼 進行互斥或動作之後的結果,” P”為同位元檢查碼及新 同位元檢查碼進行互斥或動作之後的結果,” D”為資料 碼及新資料碼進行互斥或動作之後的結果,” X”代表不 用在意(don’ t care),” 1”代表至少一筆讀取資料具有 1位元錯誤,” 0”代表至少一筆讀取資料片段不具有1位 元錯誤。 當(E,P,D)為(0,0,X)時,即代表依據錯誤修正碼 13EPD 0 0 X 0 1 0 0 1 1 1 0 X 1 1 X Table 1 In Table 1, “E” is the result of mutual exclusion or action between the error correction code and the new error correction code. “P” is the same position. The result of mutual exclusion or action after the meta-check code and the new parity check code, "D" is the result of mutual exclusion or action of the data code and the new data code, "X" stands for don't care, "1" means that at least one reading data has a 1-bit error, and "0" means that at least one piece of reading data does not have a 1-bit error. When (E, P, D) is (0, 0, X), it means that according to the error correction code 13
346PA 200908007 及新錯誤修正·请至少—㈣取㈣諸不具有丨位元 錯誤且依據同位元檢查碼及新同位元檢查碼判斷至少— 筆讀取資料>1段不具有丨位元錯誤,於是至少—筆讀取: 料巧係相同於至少一筆資料片段。此時,若D為i,貝二 表不貢料碼及新資料碼產生錯誤。 、 。當(E,P)為(0 ’ _,即代表依據錯誤修正竭及新夢 誤修正碼判斷至少—筆讀取資料諸不具有1位元錯誤: 仁依,同位元檢查碼及新同位元檢查碼判斷至少一筆讀 取資料片段具有1位元錯誤’此時,則檢視資料竭及新資 料碼以進行更進一步的判斷。當(E,P,D)為(〇, 1,丨)時, 即表不依據資料碼及新資料碼判斷至少一筆讀取資料片 段具有1位元錯誤,則修正此1位元錯誤,此1位元錯誤 係為資料碼及新資料碼所相對應之位元。當(E,p,W為 (〇,1,0)時,即表示依據資料碼及新資料碼判斷至少一 筆項取> 料片段不具有1位元錯誤,亦即發生錯誤者為同 位元檢查碼及新同位元檢查碼。 萬(E P D)為(1,0,X)時,即代表依據錯誤修正碼 ,新錯誤修正碼判斷至少—筆讀取資料片段具有1位元錯 誤,但依據同位元檢查碼及新同位元檢查碼判斷至少一筆 5貝取貝料片段不具有1位元錯誤,於此情況下,產生錯誤 者為錯誤修正碼及新錯誤修正碼,至少一筆讀取資料片段 相對於至少—筆資料片段不具有1位元錯誤。 冨(E P,D)為(1,1,X)時,即代表依據錯誤修正碼 及新錯誤修正碼韻至少—筆讀取資料片段具有丨位元錯346PA 200908007 and new bug fixes. Please at least—(4) fetch (4) none of the bit errors and judge at least based on the same bit check code and the new parity check code—the pen read data >1 segment does not have a bit error, So at least - pen reading: the same is true for at least one piece of data. At this time, if D is i, the two gongs and the new data code are incorrect. , . When (E, P) is (0 ' _, which means that at least the error correction code and the new dream error correction code are judged at least - the pen reading data does not have a 1-bit error: Renyi, the parity check code and the new parity The check code judges that at least one piece of read data has a 1-bit error. At this time, the data is exhausted and the new data code is used for further judgment. When (E, P, D) is (〇, 1, 丨) , that is, the table does not judge that at least one piece of read data has a 1-bit error according to the data code and the new data code, and the 1-bit error is corrected, and the 1-bit error is the corresponding position of the data code and the new data code. When (E, p, W is (〇, 1, 0), it means that at least one item is taken according to the data code and the new data code.] The material fragment does not have a 1-bit error, that is, the error occurs. The parity check code and the new parity check code. When the (EPD) is (1, 0, X), it means that the error correction code is used, and the new error correction code determines that at least the pen read data segment has a 1-bit error. However, based on the parity check code and the new parity check code, at least one 5 bar is determined. The material segment does not have a 1-bit error. In this case, the error-generating code is the error correction code and the new error correction code, and at least one of the read data segments does not have a 1-bit error with respect to at least the pen data segment. When D) is (1,1,X), it means that at least the code is based on the error correction code and the new error correction code segment has a bit error.
46PA 200908007 誤’且依據同位元檢查碼及_位元檢查碼麟至少一筆 讀Ϊ資料片段具有1位•誤,於此情況下,至少一筆讀 取貝料>|段具有1位疋錯誤,於是,依據錯誤修正碼及新 錯誤修正碼,湘錯誤修正檢測演算法修正至少—筆 資料片段所具有之1位元錯誤。 w 舉至少一筆資料片段為(00101011),而至少一筆讀敢 貧料片段為__為例做說明。依照上述之記憶 方法,至少料片段之錯誤敍妈 至::_签)=(111) ’同位元檢查碼為0’資料碼為卜 /錢取資料片段之新錯誤修正碼係為(P4 P2 P1) = ίΓΓ :同位元檢查碼為1,新資料碼為〇。故可以得到 最低位-為(G ’ 1,^ ’即得知至少一筆讀取資料片段之 取低位7〇具有1位元錯誤。 段為_01011)。 d正至〆 <讀取育料片 3圖,讀示乃紐本發日繼實施例之記 記憶體_包括記憶單元陣列枷以及錯 少二筆資:片32二記t憶單元陣列310係用叫 取至少^ 記憶體300從記憶單元陣列310讀 葦賢料片段Data為至少一筆讀取資科片46PA 200908007 Error 'and according to the parity check code and _ bit check code Lin at least one reading Ϊ data segment has 1 bit error, in this case, at least one reading bait > | segment has 1 疋 error, Therefore, according to the error correction code and the new error correction code, the Xiang error correction detection algorithm corrects at least one bit error of the pen data segment. w Take at least one piece of data (00101011), and at least one piece of reading the scam is __ as an example. According to the above memory method, at least the error of the fragment is described to::_sign)=(111) 'The parity check code is 0'. The new error correction code of the data code is the data/code. (P4 P2 P1) = ίΓΓ : The parity check code is 1, and the new data code is 〇. Therefore, the lowest bit can be obtained (G ’ 1,^ ’, that is, at least one bit of the read data segment is found to have a 1-bit error. The segment is _01011). d is to 〆<Read the cultivar 3, read the memory of the continuation of the embodiment _ including the memory cell array 枷 and the wrong two transcripts: the slice 32 two remembers the cell array 310 The system uses at least the memory 300 to read the data from the memory unit array 310 to at least one reading of the film.
DataR,至φ —容次β ~ 々子又DataR, to φ - tolerance β ~ 々子
DataR m 段恤及至少一筆讀取資料片段 •小係為2n位元’ n為大於或等於〇之敕數 生一正電路320係依據至少一筆資料片段正㈣產 生錯誤修正碼、一同位元檢查碼及一資料竭 , 相對應於錯誤修正碼,且依據至少-筆讀取資料片段’、 15DataR m paragraph shirt and at least one reading data fragment • The small system is 2n bits 'n is greater than or equal to 〇 敕 生 生 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 Code and data exhaustion, corresponding to the error correction code, and according to at least - pen read data fragment ', 15
346PA 200908007 新錯誤修正碼、—新同位元檢查碼及一新資 科碼,新貝料碼係相對應於新錯誤修正碼。 元或其:數2修二誤修正碼為錯誤修正同位位 位元,w 輯錯婦正碼大小係為n 元,資糾碼及新同位元檢查碼之大小係為1位 修正大顿為1位元。其中,當錯誤 為至為錯誤修正同位位元時,資料碼係 讀取資料片段之最低位70,新㈣碼係為至少一筆 為錯誤修數r::正碼及新錯誤修正碼 月^補數呀,—貝料碼係為至少一筆資料 最^ μ’新資料碼係為至少-筆讀取資料片段之 取尚位兀。 記憶體300係利用錯誤修正碼及新錯誤修正碼、同位 :查碼及新同位元檢查碼,以及資料碼及新資料碼,判 =少一筆讀取資料片段相對於至少-筆資料片段是否 1位7L錯誤。此外,記憶體3〇〇所應用之1位元讀取 二=、檢測方法’係、已詳述於本發明上述實施例所揭露之記 ^體1位元讀取錯誤檢财法,故於此不再重述。 本&明上述實施例所揭露之記憶體及其1位元讀取 h曰誤;U /則方法’利用僅具有錯誤修正同位位元(ECC㈣i ty u)或其補數之一之錯誤修正碼、1位元大小之同位元檢 二竭以及1位7C大小之資料碼,以較簡單之1位元讀取錯 =双測方法來檢測記憶體所儲存之資料是否具有i位元錯 :、對於2位7〇大小之至少一筆資料片段而言,相較於傳 Ϊ6ΡΑ 200908007 統記憶體1位元讀取錯誤測方法所需要之2η位元大小之 管理位元,本發明所揭露之記憶體1位元讀取錯誤檢測方 法僅需要η+2位元大小之管理位元,大幅節省記憶體空 間,同時更使得記憶體能具有較簡單之硬體架構。 此外,傳統亦應用漢明碼來確保資料之完整性。漢明 碼係於至少一筆資料片段之特定位置上附加檢查位元。例 如當至少一筆資料片段之大小為η位元時,則依循下列之 公式7附加k個檢查位元於2°、21、22…及2k_1位元,k 為正整數。 2kgn + k+l (公式 7) 其中,檢查位元及其相對應之位元之” Γ的個數必須為 偶數個。利用檢查位元來偵測並修正至少一筆資料片段之 1位元錯誤。然而,由於記憶體中之位元係彼此相鄰,而 漢明碼須於特定位置附加檢查位元,故漢明碼不適用於記 憶體。 綜上所述,雖然本發明已以一較佳實施例揭露如上, 然其並非用以限定本發明。本發明所屬技術領域中具有通 常知識者,在不脫離本發明之精神和範圍内,當可作各種 之更動與潤飾。因此,本發明之保護範圍當視後附之申請 專利範圍所界定者為準。 17346PA 200908007 New error correction code, - new parity check code and a new capital code, the new shell code corresponds to the new error correction code. The element or its number 2 is corrected by the error correction bit, and the size of the w code is n yuan. The size of the code and the new parity check code are 1 bit. Bit. Wherein, when the error is to correct the parity bit, the data code reads the lowest bit 70 of the data segment, and the new (four) code system is at least one error correction number r:: positive code and new error correction code month ^ The number, the shell code is at least one piece of data ^ μ 'new data code is at least - the pen reading data fragment is still in place. The memory 300 uses the error correction code and the new error correction code, the parity: the code and the new parity check code, as well as the data code and the new data code, and judges whether a small piece of the read data segment is relative to at least the data segment of the pen. Bit 7L error. In addition, the 1-bit read two==detection method used in the memory 3〇〇 is described in detail in the above-described embodiment of the present invention. This will not be repeated. The memory disclosed in the above embodiment and its 1-bit read h error; U / then method 'utilizes error correction with only one of the error correction parity bits (ECC (4) ty u) or one of its complements The code, the 1-bit size of the parity check, and the 1st 7C size data code, with a simple 1 bit read error = double test method to detect whether the data stored in the memory has i bit error: For at least one data segment of the size of 2 digits, the memory of the invention disclosed in the present invention is compared with the management bit of the 2 η bit size required for the 1-bit read error detection method of the memory. The body 1-bit read error detection method only needs the management bit of η+2 bit size, which greatly saves the memory space and makes the memory have a simple hardware architecture. In addition, the Hamming code is also used in the tradition to ensure the integrity of the data. The Hamming code attaches a check bit to a specific location of at least one piece of data. For example, when the size of at least one piece of data is η bits, then k check bits are appended to 2°, 21, 22... and 2k_1 bits according to Equation 7 below, where k is a positive integer. 2kgn + k+l (Equation 7) where the number of the check bits and their corresponding bits must be an even number. The check bit is used to detect and correct at least one bit error of a piece of data. However, since the bits in the memory are adjacent to each other and the Hamming code has to add a check bit at a specific position, the Hamming code is not suitable for the memory. In summary, although the present invention has been implemented in a preferred embodiment It is to be understood that the invention is not intended to limit the invention, and that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application attached.
346PA 200908007 【圖式簡單說明】 第1A圖繪示傳統記憶體1位元讀取錯誤檢測方法之 流程圖。 第1B圖繪示錯誤修正檢測演算法之示意圖。 第2圖繪示依照本發明較佳實施例之記憶體1位元讀 取錯誤檢測方法之流程圖。 第3圖繪示依照本發明較佳實施例之記憶體之方塊 圖。 【主要元件符號說明】 300 記憶體 310 記憶單元陣列 320 錯誤修正電路 18346PA 200908007 [Simple description of the diagram] Figure 1A shows a flow chart of the conventional memory 1-bit read error detection method. FIG. 1B is a schematic diagram showing an error correction detection algorithm. FIG. 2 is a flow chart showing a method for detecting a 1-bit read error of a memory according to a preferred embodiment of the present invention. Figure 3 is a block diagram of a memory in accordance with a preferred embodiment of the present invention. [Main component symbol description] 300 Memory 310 Memory cell array 320 Error correction circuit 18
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW096130066A TWI349290B (en) | 2007-08-14 | 2007-08-14 | Memory and 1-bit error checking method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW096130066A TWI349290B (en) | 2007-08-14 | 2007-08-14 | Memory and 1-bit error checking method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200908007A true TW200908007A (en) | 2009-02-16 |
TWI349290B TWI349290B (en) | 2011-09-21 |
Family
ID=44723573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096130066A TWI349290B (en) | 2007-08-14 | 2007-08-14 | Memory and 1-bit error checking method thereof |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI349290B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI447739B (en) * | 2010-03-22 | 2014-08-01 | Phison Electronics Corp | Error correcting method, and memory controller and memory storage system using the same |
-
2007
- 2007-08-14 TW TW096130066A patent/TWI349290B/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI447739B (en) * | 2010-03-22 | 2014-08-01 | Phison Electronics Corp | Error correcting method, and memory controller and memory storage system using the same |
Also Published As
Publication number | Publication date |
---|---|
TWI349290B (en) | 2011-09-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9195551B2 (en) | Enhanced storage of metadata utilizing improved error detection and correction in computer memory | |
TWI307100B (en) | Memory and method for reading error checking thereof | |
US7149947B1 (en) | Method of and system for validating an error correction code and parity information associated with a data word | |
TWI332611B (en) | Method for writing data in flash memory and error correction coding/decoding method thereof | |
US20200401474A1 (en) | Optimized error-correcting code (ecc) for data protection | |
US20080215953A1 (en) | Three bit error detection using ecc codes | |
JPS60163138A (en) | Error correction system | |
TW201128653A (en) | Two-plane error correction method for a memory device and the memory device thereof | |
JPH05108495A (en) | Error correction detection method for data and error detection circuit for computer memory | |
US20160124803A1 (en) | Storage Device Data Access Method and Storage Device | |
CN101477481A (en) | Automatic error correction system and method | |
US20090055706A1 (en) | Method and apparatus for flash memory error correction | |
TW200845020A (en) | Memory, repair system and method for testing the same | |
US20240427664A1 (en) | Error rates for memory with built in error correction and detection | |
US8464093B1 (en) | Memory array error correction | |
CN108511028A (en) | The device and method for accessing storage device data is automatically corrected using error correcting code | |
US7721181B2 (en) | Memory and 1-bit error checking method thereof | |
CN1825495A (en) | Error correction circuit and method | |
CN109726030A (en) | Memory Architecture Including Response Manager for Error Correction Circuit | |
TW200908007A (en) | Memory and 1-bit error checking method thereof | |
US11928027B1 (en) | System and method for error checking and correction with metadata storage in a memory controller | |
CN104424046B (en) | Method, device and the equipment of data processing | |
US6425108B1 (en) | Replacement of bad data bit or bad error control bit | |
CN101373641B (en) | Memory and its 1-bit read error detection method | |
US10250279B2 (en) | Circuits and methods for writing and reading data |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |