200907664 0960132 24147twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種開機方法及系統，且特別是有關 於一種檢查電腦系統開機程序正確性的開機方法及系統。 【先前技術】 一般而言’電腦系統在開機時’首先會透過基本輪出 入系統（Basic Input Output System，以下簡稱 bios )執行 啟動自我測試（Power On Self Test, POST )，以初始化電 腦系統中的每個硬體裝置，例如中央處理器（Center Process Unit, CPU )、週邊控制器介面（peripheral contr〇ller Interface，以下簡稱PCI)、隨機存取記憶體（Rand〇m八咖沾 Memory，RAM)與南北橋晶片組（chipset)等等。在電腦 内的硬體設備通過檢驗與測試後，BIOS便會將電腦内的硬 體資訊交給作業系統’讓作業系統繼續完成開機的動作。 上述自我測試的過程中，BIOS依序對每個硬體裝置 發出測試的指令’並等待硬體裝置回覆應答（acknowledge， 以下簡稱ACK)訊息。舉例來說，當BIOS要測試受測單 元時’將先發出測試的指令至受測單元。接著受測單元會 發出一 ACK訊息表示受測單元運作正常。然而，當電腦 系統的硬體裝置發生異常，異常的硬體裝置將無法發出 ACK訊息，導致BI〇S陷於無窮等待的情況，而無法正常 開機。 另外，在傳統檢查BIOS映像檔的方法中，一般是檢 查映像檔中的循環冗餘檢測碼（Cyclic Redundancy Check， 200907664BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booting method and system, and more particularly to a booting method and system for checking the correctness of a booting procedure of a computer system. [Prior Art] Generally speaking, when the computer system is turned on, it first performs a Power On Self Test (POST) through the Basic Input Output System (hereinafter referred to as bios) to initialize the computer system. Each hardware device, such as a central processing unit (CPU), a peripheral controller interface (peripheral contr〇ller interface, hereinafter referred to as PCI), random access memory (Rand〇m eight coffee, RAM, RAM) With the North and South Bridge chipset (chipset) and so on. After the hardware device in the computer passes the inspection and testing, the BIOS will deliver the hardware information in the computer to the operating system to let the operating system continue to complete the booting action. In the above self-test process, the BIOS sequentially issues a test command to each hardware device and waits for a hardware device reply (acknowledge, hereinafter referred to as ACK) message. For example, when the BIOS wants to test the unit under test, the test command will be issued to the unit under test. The unit under test will then send an ACK message indicating that the unit under test is functioning properly. However, when the hardware of the computer system is abnormal, the abnormal hardware device will not be able to send an ACK message, causing the BI〇S to be in an infinite waiting condition and fail to boot normally. In addition, in the traditional method of checking the BIOS image file, the cyclic redundancy detection code in the image file is generally checked (Cyclic Redundancy Check, 200907664)
WbOlSZ ^4i4/twf.d〇c/n CRC)或總和碼（checksum)來偵測BI〇s映像 整，，若臓映像標的程式碼出現邏輯性： 如…窮迴圈等等）日夺’在檢查BI〇s映像樓 檢測碼或檢查或總和碼時，並不會檢查出此種錯誤盾=餘 在開機過程中’邏輯性錯誤的程料仍會被執行、-二 成電腦系統無法正常開機。 & 【發明内容】 f 本發明提供-種開機方法與系統，使得在硬體 序發生錯誤時，電腦系統能夠及時做出適當 、= ^開機程序停滯在某個階段㈣法繼續執彳t硬體測試Ξ 土發明提出—種開機方法，用峨動電腦系統 先’執行硬體測試祕，其中，硬體職 試階段，而各測試階段皆對應—到期時間上括:個： 測試階段中，當-特定測試階段之特定測試 = 的到期時間時，判斷此特定測試階段是否為 段。當此蚊賴階段為次要測試階段時，提示錯誤= 錢續執行其他的硬體賴程序。當此特㈣試;；；二 次要測試階段時，重新啟動電腦系統。 又非為 在本發明之一實施例中，開機 各測試階段時’將計時器重置(=更==執行 對應的測試時間。另一方面，開機方法更包括建丄：*段 格，此測試表格中記錄各測試階段對應的到 2表 應的重要階段攔位。並且，依據特⑽試階段對應之= 200907664 0960132 24147twf.d〇c/n 階段料測試階段是否為次要測試階段。 步驟包触序財上^執行硬體測試程序的 當測心間Γ超過對應的到期時間。 體測試程序Γ心間未超過到期時間時’則繼續執行硬 否為實施例中，上述之判斷特定測試階段是 在中斷服務常中f服務常式。接著， ；：： , 式，以繼續執行不錯誤訊息’並離開令斷服務常 階段為非體賴程序；反之，#特定測試 電腦系統。"忒匕段時，透過中斷服務常式，重新啟動 標，實施例巾，_料更包括提供一旗 次要測試階段^=否啟動成功。#特定_階段為非 以又守’則设置旗標，並於該階段結束時清除之， 用以執行查旗標。當旗標被設置時，將要求更新 執1體測試=序之映當旗標未被設置時，則 動電=二觀點來看，本發明提出一種開機系統，用以啟 系、、先。此開機系統包括硬體測試模組以及計時器。 200907664 0960132 24147twf.doc/n 而計時器耦接至硬:目,丨 體測試程序，其中硬體測試;序:執行硬 試階段皆對應-到期時間。計時哭用二十段’各測 應的測試時間。在這些測試階段二^測試階段對 特定測試時間超過對應的田特足測試階段之 特定測試階段是否為;要測試階;組判斷 ίΓ=地，;誤訊息，並 動電腦系ι 4以'_段為制試·時，重新啟 中斷控制器、處理機系統更包括測試表格、 試階段對應的到二==表格用以記錄各測 制器耦接至計時器，用以產位。中斷控 元。處理單元用以啟動中斷服斷_並傳送^處理單 段對應之重要階段攔位，來判斷特^測定測試階 測1:;:票則用以記錄電腦系統是否二=為次要 特定測4::::=段=當:斷服務常式判定 旗標，並重新啟動電腦系統。非-人要_皆段時，則設置 在本發明之一實施例中， 檢查旗標。者旗述之硬體測試模組更包括 行硬體·;執 入輸出系統。 兄賵測5式模組例如是基本輸 200907664 uyotfi i h /twf.doc/n 在本發明之一實施例中，上述之計時器M 測試階段的測試_是否超過職的到㈣ 各 判斷出測試時間超過到期時間時，則驅口時器 產生中斷訊號。 巧?工制益，以 電 在某_段而紐免開機程序停滞 為，本發明之上述特徵和優點能更明顯易懂 牛較佳實施例，並配合所附圖式，作詳 【實施方式】 —本發明透過將各測試階段設置—對應的到 得备各測忒階段無法在對應的到期時間内執+里 “ 斷此測試階段是科次要測試階段，以決定是^要^ 行硬體測雜序。0此，在硬體測試程序發生 /執 月®系統便能夠及時做出適當的反應， ^ 下文特 說明如下 塊圖圖依照本發明第一實施例所繪示之開機系統的方 以。1 m统⑽包括硬體測試模組110 以ι4 =，。而言十時器120耗接至硬體測試模組⑽。 下p開始；1紹開機系統100各構件之功能。 ;逆===:二 出系=ί統而言’硬體測試敝110例如是基本輸入輸 、’、（asic Input Output System，以下簡稱 m〇s )，上 200907664 vyovi^z z^i^/twf.doc/n 述硬體測試程序例如是啟動自我測試（Power On Self Test, POST)。而當電腦系統的電源開啟後，BIOS將進行啟動 自我測試，並在完成啟動自我測試後，BIOS再將作業系統 載入。然而，此領域具有通常知識者可以視其需求而將本 發明實施於各種應用中，故上述之假設不能用以限定本發 明。 計時器120是用來計數各測試階段對應的測試時間。 在硬體測試程序中，每當硬體測試模組11〇在執行其中之 一測試階段時，計時器120便開始測量此測試階段所經過 的測試時間。而硬體測試模組11〇在執行硬體測試程序中 各測試階段之前’將先重置（feset)計時器12()，以重新 計數各測試階段之_時間。另外，計時器12()亦用於判 斷所經過❹m日f暇否超過此測試階段對應的到期時 間。 / =地况’在開機過程中’硬體測試模組ιι〇將依序 程每個測試階段。在硬體測試模組 試階段所對應之到期===先 試時間。因此’若計時哭12 ” 〇又所化費的特定測 費的特定測試時間已經;過設置的;試:段所花 體測試模組110。 L月寺間8寸’便通知硬 在硬體測試模組 110得知此特定賴階段的特定測試 200907664 υ^ουυζ zHi^7twf.doc/n 時間已超過到期時間之後，硬體測試模組110將判斷此特 定測試階段是否為次要測試階段。以目前的電腦系統來 說’上述次要測試階段所測試的硬體裝置可以是通用串列 匯流排（Universal Serial Bus,以下簡稱USB)或軟碟機 (floppy)等等不影響電腦系統正常運作的硬體裝置。另 一方面，目前電腦系統的測試階段中，相反於次要階段的 測試階段所測試的硬體裝置則例如是中央處理器（Center Process Unit，CPU)、隨機存取記憶體（Random Access Memory，RAM)、南北橋晶片組（chipset)與週邊控制器 介面（Peripheral Controller Interface,以下簡稱 PCI)匯流 排等等主要影響電腦系統正常運作的硬體裝置。 因此，若硬體測試模組110判斷此特定測試階段為非 次要測试階段時，則重新啟動電腦系統，以中斷硬體測試 程序。舉例來說，若此特定測試階段為PCI匯流排的測試 階段，當PCI匯流排初始化失敗，則利用PCI匯流排連接 之硬體裝置也將無法被使用，因而此特定測試階段便判定 為非次要測試階段。另一方面，若硬體測試模組110判斷 此特定測試階段為次要測試階段，則提示錯誤訊息，並繼 續執行硬體測試程序。換言之，若發生錯誤的測試階段為 次要摩讀段’便可以忽略此一測試階段而往下執行硬體 測忒私序。舉例來說，當軟碟機的測試 續之硬體測試程序並不會受到影響，因此便提示一錯誤訊 息後’繼續後續動作。 從另-觀點來看，依據上述之開機系統可歸納出一個 11 200907664 t7twf.doc/n 間機方法。圖2是依照本發明第一實施例所繪示之 法的流程圖。請同時參照圖！及圖2，首先，在步汗方 中，硬體測試模組110執行一硬體測試程序。其 201 測试％序包括多個測試階段，而每個測試階段〜更體 時間:在執行硬體測試程序時，硬體測試模組期 序執行硬體測試程序中的各個測試階段。並且門依 ==段之前，硬體測試模組職重置計時= 仔冲12〇重新計數每個賴階段的測試時間。 〜^著如步驟S203所示，當硬體測試程序 — 的特定測試時間超過對應的到期時間時，硬‘ 也ί二此特定測試階段是否為次測試階段： 到達對岸的::二在計數特定測試階段的測試時間 階段是否為次二u 0便會判斷此特定測試 試程序，或是=決定繼續執行後續之硬體測 在步驟S203中，若硬體測試模 試階段為次要測試階段，則驟〇判疋此特疋測 ⑽提示錯誤訊息，並繼續執體測· 顯示在螢幕上。另-方面，若硬‘=，定測試階段 定測試階段為非4要:則忒挺組u〇判定此特 no S207 5 階段為非次要測試階段時，若是忽略二定:=: 12 200907664 /twf.doc/n 繽將硬體測試程序執行完畢，電腦系統亦無法正常啟動。 以目前電腦系統為例，當開機過程發生上述特定測試 階段超過到期時間的情況，可能是由於特定測試階段所測 試的硬體裝置作異常，也有可能是BI〇s映像射的程式 碼邏輯上錯誤，衍生出無線迴圈等等的情況。因此，在電 腦系統重新啟動後，BI0S可以進入啟動區塊（b〇〇tbl〇ck) 來更新BIOS映像檔，以解決發生BI〇s映像檔中的程式 碼邏輯上錯誤的情況。 V J ^ 綜上所述’本實施例在電腦系統開機過程中，一旦測 喊階段發生異常，電腦系統將及時做出適當的反應 ，來決 定是否重新開機或繼續硬體測試程序，使得電腦系統不至 於停頓在某一測試階段，而造成當機。 由於目别電腦系統為一分工精密之系統，故本發明於 實際應用上將有更詳細之步驟與構件。為了更清楚地說明 本發明之精神，以下則再以第二實施例來說明之。 弟二實施例 圖3是依照本發明第二實施例所繪示之開機系統的方 塊圖。請參照圖3，開機系統300包括硬體測試模組310、 晶片組320、處理單元33〇、旗標34〇以及記憶體35〇。晶 片組320麵接至硬體測試模組310以及處理單元330，旗 標340輕接至硬體測試模組31〇，而記憶體35〇則耦接至 處理單元330。 就現今電腦系統架構來說，本實施例之硬體測試模組 13 200907664 ^iH；twf.doc/n 310例如是Bi〇s ’晶片組320例如為南北橋晶片組，而處 理單元330例如是中央處理器（Center Process Unit， CPU)。在實際應用上’計時器321以及中斷控制器323 可配置在晶片組320中。並且，在硬體測試模組31〇中設 置一測試表格31卜當電腦系統啟動時，CPU將執行Bi〇s 映像播中未壓縮的程式瑪’以進行初期的測試動作。接著 由BIOS來掌控電腦系統的開機動作，而開始進行硬碟測 試程序。當BIOS將記憶體350初始化完成後，cpu便將 BIOS映像標中堡縮的程式碼，解壓縮並載入記憶體350 中執行。然而’在此僅為方便說明，並不限制本發明實際 應用的方式。 在本實施例中’硬體測試模組310之功能與上述實施 例之硬體測試模組110相同或相似，用以執行硬體測試程 序。不同的是，本實施例之硬體測試模組310裡設置了一 測試表格311 ’在測試表格311中記錄各個測試階段對應 之到期時間以及對應的重要階段攔位。以下假設本實施^ 所使用的測試表格311如圖4所示。圖4是依昭本發第 二實施例所繪示之測試表格311的示意圖。請; 在測試表格311中，硬體測試程序中的每一個測試階段皆 有其對應之到期時間與重要階段攔位。在重要階段 以則代表次要測試階段，‘‘丨，，代表為非次要測試階段。 在本實施例巾，次要測朗段所測試的硬體與電腦系統的 正常運作無關，例如：USB匯流排或軟碟機等等。 實際應用時，測試表格311可以儲存於m〇s的唯讀 14 200907664 uyowijz z^+iH/twf.doc/n 記憶體（Read Only Memoiy，R0M )或是電腦系統中的任 一記憶體。另外，測試表格311可以是在m〇s開發時期， 由BIOS工程師將硬體測試程序分為多個測試階段，將每 -個測試階段執行時所需之最長的測試時間記錄至測試表 格311中，並將每一個測試階段對應之重要階段欄位中， 根據各測試階段的重要性來記錄之，並且不限定用“〇，，與 “1”表示其重要性。 〃 、 接下來，當硬體測試模組310執行硬體測試程序時， 首先，將重置計時器321。本實施例之計時器321與第一 實施例之計時器12〇的功能相同或相似，故在此不再詳 述。於實際應用中，計時器321可耦接一中斷控制器323 來使用。也就是說，當計時器321測量之特定測試時間超 過目前正在執行之特定測試階段所對應的到期時間時，計 時器321將驅動中斷控制器323產生中斷訊號。而中斷控 制器323在產生中斷訊號之後，便將中斷訊號傳送至處理 單元330，使得處理單元33〇得以啟動中斷服務常式 ‘ （InterruptService Routine, ISR)，來判斷特定測試階段是 否為次要測試階段。 在處理單元330接收到中斷訊息時，便會啟動中斷服 務常式來服務此中斷訊息。此時，中斷服務常式則依據特 定測試階段在測試表格311中所對應之重要階段攔位，判 斷特定測試階段是否為次要測試階段。詳細地說，中斷服 務常式自硬體測試模組310讀取測試表格311中之特定測 試階段對應之重要階段欄位，當特定測試階段為次要測試 15 200907664 υ^υυι ζ,ηχη /twf.doc/n 階段時，中斷服務常式便提示錯誤訊息，並將控制權交還 硬體測試模組310，以繼續執行硬體測試程序。另一方面， 當特定測試階段對應之重要階段攔位中記錄著特定測試階 段為非次要測試階段時’中斷服務常式便設置旗標34〇, 並重新啟動電腦系統。 另外’在本實施例中’開機系統3〇〇中還包括有旗標 340,以記錄電腦系統是否啟動成功。例如，旗標34〇以“〇，， 與“1”分別表示開機成功與開機失敗，且在旗標34〇沒有被 設置的情況下，其預設值為“〇，，，表示預設上一次電腦系統 開機成功。也就是說，當處理單元330所啟動的中斷服務 常式判定出特定測試階段為非次要測試階段時，則旗標 340將被設置為“1，，，來表示開機失敗。反之，當處理單元 330所啟動的中斷服務常式判定出特定測試階段為次要測 試階段時，則旗標340將不會被設置，使其值維持在預設 值“0” ’來表示開機成功。因此，藉由硬體測試模組31〇 來檢查旗標340是否被設置，以判斷電腦系統上一次的開 機是否成功。 以下即利用上述圖4中的測試表格311，來說明圖3 中開機系統300中各元件的操作。首先，假設測試階段1 與2皆已在到其時間内完成（也就是已將記憶體35〇與晶 片組320初始化完成）。接著，硬體測試模組310便開始 進入測試階段3 (也就是測試PCI匯流排），將測試階段 所對應的到期時間300ms ( millisecond，ms )設定至計時器 321並重置計時器321，以讓計時器開始計數測試階段3 16 200907664 ^H-iH7twf.d〇c/n =::時T接下來’便開始進行測試階段3。在 、 執仃時，若測試時間超過300ms，計時器321 ^動3控制器323發出中斷訊號至處理單元现。處 好Π將啟動情服務常式，並依制試階段3在測 非二之重要階段攔位’判定出測試階段3為 i 這個時候，旗標將被設置，且電腦 Γ 二4啟動。在電腦系統重新啟動後，硬體測試模組31 〇 由:取到旗標340已被設置，並進入啟動區塊，以更新其 4負貝硬體測試模_程式碼，並防止因程式碼邏輯錯 §吳所造成的開機中斷。 —另一=面，假設上述測試階段3已在到期時間内完成 4式接著硬體測试模組31〇便開始進入測試階段4。若 ，執仃測觸段4時，其測試_超過⑽邮，處理單元 3〇將啟動巾斷服務常絲判定職階段4是否為次要測 1#又根據圖4中的測試表格311可知，測試階段4要 ，仃USB匯流排的測試，並且，測試階段4為次要測試階 ^因此，硬體測试模組310便提示錯誤訊息，而繼續執 行下一個測試階段5，以測試並初始化軟碟機。 乂為了更清楚地表達上述概念，以下即搭配上述之開機 =統300詳細說明開機方法的各步驟。圖5是依照本發明 苐二實施例所繪示之開機方法的流程圖。請同時參照圖 圖4及圖5，首先，在步驟S501中，當使用者開啟電 腦系統的電源時，電腦系統將啟動。 接著，如步驟S503所示，硬體測試模組31〇會檢查 17 200907664 iH7twf.doc/n 旗標340，以判斷上一次電腦系統開機是否成功。舉例來 說，旗標340定義“0”與“1”分別表示上一次電腦系統開機 成功與失敗。因此，在步驟S503中，若硬體測試模組31〇 檢查旗標340為“Γ，則執行步驟S505 ;若硬體測試模組 310檢查旗標340為“0”，則執行步驟S507。WbOlSZ ^4i4/twf.d〇c/n CRC) or the sumsum (checksum) to detect the BI〇s image, if the image of the image is logical: such as ... poor circle, etc.) When checking the BI〇s image building detection code or check or the sum code, it will not check out the error shield = the remaining logic during the boot process will still be executed, and the computer system will not function properly. Boot up. & [Summary of the Invention] f The present invention provides a booting method and system, so that in the event of an error in the hardware sequence, the computer system can make appropriate in time, = ^ boot program stagnation at a certain stage (four) method continues to enforce t hard The body test 提出 soil invention proposed - a boot method, use the computer system to 'execute the hardware test secret, which, the hardware test phase, and each test phase corresponds to - the expiration time is included: one: in the test phase When the expiration time of a specific test = specific test phase, determine whether this particular test phase is a segment. When this mosquito-repellent phase is a secondary test phase, the error is indicated = the money continues to execute other hardware programs. When this (4) test;;; the second test phase, restart the computer system. In addition, in an embodiment of the present invention, the timer is reset when the test phase is turned on (= more == the corresponding test time is executed. On the other hand, the boot method further includes: * segment, this The test table records the important stage stops corresponding to the 2 tables in each test phase, and according to the special (10) test phase corresponding to = 200907664 0960132 24147twf.d〇c / n phase test phase is the secondary test phase. When the hardware test program executes the hardware test program, the test time exceeds the corresponding expiration time. When the body test program does not exceed the expiration time, the process continues to execute hard. The specific test phase is in the interrupt service routine f service routine. Then, ;:: , , to continue to execute the error message 'and leave the service phase as a non-reliant program; otherwise, # specific test computer system. "In the middle of the period, through the interrupt service routine, restart the standard, the implementation of the towel, _ material also includes a flag to provide a secondary test phase ^ = no startup success. #specific _ phase is not and then 'set' Flag And at the end of the phase, it is cleared to perform the check flag. When the flag is set, it will be required to update the body test = the sequence of the flag is not set, then the power = two points of view The present invention provides a booting system for booting, first. The booting system includes a hardware test module and a timer. 200907664 0960132 24147twf.doc/n and the timer is coupled to the hard: mesh, body test program , in which the hardware test; preface: the execution of the hard test phase corresponds to - the expiration time. The timing is crying with twenty segments of the test time of each test. In these test phases, the test phase exceeds the corresponding test time for the specific test time. Whether the specific test phase of the foot test phase is; test the order; group judgment Γ Γ = ground, error message, and move the computer system ι 4 to use the '_ segment for the test, restart the interrupt controller, the processor system is more Including the test table, the test phase corresponding to the two == table is used to record each of the testers coupled to the timer for the production position. The interrupt control unit. The processing unit is used to initiate the interrupt service _ and transmit ^ processing single segment Corresponding to the important stage of the block, to judge ^ Determination test step 1::: The ticket is used to record whether the computer system is two = for the secondary specific test 4:::: = segment = when: break the service routine decision flag, and restart the computer system. When a person wants to be in the same stage, it is set in an embodiment of the present invention to check the flag. The hardware test module of the flag further includes a line hardware; the input and output system. The brother test 5 type module For example, the basic input 200907664 uyotfi ih /twf.doc / n In an embodiment of the present invention, the above test of the timer M test phase _ whether it exceeds the job to (4) each judges that the test time exceeds the expiration time, then The vent timer generates an interrupt signal. The above-mentioned features and advantages of the present invention can be more clearly understood, and the preferred embodiment of the present invention can be more clearly understood. 】 - The present invention can not be executed within the corresponding expiration time by setting each test phase to the corresponding test phase. "This test phase is the secondary test phase to determine whether it is OK. The hardware test is performed. In this case, the hardware test program occurrence/permanent month system can make an appropriate response in time. ^ The following block diagram shows the booting system according to the first embodiment of the present invention. The 1 m system (10) includes the hardware test module 110 with ι4 =, and the chronograph 120 is consuming the hardware test module (10). The next p starts; 1 the functions of the components of the boot system 100. Inverse ===: two out system = ί system, 'hard body test 敝 110 is for example, basic input and output, ', (asic Input Output System, hereinafter referred to as m〇s), on 200907664 vyovi^zz^i^/twf .doc/n The hardware test program is, for example, Power On Self Test (POST). When the power of the computer system is turned on, the BIOS will initiate self-test, and after completing the self-test, the BIOS will load the operating system. However, those skilled in the art can implement the present invention according to their needs. In the various applications, the above assumptions cannot be used to limit the present invention. The timer 120 is used to count the test time corresponding to each test phase. In the hardware test program, whenever the hardware test module 11 is executing During a test phase, the timer 120 begins to measure the test time elapsed during this test phase, and the hardware test module 11 ' first resets the timer 12 before performing the test phases in the hardware test program. (), to re-count the _ time of each test phase. In addition, the timer 12 () is also used to determine whether the ❹m day f 暇 exceeds the expiration time corresponding to this test phase. / = the situation 'in the boot process 'Hard test module ιι〇 will follow the sequence of each test phase. In the hardware test module test phase corresponding to the expiration === try first time. So 'if the time is crying 12 〇 〇 and the cost The specific test time for the specific measurement has been set; the test: 110 of the segmental test module. L month temple 8-inch 'will inform the hard test module 110 to know the specific test of this particular stage 200907664 υ ^ υυζ υυζ zHi^7twf.doc / n time has exceeded the expiration time, the hardware test module 110 will determine if this particular test phase is a secondary test phase. In the current computer system, the hardware device tested in the above-mentioned secondary test phase may be a Universal Serial Bus (USB) or a floppy disk (floppy), etc., etc., which does not affect the normal operation of the computer system. Hardware device. On the other hand, in the test phase of the current computer system, the hardware devices tested in the test phase opposite to the secondary phase are, for example, a central processing unit (CPU), a random access memory (Random Access Memory, RAM), chipset and peripheral controller interface (PCI) busbars, etc., which mainly affect the normal operation of the computer system. Therefore, if the hardware test module 110 determines that the specific test phase is a non-secondary test phase, the computer system is restarted to interrupt the hardware test procedure. For example, if the specific test phase is the test phase of the PCI bus, when the PCI bus initialization fails, the hardware device connected by the PCI bus will not be used, and thus the specific test phase is determined to be non-time. To test the stage. On the other hand, if the hardware test module 110 determines that the specific test phase is the secondary test phase, an error message is displayed and the hardware test procedure is continued. In other words, if the test phase in which the error occurred is the secondary read segment, then the test phase can be ignored and the hardware test private sequence can be performed. For example, when the test of the floppy disk drive continues without affecting the hardware test program, an error message is displayed to 'continue the follow-up action. From another point of view, according to the above-mentioned booting system, a method of 11 200907664 t7twf.doc/n can be summarized. 2 is a flow chart of a method in accordance with a first embodiment of the present invention. Please refer to the map at the same time! And in Fig. 2, first, in the step of sweating, the hardware test module 110 executes a hardware test procedure. The 201 test % sequence includes multiple test phases, and each test phase ~ more time: When the hardware test program is executed, the hardware test module program executes each test phase in the hardware test program. And before the door == segment, the hardware test module job reset timing = rushed 12 〇 re-count the test time of each lag phase. ~^ As shown in step S203, when the specific test time of the hardware test program exceeds the corresponding expiration time, the hard test is also the second test phase: the arrival of the opposite bank:: two in the count Whether the test time phase of the specific test phase is the second test result, the specific test test procedure is judged, or = the decision to continue the subsequent hardware test is performed in step S203, and if the hardware test test phase is the secondary test phase, Suddenly, this special test (10) prompts an error message and continues to perform the physical measurement and display on the screen. On the other hand, if the hard '=, the test phase is set to be non-four: then the group is determined to determine the special phase of the non-S207 5 is a non-minor test phase, if it is ignored two == 12 200907664 /twf.doc/n The hardware test program is executed and the computer system cannot be started normally. Taking the current computer system as an example, when the specific test phase exceeds the expiration time during the boot process, it may be due to an abnormality of the hardware device tested in the specific test phase, or it may be that the code of the BI〇s image is logically Error, derived from the situation of wireless loops and so on. Therefore, after the computer system is restarted, BIOS can enter the boot block (b〇〇tbl〇ck) to update the BIOS image to resolve the logic error in the BI〇s image. VJ ^ In summary, in this embodiment, during the startup process of the computer system, once an abnormality occurs in the phase of the call, the computer system will promptly respond appropriately to decide whether to reboot or continue the hardware test procedure, so that the computer system does not As for the pause in a certain test phase, causing a crash. Since the computer system is a system of precision division, the present invention will have more detailed steps and components in practical applications. In order to more clearly illustrate the spirit of the present invention, the following description will be made in the second embodiment. Second Embodiment FIG. 3 is a block diagram of a booting system according to a second embodiment of the present invention. Referring to FIG. 3, the booting system 300 includes a hardware test module 310, a chipset 320, a processing unit 33, a flag 34, and a memory 35. The chip set 320 is connected to the hardware test module 310 and the processing unit 330, the flag 340 is lightly connected to the hardware test module 31A, and the memory 35 is coupled to the processing unit 330. In the present computer system architecture, the hardware test module 13 200907664 ^iH; twf.doc/n 310 of the present embodiment is, for example, a Bi〇s chipset 320 such as a north-south bridge chipset, and the processing unit 330 is, for example, Central Processing Unit (CPU). The timer 321 and the interrupt controller 323 can be disposed in the chip set 320 in practical applications. Further, a test table 31 is set in the hardware test module 31A. When the computer system is started, the CPU executes the uncompressed program in the Bi〇s image to perform the initial test operation. Then the BIOS takes control of the booting action of the computer system and starts the hard disk test procedure. When the BIOS initializes the memory 350, the CPU will decompress the BIOS image and load it into the memory 350 for execution. However, the description herein is merely for convenience of description and does not limit the manner in which the present invention is actually applied. In the present embodiment, the function of the hardware test module 310 is the same as or similar to that of the hardware test module 110 of the above embodiment for executing a hardware test program. The difference is that the test table 311' is set in the hardware test module 310 of the embodiment, and the expiration time corresponding to each test phase and the corresponding important phase block are recorded in the test table 311. The following assumes that the test table 311 used in the present embodiment is as shown in FIG. 4 is a schematic diagram of a test table 311 shown in the second embodiment of the present invention. Please; In test form 311, each test phase in the hardware test program has its corresponding expiration time and important phase block. In the important phase, it represents the secondary testing phase, ‘‘丨,, the representative is a non-secondary testing phase. In the embodiment of the invention, the hardware tested in the secondary measurement section has nothing to do with the normal operation of the computer system, such as a USB bus or a floppy disk drive. In practical application, the test table 311 can be stored in the m〇s read-only 14 200907664 uyowijz z^+iH/twf.doc/n memory (Read Only Memoiy, ROM) or any memory in the computer system. In addition, the test table 311 may be in the development stage of the m〇s, the BIOS engineer divides the hardware test program into multiple test phases, and records the longest test time required for each test phase to be executed in the test table 311. And each important test phase corresponding to the test phase is recorded according to the importance of each test phase, and is not limited to use "〇,, and "1" to indicate its importance. 〃, Next, when hard When the body test module 310 executes the hardware test program, first, the timer 321 will be reset. The timer 321 of the present embodiment has the same or similar functions as the timer 12 of the first embodiment, and therefore is not detailed here. In practical applications, the timer 321 can be coupled to an interrupt controller 323. That is, when the specific test time measured by the timer 321 exceeds the expiration time corresponding to the specific test phase currently being executed, The timer 321 will drive the interrupt controller 323 to generate an interrupt signal, and the interrupt controller 323 will transmit the interrupt signal to the processing unit 330 after the interrupt signal is generated, so that the processing unit 33 The Interrupt Service Routine (ISR) can be started to determine whether the specific test phase is a secondary test phase. When the processing unit 330 receives the interrupt message, the interrupt service routine is started to service the interrupt message. The interrupt service routine determines whether the specific test phase is a secondary test phase according to the important phase of the corresponding test phase in the test table 311. In detail, the interrupt service routine self-hardware test module 310 The important phase field corresponding to the specific test phase in the test table 311 is read. When the specific test phase is the secondary test 15 200907664 υ^υυι ζ, ηχη / twf.doc/n phase, the interrupt service routine prompts an error message. And return control to the hardware test module 310 to continue the hardware test procedure. On the other hand, when the specific test phase corresponds to the important phase of the test, the specific test phase is recorded as a non-minor test phase. The service routine sets the flag 34〇 and restarts the computer system. In addition, in this embodiment, the booting system 3〇〇 Flag 340 is included to record whether the computer system is successfully started. For example, the flag 34〇 indicates “power, success, and power failure, respectively, and “1” indicates that the flag 34〇 is not set, The preset value is “〇,,, indicating that the previous computer system was successfully turned on. That is, when the interrupt service routine initiated by the processing unit 330 determines that the specific test phase is a non-secondary test phase, the flag is The flag 340 will be set to "1,," to indicate that the boot failed. On the contrary, when the interrupt service routine initiated by the processing unit 330 determines that the specific test phase is the secondary test phase, the flag 340 will not be set, and its value is maintained at the preset value "0" to indicate booting. success. Therefore, it is checked by the hardware test module 31〇 whether the flag 340 is set to determine whether the computer system was successfully turned on last time. The operation of each component in the booting system 300 of FIG. 3 will be described below using the test table 311 of FIG. 4 described above. First, assume that test phases 1 and 2 have been completed in their time (i.e., memory 35〇 and slice group 320 have been initialized). Then, the hardware test module 310 begins to enter the test phase 3 (that is, tests the PCI bus), and sets the expiration time 300ms ( millisecond, ms ) corresponding to the test phase to the timer 321 and resets the timer 321 . In order for the timer to start counting the test phase 3 16 200907664 ^H-iH7twf.d〇c/n =:: T then 'test' is started. At the time of execution, if the test time exceeds 300ms, the timer 321 controller 3 sends an interrupt signal to the processing unit. The Π Π 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 , 启动 , , , , , , , , , , , 启动 , 启动 启动 启动 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ After the computer system is restarted, the hardware test module 31: is set to the flag 340 has been set, and enters the boot block to update its 4 negative shell hardware test mode code, and prevent the code The logic is wrong, § Wu caused the power-on interruption. - Another = face, assuming that the above test phase 3 has been completed within the expiration time. Then the hardware test module 31 begins to enter the test phase 4. If the test segment 4 is executed, the test _ exceeds (10) mail, the processing unit 3 〇 will start the towel service service wire determination stage 4 is a secondary test 1 # and according to the test table 311 in FIG. 4, In the test phase 4, the test of the USB bus is performed, and the test phase 4 is the secondary test step. Therefore, the hardware test module 310 prompts the error message and continues to execute the next test phase 5 to test and initialize the soft. Disc player. In order to express the above concept more clearly, the following steps are described in detail with the above-mentioned power-on system 300. FIG. 5 is a flow chart showing a booting method according to a second embodiment of the present invention. Referring to FIG. 4 and FIG. 5 simultaneously, first, in step S501, when the user turns on the power of the computer system, the computer system will start. Next, as shown in step S503, the hardware test module 31 will check 17 200907664 iH7twf.doc/n flag 340 to determine whether the last computer system was successfully turned on. For example, flag 340 defines "0" and "1" to indicate the success and failure of the last computer system boot. Therefore, in step S503, if the hardware test module 31 〇 check flag 340 is "Γ, step S505 is performed; if the hardware test module 310 checks flag 340 is "0", step S507 is performed.
i. 在步驟S505中’硬體測試模組310將更新用來執行 硬體測試程序之程式碼，以電腦系統為例，步驟S5〇5即 疋直接更新BIOS的程式碼。也就是說，若上次電腦系統 開機失敗’旗標340將被設置為“1” ’以在電腦系統重^啟 動時，直接進入更新程式碼的模式，以防止因程式碼邏 錯誤而造成的開機失敗。在程式碼更新完成後，執行步 S501以重新將電腦系統啟動。此時，程式碼更新完畢 旗標340的設定值亦恢復為預設值“〇，，。 汉之 若在步驟S503中 成功，在步驟叫，硬體測;=¾ 行硬體測試程序中的測試階段卜5。 。執 體測試模組310重置計時哭π /心’中，硬 序中此時的特定二體測試種 試模:π計時器321歸零，並二 然後，在步驟S511中，計時哭,/數料日琳 階段的過程中’計數測試時間她執行特定剛試 的特定測試_是否超鱗Ί續段花費 模組310是否在此特定測試階段對庫=，思即硬體漁m 成此特定測試階段。若 時間之内，完 如期完成特定挪 200907664 z-Hin/twidoc/n =即特定測試時間未超過對應之到期時間，執行 接著，在步驟S513中，硬體測試槿 測試程序是否執行完畢，換言之，就是判斷此 段是否為硬體測試程序中最後一個測試階== 定測試階段是最後一個測試階段，則在步驟S515^i 體測試模組310將載入作聿孚统。 中更 f μ, 另外，絲時的測試階 ，疋取後一個測試階段，則繼續回到步驟 執行下一個測試階段。 龜巧 請回到步驟灿，當計時器切判 過到期時間，則在步獅，計時器321將驅動式= 器323產生中斷訊號至處理單元33()，以驅動處理單元挪 啟動中斷服務常式。接下來，在倾S519中，處理 =〇將開始執行中斷服務常式，並在中斷服務常式中，依 據測成表格3U中特定測試階段對應之重要階段搁位，判 ^寺定測試階段是否為次要測試階段。以目前的電腦系統 ，矹，在處理單元330接收到中斷控制器323所發出之中 斷訊號時’將會啟動中斷服務常式來服務此中斷^號。這 個時候，處理單元330便利用中斷服務常式來檢查特定測 試階段對應的重要階段攔位，來判斷特定測試階段是否為 次要測試階段。 若特疋測式階段為非次要測試階段，如步驟S521所 不’中斷服務常式便會去設置旗標340的設定值為開機失 敗（例如設置為“1”），之後重新開機，返回步驟S5〇i。 19 200907664i. In step S505, the hardware test module 310 will update the code used to execute the hardware test program. Taking the computer system as an example, step S5〇5 directly updates the BIOS code. That is to say, if the last time the computer system fails to turn on, the flag 340 will be set to "1". When the computer system is restarted, it will directly enter the update code mode to prevent the code logic error. Boot failed. After the code update is completed, step S501 is executed to restart the computer system. At this time, the set value of the code update flag 340 is also restored to the preset value "〇,,. If the success is successful in step S503, the step is called, the hardware test; = 3⁄4 line test in the hardware test program Stage Bu 5. The performing test module 310 resets the timing of the crying π / heart ', the specific two-body test type test mode in the hard sequence at this time: the π timer 321 returns to zero, and then, in step S511 , timed to cry, / count in the process of the Linlin stage 'count test time she performs a specific test for a specific test _ whether the super-segment continues to spend the module 310 on this particular test phase against the library =, thinking is the hardware The fishing m is in this specific test phase. If it is within the time, the specific flight 200907664 z-Hin/twidoc/n is completed as scheduled, that is, the specific test time does not exceed the corresponding expiration time, and then executed, in step S513, the hardware test槿 Whether the test program is executed, in other words, whether the segment is the last test step in the hardware test program == The test phase is the last test phase, then the test module 310 will be loaded in step S515聿孚统. 中更f μ, In addition, the test step of the wire, after taking a test phase, continues to return to the step to perform the next test phase. Turtle Qiao please return to the step can, when the timer cuts the expiration time, then in the lion, timing The driver 321 generates an interrupt signal to the processing unit 33() to drive the processing unit to start the interrupt service routine. Next, in the dump S519, the processing = 〇 will start to execute the interrupt service routine, and In the interrupt service routine, according to the important stage of the specific test phase corresponding to the test form 3U, it is determined whether the test phase is a secondary test phase. In the current computer system, 矹, the interrupt is received at the processing unit 330. When the interrupt signal is sent by the controller 323, the interrupt service routine will be started to serve the interrupt ^. At this time, the processing unit 330 facilitates checking the important phase block corresponding to the specific test phase by using the interrupt service routine to judge Whether the specific test phase is the secondary test phase. If the special test phase is a non-secondary test phase, if the service routine is not interrupted in step S521, the flag 340 is set. Power failure is set (e.g., set to "1"), after the restart, the step returns S5〇i. 19200907664
KjyvviDZ. ^iH/twf.doc/n 反之丄若特定測試階段為次要職階段， 示，中斷服務常式則提示錯誤訊息。接著，;【Μ23所 將結 '中斷服務常式，_步驟咖，由=^33〇 310判斷此特定測試階段是否為最後—個 ^'猶挺 斷出此特定測試階段並非最後一個測試階严°二。若判 組310將回到步驟S5〇7繼續執行下一個^階段體㈣模 點：1示上所述’本發明之開機方法及系統至少具有下列優 1. 藉由判斷各測試階段之測試時間是 期時間’而在峨時間超過_ 夠及時=到 常開機。 硬體測社序W在某個階段而無法正 2. 當發生錯紅賴階段為次 =測試階段後，讓使用者或是生產研二= 夠仔知發生錯誤的裝置，減少找尋錯誤的時間。 以3.當硬體測試程序之非次要測試階段發生錯誤時，電 腦^統將重新開機’讓電腦系統能夠更新硬體測試程序的 私式碼’以防止電腦系統因程式碼邏輯錯誤所造成的開機 失敗。 〜雖然本發明已以較佳實_揭露如上，然其並非用以 限定本發明’任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範_，當可作些許之更動與潤飾， 口此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 20 200907664 7twf.d〇c/n 【圖式簡單說明】 機系統的方 機方法的流 圖1是依照本發明第一實施例所繪示之開 塊圖。 圖2是依照本發明第一實施例所繪示之開 程圖。 圖3是依照本發明第二實施例所繪示之開機系統的方 意圖 圖4是依照本發明第二實施例所繪示之測試表 格的示 圖5是依照本發明第二實施例所繪示之開機方法的流 程圖。 【主要元件符號說明】 110、310 :硬體測試模組 120、321 ··計時器 311 .測試表格 320 .晶片組 323 :中斷控制器 330 :處理單元 340 :旗標 350 :記憶體 S201〜S207 :本發明第一實施例之開機方法的各步驟 S501〜S523 :本發明第二實施例之開機方法的各步驟KjyvviDZ. ^iH/twf.doc/n Conversely, if the specific test phase is a secondary phase, the interrupt service routine will prompt an error message. Then, [Μ23 will end the 'interruption service routine', _step coffee, by =^33〇310 to determine whether this particular test phase is the last one ^^'s quite a break from this particular test phase is not the last test strict ° II. If the judgment group 310 will return to step S5〇7 to continue to execute the next stage body (four) module point: 1 shows that the invention method and system have at least the following advantages. 1. By judging the test time of each test stage It is the time 'and the time is over _ enough time = always turn on. The hardware test sequence W is not positive at a certain stage. 2. When the error occurs, the user is either a tester or a production tester. It is enough to know the device that has the error and reduce the time for finding the error. 3. When an error occurs in the non-minor test phase of the hardware test program, the computer will reboot and 'enable the computer system to update the private code of the hardware test program' to prevent the computer system from being caused by logic errors in the code. The boot failed. The present invention has been described as a preferred embodiment of the present invention, and is not intended to limit the invention to any of ordinary skill in the art, and may be modified and modified without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended patent application. 20 200907664 7twf.d〇c/n [Simplified illustration] Flow of the method of the machine system Fig. 1 is an open block diagram according to the first embodiment of the present invention. Figure 2 is a schematic illustration of a process in accordance with a first embodiment of the present invention. 3 is a schematic view of a booting system according to a second embodiment of the present invention. FIG. 4 is a diagram showing a test table according to a second embodiment of the present invention. FIG. 5 is a diagram of a second embodiment of the present invention. Flowchart of the boot method. [Description of main component symbols] 110, 310: hardware test module 120, 321 · timer 311. test table 320. chip set 323: interrupt controller 330: processing unit 340: flag 350: memory S201~S207 Steps S501 to S523 of the booting method of the first embodiment of the present invention: steps of the booting method of the second embodiment of the present invention