200901846 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電路板結構及其製法，尤指—種具 有細線路之電路板結構及其製法。 、 【先前技術】200901846 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board structure and a method of manufacturing the same, and more particularly to a circuit board structure having a fine line and a method of manufacturing the same. [Prior Art]
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20 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 忐、鬲性能的研發趨勢。為滿足半導體封裝件高積集度 (integration)及微型化（miniaturizati〇n)的封裝需求，以供更 多主破動元件及線路載接，半導體封裝基板亦逐漸由雙層 2路板演變成多層電路board)，俾在有限的 二間下運用層間連接技術（interlayer connection)以擴大半 ^ ΐ哀基板上可供利用的線路佈局面積，藉此配合高線 路=、度之積體電路（lntegrated。则⑴需要，㈣封裝基板 的厚度’以在相同基板單位面積下容納更多數量的線路及 為因應微處理器、晶片組、緣圖晶片與特殊 電=SIC)等高效能晶片之運算需要，佈有導線之半導體 ^ 需提昇其傳遞晶“號、改善頻寬、控制阻抗20 With the rapid development of the electronics industry, electronic products have gradually entered the development trend of multi-functionality and performance. In order to meet the high integration and miniaturization requirements of semiconductor packages for more main broken components and line carriers, semiconductor package substrates have gradually evolved from two-layer two-way boards. Multi-layer circuit board), using the interlayer connection technology to expand the layout area available on the substrate, thereby matching the high-line=, degree integrated circuit (lntegrated) (1) required, (4) the thickness of the package substrate 'to accommodate a larger number of lines in the same substrate unit area and to meet the operational needs of high-performance chips such as microprocessors, chipsets, edge wafers and special power = SIC) , a semiconductor with a wire ^ need to increase its transfer crystal number, improve bandwidth, control impedance
力能’來成就高1/0數封裝件的發展 體封裝件輕薄短小、多功处上 寸。千V 化的開發w/速度、高線路密度及高頻 放土板已朝向細線路及小孔徑發展。現 至規才&封A基板製程從傳統1GG微米之線路尺寸，已縮減 見在的30微米以下’其中，包括導線寬度π—)、 5 200901846 線路間距（space)及深寬比（aspect rati〇)等持續朝向更小的 線路精度進行研發。 5 10 15 為提高半導體封裝基板之佈線精密度，業界發展出一 種增層技術（bulld-up)’亦即在—核心電路板（咖⑽此 表面利用線路增層技術交互堆疊多層介電層及線路 層，亚於該介電層中開設導電盲孔(conduct〗ve Vla)以供上、 下層線路之間電性連接，而該線路增層製程係影響半導體 =裝基板線路密度的關鍵，依照現行技術，業者多以半力: 成法（semHdditive process，SAp)製作線路增層結構。 _而該半加成法之流程請參考^ajLlf。首先如圖㈣ 不’提供-核心板10’該核心板】〇上下表面各具有—線路 p，且該核心板附形成有複數導電通孔⑻，以電性連 =該核心板10上下表面之線路層11，其中，該也導電通孔 真一2,再參恤，形成-介電二 二；=:板10及該線路層n之表面。接著如圖卜所示， 電層13上形成複數開孔131，以顯露部分該線路和 作為電性連接塾1 1 1 , # 並於騎電層U及其該些開孔131上 ’一 導電曰16 °接著如圖1d所示，於該導電層16上幵4 :)圖：化阻層14。而後將該核心板10置入電鑛槽内(圖；未 圖案一之開“再:圖^ 層14後，並進㈣刻去 I &除㈣案化阻 該導電層心便完成層14所覆蓋之 如此，運用上述=;;=51及複數導電盲孔152。 重覆形成介電層及線路層，即製成一 20 200901846The ability to achieve a high 1 / 0 package development The body package is light and thin, multi-functional. Thousands of V developments w/speed, high line density and high frequency earthmoving plates have evolved towards thin lines and small apertures. Now the standard & A substrate process from the traditional 1GG micron line size, has been reduced below 30 microns 'including, including the wire width π -), 5 200901846 line spacing (space) and aspect ratio (aspect rati 〇) etc. Continue to develop toward smaller line accuracy. 5 10 15 In order to improve the wiring precision of the semiconductor package substrate, the industry has developed a bulk-up technology, that is, on the core circuit board (the surface of the coffee (10), the surface-layering technology is used to alternately stack the multilayer dielectric layer and In the circuit layer, a conductive blind via (ve Vla) is formed in the dielectric layer for electrically connecting the upper and lower layers, and the line build-up process affects the density of the semiconductor=package substrate line, according to The current technology, the industry is more than half the force: semHdditive process (SAp) to make the line build-up structure. _ And the process of the semi-additive method please refer to ^ajLlf. First, as shown in Figure (4) not 'provide - core board 10' The upper and lower surfaces of the core plate have a line p, and the core plate is formed with a plurality of conductive through holes (8) electrically connected to the circuit layer 11 of the upper and lower surfaces of the core plate 10, wherein the conductive vias are also true , refitting, forming - dielectric 22; =: the surface of the board 10 and the circuit layer n. Then, as shown in Fig. 2, a plurality of openings 131 are formed on the electric layer 13 to reveal part of the line and as electrical Connect 塾1 1 1 , # and on the riding layer U and The plurality of openings 131 on 'Next a 16 ° said conductive shown in FIG. 1d, Jian FIG. 4 :) on the conductive layer 16: 14 of the barrier layer. Then, the core board 10 is placed in the electric ore tank (figure; unpatterned one open) again: after the layer 14 is layered, and then (4) is engraved with I & (4) except that the conductive layer is completed and the layer 14 is completed. Covering this, using the above =;; = 51 and the plurality of conductive blind holes 152. Repeated formation of the dielectric layer and the circuit layer, that is, a 20 200901846
具有多層線路增層社M 對位極限之關係，、：電路板。另夕卜因微影钱刻製程 ⑸，所以如圖lg所；且：14開孔131必須大於導電盲孔 該些導電其為圖lf虛線a標示處之上視圖， 咖，目2周m繞有-延伸部，以作為孔環 ^ * 52a與該線路層丨51連接。 兩述半加成法之制 Ι4，. φ .. 氣作中，需要蝕刻去除該圖案化阻層 ίο 15 =广，：導電層16，使得原本位於介電層_面之線 缘、太二過蝕刻後必定減少其寬度，而使線路層151之 二1預估之線寬還低’因此無法維持原本線路層之 :二：中品質不穩定可能會造成其中線路過窄發生 2的㈣，但倘若增加原本線路層151之線寬，則有礙於 能力之提升。此外，圍繞在該導電盲侧周緣 仍存在之結構’對於提升細線路製程能力， 【發明内容】 路板Si!::本發明之主要目的即在於提供-種電 細線i之㈣^ ，藉以有效控制線路之形狀，形成 、、之電路板，同時可提升電路板之電性功能。 —為達成上述目的，本發明一種電路板結構，係包括· =面具有一第一線路層’該第-線路層具有 4接塾·’以及至少-增層結構覆蓋該核心板之表 ’该增層結構包含—介電層、—第二線路層、以及複數 20 200901846 中該些導電盲孔係電性連接該些電性連接墊 係與該介電層之表面齊平。 盲孔之表面 因該第二線路層及該些導電盲孔之表面均盥节介 故能有效控制線路之形狀，而可形成細線：The relationship between the M-bit limit of the multi-layer line-gathering company,: circuit board. In addition, due to the lithography engraving process (5), so as shown in Figure lg; and: 14 openings 131 must be larger than the conductive blind holes, which are conductive, which is the top view of the dotted line a of the figure lf, coffee, eyes 2 weeks m winding There is an extension portion to be connected to the wiring layer 51 as a hole ring ^*52a. The two semi-additive methods are Ι4,. φ.. In the gas process, the patterned resist layer needs to be removed by etching. ίο 15 = wide, the conductive layer 16 is placed on the edge of the dielectric layer _ surface, too After over-etching, the width must be reduced, and the line width of the circuit layer 151 is still low. Therefore, the original circuit layer cannot be maintained: Second, the medium quality instability may cause the line to be too narrow (4). However, if the line width of the original circuit layer 151 is increased, it will hinder the improvement of the capability. In addition, the structure still exists around the periphery of the conductive blind side. For improving the fine line process capability, the invention provides a road board Si!:: The main purpose of the present invention is to provide (four)^ of the electric thin line i, thereby effectively Control the shape of the circuit, form the circuit board, and at the same time improve the electrical function of the circuit board. - In order to achieve the above object, a circuit board structure of the present invention comprises: a mask having a first circuit layer 'the first circuit layer having 4 ports · ' and at least - a layered structure covering the surface of the core board' The build-up structure includes a dielectric layer, a second circuit layer, and a plurality of conductive blind vias in the plurality of layers 200901846. The conductive vias are electrically connected to the surface of the dielectric layer. The surface of the blind hole can effectively control the shape of the line due to the uniformity of the surface of the second circuit layer and the conductive blind holes, and a thin line can be formed:
10 上述電路板結構中，該些導電盲孔可為實心金屬柱 而該介電層與該第二線路層，以及該介電層與該 二 狀間具有—導電層。另外，更可包含—絕緣保護層覆= °亥至v —增層結構之最外層’且該絕緣保護層具有複數開 孔，以露出該最外層增層結構之之部分導: :線路層用以作為電性連接塾，而該絕緣保護層 焊層。 苴^述電路板之兩側，分別可為一置晶側及一植球侧， 15其中垓置晶側及植球側具有複數導電盲孔，該些導電盲孔 之周緣均無孔環。 此外，上述電路板結構中，該核心板係以一基板為核 且忒第一線路層係形成於該基板表面，而該基板中形In the above circuit board structure, the conductive blind vias may be solid metal pillars, and the dielectric layer and the second wiring layer, and the dielectric layer and the dipole have a conductive layer. In addition, the insulating layer can be further covered—the outermost layer of the build-up structure and the insulating protective layer has a plurality of openings to expose a part of the outermost layered structure: : for the circuit layer As an electrical connection, the insulating protective layer is soldered. The two sides of the circuit board may be a crystal side and a ball-ball side, respectively, 15 of which have a plurality of conductive blind holes on the side of the chip and the ball-ball side, and the peripheral edges of the conductive blind holes have no hole rings. In addition, in the above circuit board structure, the core board has a substrate as a core and a first line layer is formed on the surface of the substrate, and the substrate is shaped
成有複數導電通孔電性連接至該基板表面之該第一 2Q 芦0 甘 I 曰。/、T，該核心板層數不限，可為雙層電路板或多層電 路板。另外，現有介電材料常填充有大分子填充物 μΐΏ)，而不利於製作細線路（線寬/線距，L/S < 15/15 μιη), 本發明之介電層係為一具有高電阻率之感光性介電材料， 而可有效阻擋線路間距縮小造成之電遷移或尖端放電效 8 200901846 應’並可進行曝光顯影以形成開孔，其中，該感光性介電 材料可選擇添加有至少一小分子填充物，亦或選擇不添力 填充物’因此可利於製作細線路（L/s < 1 5 /15 μπι)。 f 10 15 20 本發明另提供一種電路板結構之製法，包括以下步 驟：提供一核心板，該核心板表面具有一第一線路層，且 該第一線路層具有複數電性連接墊；形成一介電層覆莫气 核心板及該第一線路層之表面，於該介電層形輸：： 開口，其中部分線路開口則再進行雷射鑽孔，以形成 顯露出該些電性連接墊；形成一金屬層覆蓋 層，面、該些線路開口内及該些開孔内；以及移除… =介電：表面之該金屬層，該些線路開口内及於該：： 孔内之该金屬層係分別形成一第二 、:一汗 孔’以完成-線路增層結構，日雷複數導電盲 接該些電性連接塾及該第二線路盲孔係電性連 些導電盲孔之_ ^ 且邊第二線路層及該 育孔之表面係與該介電層 上述電路板結構之製法中 = 導電盲孔，其可為實心金屬 屬層所形成之該些 開口係利用曝光顯影形成， ^介電層之該些線路 開孔，以顯露出該第—線路^雷射鑽孔方式形成該些 再者，上述製法所形成二亥：：電性連接墊。 係小於該些開孔之深度。。"二線路開口之深度，較佳 9 200901846 【實施方式】 以下係藉由特定的具體實施例說明本發明之输 式’熟習此技藝之人士可由本說明書所揭示之内容二 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體貫施例加以施行或應用，本說明查 ^ w 乃曰τ的各項細節亦 ° 土於不同觀點與應用’在不悖離本發明之精神下久 種修飾與變更。 ％仃σ 本發明之實施例中該等圖式均為簡化之示意今 :圖示僅顯示與本發明有關之元件，其所顯示 ： ⑴實際實施時之態樣，其實際實施時之元件數目、形比 例為延擇性之設計，且其元件佈局型態可能更複雜。 實施例1 ' 月芩考圖2a〜2h ’此為本實施例電路板結構製 示意圖。 再展忐之“王 如圖2a所示，首先提供一核心板2〇，該核心板2〇上下 表面各具有一第一線路層21 ’且該第一線路層21具有複數 電性連接墊211。因此，本實施例所使用之核心板可為已完 t有第一線路層的雙層或多層電路板，另該核心板2〇係= —基板201為核心，將該第一線路層21形成於該基板2〇1上 下表面，而該基板201中形成有複數導電通孔2〇2，並電性 連接該基板201兩側表面之該第一線路層21，其中，該些導 電通孔202中係填充有樹脂22。 ,接著如圖2b所示，透過印刷、旋塗、或壓合的方式， 形成介電層23完全覆蓋該核心板2〇及該第一線路層η之 200901846 二：Γ中，該介電層23屬於—具有高電阻率之感光 電材料’並且可添加有至少 不添加填絲亦可。 Μ充物，或選擇 5 Ο 10 15 C, 20 ，然後參考圖2e，利料光顯影的方式，於該介電層23 上形成複數線路開口 231。 、 曰 接著如圖2d所示，再透過雷射雷射鑽孔的方式’將部 ^路開口231則再進行雷射鑽孔’形成複數開孔232至顯 路出㈣-線路層21之該些電性連接墊211。而後透過滅 =、或無電電鍍等方式’先形成一導電層％覆蓋該些線路 4 口 231、該些開孔232、以及該該第—線路層以之該些電 性連接墊2 I 1。 、接著參考圖2e，透過該導電層26傳導電流，以電錢形 成—金屬層24覆蓋該介電層23表面、該些線路開口 23丨内及 該些開孔232内。該金屬層24係選自由鉛、錫、銀、銅、金、 级、録、鋅、鎳、錯、鎮、銦、碑、紹以及錄等金屬及其 合金所組群組之其中一者所製成。 接著參考圖2f ’利用刷磨或蝕刻的方式，移除高度高 於該介電層表面23a之該金屬層24及該導電層26，二=二二 開口 231内及於該些開孔232内之該金屬層24係分別形成一 第二線路層242及複數導電盲孔241。其中部分導電盲孔241 係電性連接該核心板2 〇上該第一線路層2丨之該些電性連接 墊211及該第二線路層242’且該第二線路層242及該些導電 盲孔241之表面係與該介電層23之表面齊平，如此透過上述 步驟，可完成增層結構。 11 200901846 此外上述電鑛所形成之該金屬層24，可如圖2f完全 充滿忒些開孔232，如此所形成之該些導電盲孔24丨便形成 實心金屬柱。 至此’可依需要重複上述圖2b至圖2f之步驟，製作出 5多層之增層結構。如此便完成本發明之電路板結構，如圖 2g所示其包括：一核心板2〇，其表面具有_第一線路層^， 該第一線路層21具有複數電性連接墊2n;以及至少一增層 〇 結構覆蓋該核心板20之表面，該至少一增層結構包含一介 電層23、一第二線路層242、以及複數導電盲孔1，其中 1〇該些導電盲孔2 41係電性連接至該些電性連接墊2丨丨及該第 二線路層242,且該第二線路層242及該些導電盲孔川之表 面係與該介電層2 3之表面齊平。 再如圖2g所示，於增層結構之該介電層23 '該些導電 盲孔241、及該第二線路層242上，形成一絕緣保護層π: 接著參考圖2h，於該絕緣保護層27上，開設有複數開孔 r 7卜以露出該最外層增層結構之部分導電盲孔241及部分 I’ 帛二線路層242’以作為電性連接墊。本實施例中，該絕緣 保護層27係為一防焊層。 1且，如圖处所示之電路板結構所示，其兩側分別為 置晶側25a及植球側25b ’其中，置晶側25a係利用部分導電 盲孔241及部分第二線路層242，作為電性連接墊，以供形 成焊錫凸塊並接置半導體晶片。其中，圖2i為圖&虛線/ 標示處之上視圖，由圖2i可知，置晶側仏導電盲孔241周 緣沒有如先前技術圖lf& lg所揭示的孔環i52a。 12 200901846 力一惻表面即為—植球側25b，其係供 刷電路板’該植球側25b亦利用部分導電盲孔= =!; =4Γ以作為電性連f#，惟此側之谭錫球遠 板栢找彳丨以利於植②焊錫球，並接置印刷電路 板，植球側25b之導電盲孔24丨周綠 如同置晶側25a之導電盲孔241用@介 ，.泉路層242,但 等电首孔24丨周緣亦沒有孔環。 另外，於絕緣保護層27上形成開孔271 電盲孔如及部分第二線路層242，以作為電性連料= 電性連接墊之定義形式如下。 ίο 15 20 其一為如圖2h所示，該些具開孔271之絕緣保错層η 係部分覆蓋（Panlally c。叫該置晶側…之電性連接塾的 周緣部分，並料覆蓋㈣球㈣仏電性連接墊的周緣部 分’此電性連接墊為防焊層定義型電性連接墊（⑹加_k defined pad，SMD pad ); 其二為如圖3所示，電路板置晶侧25a之該些具開孔 川之絕緣保護層27係未覆蓋㈣c。叫該置晶側25a之電 性連接墊，且絕緣保護層27亦未接觸該電性連接墊，此電 性連接㈣非防焊層定義型電性料㈣麵_5()1加咖以 defined pad，NSMD pad)，電路板植球側25b之該些具開孔 271之絶緣保護層27則係部分覆蓋該些電性連接墊的周緣 部分； 其二為如圖4所示’電路板置晶側25a之該些具開孔 271之絕緣保護層27係未覆蓋該些電性連接墊，且絕緣保護 層27亦未接觸該電性連接墊，電路板植球側25b之該些具開 13 200901846 孔2 7 1之絕緣保護層2 7亦 分，且絕緣保護層27亦=该些電性連接墊的周 未接觸遠電性連接墊；以及 』為如圖5所示，電路板置晶側2 ⑺之絕緣保護層27係部分 二:孔 分，電路板植球側25b之該此一 Y生f接塾的周緣部 去罗#+ — 〃、開孔271之絕緣保護層27則 未:盍遠些導電結構241的電性連接塾，且絕 貝 亦未接觸該電性連接墊。 ” 4層27 ίο 因此’本發明之電路板結構及其製作方法，因 線路層242及該些導電盲孔⑷之表面均㈣ ^弟- 面齊平，故能有效控制線路之形θ 3之表 玫门* 小狀而可形成細線路之命 路板，同恰可提升電路板之電性功能。 屯 上述實施例僅係為了方便說明而舉例而已 主張之權利範圍自應以巾請專利範圍所述為準㈣所 於上述實施例。 非僅限 15 【圖式簡單說明】 圖1 a至1 f係習知半加成法之流程示意圖。 圖1 g係圖1 f虛線A標示處之上視示意圖。 圖2a至2h係本發明實施例之電路板結構 圖。 表忐之流程示意 圖2i係圖2h虛線A，標示處之上視示意圖。 圖3係本發明貫施例電路板結構之剖面示意圖 圖4係本發明實施例電路板結構之剖面示意圖。 圖5係本發明實施例電路板結構之剖面示意圖。 14 200901846The first plurality of conductive vias are electrically connected to the first 2Q reed of the substrate surface. /, T, the number of core boards is not limited, and it can be a double-layer circuit board or a multi-layer circuit board. In addition, the existing dielectric material is often filled with a macromolecular filler (μ), which is not advantageous for making a fine line (line width/line spacing, L/S < 15/15 μιη), and the dielectric layer of the present invention has High-resistivity photosensitive dielectric material, which can effectively block the electromigration or tip discharge effect caused by the narrowing of the line spacing. 200901846 should be able to be exposed and developed to form openings, wherein the photosensitive dielectric material can be optionally added. There is at least one small molecule of filler, or you can choose not to add a filler' so it can be used to make fine lines (L/s < 1 5 /15 μπι). The invention further provides a method for manufacturing a circuit board structure, comprising the steps of: providing a core board having a first circuit layer on the surface thereof, and the first circuit layer has a plurality of electrical connection pads; forming a The dielectric layer covers the surface of the Mo gas core plate and the first circuit layer, and the dielectric layer is shaped to: open, and some of the circuit openings are further subjected to laser drilling to form the electrical connection pads. Forming a metal layer cover layer, the surface, the line openings, and the openings; and removing... = dielectric: the metal layer of the surface, the line openings and the:: holes The metal layer respectively forms a second, a sweat hole' to complete the - line build-up structure, the plurality of conductive conductive blind connections to the electrical connection ports, and the second line blind holes are electrically connected to the conductive blind holes. _ ^ and the second circuit layer and the surface of the hole and the dielectric layer in the above-mentioned circuit board structure manufacturing method = conductive blind hole, which can be formed by solid metal layer openings are formed by exposure and development , ^The lines of the dielectric layer are opened, These are formed by exposing the first-line ^ laser drilling method, and the above-mentioned manufacturing method forms a second connection: an electrical connection pad. It is smaller than the depth of the openings. . "Distance of the two-line opening, preferably 9 200901846 [Embodiment] The following describes the transmission of the present invention by a specific embodiment. Those skilled in the art can understand the other aspects of the present invention from the content disclosed in the present specification. Advantages and effects. The present invention can also be implemented or applied by other different specific embodiments. The details of the description of the present invention are also different from the viewpoints and applications of the present invention. Modifications and changes. %仃σ In the embodiments of the present invention, the drawings are simplified. The illustration shows only the components related to the present invention, which show: (1) the actual implementation, the number of components in actual implementation. The shape ratio is a design of choice, and its component layout may be more complicated. Embodiment 1 'After a month, Figs. 2a to 2h' are schematic views showing the structure of a circuit board of the present embodiment. As shown in Fig. 2a, a core board 2 is provided first, and the upper and lower surfaces of the core board 2 have a first circuit layer 21' and the first circuit layer 21 has a plurality of electrical connection pads 211. The core board used in this embodiment may be a double-layer or multi-layer circuit board having a first circuit layer, and the core board 2 is a core, and the first circuit layer 21 is formed on the core layer 2 The substrate 2 is formed on the upper and lower surfaces of the substrate 201, and the plurality of conductive vias 2〇2 are formed in the substrate 201, and the first circuit layer 21 is electrically connected to the two sides of the substrate 201, wherein the conductive vias 202 are Filled with a resin 22. Then, as shown in FIG. 2b, a dielectric layer 23 is formed to completely cover the core board 2 and the first circuit layer η by printing, spin coating, or pressing. The dielectric layer 23 belongs to a photosensitive material having a high electrical resistivity and may be added with at least no filler filler. For filling, or 5 Ο 10 15 C, 20 , and then referring to Figure 2e, In the manner of material development, a plurality of line openings 231 are formed on the dielectric layer 23. Then, as shown in FIG. 2d, through the laser laser drilling method, the portion of the opening 231 is further subjected to laser drilling to form a plurality of openings 232 to the explicit circuit (four)-circuit layer 21. Electrically connecting the pad 211. Then, through a method of extinguishing or electroless plating, a conductive layer is formed to cover the plurality of lines 231, the openings 232, and the first circuit layer for the electrical properties. Connecting the pad 2 I 1 , and then referring to FIG. 2 e , the current is conducted through the conductive layer 26 and formed by the electric money—the metal layer 24 covers the surface of the dielectric layer 23 , the inside of the line opening 23 , and the openings 232 . The metal layer 24 is selected from the group consisting of lead, tin, silver, copper, gold, grade, recorded, zinc, nickel, wrong, town, indium, inscription, sho, and recorded metals and alloys thereof. Then, referring to FIG. 2f, the metal layer 24 and the conductive layer 26 having a height higher than the surface 23a of the dielectric layer are removed by brushing or etching, and the second=two opening 231 and the The metal layer 24 in the opening 232 is formed with a second circuit layer 242 and a plurality of conductive blind holes 241, respectively. The electric blind hole 241 is electrically connected to the electrical connection pads 211 and the second circuit layer 242 ′ of the first circuit layer 2 , and the second circuit layer 242 and the conductive blind holes The surface of the 241 is flush with the surface of the dielectric layer 23, so that the layered structure can be completed through the above steps. 11 200901846 In addition, the metal layer 24 formed by the above-mentioned electric ore can be completely filled with openings according to FIG. 2f. 232, the conductive blind holes 24 thus formed form a solid metal column. Thus, the steps of the above FIG. 2b to FIG. 2f can be repeated as needed to produce a multi-layered multi-layer structure. Thus, the circuit board structure of the present invention is completed, as shown in FIG. 2g, comprising: a core board 2 having a surface having a first circuit layer, the first circuit layer 21 having a plurality of electrical connection pads 2n; A build-up layer structure covers the surface of the core board 20. The at least one build-up structure comprises a dielectric layer 23, a second circuit layer 242, and a plurality of conductive blind vias 1, wherein the conductive vias 2 41 Electrically connecting to the electrical connection pads 2 and the second circuit layer 242, and the surface of the second circuit layer 242 and the conductive blind holes are flush with the surface of the dielectric layer 23 . As shown in FIG. 2g, an insulating protective layer π is formed on the conductive vias 241 of the build-up structure, the conductive vias 241, and the second trace layer 242. Referring to FIG. 2h, the insulation protection is further provided. On the layer 27, a plurality of openings r 7 are opened to expose a portion of the conductive vias 241 and a portion of the second via layer 242' of the outermost layer build-up structure as electrical connection pads. In this embodiment, the insulating protective layer 27 is a solder resist layer. 1 and, as shown in the circuit board structure shown in the figure, the two sides are respectively a crystallizing side 25a and a ball-balling side 25b', wherein the crystal-plating side 25a utilizes a partial conductive blind hole 241 and a part of the second wiring layer 242. As an electrical connection pad for forming solder bumps and connecting semiconductor wafers. 2i is a top view of the figure & dashed line/marked, and as can be seen from FIG. 2i, the periphery of the plated side turns blind hole 241 has no hole ring i52a as disclosed in the prior art diagram lf & lg. 12 200901846 The surface of the force is the ball-side side 25b, which is used to brush the circuit board. The ball-handling side 25b also uses a part of the conductive blind hole ==!; =4Γ as the electrical connection f#, but the side of the tin ball Far board plaque finds 彳丨 to facilitate planting 2 solder balls, and is connected to the printed circuit board. The conductive blind hole 24 of the ball-side side 25b is green as the conductive blind hole 241 of the crystal-plating side 25a. @介,. 242, but there is no hole ring in the circumference of the 24th hole of the isoelectric hole. In addition, an opening 271, such as an electrical blind via, and a portion of the second wiring layer 242 are formed on the insulating protective layer 27 as a defined form of electrical interconnect = electrical connection pad as follows. Ίο 15 20 is as shown in FIG. 2h, the insulating fault-preserving layer η of the opening 271 is partially covered (Panlally c. The peripheral portion of the electrical connection 叫 is called the crystallized side... and covered (4) Ball (4) The peripheral portion of the electrical connection pad' This electrical connection pad is a solder-proof layer-defined electrical connection pad ((6) plus _k defined pad, SMD pad); the second is as shown in Figure 3, the circuit board is placed The insulating protective layer 27 of the crystal side 25a is not covered with (4)c. The electrical connection pad of the crystallizing side 25a is called, and the insulating protective layer 27 is not in contact with the electrical connecting pad. (4) Non-solderproof layer defined type of electric material (4) surface _5 () 1 plus coffee to define pad, NSMD pad), the insulating layer 27 of the circuit board side 25b with the opening 271 is partially covered The peripheral portion of the electrical connection pads; the second is the insulating protective layer 27 having the openings 271 of the circuit board side 25a as shown in FIG. 4, the electrical connection pads are not covered, and the insulating protection layer is 27 is also not in contact with the electrical connection pad, and the insulating protection layer 2 of the circuit board side 25b of the circuit board 25b is also divided into 13 200901846 holes 2 7 1 , and The edge protection layer 27 also=the circumferences of the electrical connection pads are not in contact with the remote electrical connection pads; and the insulation protection layer 27 of the crystal plate side 2 (7) of the circuit board is as shown in FIG. The peripheral portion of the board ball-forming side 25b of the Y-f-joint is connected to the outer surface of the Y-f # # + + + + + 开 开 开 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 The shell is also not in contact with the electrical connection pad. 4 layer 27 ίο Therefore, the circuit board structure of the present invention and the manufacturing method thereof can effectively control the shape of the line θ 3 because the surface of the circuit layer 242 and the conductive blind holes (4) are both flush and flat. The table door* is small and can form the lifeline of the thin circuit, which can improve the electrical function of the circuit board. 屯 The above embodiments are only for the convenience of explanation and the scope of claims has been claimed. The above is the above-mentioned embodiment. Not limited to 15 [Simplified description of the drawings] Figure 1 a to 1 f is a schematic flow chart of a conventional semi-additive method. Figure 1 g is a diagram of Figure 1 f dotted line A 2a to 2h are structural diagrams of a circuit board according to an embodiment of the present invention. FIG. 2 is a schematic view of a schematic diagram of a circuit board structure according to the embodiment of the present invention. Figure 4 is a schematic cross-sectional view showing the structure of a circuit board according to an embodiment of the present invention. Figure 5 is a cross-sectional view showing the structure of a circuit board according to an embodiment of the present invention.
【主要元件符號說明】 10 核心板 11 線路層 12 樹脂 131 開孔 152 導電盲孔 16 導電層 20 核心板 202 導電通孔 211 電性連接墊 23 介電層 232 開孔 242 第二線路層 25a 置晶側 23a 介電層表面 271 開孔 101 導電通孔 1 11 電性連接墊 13 介電層 14 阻層 151 線路層 152a 孔環 201 基板 21 第一線路層 22 樹脂 231 線路開口 24 金屬層 241 導電盲孔 27 絕緣保護層 25b 植球側 26 導電層 15[Main component symbol description] 10 core board 11 circuit layer 12 resin 131 opening 152 conductive blind hole 16 conductive layer 20 core plate 202 conductive via 211 electrical connection pad 23 dielectric layer 232 opening 242 second circuit layer 25a Crystal Side 23a Dielectric Layer Surface 271 Opening 101 Conductive Through Hole 1 11 Electrical Connection Pad 13 Dielectric Layer 14 Resistive Layer 151 Circuit Layer 152a Bore Ring 201 Substrate 21 First Circuit Layer 22 Resin 231 Line Opening 24 Metal Layer 241 Conductive Blind hole 27 insulating protective layer 25b ball-balling side 26 conductive layer 15