TW200900945A - Data transfer device, clock switching circuit and clock switching method - Google Patents

Abstract

A data transfer device includes: a first serial-parallel converter converting a first serial signal in a first system to a first parallel signal and recovering a first clock; a second serial-parallel converter converting a second serial signal in a second system to a second parallel signal and recovering a second clock; a data switch selecting one of the parallel signals, according to a switch control signal indicating a selected system; a clock switch selecting one of the clocks, according to the control signal; a parallel-serial converter converting the selected parallel signal to a serial output signal; a phase comparator outputting a phase difference between the selected clock and one of not-selected clocks; and a phase shifter shifting the selected clock's phase according to the phase difference when the selected system is changed. A clock switching circuit includes the clock switch, the phase comparator and the phase shifter.

Description

200900945 IX. INSTRUCTIONS: Incorporation of References This application is based on March 2, 2007. η 丹山出^ [Technical Field of the Invention] The present invention relates to a data transmission device, a clock switching circuit, and a pulse method. A method for selecting a reverse-switching circuit and a pulse-to-mode switching method from a plurality of serial data signals. , Τ 的 日 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 In the case of =, for example, the audio-visual sound data, in the communication, switching between the transmission systems is not provided, for example, in Japanese Patent Application Laid-Open No. _151568. In the television (TV) broadcasting station equipment, the device transmits the digital image signal in (4) money mode. The serial signal is transmitted to the other-broadcast station. SMPTE259M (Standard-Definition (SD)), and SMPTE292M (High-Defmiticm (HD)) are used as broadcast stations. ) fresh. There are two transmission systems, the primary system and the backup system, between the broadcast station towel and the Guangshi to transmit serial video signals. ♦ When using the main system to transmit an error, the secret of the transmission is from the main system: to the backup secret. In the case of _, it must be implemented without _ interference, while maintaining the same transmission quality as the main system. The 200900945 t field shows a block diagram of the configuration of the data transfer device in the related art. Cautiously, it has an uninterrupted switching function. °B rDstt column parallel converter (S/P) 110 receives the serial data (DS1) of the first system. In the data reproduction from DS1 / 夕Jbe shake and = flat _ (then. More Λ夂 s " p 1 (PCLK!) 平行 parallel day ^ ^ ^ _ material (DS2) regeneration parallel (four) (10)) and select one. By a predetermined switch (not shown) ϋ f is emitted, and the output data is output as a parallel resource DP0 is output to the parallel-serial converter (P/S) 130 〇, ^i=tmcsu) 150 Receive PCLK1 And PCLK2, select i^K2 as PCLK0 'and output pclk〇 to p/s 13〇. Select parallel to select the parallel clock as the parallel data of DP0. For example, delete 'Lan choose pclki as pclkq. As shown in Fig. 6, 〇L s clock switch 151 and phase lock loop (hase 1〇ck d iLL; ^1; 1 ^#PCLK1 ^ as clock PCLKO. PLL I54 outputs PCLKO to P/S 13〇. The P/S 130 performs parallel-to-serial, '=production, serial data (DS〇) and outputs the generated data for the received DP〇 and pCLK〇. The transmission system in use When it is inside, it is switched to the ancestral lamp for Dp〇. For example, when parallel data DP1 has been selected as the Dp〇 for transmission, and the parallel data for DPG/Bus for DPG is switched to DP2. Therefore, the _ switch 151 k 仃 脉 P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Off phase difference. When switching the serial data in the system, the phase of PLL ^ ' PCLK〇 changes to follow the phase of the parallel clock. However, if the phase difference between the data in the system is Γϊίί In practice, the PCLK hops until the PLL 154 has completed following the phase change. 200900945 The amount is in the itf1 standard The timing jitter and the alignment jitter can be accommodated in the case of the sequence jump. The specified beat frequency must be equal to or greater than the change rate of the reference value. smpte_ toerva丨, single Μ, _在. (四) The card is also known as 'the fixed time jump is equal to or less than the f (when the frequency is 27_ZBLD. Leverly minus the key 0 fine movement. Fine, difficult to meet 2004^=^^32. in the Japanese Patent Application Publication No. , the frequency division $, the 3 phase than the car thief, the integration circuit, the voltage control and the removal of the two parameters; the letter 5 of the 2 2! ^ 7 of the selection circuit, the difference removal circuit contains the signal ^ detect two circuit. The phase exists. The phase difference exists in the detection circuit ώ 作 =ί, ί There is a phase difference. The delay circuit delays the two reference signals among them. Between the tigers 【 No [invention content] Less on the target to provide - data transmission The device, which can reduce the other exemplary object of the present invention, is to increase the value of the method. The transmitting device comprises: the first 蛊f H column signal is the first money Converting the first system to recover the first time in the first system. When _ ding 45 tiger, and the second serial signal from the first string system is the second system 2 parallel converter, the conversion The two serial signals recover the second system 1, the difference; and the second parallel signal, and from the second H data _, according to the selected 200900945 control letter selection - parallel signal and the second parallel extension i - select Clock = phase =; turn ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ , select the clock according to the movement, according to the phase clock switching circuit when the green changes the timing, the circuit includes the pulse signal of the μ temple switch, selects the first clock and the first two:: 屎 table: the phase of the switching control of the system (four) The clock phase shifter selected by the time pulse is used to indicate the choice of the system by the switching control signal, and the method is based on the switching of the selection system. One is selected as the clock; when the output is 0^t, the miscellaneous change is selected according to the system change. The pulse phase. 'Phase Difference' and Moves [Embodiment] Hereinafter, an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. 1. The first exemplary embodiment of the present invention provides a data transfer diagram of an exemplary embodiment of the invention. 1 is a diagram showing a data transmission configuration of the first exemplary embodiment of the present invention. The data transfer device i includes a function of switching the serial data interrupted by a plurality of serials and transmitting the data. , & unknown, 'data transfer device i contains the first serial_parallel conversion S/P) 10, the second serial, parallel converter (the first ι / ρ) 20, and parallel y: - (10) 30. In addition, the material conveying device i includes the first data memory t== two data memory 42, the first-writer address generator (--WAG) 43-^, the younger one writes 200900945, the more advanced step-by-step ΙΤ包: 资 = address generator _) 45. The first-number of serial data. For example, (called the second system = string ^ terminal (for example, the -_ ^ ^ line to the standby system. When the data transfer device J is used for zt, the system is for the system, and the DS2 is for the serial format device, the system of the μ j(10) and the DS2 transmitted in series with the DS1 and the DS2 is Shift, clock recovery circuit. In the 10th implementation of the (10) magic recovery, the flat conversion is performed to output parallel data (=, out to the second data memory 42. PCLK2 output to the second wag 44 and 41 Γ = ΐ Ρ Ρ ? ? ? Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Κΐ Outputting the read address to the nurturing memory 41 and the second data memory 42. From the first data memory & read 200900945 ίίίΐϊΐ! (DP1,), and The second data memory 42 reads the flat r μ (DP2 ) output to #料_46. The stomach of the tenth data gift = off 46^ D 46 selects the foot or off 46; IPMnr + Ai output "" The choice is as parallel sage 0 (DP0). 粗粗Μ ^ Dpr^ «sc ^ is the flat squama. PQL pulse is the choice of the thousand whistling her, and outputs the phase shifting clock to (10) and = The action is selected as the phase of PCLK0 for 'and _. Therefore, cs=! 50 performs switching without changing the phase adjustment system to first U 52 ^ in the following manner. Off 5! Select parallel clock (pcLK B) first, pc [SU 52 = fine off 51 is selected as the selection parallel clock (pcLK a) 0 bis: pulse: === will, the resulting phase difference amount, ten, iU 疋 knife changed to the unselected parallel time Pulse (pclk-b). After the weapon, 'still the money will change. The foot, the beat will not happen in pcLK〇.", to describe the operation of the CSU 50. Suppose you choose PCLK1 for ..., the PSU 52 gets As the phase difference between PCLK2 and PCLK0 f of PCLK-B. When sc is input from the switching controller 6〇 to csu 5〇, re=P〇^乍 is PCLK_A. At this time, the ship 52 is based on PCLK2 The phase difference between the two adjusts the phase of PCLK2. Because phase 10 200900945 mouth ==== object Chan p (four), rainbow = ° step and to:: redemption, output terminal _) lose _ to pass =. _ (reward. Although wrong When the system in use occurs, the switching of the switching system (4) money (SC) to the capital_off 461 = TTG output is used to switch 46 嫌 _ and 'the data switch 46 and CS (10) operate like the last clock. At the time of switching, as described above, when switching the system, the first phase adjusts the phase of the clock according to the clock selected by the switching and the f-object transmission tolerance. Therefore, the phase between the metrics does not produce a jump in the output signal. When there is a self-switching system, Figure 2 shows the minimum necessary components of the dispensing device of the data transfer device 2. In the data of the 堇^^, the second data memory 42 is =:=====. The accommodating device can be installed in the first s/pi 〇t, the inner DP1 and the DP2, and the data transfer device 2 does not need to be in the middle. In this case, the device also has a clock switch that can be equal to the number of systems, the material switch and the write, and the number of the burners is also set to the port memory. 2. The second exemplary embodiment is equal to the number of H deaths. The foot of the present invention will not be described with reference to the drawings. Data Transfer of the Second Embodiment 200900945 U = Sexual configuration. Fig. 3 is a block diagram showing the capital according to the second exemplary embodiment. The data transfer device 3 includes a second parallel t L tf second serial 'parallel converter (second s/p) 2G, 4· string 1J conversion (P/S) 30, timely pulse switching unit (csu) 5〇 . Shi Ding Er Fan (CSU) 5〇 contains clock switch 5 I I 1 early (PSC) 56 ° ^ , 0 ^ field comparison state 55, and phase shift controller (PSC) 56 groups ^

(prrr, Αλ * / 疋 疋 PCLK2 as one of the parallel clocks clock A ^ sTml SU ^ tl ^ 51A ' 51B ' 51C ' is indicated by the x mark. The switch 51A disk door ^ is shown by the clock switch 51 shown in FIG. The system works in conjunction with each other. ^ Root switch / ^, and switch and switch 51D select PCLK2 as PCLK1 - A, and select PCLK1 as ρ "τ γ d 士 select PCLK2 as PCLK-A, open switch 51B and Switch 51D; 8 s' off switch 51 eight and switch 51C, and

51〇ί=/ί?=Γ:, an open sentence, 51BI, therefore ^彳^ have and examples. -t PLL 54. The PCLK_A received from the k-pulse switch 51 to 12 200900945 The PLL 54 receives the pCLK A output from the clock switch 51 through the phase shifter 53. The PLL 54 generates pcLK 藉 by using the received PCLK_A as a reference signal, and rotates PCLK0 to P/S 30, and the phase comparator 55. The phase difference between PCLK0 and PCLK_B on the phase comparator 55 side. Specifically, the phase comparator 55 receives the pcLK 输出 output from the PLL 54 and the PCLK-B output from the clock switch 51. The phase comparator 55 detects the phase difference between the two parallel clocks (PCLK0 and PCLK_B) received. A phase difference signal (SP) equivalent to the phase difference detected by the phase comparator % is output to pSc56. " PSf 56 receives sp from phase comparator 55. The psc % is output to the phase shifter 53 according to the sc. When the input sc and the clock is switched, the 'SP' is input from the PSC S6 to the phase shifter 53. At this time, the phase shifter 53 shifts the phase of PCLK_A in the following manner. In the state towel that does not switch the selection (PCLK-A), phase (4) 53 does not move the phase, and outputs PCLK_A with the existing phase. When the system is switched, the SC is input to the CSU5G. Clock switch 51 responds to SC and selects parallel clock PCLK1 or parallel clock PCLK2 as PCLK_A ° back

The SP is input to the phase shifter 53 in response to SC. The phase shifter 53 controls the phase of PCLK_A f according to sp. Specifically, the phase shifter 53 only shifts the phase of PCLK_A by S; the phase difference amount indicated. The phase adjusted pCLK_A is input to ριχ54. The operation of the phase shifter 53 will be clearly described. Assume that pCLK1 is selected as the PCLK_A' phase comparator 55 to obtain a _ difference between pCLK〇 and PCLK_B (i.e., PCLK2) which is output to p/s 3〇. Here, when inputting sc, select =LK2 as PCLK-A. At this time, the phase shifter 53 adjusts the phase difference between pCLK 〇 and LK 2 in accordance with sp. Therefore, when the parallel clock is switched from pCLKi to PCLK2, the phase of PCLK0 does not change. In the data transfer device 3 shown in Fig. 3, the clock switch 51 selects pcLKi as PCLK0. Therefore, the clock switch 51 outputs pCLK2 to the phase comparator. ί ΐΪΐ % _ PCLKi) and the phase difference between PCLK2. When the error is in the first, 'charged' clock switch 51 selects PCLK2 as pCLK〇. At the same time, the phase shifter 53 receives the SP and shifts only the phase difference amount measured by the phase of PCLK2. 13 200900945 ΡΓΤ = upper phase comparator 55 detects the phase difference signal of the phase difference between the selected and output parallel clocks [CLK0, and the other parallel clocks that have not been selected, and shifts just in the system. The amount of this phase difference. As a result, the input /PLSLP54t^3士f shifts the phase of the belly. In other words, the phase difference in the parallel clock money can be achieved. Therefore, the slashing and dragging is not caused by the *phase difference: / When changing green, the financial quality can be reduced by the signal: ===== Data and transmission, = refueling conveyor can reduce the number of transmissions in the transmission system Figure 5 shows the clock switching in Figure 3, the jitter generated when the jump has been reduced in the two systems ^^ The clock switch. That is, it can be repaired. The clock is extended to the number of more than two systems to select a clock-synchronous device, wherein the H-th or 疋-clock switching unit can be used to not transmit J. The clock in the second complex system 忒The data shown in the PCLK^^i system is transmitted (PCLK, PCLK2, select a clock signal (for example, only the system is selected. The other two clocks are transmitted ^ [like the above two phase differences ,=========================================================================================================================== The phase of PCLK A. Therefore, the choice of the clock is set even if the clock is cut: it does not change. Incidentally, according to the application 14 200900945, although the invention has been explicitly shown and described with reference to the exemplary embodiments, The present invention is not limited to the embodiments, and various modifications of the form and details of the present invention can be made without departing from the spirit and scope of the invention as defined by the appended claims. Further, even if the patent application scope is patented During the correction process is being requested, but the inventors to be still comprise all of the requested scope of the invention uniformly.] [Brief Description of the drawings

</ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; FIG. 4 is a circuit diagram showing a configuration of the present invention; the old configuration of the circuit is shown in the figure. FIG. 4 is a circuit diagram showing a configuration of the present invention. FIG. 6 is a block diagram showing the configuration of a data transfer device of the prior art. [Main component symbol description] 1 : Data transfer device 2. Data transfer device

3. Data transmission and aggregation 10: First S/P

20: second S/P 30 : P/S 41 : first data memory 15 200900945 42 : second data memory

43: First WAG

44: Second WAG

45 : RAG 46 : Data switch

50 : CSU 51 : Clock switch

52 : PSU 53 : Phase shifter

54 : PLL 55 : Phase Comparator

56 : PSC

60: switching controller 110: first S/P 120: second S/P 130: P/S

150 : CSU

151: Clock switch 154 : PLL

Claims (1)

200900945 X. Patent application scope ·· 1. A data transmission device, comprising: loading one of the first systems in the first system of H-Ba, recovering 2 lines of signals in the first system, and from the first-series The signal recovers the signal of the second system in the second system and selects the second flat H2 from the second serial signal: - the switching control signal of the selection system; σ 1 and 5 One of the parallel signals is selected as a parallel to the first surface of the 'one clock and pulse device' __ parallel recorded as having the selection: = ί and output the selected clock and the unselected clock One of them - phase.斤 的 δ 相位 相位 phase shift and move the selection clock 2. As claimed in the patent scope! The data of the item is used to f move the phase so that the serial wheel sends a signal to the phase shifting device. 3. The data transmission I ^ of the first application of the patent scope is fixed. The clock for the selection of the clock after the phase shift and the system change, and in the system 4. For example, the third item; 2; i phase: : Quantity. When the clock switching device is in the system, the phase shifting device causes the second clock to have the same magnitude of the phase difference between the second clock and the second clock. 1 moving with the first-clock and the 17 200900945 = face-to-hand switching device in the system &amp; and the pulse _ phase shifting device causes the first clock to select the second phase when the second clock phase difference Moving with the i-th pulse, 5, as claimed in the i-th item of the patent scope, - the third serial-parallel conversion device 2 includes: the signal is in the third system - the third series The third clock in the system recovers from the third serial signal, and the switching device according to the switching control number, the second parallel signal, and the selected first parallel signal The switching device selects the first-clock according to the switching, the second clock, and the third clock, and the data is transmitted according to the data of the fifth item of the application. Clock. Right after the system changes the timing, select the second clock before the second S (four) sequence:: :ίϊ: then the phase shift device roots the difference and the second phase is the phase sequence of the remote selection clock The phase-phase shifts the __ phase of the first-clock according to the phase shifting root difference. Selecting a "phase-phase 7"-type clock switching circuit, comprising: a clock switching device, according to a selection of a second-clock and a second clock-switching control domain, setting the selection, For outputting the selected clock and the sinusoidal __phase difference 供 and the 供 变 , , , , , , , , , , , , , , , SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL SSL Change =. The root of the money changes the material of the time _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ So that the phase of one of the selected clocks is 10. As in the ninth application of the patent scope / if the clock switching device is in the middle of the line, the phase shifting device makes the _.r The phase shift between the second clock and the second pulse has been selected before, and the phase shifting device is in the JJ pulse of the system, and the phase shifting device causes the first phase to be Then, the phase difference between the second clock and the second phase has been selected to be the same phase shift and the time of the first clock and the seventh item of the 11H patent range = the clock switching device is switched according to the switching H path. Wherein the second clock, and a third clock 1 towel,: D娆, select the first clock, the 12. If the scope of the patent application = item: = the cut if the system is changed after the timing is selected, the road According to the third clock and when the system changes, the phase shifts the μ bit difference and shifts the phase of the third clock, and then the phase between the selected clocks is at 5 After the system changes the timing, the selected one is moved according to the second clock and when the system changes, the second pulse 'position shifts the root position difference One phase of the second clock, and a phase between the 3 Hz selection clocks, after the system changes the timing, according to the first clock and the system is changed, the tree device root position difference is moved. The first clock selects the phase-phase switching method between the selected veins, including: selecting the step 'er'_synchronous-cutting axis signal, selecting one of 19, 200900945, the second and second clocks as one When the selection is off, the output step, the round-off of the selection of the clock, the second phase of the phase difference, and the stop of the wind, and the selection of the time when the wife is moved - the step between the move When the age changes according to the S Hai system, when the sun is abundance/k is changed, the phase is one of the glands. The phase is fixed, which is the movement of the _ bit to make the one of the selected clocks of the rounded i5n special range of the clock switching method of the thirteenth item, wherein the pulsating step makes the phase shift _ = = and _ The money change time __clock switching method, wherein the phase shift of one of the second clocks is the same as the phase difference of the moving step, and the human guardian pulse and the 5th second clock If the phase of the first-clock is moved to the clock before the system changes timing, then the moving step has the same magnitude. , / between the first pulse and the second clock 17. If two = the data ==, the method, where the second clock, and a third clock ^ _,: 1 乜唬, select the first Clock, the 18th. As claimed in the patent scope, and output the selection clock. If, after the system changes the timing, according to the third clock and the system clock, the moving step is a difference between the selected clocks of the third clock and the phase of the third clock. If the phase changes the timing in the system: the pendulum is based on the second clock and the system is a clock, the moving step is a bit difference and the selection before the second clock is moved. a phase between the clocks, and 20 200900945. If the first clock is selected after the system changes the timing, the moving step is the selection clock before the timing is changed according to the first clock and the system. One phase difference between the ones of the first clock is shifted. XI. Schema: 21