TW200849557A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device includes a field effect transistor including a semiconductor substrate having a channel-forming region, an insulating film formed on the semiconductor substrate, a gate electrode trench formed in the insulating film, a gate insulating film formed at the bottom of the gate electrode trench, a gate electrode formed by filling the gate electrode trench with a layer on the gate insulating film, offset spacers composed of silicon oxide or boron-containing silicon nitride and formed as a portion of the insulating film to constitute the sidewall of the gate electrode trench, sidewall spacers formed as a portion of the insulating film on both sides of the offset spacers on the side away from the gate electrode, and source-drain regions having an extension region and formed in the semiconductor substrate and below at least the offset spacers and the sidewall spacers.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device including a field effect transistor and a method of fabricating the same. The present invention includes the subject matter of the copending patent application JP 2007-108953, filed on Apr. 18, 2007, the disclosure of which is incorporated herein by reference. [Prior Art] In the method of manufacturing a semiconductor device, a damascene program is generally used as a method of forming a line. In the damascene process, for example, a trench of a gate electrode is formed in an insulating film on a substrate, and a conductive material is deposited to fill the trench of the gate electrode, and then the trench is removed from the outside by CMP (Chemical Mechanical Polishing), leaving A conductive material in the trench of the gate electrode to form a line. A MOSFET (a MOS field effect transistor; hereinafter referred to as a "M0S transistor") which is a basic element of a semiconductor device is increasingly miniaturized due to an increase in the miniaturization progress and the integration of the semiconductor I. Therefore, the gate length and the thickness of the idler insulating film are reduced in association with the ratio. The NMOS insulating film used as the gate insulating film causes a large leak after 32-nm generation, and thus it is difficult to use the SiO insulating film as the gate insulating film. 8. Therefore, there has been studied a method of using a high dielectric constant film (so-called high-k film) whose solid film thickness can be increased as a gate insulating film material. Since the high-k film generally has low heat resistance, it is desired to form a fine film after the diffusion heat treatment of the source-汲# region in which the high-temperature treatment is performed:: 128076.doc 200849557 Membrane. As a method of allowing such steps, the inlaid closed-pole program of the gate electrode of the M〇s transistor is formed by using an inlay process. Japanese Unexamined Patent Publication No. 2005-303256 discloses a method of forming a M〇s transistor having a source-drain region in which an extension region is provided using a damascene interpole procedure. In this method, for example, a dummy gate insulating film and a dummy interlayer electrode are formed on an active region of the semiconductor substrate, and an offset composed of nitrided rays is formed on both sides of the dummy insulating film on the substrate. a spacer, and the semiconductor substrate implants ions using the dummy gate electrode and the offset spacers as a mask forming an extended region. Forming sidewall spacers on both sides of the offset spacers on the substrate, and using the dummy gate electrodes, the offset spacers, and the sidewall spacers as source-drain electrodes A mask of the area to implant ions. As described above, the source-drain regions each having the extended region are formed. Next, an interlayer insulating film is formed on the entire surface to cover the dummy interlayer electrode, and the top surface is polished until the surface of the dummy gate electrode is exposed, and then the dummy gate electrode is insulated from the dummy gate by etching. The membrane forms a trench for the gate electrode. Next, a gate insulating germanium is formed at the bottom of the trench of the gate electrode, and then a gate electrode is formed on the gate insulating film to fill the gate electrode. / As mentioned above, the MOS electro-crystal system is formed using a damascene procedure. 128076.doc 200849557 When forming a trench for a gate electrode, the dummy gate insulating layer is preferably removed by a wet residual to avoid damage to the substrate. Therefore, in the unexamined patent application publication No. 2005-303256, the offset spacers are composed of tantalum nitride so as to prevent the offset spacers from being removed by wet etching. Although the offset spacers can be prevented from being removed by wet etching, the parasitic capacitance between the gate electrode and the source-drain region is increased because of nitrogen.

The dielectric constant of ruthenium is higher than that of ruthenium oxide. This causes the characteristics of the M〇s transistor to deteriorate. SUMMARY OF THE INVENTION One problem to be solved is that when a MOS transistor is formed using a damascene process, it is difficult to form a transistor having high characteristics. A semiconductor device according to an embodiment of the present invention includes a field-effect solar cell comprising: a semiconductor substrate having a channel formation region, an insulating film formed on the semiconductor substrate; and a gate An electrode trench formed in the insulating film; a gate insulating film formed at a bottom of the gate electrode trench; and a gate electrode formed on the gate insulating film: filling the gate electrode trench An offset spacer consisting of yttrium oxide or yttrium nitride and formed as part of the insulating film to form a sidewall of the gate electrode trench; a sidewall spacer on a side facing away from the gate electrode Forming a portion of the insulating film on both sides of the offset spacer, and a source-drain region each having an extended region and offset spacers in the semiconductor substrate and at least 1 hai Formed under the side I spacers.乂128076.doc 200849557 The semiconductor device is included in the v 电极 形成 或 或 或 或 或 或 或 或 或 或 ; ; ; ; ; ; ; ; ; ; ; 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体== __ and the gate electrode of the gate electrode electrode. For the insulation:: a portion of the crucible formed by the offset-cut spacer formed by the mouse to form the sidewall of the closed-electrode trench, and the 哕== spacer is on the side facing away from the gate electrode A portion of the insulating film is formed on the side of the offset interval μ. Further, the source-drain regions of each of the extension regions are formed in the body: and are formed under at least the offset spacers and the sidewall spacers. The % effect cell system was configured as described above. According to another embodiment of the present invention, a semiconductor device includes an effect transistor including: a semiconductor substrate having a channel formation region or an insulating barrier formed on the semiconductor substrate; a closed electrode trench == is formed in the insulating film; a pole insulating film is formed at the bottom of the idle electrode trench; a gate electrode is shielded on the gate insulating film to fill the gate An interpolar electrode trench; an offset spacer, each of which comprises a nitride film or a nitride nitride film and a oxidized oxide film laminated on the side of the idle electrode and formed as a part of the insulating film Forming a sidewall of the gate electrode trench; a sidewall spacer formed as a portion of the insulating film on both sides of the offset spacer on a side facing away from the gate electrode; and a source-drain region 'Eachly having an extension region and being on the semiconductor substrate; and forming at least the offset spacers below the sidewall spacers. 128076.doc 200849557 :Heil: a conductor device includes an insulating film formed on a semiconductor substrate having the channel forming region, a gate electrode trench formed in the insulating film, and a bottom insulating film formed between the bottom of the gate electrode trench And forming a gate electrode on the dummy insulating film to fill the gate electrode trench. At the same time, each of the insulating films including the nitrogen enthalpy or the (iv) fossil film and the oxidized stone film formed on the side of the idle electrode is formed as one side of the insulating film to constitute the sidewall of the gate electrode trench. And the side of the sidewall spacer facing away from the idler electrode is formed as a part of the insulating film on both sides of the offset spacer. Further, the source 1 pole regions each having an extension region are formed in the body substrate and formed under at least the offset spacers and the sidewall spacers. / The field effect crystal system is configured as described above. According to still another aspect of the present invention, a method of fabricating a semiconductor device of the present invention includes the steps of: forming a dummy gate insulating film and a dummy gate electrode on a semiconductor substrate having a channel formation region - forming a two-shift spacer formed by oxygen-cutting or nitriding-containing nitride on both sides of the idle electrode, such that (4) an offset spacer and the gate electrode form an extended region in the semiconductor substrate Equal offset spacers: sidewall spacers are formed on both sides, and the sidewall spacers, the spacers and the gate electrode material are masked in the semiconductor substrate to form: a pole-polar region An insulating film covers the dummy interpole electrode, and the insulating film is removed until the dummy gate is exposed from the top of the insulating pad, and the dummy gate electrode and the dummy gate insulating film are removed to form a gate 128076. .doc 200849557 A pole electrode trench, forming a gate insulation at the bottom of the idle electrode trench, forming a conductive layer on the gate insulating barrier to fill the closed electrode trench f' and from the gate electrode trench outer The conductive layer is removed sideways to form a % effect transistor. The step of removing at least the dummy gate insulating film includes a button process which includes a first process of treating the surface of the exposed surface of the insulating layer with a gas containing ammonia and Dunhua hydrogen, and decomposing and evaporating at the first A second treatment to treat the product formed by t. In the manufacturing method of the conductor device, a dummy gate insulating and a dummy gate electrode are formed on the semiconductor substrate having a channel forming region, and the both sides of the dummy gate electrode are formed by the oxide oxide or An offset spacer comprising a shiban nitride, and the use of the offset spacer and the closed electrode as an extension region of the semiconductor substrate. Then, the sidewall spacers are on both sides of the offset spacers, and the source-drain regions use the sidewall spacers, the offset spacers, and the gate electrodes as a mask Formed in a semiconductor substrate. Next, an insulating film is formed to cover the dummy closed electrode, the insulating film is removed until the dummy gate electrode is exposed from the top of the insulating film, and the dummy gate electrode and the dummy gate insulating film are removed. A gate electrode trench is formed. Next, a m-edge (four) is formed at the bottom of the gate (four) (four) channel, and a conductive layer is formed on the gate insulating film to fill the gate electrode trench, and the conductive layer is removed from the outer side of the gate electrode trench. In this way, a potent transistor is formed. The step of removing at least the dummy gate insulating film includes a first-order process, and the 128076.doc -10- 200849557 includes a first process of treating the exposed surface of the insulating layer with an etching gas containing ammonia and hydrogen fluoride, and decomposing and evaporating A second treatment of the product formed in the first treatment. According to still another embodiment of the present invention, a method of fabricating a semiconductor device includes the steps of: forming a dummy gate insulating film and a dummy gate electrode on a semiconductor substrate having a channel formation region, sequentially laminating a nitriding film and a cerium oxide film or a cerium-containing cerium film for opening the spacers on both sides of the dummy gate electrode, using the offset spacers and the gate The electrode is formed as a mask in the semiconductor substrate to form an extended region, and the side spacers are formed on the offset spacers, and the sidewall spacers, the offset spacers, and the gate electrode are used. Forming an insulating film to cover the dummy gate electrode as a mask in the semiconductor substrate, and removing the insulating film until the dummy gate electrode is exposed from the top of the insulating film And forming a gate insulating film between the dummy pad electrode and the dummy gate insulating film to form a gate electrode trench, and removing a nitrogen cut film constituting the offset electrode, forming a pole insulating film at a bottom of the gate electrode trench; A conductive layer is formed on the gate insulating film to fill the (four) pole electrode trench, and the conductive layer is removed from the outside of the gate electrode trench to form a field effect transistor. In a method of fabricating a semiconductor device, ^^^ 々*^ τ forms a dummy gate w-bit, a germanium edge and a dummy gate electrode, and a germanium gate on the semiconductor substrate having a channel formation region. The film and the oxidized one can be disposed on both sides of the dummy interpole electrode to form an offset spacer on one m side, and the offset spacer and the gate electrode humming mask An extended region is formed in the semiconductor substrate 128076.doc 200849557. Then, sidewall spacers are formed on both sides of the offset spacers, and the source-drain regions use the sidewall spacers, the offset spacers and the interpolar electrodes as a mask Formed in a semiconductor substrate. Next, an insulating film is formed to cover the dummy gate electrode, and the insulating film is removed until the dummy gate electrode is exposed from the top of the insulating film, and the dummy gate electrode and the dummy gate insulating film are removed to form A gate electrode trench' removes the tantalum nitride film that constitutes the offset spacers. r

f V, a gate insulating film is formed at the bottom of the gate electrode trench, and a conductive layer is formed on the gate insulating film to fill the gate electrode trench and move laterally from the gate electrode trench In addition to the conductive layer. In this way, a potent transistor is formed. According to still another embodiment of the present invention, a method of fabricating a semiconductor device includes a step of forming a dummy gate insulating film and a dummy gate electrode on a semiconductor substrate having a channel forming region. Forming a nitride film or a nitrogen-containing slit film and an oxygen (tetra) film to form offset spacers on both sides of the dummy gate electrode, using the offset spacers and the gate Forming, by the electrode, an extension region in the semiconductor substrate: forming sidewall spacers on both sides of the offset spacers, using the sidewall spacers, the offset spacers, and the gate electrode Forming a source/drain region _ in the semiconductor substrate, forming an insulating film to cover the dummy gate electrode, and removing the insulating film until the dummy (tetra) electrode is exposed from the insulating film portion Except for the dummy gate electrode riding the dummy interlayer insulating film to form a gate electrode trench while leaving the composition: 128076.doc 200849557 At least a part of the tantalum nitride film or the boron-containing tantalum nitride film of the spacer spacer The gate is very private Portion forming a gate insulating film formed on the conductive layer private gate insulating film to fill the trench gate electrode, and removing the electrically conductive layer from the outside of the gate electrode trench to form a field effect transistor. In the manufacturing method of the semi-body device, a dummy gate insulating film and a dummy gate electrode are formed on the semiconductor substrate having the channel forming region, and a tantalum nitride film or a boron-containing tantalum nitride layer is laminated. a film and a hafnium oxide film so as to be able to form an offset interval on both sides of the dummy 35 gate electrode, and using an offset spacer such as a barrier or the gate electrode as a mask to form in the semiconductor substrate Extended area. Forming sidewall spacers on both sides of the offset spacers, and the source-drain regions use the sidewall spacers, the offset spacers, and the gate electrode as a mask Formed in a semiconductor substrate. Next, an insulating film is formed to cover the dummy gate electrode, the insulating film is removed until the dummy gate electrode is exposed from the top of the insulating film, and the dummy gate electrode and the dummy gate insulating film are removed. Forming a gate electrode trench material leaves at least a portion of the offset spacer < the nitride nitride film or the tantalum nitride containing film. Then, a gate insulating film is formed on the bottom of the gate electrode trench, and a conductive layer is formed on the gate insulating film to fill the gate electrode trench and is removed from the outside of the gate electrode trench The conductive layer. In this way, a potent transistor is formed. A semiconductor device according to an embodiment of the present invention has a structure in which an oxygen having a dielectric constant lower than a dielectric constant of 128,076.doc -13 - 200849557, which is an offset spacer composed of tantalum nitride, is used. Cut M and leave the oxidized stone film in the process (4). Therefore, high characteristics may be maintained because the MOS transistor is formed by a damascene interpole program. According to the present invention, a method of fabricating a semiconductor device includes forming a brain crystal using the damascene gate process, each of which includes an offset spacer composed of a nitride nitride Dielectric: a low-density dielectric constant of the oxidized stone. Since the ritual stone is not removed during the process, the characteristics of the MOS transistor may be enhanced. [Embodiment] Hereinafter, a specific embodiment and a method of manufacturing the same according to the present invention will be described with reference to the drawings. Conductor First Embodiment A schematic fef view of a semiconductor device according to a first embodiment is shown. For example, the element isolation insulating film u is formed by the STI (Shallow Trench Isolation) method for the area on the Shih-Semiconductor substrate 10 (which has a channel formation region). Further, on the semiconductor substrate (4), a film (side spacer) 17a and an interlayer insulating film insulating film I are formed. For example, a pole electrode trench A is formed in the insulating film!, and an oxidized film or an oxidized film having a dielectric constant which is more than a dielectric constant of oxygen is formed at the bottom of the electrode trench A (ie, 2 In addition, by using polycrystalline: charging the idle electrode trench A to form a closed electrode 128076.doc 14 200849557 22 in addition to the pole insulation. In addition, as shown in Figure 1, go When the gate electrode 22 is composed of polycrystalline germanium, a refractory metal telluride layer 23 composed of NiSi is formed on the surface of the gate electrode 2, which is composed of NiSi. When the gate electrode 22 is composed of a metal material, for example, it is selected from

, a metal of the group consisting of Putian grasshopper, button, titanium, molybdenum, niobium, nickel and platinum, and a female alloy.] > Man A 蜀 3 5 metal alloy or a compound of the metal.

For example, the offset spacers 15 are formed as part of the insulating film so as to be in contact with the semiconductor substrate 1G and constitute the side walls of the gate electrode trenches. The offset spacers 15 are composed of yttrium oxide. The tantalum nitride film (side spacer) 17a is formed as a part of the insulating film z so as to contact the semiconductor substrate i. The tantalum nitride films 7a are formed on both sides of the offset spacers 15 facing away from the gate electrode 22. The interlayer insulating film 20 is composed of, for example, cerium oxide. In addition, source-drain regions 18 each having an extended region 16 are formed on at least the offset spacers 5 and the tantalum nitride films (side spacers) 17a and on the semiconductor substrate 1A. . A refractory metal telluride layer 19 composed of NiSi is also formed on the surface layer of each of the source-drain regions 丨8. A field effect crystal system is configured as described above.

Further, an insulating film 24 composed of ruthenium oxide is formed to cover the insulating film I and the gate electrode 22 (or the refractory metal germanide layer 23). Further, an opening CH is provided to pass through the upper insulating film 24 and the interlayer insulating film 2 to reach the refractory metal lithium layer 19 of each of the source-drain regions 18 and the gate The refractory metal lithium layer 23 of the electrode 22. The mother of these openings CH 128076.doc 15 200849557 is filled with a plug 25 composed of a conductive material. Further, a line 26 composed of a conductive material is formed on the upper insulating spacer 24 so as to be connectable to each of the plugs 25. The offset spacers 15 are used to form a mask layer of the extended regions. Accordingly, depending on the conditions of the activation heat treatment, the positions of the offset spacers 15 facing away from the gate electrode 22 are used to substantially position the channel side ends of the extension regions 16. Accordingly, the width of each of the offset spacers 15 is related to the contour of the extended regions, and it is possible that the contour determines the oxide oxide film for the offset spacers 丨5. At the same time, the tantalum nitride films (side spacers) 17a are used as a mask layer for forming the source-drain regions. Therefore, depending on the conditions of the activation heat treatment, the end positions of the tantalum nitride film (side spacers) 17a facing away from the gate electrode 22 serve to substantially position the channel side ends of the extension regions 18. The semiconductor device according to this embodiment has a structure in which a hafnium oxide film having a dielectric constant lower than a dielectric constant of an offset spacer composed of a nitride nitride is used and the hafnium oxide film is retained after the process. Therefore, high characteristics may be maintained because the MOS transistor is formed by the damascene gate process. The material of the offset spacers 15 is not limited to hafnium oxide, but a hafnium boron nitride (SiBN) film may be used. The SiBN臈 has a dielectric constant lower than that of the tantalum nitride film, and the dielectric constant is about 5 at the same time when the B/N ratio is 2, and the SiBN film has higher acid resistance than the oxidized film. It is resistant to acid, so the amount of money is small. Therefore, even if a SiBN film is used, it is possible to maintain high crystal characteristics as in the above specific embodiment. Next, a manufacturing method of the semiconductor through-hole 128076.doc-16-200849557 according to this embodiment will be described with reference to the drawings. First, as shown in Fig. 2A, an element isolation insulating film 11 is formed by an STI (Shallow Trench Isolation) method to isolate an active region in a germanium semiconductor substrate 1 having a channel formation region. Next, a thickness of about 4 nm is deposited on the entire surface by, for example, thermal oxidation, and the polycrystalline germanium is deposited by a CVD (Chemical Vapor Deposition) method to a thickness of 150 to 200 nm, and further nitrided.矽达咒至丨(9) The thickness of r nm. Then, in addition to the gate formation region, photolithography is performed to form an oxide oxide dummy film 12 on the gate electrode formation region in the active region of the semiconductor substrate 10, and a polycrystalline stone dummy electrode _ Hardened layer 14 of tantalum nitride. Next, as shown in FIG. 2A, a thickness of 8 to 14 nm of yttrium oxide is deposited on the entire surface by a CVD method using, for example, TE〇s (tetraethyl orthosilicate) as a raw material gas, and then returned. The etching is performed on both sides of the dummy gate electrode u and contacting the semiconductor substrate to form the offset spacers U. L material, as shown in FIG. 3A, the active region uses the offset spacers 15 and the hard mask layer 14 (or the dummy gate electrode 13) as a mask to implant impurity ions in the semiconductor A pocket layer (halo; not shown) and an extended region 16 are formed in the substrate 10. Next, as shown in Fig. 3B, the thickness of the nitride is deposited on the entire surface by, for example, a plasma CVD method, and the thickness of the oxygen is further deposited. Then, the worm is performed on the entire surface to form the sidewall spacers 17' on both sides of the spacer spacer 15 and contacting the semiconductor substrate 10, each of which includes the nitrogen cut film 17a and the oxygen cut film. (7). 128076.doc 200849557 Each of the sidewall spacers 17 can be a three-layer laminated insulating film such as a hafnium oxide/tantalum nitride film/yttria film. Next, as shown in FIG. 4A, the active area uses, for example, the sidewall spacers 17, the offset spacers 15 and the hard mask layer 14 (or the dummy (2) gate electrode 13) as a mask. The cover is implanted with impurity ions to form the source-drain region 丨8 in the semiconductor substrate 10. For example, boron is implanted at a dose of 15 to 35 x 1 〇 15/cm 2 at an energy of 2 to 4 keV. As described above, the source-drain regions each having the extended region 16 are formed in the semiconductor substrate 10 and formed under at least the offset spacers 15 and the side wall spacers 17. Then, RTA (rapid thermal annealing, 1 〇 5 〇 dC) heat treatment was performed to activate the impurities. Next, as shown in FIG. 4B, after pretreatment with diluted hydrofluoric acid (DHF), a refractory metal such as nickel, cobalt or platinum is deposited by sputtering on the entire surface to a thickness of 8 nm, and then The surface of each of the source-drain regions (i.e., the contact between the refractory metal and the crucible) is deuterated to form the refractory metal fragment layer 19. Then, the unreacted refractory metal is removed. In the DHF process, the hafnium oxide film 17b constituting the sidewall spacers 17 is removed. Hereinafter, the tantalum nitride film na may be referred to as a "side spacer". Next, as shown in FIG. 5A, an oxidized stone is deposited on the entire surface by a CVD method to cover (for example, the hard mask layer 14). (or the dummy gate electrode Η) to form the interlayer insulating film 2〇. Then, the top surface is polished by the CMp (Chemical Mechanical Polishing) method until the hard mask layer 14 is exposed (or the dummy interlayer 128076.doc 200849557) The surface of the electrode 13) is formed as described above, and the film including the interlayer insulating film 2, the offset spacer 15 and the nitride film (side spacer) i7a are referred to as "insulating film I,". As shown in FIG. 5B, the dummy electrode 13 (and the hard mask layer 14) is removed by, for example, etching under predetermined conditions. The etching is performed under such conditions so that the dummy gate insulating film of the yttrium oxide is exhibited. Sufficient selection ratio. Next, as shown in Fig. 6A, the dummy gate insulating film 12 is removed by, for example, a moth as described in detail below. Etching for removing the dummy gate insulating film 12 Including the treatment of the dummy gate with ammonia and hydrogen fluoride a first treatment of the exposed surface of the membrane 12 and a second treatment of decomposing and vaporizing the product formed by the first treatment. The first treatment is described. The dummy gate is chemically etched with a mixed gas containing NH3, HF and Ar The surface of the insulating film 12. Specifically, a wafer (substrate 1 〇) is transferred to the chemical remnant chamber of the residual device and placed on the wafer platform, and then a gas environment is formed to form the dummy gate The surface of the insulating film 12 is formed with a complex. The gas environment is as follows: NH3/HF/Ar-50/50/80 seem, pressure=6·7 Pa, platform temperature=3〇

The chemical reaction in °C in a mixed gas environment is as follows. When HF/NHVAr is supplied as a vapor phase to the chemical etching chamber, the gas system is adsorbed on the exposed ruthenium oxide surface of the dummy gate insulating film 12 according to Lancôme 128076.doc -19-200849557 (Langmuir) adsorption. At the same time, the following chemical reactions were carried out. Si02+4HF-^SiF4+2H20 (1)

SiF4+2NH3 + 2HF->(NH4)2SiF6 (7) ie, the reaction with HF produces S1F4 and HA, and then (NH4)2SiF6 is formed on the surface of the oxidized oxide layer by the chemical reaction of nh3, HF and SiF4. The layer of the complex. The reaction is controlled by the gas adsorption control of several molecular layers according to the Lancome adsorption system and is self-contained when the coverage of the adsorbed gas molecules is saturated. Therefore, (the production of the NHdjiF6 complex is also saturated. In the subsequent second treatment, the wafer covering the (NH4)2SiF6 complex is transferred to the heating chamber and placed on the heating platform, and then the heater heating is started. The (NH^SiF6 complex is decomposed into SiF4 or the like and evaporated. The heating conditions are as follows: platform temperature = 200\:, pressure = 26.7? & The reaction system is represented by the following reaction. The dummy gate of yttrium oxide The (NH4)2SiF6 complex deposited on the surface of the insulating film 12 is decomposed into SiF4, NH3 and HF by heating the substrate to 2 Torr, and then evaporated, and then consumed as the gas passes through the dry pump. Do it.

(NH4)2SiF6~^SiF4+2NH3+HF due to. Hai Chemical I used a surface reaction, which has the advantage of having no difference in density in a pattern. For example, the etching amount of the dummy gate insulating film 12 of the crucible is controlled to a desired value by determining the gas supply time. In the process of removing the dummy insulating film, the surface of the semiconductor substrate is exposed to the surface of the semiconductor substrate, but the substrate is not damaged. As described above, the gate electrode trench A is formed in the insulating film 1. In the above etching, as described below, the etching time is selected such that the amount of the oxygen cut film formed by the thermal oxidation method can be controlled to be greater than the oxidation loss formed by the CVD method using =TEOS as a raw material. Hey. Therefore, the offset spacers 15 are only partially removed until the dummy gate insulating film is completely removed. Although the offset spacers 系5 are slightly retracted, it may be avoided to widen the gate electrode trenches. Because of &, the effectiveness of the transistor is preserved in a certain degree of privacy. For example, when the thickness of the offset spacers 15 is 8 nm, and the thickness of the dummy gate insulating film 12 is 4 nm, etching is performed under the above etching conditions until the king removes the dummy σ and the gate insulating film. It takes about 45 seconds until 12. During this time, each of the offset spacers 15 is removed by 3·9 nm, leaving an offset spacer of approximately 4.1 nm in thickness. Next, as shown in FIG. 6B, for example, a ruthenium oxynitride is deposited by a thermal oxidation method to cover the bottom of the gate electrode trench A. The ruthenium oxide or aluminum oxide is deposited by an ALD method to cover the gate electrode trench A. The inner surface forms a gate insulating film 21 composed of a high-k film. After the formation of the film, a step is performed at a treatment temperature lower than 5 ° C because the film has low heat resistance. Then, for example, a conductive material such as a metal material (for example, tantalum, titanium nitride, tantalum or tungsten) or polysilicon is deposited on the gate insulating film 21 by sputtering or CVD to cover the gate electrode trench A. The inner wall. Then, the conductive material deposited on the outside of the gate electrode trench A is removed by polishing to form the gate electrode 22. Further, when the gate electrode 2 2 is formed using polycrystalline stone, a refractory metal telluride layer 23 of NiSi can be formed on the interpole electrode 22. In a subsequent step, the upper insulating film 24 is formed by depositing an oxide stone by, for example, a CVD method to cover the 5 Å insulating film 1 and the gate electrode 2 2 (or the refractory metal slick 2 2). Then, the special opening CH is formed to pass through the upper insulating film μ and the intervening insulating film 20 to reach the refractory metal lithium layer 19 of the source-drain region 18 and the gate electrode 22 Refractory metal lithium layer 23. Each of the resulting openings CH is filled with a plug 25 composed of a conductive material such as a metal, and a wiring 26 formed of a conductive material is formed on the upper insulating film 24 so as to be connectable to the plugs 25. . As described above, a semiconductor device similar to the semiconductor device having the structure shown in the drawing is manufactured. Using the offset spacers 15 as a mask to form one of the extended regions, and thus depending on the conditions of the activation heat treatment, the position of the offset spacers away from the end of the interpole electrode 22 is substantially used to position the spacer The channel side end of the extension region 16 is equal. At the same time, the tantalum nitride film (side spacer) 17a is also used as a material for forming the source region of the source, and thus the tantalum nitride film (side spacer) 17a is deviated depending on the conditions of the activation heat treatment. The end position of the gate electrode 22 is substantially used to locate the end of the f source/drain region. A method of fabricating a semiconductor device according to this embodiment of the present invention includes forming an offset between 128076.doc -22-200849557 b when the transistor is formed using the damascene gate program, each of which includes a ratio of nitridation一 The composition of the offset spacer is a dielectric constant of a low dielectric constant of the ruthenium oxide film. Since the A yttrium oxide film is not removed in the process, it is possible to increase the characteristics of the M 〇 s transistor. Second Embodiment A semiconductor device according to a second embodiment of the present invention is substantially the same as a specific embodiment. A method of fabricating a semiconductor device according to this embodiment will be described with reference to the drawings. ★ First, as shown in Fig. 7A, the element isolation insulating film 11 is formed by the STI method to isolate the active region in the stellite semiconductor substrate 10 having a channel formation region. Next, the thickness of the oxidized stone is deposited on the entire surface by a thermal oxidation method. In addition, the CVD method deposits polycrystalline stone with nitrite and except for the deposition of the dummy gate insulating film i 2, which is composed of polycrystalline stone eve, and the gate electrode 13 is hard composed of nitrite Photolithography is performed outside the region where the mask layer is formed. Next, a thickness of SiO 2 · 28 nm is deposited on the entire surface by a plasma CVD method or an ALD (Atomic Layer Deposition) method, and Further, the thickness of the oxidized materials 8 to 14 (10) is deposited by a CVD method. Then, a reciprocating portion is formed on both sides of the dummy gate, and the semiconductor substrate 10 is contacted to form the same. The spacers 5, the long sentences * The milk sets each include a tantalum film 15a and a tantalum oxide film 15b. The subsequent steps are continued until an interlayer insulating film 20 is formed as shown in Fig. 7B. It is the same as the first embodiment. Next, as shown in FIG. 8 , the dummy gate electrode 13 is removed by, for example, etching shift 128076.doc -23- 200849557 under the predetermined condition of Dingbey. (with the hard mask 14). Perform etching under these conditions to make the yttrium oxide The gate insulating film exhibits a sufficient selection ratio. Next, as shown in FIG. 8B, the etching is removed by, for example, the same etching as that used in the first embodiment for removing the dummy gate insulating film 12. The gate insulating film 12 is dummy.

As described above, the gate electrode trench A is formed in the insulating film. In the above etching, as described below, the etching rate of tantalum nitride is sufficiently lower than the etching rate of the hafnium oxide film formed by the thermal oxidation method. For example, when each of the offset spacers |5 includes a vaporization having a thickness of 〇.28: a laminate of a film and a ruthenium oxide film having a thickness of 8 nm, until the dummy electrode insulating film 12 is completely etched During the 45 second period, the nitrogen cut film of each of the offset spacers 15 is removed by G. 28 nm (ie, the tantalum nitride film is completely removed). Because, Shi, @. ^ } U The yttrium oxide film 15b having a twist of 8 nm is as follows: the total remaining T ′ thus avoids widening the gate electrode trench. At this time, the iridium oxide 15 constitutes the individual offset spacer 15. As described above, in this embodiment, the nitriding is previously deposited as the trench side portion of the offset spacers, the thickness of which is such that the nitride is removed during the time of removing the dummy 1-pole insulation. Evening film. Spear, Hai Xu. Further, the processing time required for the closed electrode and the insulating film is changed in a wide range, and the thickness of the vaporized tantalum film 15a can be appropriately changed. This can be applied to the process of removing the dummy interlayer insulation. In this case, IV is required to remove the oxygen enthalpy of the four sides formed by the thermal oxidation method. " This day, the defensive division removes 0.86 _ in the DHF treatment. Thus, for example, when each of the offset spacers 15 comprises a layer of tantalum nitride film having a thickness of 〇% nm and a yttrium oxide film having a thickness of 8 nm, until completely During the period of 1 〇 3 seconds required to etch the dummy electrode insulating film 12, the tantalum nitride film 15a of each of the offset spacers 15 is removed by 0.86 nm (ie, the nitridation is completely removed). Diaphragm). Therefore, the yttrium oxide film 15b having a thickness of 8 is completely left as it is.

Then, in the first embodiment, for example, the gate insulating film 21, the gate electrode 22 and the refractory metal germanide layer 23 are formed in the gate electrode trench A, and the upper insulating film 24 is formed. The openings CH are formed and filled with the plugs, and the upper layer % is formed. As described above, a semiconductor device similar to the semiconductor device according to this embodiment is fabricated. A method of fabricating a semiconductor device according to this embodiment of the present invention includes forming offset spacers each including an offset interval composed of tantalum nitride when forming a M?s transistor using the damascene gate process A niobium monoxide film having a dielectric constant with a low dielectric constant. The characteristics of the transistor may be enhanced because the 4 oxidized film is not removed during the process. k & using the yttrium oxide film i5b as a film constituting the offset spacers ,5, however, the offset spacers 15 are not limited thereto, and a boron-containing nitridation may be used outside the yttrium oxide film. Silicon (SiBN) film. The SiBN film has a dielectric constant lower than that of the tantalum nitride film, and has a dielectric constant of about 5 in the case where the B/N ratio is 2. At the same time, the SiBN film has higher resistance to acid than the ruthenium oxide film, and thus the etching amount is small. Therefore, even if SiBN + is used, it is still salty as the above specific embodiment retains high crystal characteristics. 128076.doc -25- 200849557 THIRD EMBODIMENT FIG. 9 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention. Each of the offset spacers 15 is used as the main layer except for the layered layer of the tantalum nitride film 15a and the oxygen film 15b. Α 虱 矽 , , 、 , , , , , , , , 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体 具体The example is the same. The method of the semiconductor device according to this embodiment is shown in FIG. χ < Hundreds first as shown in Fig. 10A, performing the same steps as the second concrete embodiment until the dummy gate electrode 13 is removed (with the hard mask layer (4). ...' For example, controlling the thickness of the nitrogen cut film 15a constituting each of the offset spacers 15 such that the tantalum nitride film is removed by the same process as in the first embodiment or the processing of the first embodiment (4) of the dummy gate insulating film 12 is completely removed during the day when the dummy gate insulating film 12 is removed. As described above, the gate electrode trench A is formed in the insulating film. Expenditure, as described below, the nitrogen cut (four) is lower than the etch rate of the hafnium oxide film formed by the thermal oxidation process. For example, when each of the offset spacers 15 includes a thickness of 〇·5〇 Each of the offset spacers 15 is laminated for a period of 45 seconds required until the dummy electrode insulating film 丨2 is completely etched by the tantalum nitride film of nm and the yttrium oxide film having a thickness of 8 nm. The tantalum nitride film 15a removes germanium, 28 nm, that is, the tantalum nitride film 15a is thinned to a thickness of 0.22 nm. However, it is not completely removed. Therefore, the 'Oxide film with a thickness of 8 nm is completely left as it is, so as to avoid widening the gate electrode trench by 128076.doc -26- 200849557. As mentioned above, In the embodiment, the nitride film is previously formed as the "ditch side portion of the "fourth spacer" whose thickness is greater than the thickness which is removed during the time required to remove the dummy gate insulating film. The isoelectric film having a high dielectric constant is preferably as thin as possible and sufficiently thinner than the oxidized oxide film constituting the individual offset spacer. When the dummy gate insulating film is removed, The processing time is changed, and the thickness of the tantalum nitride film 15a can be appropriately changed. This treatment can be applied to the dhf process of removing the dummy gate insulating film. In this case, the removal is formed by a thermal oxidation method. The 4 nm yttrium oxide film takes 103 seconds, and this time the tantalum nitride system removes 〇86 nm in the DHF process. Thus, for example, when each of the offset spacers 15 includes a thickness of 1.3 Lamination of a tantalum nitride film of nm and a yttrium oxide film having a thickness of 8 nm During the time period of 1 〇 3 seconds required until the dummy electrode insulating film 1 2 is completely left, the tantalum nitride film 1 5 a of each of the offset spacers 1 is removed by 0.86 nm. (ie, the tantalum nitride film leaves a thickness of 〇·44 nm.) Therefore, the yttrium oxide film 15b having a thickness of 8 nm is completely left as it is. Then, as in the first embodiment, for example, The gate insulating film 21, the gate electrode 22 and the refractory metal lithium layer 23 are formed in the gate electrode trench A, and the upper insulating film 24 is formed, and the openings are filled with the plugs 25. CH, and forming the upper layer wiring 26. As described above, a semiconductor device similar to the semiconductor device according to this embodiment is fabricated. A method of fabricating a semiconductor device according to this embodiment of the present invention is disclosed in a package of 128076.doc -27-200849557, which is formed by using the gate-embedded gate program to form an eraser crystal. Dielectric of the nitrided offset spacer: a low number of electrical constants of the hafnium oxide film. Since the oxime film is not removed in the process, the characteristics of the MOS transistor may be increased. Fourth Embodiment Fig. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. This embodiment is essentially the same as the first embodiment except that the offset spacers are included! 5, the nitride film (the sidewall spacers and the insulation between the layers: 20 'insulation film work further thinning (that is, the height of a gate electrode π becomes lower). Other components and the first implementation The same is true. The method of the semiconductor device according to this embodiment will be described. The first step, as shown in FIG. 12A, is performed and steps until the surface is formed on the surface of each of the source-drain regions. The refractory metal telluride layer 19 is connected. As shown in FIG. 12B, for example, an oxygen cut is deposited on the entire surface by a CVD method to cover the hard mask layer 14 (or the dummy gate electrode). The interlayer insulating film 2 is polished and the top surface is polished by a cMp (a) mechanical polishing method until the surface of the hard mask (4) (or the dummy gate electrode 13) is exposed. 151?: The film including the interlayer insulating film 20, the offset spacer /, the ruthenium (side spacer) 17a is referred to as an insulating film Γ. "In this embodiment, polishing is further performed to make the insulating film 溥0, 128076.doc 28-200849557. For example, when the hard mask 14 is present, the insulating film i can be polished until the hard mask layer 14 is completely polished. To expose the surface of the dummy electrode (4) or to polish it to the middle height of the dummy gate electrode 13. No hard mask 14 appears in the field, by polishing to the middle of the dummy electrode 13 The insulating layer I is removed from the south. ',, and; as in the first embodiment, the dummy interpole electrode 13 (and the hard mask layer 14) and the dummy gate insulating film 12 are removed. Forming the gate electrode trench 8 in the insulating film I, forming the gate insulating germanium 21, the gate electrode 22 and the refractory metal lithiation layer in the inter-electrode trench A, forming the upper insulating layer The film 24 is formed and filled with the openings CH' and formed with the upper layer line 26. As described above, a semiconductor device similar to the semiconductor device according to this embodiment is fabricated. According to this embodiment of the present invention An example of a method of manufacturing a semiconductor device includes When the M〇s transistor is formed by the σ 肷 肷 gate process, the offset spacers each include one having a lower electric dielectric number than the offset spacer composed of tantalum nitride. Oxidized oxide film. Since the ruthenium film is not removed/oxidized in the process, it is possible to enhance the characteristics of the M〇s transistor. In this embodiment, as in the second embodiment, nitrogen may be formed previously. The fossil film serves as a trench side portion of the offset spacers, the thickness of which causes the tantalum nitride to be moved during the time required to remove the dummy gate insulating film. "Fifth Embodiment FIG. 13 A cross-sectional view of a semiconductor device according to a fifth embodiment. 128076.doc -29- 200849557 This embodiment is essentially the same as the embodiment of the production, except for the specific embodiment of the fourth embodiment, except that the package, .. B0 includes an offset spacer 1 5. The tantalum nitride film (side spacer) 17 a and a gate are provided. The insulating film I of one of the 曰], 邑, 邑 膜 20 is thinned (ie, the height of a closed electrode 22 is lowered) Bu is low again. The other components are the same as the third embodiment. The manufacturing method of the feasting device according to this embodiment is the same as that of the third embodiment, except that 4 is shown to further thin the insulating film I as in the fourth embodiment. . In the method of fabricating a semiconductor device according to this embodiment of the present invention, when the MOS electro-crystal system is formed using the damascene interpole program, offset spacers are formed, each of which includes an offset from the composition of the nitride A niobium monoxide film having a dielectric constant with a low dielectric constant of the spacer. Since the yttrium oxide film is not removed in the process, the characteristics of the MOS transistor may be enhanced. DETAILED DESCRIPTION OF THE INVENTION Figures 14 through 17 are cross-sectional views of a semiconductor device in accordance with an embodiment of the present invention. These specific embodiments are substantially the same as the first to fifth embodiments except that an interlayer insulating film 30 composed of a so-called high material such as cerium oxide or aluminum oxide is formed by an ALD method to cover a gate. The gate electrode a of the electrode electrode trench A is filled with a metal material such as tantalum or tungsten to form a gate electrode 3 on the gate insulating film 3 . 14, 15, 16 and 17 correspond to the first and second specific embodiments, the third embodiment, the fourth embodiment and the fifth embodiment, respectively. In the method of fabricating a semiconductor device according to an embodiment of the present invention, 128076.doc -30 - 200849557, when the MOS electro-crystal system is formed using the damascene gate program, offset spacers are formed, each of which includes Oxidized oxide film having a lower dielectric constant than the dielectric constant of the offset spacer composed of tantalum nitride. Since the yttrium oxide film is not removed during the process, the characteristics of the transistor may be enhanced. Examples of the method for removing the dummy (four) insulating film from the first embodiment, inspecting (4) the oxidized stone film formed by the thermal oxidation method, and (9) using the TEOS as the raw material by the CVD method to form the oxygen cutting film And (4) the relationship between the (four) time discs of the nitrogen cut film formed by the plasma CVD method. The results are shown in Fig. 18. Figure 18 shows that at a quotation time of more than 40 seconds, (4) by thermal oxidation method =: oxidized seconds film sizing amount becomes greater than (n) use _ as the original 1 fine by electricity: CVD method formed by the oxygen cut film surname Engraving. Therefore, although the films (a) and (b) are respectively used as the material of the dummy gate insulating film and the offset P, the dummy can be removed.屣° and the gate electrode, leaving the offset interval. In addition, (c) the etching amount of the tantalum nitride film is less than (a) the reduction by the thermal oxidation method (4) (10) U, 胄 and (4) respectively act as dummy gates' except for the dummy gate electrode, leaving a bias: the material of the spacer spacer' can move the offset spacer. The invention is not limited to the above description. For example, the gate is insulated from the gate embodiment. The material is not limited to the above. 128076.doc 200849557 does not necessarily form the refractory metal telluride layer. For example, 'in the first embodiment, a boron-containing nitridation film can be used to oxidize the ruthenium film, and in the second embodiment, a nitride layer and a delamination-free film can be used instead of the nitrogen film. The laminate with the oxygen cut film, and the laminate of the pure cut film of the third filler film (4), not the nitride film and the oxygen cut. The Wei-containing film has a dielectric constant lower than that of the bismuth telluride film, and the dielectric constant is about 5 in the case where the b/n ratio is 2. At the same time, Can Lai has an acidity that is more acidic than that of the oxidized stone, so the surname is ^^^彳. Therefore, a thinner offset spacer can be formed using a tantalum nitride film as compared to the offset spacers. Those skilled in the art should understand that all modifications, combinations, and reorganizations are subject to the requirements of the stipulations and other factors, as long as they are attached to the scope of the patent application or Within the scope of its equivalent content. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a specific embodiment of the present invention; FIG. 2 shows a schematic diagram of a semiconductor device according to a specific embodiment of the present invention; A cross-sectional view of a method of manufacturing a semiconductor device according to a first embodiment of the present invention; and FIGS. 3A and 3B are diagrams showing a method of manufacturing a semiconductor device according to a specific embodiment of the present invention. FIG. 4 is a cross-sectional view showing a step of manufacturing a semiconductor device according to the first embodiment of the present invention; FIG. 5 and FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6A and (4) each show a first embodiment of the present invention in accordance with a first embodiment of the present invention. FIG. 7A and FIG. 7B are cross-sectional views showing steps of a method of manufacturing a semiconductor device according to a second embodiment of the present invention; FIGS. 8A and 8B are each a cross-sectional view; Showing the second item according to the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 9 is a schematic cross-sectional view showing a semiconductor device according to a third embodiment of the present invention; FIG. 1 is a view showing a 根据A and a system according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a specific embodiment of the present invention; FIG. 12B is a cross-sectional view showing a step of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention; and FIG. 1 is a semiconductor device according to the present invention. Figure 14 is a schematic cross-sectional view of a semiconductor device according to the present invention, and a semiconductor device according to the specific embodiment; Figure 15 is a seventh embodiment of the present invention according to the present invention A schematic cross-sectional view of a semiconductor device according to a specific embodiment;

Figure 16 is a schematic cross-sectional view of a semiconductor device according to a specific embodiment of the first embodiment of the present invention; Figure 17 is a diagram showing a semiconductor device according to a ninth embodiment of the present invention. 128076.doc -33 - 200849557 A cross-sectional view; and Figure 18 shows a graph of the etch rate measured in an example of the present invention. [Main component symbol description] / 10 矽 Semiconductor substrate 11 Component isolation insulating film 12 dummy gate insulating film / dummy electrode insulating film 13 dummy gate electrode 14 hard mask layer 15 offset spacer 15a tantalum nitride film 15b yttrium oxide Film 16 extension region 17 sidewall spacer 17a tantalum nitride film (side spacer) 17b oxide S film 18 source - > and pole region 19 refractory metal telluride layer 20 interlayer insulating film 21 gate insulating film 22 gate Electrode 23 refractory metal telluride layer 24 upper insulating film 25 plug 128076.doc -34· 200849557

26 30 31 A CH Upper line Gate insulating film Gate electrode Gate electrode trench Opening Insulation film / 128076.doc -35-

Claims (1)

200849557 X. Patent Application Range: 1. A semiconductor device comprising a field effect transistor, comprising: a semiconductor substrate having a channel formation region; an insulating film formed on the semiconductor substrate; and a gate electrode trench Forming in the insulating film; a gate insulating film formed at the bottom of the gate electrode trench; - a gate electrode formed on the gate insulating film to fill the gate electrode trench; a spacer consisting of oxidized stone or shi shi shi shi shi and formed as part of a ruthenium insulating film to form a sidewall of the gate electrode trench; a side surface on the side facing away from the gate electrode Forming a portion of the insulating film on both sides of the offset spacers; and source-drain regions each having an extension region and in the semiconductor substrate and at least the offset spacers Formed under the sidewall spacers. 2. The semiconductor device of claim 1, wherein the gate electrode side ends of the offset spacers are substantially used to locate the channel side ends of the extension regions. 3. The semiconductor device of claim 1, wherein the idle electrode is a metal selected from the group consisting of tungsten, tantalum, niobium, titanium, platinum, rhodium, nickel, and iridium. One compound composition. 4. A semiconductor device comprising a field effect transistor, comprising: - a semiconductor substrate having a channel formation region; and a 'bar film formed on the semiconductor substrate; a gate electrode trench Formed in the insulating film; 128076.doc 200849557 a gate insulating film-gate electrode, an electrode trench; formed at the bottom of the gate electrode trench; formed on the gate insulating pad to fill The gate offset spacers each comprise a layer of germanium nitrided from the gate electrode side: a film: a germane film and a oxidized stone film, and formed into the insulating layer a sidewall of the gate electrode trench; a sidewall spacer forming a portion of the insulating film on both sides of the offset spacer on a side facing away from the gate electrode; and a source and a pole region Each with an extension And in the semiconductor base and formed under at least the offset spacers and the sidewall spacers. ^ 5. The gate channel side is the semiconductor device of claim 4, the offset spacers in # The electrode side end is substantially for locating the end of the extended region. The semiconductor device of claim 4, wherein the tantalum nitride film or the each of the offset spacers The bismuth-containing lanthanum nitride film is thinner than the yttrium oxide film. The semiconductor device of claim 4, wherein the gate electrode is composed of a material selected from the group consisting of tungsten, tungsten, molybdenum, niobium, nickel, and platinum. a group consisting of a metal, an alloy of the metal, or a compound of the metal. 8. A method of fabricating a semiconductor device, comprising the steps of: forming a dummy on a semiconductor substrate having a channel formation region a pole insulating film and a dummy gate electrode; forming offset spacers composed of yttrium oxide or boron-containing nitridation 128076.doc 200849557 on both sides of the dummy gate electrode; using the offset spacers The gate electrode serves as a mask Forming an extension region in the semiconductor substrate; forming sidewall spacers on both sides of the offset spacers; using the sidewall spacers, the offset spacers, and the interpole electrodes as masks in the semiconductor substrate Forming a source-drain region; forming an insulating film to cover the dummy gate electrode; removing the insulating film until the dummy gate electrode is exposed from the top of the insulating film; the dummy gate electrode and the dummy gate are shown a gate insulating film to form a gate electrode trench; a gate insulating film is formed on the bottom of the gate electrode trench; a conductive layer is formed on the gate insulating film to fill the closed electrode channel; The conductive layer is removed from the outer side of the open electrode trench to form a transistor; wherein the step of removing at least the dummy gate insulating film includes a moment: the germanium includes an etching gas containing ammonia and hydrogen fluoride to treat the anode The second process of processing and decomposing and evaporating at 9. 10. The product formed by the first treatment. The method of claim 8 is formed in the first process of the ww haiqin processing and is in the second process & The product of knife dissection and healing is a complex. A method for fabricating a semiconductor device, comprising the steps of: 128076.doc 200849557 forming a dummy gate insulating film and a dummy interlayer electrode on a semiconductor substrate having a channel formation region; a nitride spacer and a nichrome oxide film or a stone-containing stone fossil film to form offset spacers on both sides of the dummy gate electrode; using the offset spacer and the gate electrode as a conductor Forming an extension region in the substrate; forming a sidewall spacer on both sides of the offset spacers, using the sidewall spacers, the offset spacers, and the dummy electrode as a mask on the semiconductor substrate Forming a source _ 没 region; forming an insulating film to cover the dummy gate electrode; removing the insulating film until the dummy electrode is exposed from the top of the insulating film; removing the dummy gate electrode The dummy pad insulating film forms a pole electrode trench and removes a tantalum nitride film constituting the offset spacers; and a gate insulating barrier is formed at the bottom of the drain electrode trench; Forming a conductive layer on the closed-electrode insulating layer to fill the dummy trench; and removing the conductive layer-effect transistor from the outside of the closed-electrode trench.氐苟n.= The method of claim 10, wherein the removing at least the dummy gate insulating film comprises a 1st etching process, comprising: treating the insulating layer with a gas containing ammonia and hydrogen fluoride A first surface of the surface of the exposed surface is treated and decomposed and evaporated to a treatment of the product formed in the first treatment. 128076.doc 200849557 (NH4)2SiF6 complex. The method of claim 11, wherein the product formed in the first treatment of the etching treatment and decomposed and evaporated in the second treatment is 13· A manufacturing method of a semiconductor device, comprising the steps of: forming a dummy gate insulating film and a dummy gate electrode on a semiconductor substrate having a Si-Si region; sequentially laminating a tantalum nitride film or a boron-containing layer a tantalum nitride film and a hafnium oxide film form offset spacers on both sides of the dummy gate electrode; using the offset spacers and the gate electrode as a conductor substrate (4) domain; Forming a sidewall spacer on both sides of the offset spacer such as 亥; using the sidewall spacers, the offset spacers, and the gate electrode 遮 to form a source in the semiconductor substrate a drain region is formed to cover the dummy gate electrode; the H edge film is removed until the dummy electrode is exposed from the top of the insulating film; ^ virtual " gate electrode and the dummy gate insulating film To form a gate The pole trench simultaneously leaves at least a portion of the tantalum nitride film or the boron-containing tantalum nitride film constituting the offset spacers; and a gate insulating film is formed at the bottom of the 4 gate electrode trench; A conductive layer is formed on the insulating film to fill the electrode channel; and the outer side of the gate electrode is removed to form a field effect transistor. 14. The method of claim 13, wherein the method of removing at least the dummy gate insulating film comprises an etching process comprising treating the insulating layer with an etching gas containing ammonia and hydrogen fluoride. a first physics of the surface of the exposed surface and a decomposition and evaporation of the first process of the first process - a method of the product - ψ 〇 15. The method of claim 14, wherein the last name is processed The product formed in the first treatment and decomposed and evaporated in the second treatment is a (NH4)2SiF6 complex. ', 16. The method of claim 13 wherein the offset spacers are formed such that the tantalum nitride film or the boron-containing tantalum nitride film is thinner than the hafnium oxide film.