200847111 九、發明說明： 【發明所屬之技術領域】 本發明係有麵示敍轉置之控祕號產生電 路及控制方法。 【先前技術】 現今科技日新月異，為了使民科以享❹m技產品雜利，業者不 斷^•朝向高品質產品方向發展。像是早期顯示器為陰極射線管（⑽〇deRay • Tube，OT)顯示11，由於其體積龐大與耗電量大，而且所產生的輻射線， ，於人體也疋-大危吾的疑慮，因此現今市面上_示騎漸以液晶顯示 器（Liquid Crystal Display，LCD)為主。液晶顯示器具有輕薄短小、低 輻射與耗電量低等優點，也因此成為目前市場主流。 士請參閱第一圖，其為習知液晶顯示器之方塊圖。如圖所示，其包含一 7序產生益10、-垂直驅動電路2〇，、一水平驅動電路3〇，卩及一顯示 區域45。％序產生器10’接收一垂直同步訊號Vsync、一水平同步訊號 Hsy^c以及主時脈§域【〖，時序產生器，藉由步訊號吻此與 ^時脈訊號mck產生-垂直輸人時脈訊號VST與—垂直移位時脈訊號VCK。 鲁 肖理時序產生器1 〇亦依據水平同步訊號此㈣與主時脈訊號脳產生 一水平輪入時脈訊號HST與一水平移位時脈訊號HCK。 垂直驅動電路20’包括一移位暫存器22，，移位暫存器泣，係接收垂 直輸入時脈訊號vst與垂直移位時脈訊號VCK，而產生一垂直選擇訊號以控 =不區域45顯示畫面。水平驅動電路3〇，之一移位暫存器％，接收水 场脈訊號HST與水平移位時脈峨腿，產生一取樣時脈訊號用於取 樣衫像貝料’鱗騎取樣之鱗資料至顯示區域45，稿示影像。 再者’時序產生器10，更包括第一計數器12，與第二計數n 14，。第 士汁數器12用以計數時脈訊號個數，當時脈訊號之個數到達一門檻值 日守即發tlj-水平畴控伽號至水平骑電路3(}，，以控制水平驅動電 200847111 路30, ’例如’驅使水平驅動電路3〇,保持取樣影像資料所得之取樣資料， 以傳送至-數鋪tb機H (圖未繪）_触—触之顯轉號，並輪 出至顯示區域45’。第二計數器14, _上述，用以計數時脈訊號個數， 當時脈訊狀健猶f»值時’即翻—垂鱗雜制職至垂直驅動 電路20’以控制垂直驅動電路2〇，。 上述習用技術必須設置計數器12,與14，於時序產生器1〇，進行計數 而產生各猶雜制峨’如此會侧顯示面板之面積並增加電路設計之 複雜度，同時也會增加功率消耗。 基於上述缺點，中觀國專利公告第535136號發明專概出另一種產 生時序控制訊號的方式。如第二圖所示，時序產生器1〇，可分別藉由垂直 驅動電路2G’肖水平鷄電路3〇,原有之移位暫存器⑽，與移位暫存器 32,回傳-時序資料（Timing她）至時序產生器1〇，，而時序產生器 爪依據時序資料產生時序控制訊號並傳送至垂直驅動器2〇，肖水平驅動 器30，，以控制垂直驅動器20,與水平驅動器30，。 藉由上述方式產生時序控制訊號，雖然不需使用計數器，但進行雙向 掃描時，由於許多時序控舰號必須在空白(blanking)顧產生，若以典 f的10%空白週期計算，對輸出的解析度是施x32G像素解析度之顯示器而 吕’便需在水平驅動電路30，之移位暫存器32，之頭尾多加各約沈級虛 設(dummy)雜暫柿錢«序產生ϋ 10,所需之時序資料喊生時序 控制訊號。垂直驅動電路2〇，之移位暫存器22，亦是如此。 此種方式將使垂直驅動電路20，與水平驅動電路3〇，之移位暫存器 22 、32所佔用之長度需增加許多，使超出顯示面板上下左右之長度， 且增加功率消耗。現今對於顯示面板上下左右之架框的寬度大小要求日益 嚴格，如此設計方式不符合現今要求。再者，若將28級虛設移位暫存器分 別设置於顯不面板的其他地方便會將使訊號傳遞發生延遲，如此容易發生 問題’而無法順利進行雙向掃描，造成雙向切換困難。 因此’目前需要一種顯示裝置之控制訊號產生電路及產生方法，其能 200847111 改善垂直驅動電路與水平驅動電路原有之移位暫存器之級數過長、辦加抓 雜細㈣‘#，瞻刪綱，_向^ 【發明内容】200847111 IX. Description of the invention: [Technical field to which the invention pertains] The present invention has a control circuit for generating a circuit and a control method. [Prior Art] Nowadays, science and technology are changing with each passing day. In order to make the folk sciences enjoy the benefits of m-tech products, the industry continues to develop towards high-quality products. For example, the early display is a cathode ray tube ((10) 〇deRay • Tube, OT) display 11, because of its large size and power consumption, and the radiation generated, the human body is also awkward - big doubts, so Nowadays, the market is dominated by liquid crystal displays (LCDs). Liquid crystal displays have the advantages of being thin and light, low in radiation and low in power consumption, and thus have become the mainstream in the current market. Please refer to the first figure, which is a block diagram of a conventional liquid crystal display. As shown, it includes a sequence generation benefit 10, a vertical drive circuit 2A, a horizontal drive circuit 3A, and a display area 45. The % sequence generator 10' receives a vertical sync signal Vsync, a horizontal sync signal Hsy^c, and a main clock § field [, timing generator, generated by the step signal kiss and the ^ clock signal mck - vertical input The clock signal VST and the vertical shift clock signal VCK. The Lu Xiaoli timing generator 1 also generates a horizontal rounded clock signal HST and a horizontal shifted clock signal HCK according to the horizontal synchronizing signal (4) and the main clock signal. The vertical driving circuit 20' includes a shift register 22, and the shift register is configured to receive the vertical input clock signal vst and the vertical shift clock signal VCK to generate a vertical selection signal to control = no area. 45 display screen. The horizontal driving circuit 3〇, one of the shift register %, receives the water field pulse signal HST and the horizontal shift clock pulse leg, generates a sampling clock signal for sampling the shirt like the shell material 'scale riding sampling scale data To the display area 45, the image is printed. Further, the timing generator 10 further includes a first counter 12 and a second count n14. The number of the juice meter 12 is used to count the number of clock signals. When the number of the pulse signals reaches a threshold value, the tlj-level domain control gamma is sent to the horizontal riding circuit 3 (}, to control the horizontal driving power. 200847111 Road 30, 'for example' drives the horizontal drive circuit 3〇, keeps the sampled data obtained by sampling the image data, and transmits it to the number-pb machine H (not shown) _ touch-touch display turn number, and rotates to The display area 45'. The second counter 14, _ is used to count the number of clock signals, and when the pulse signal is at the value of the f», it is turned over to the vertical drive circuit 20' to control the vertical The driving circuit 2〇, the above-mentioned conventional technology must set the counters 12, and 14, in the timing generator 1〇, to count each other to generate the area of the side display panel and increase the complexity of the circuit design, In addition, the power consumption is also increased. Based on the above shortcomings, the invention of Zhongguanguo Patent Publication No. 535136 describes another way of generating timing control signals. As shown in the second figure, the timing generators 1〇 can be driven by vertical driving, respectively. Circuit 2G' Xiao level chicken electric Lane 3, the original shift register (10), and shift register 32, back-time data (Timing her) to the timing generator 1〇, and the timing generator claw generates timing control according to the timing data The signal is transmitted to the vertical driver 2, the horizontal horizontal driver 30, to control the vertical driver 20, and the horizontal driver 30. The timing control signal is generated by the above method, although the counter is not required, but the bidirectional scanning is performed due to many The timing control ship number must be generated in blank (blanking). If the 10% blank period of the code f is calculated, the resolution of the output is the display of x32G pixel resolution and L' needs to be moved in the horizontal drive circuit 30. The bit buffer 32, the head and the tail add more than about each level of dummy (dummy) miscellaneous persimmon money «order generation ϋ 10, the required timing data to call the timing control signal. Vertical drive circuit 2 〇, shift temporary storage The same is true for the device 22. This way, the vertical drive circuit 20 and the horizontal drive circuit 3, the length occupied by the shift registers 22, 32 need to be increased a lot, so that the length of the display panel is up, down, left and right, And increase Rate consumption. Nowadays, the width of the frame of the upper and lower sides of the display panel is increasingly strict, so the design method does not meet the requirements of today. Moreover, if the 28-level dummy shift register is separately set to the other panels, it is convenient. It will delay the signal transmission, so that problems are easy to occur, and the two-way scanning cannot be performed smoothly, which makes the two-way switching difficult. Therefore, there is a need for a control signal generating circuit and a generating method for the display device, which can improve the vertical driving circuit and level of 200847111. The number of stages of the original shift register of the drive circuit is too long, and it is necessary to grasp the miscellaneous (4) '#, to see the outline, _ to ^ ^ [Summary]
、本發明之目的在於提供一種顯示裝置之控制訊號產生電路及產生方 法’其可直接细輸人訊號作為垂斜序控伽號或水平時序控制訊蒙， =分別控直驅動電路或水平驅動電路’如此可避免垂施動電路:水 =動有之移位暫存器之級數過長，而增加設計之複雜度，且可順 利進仃雙向播描。 、本發明之另—目的在於提供—種齡裝置之控舰«生電路及產生 方法其直接利用輸入訊號作為垂直時序控制訊號或水平時序 以達降低消耗功率之目的。 本發明之顯示裝置之控伽號產生電路包括—料產生器，並產生方 法係由時縣生器接收-外部訊號源之—輸人訊號，產生_第二控制訊 遽’並傳杜_稍置之_水平鶴，同時輸人峨轉送至水平驅 動電路1控制水平驅純路，再者，本發明之產生方法亦可藉由使用時 序產生器接收輸人簡，產生―垂直時序測喊，並傳送至顯示裝置之 -垂直驅動電路，_輸人訊號亦傳送至水平鶴電路，以直The object of the present invention is to provide a control signal generating circuit and a generating method for a display device, which can directly input a human signal as a vertical sequence control gamma or a horizontal timing control signal, and respectively control a direct drive circuit or a horizontal drive circuit. 'This can avoid the vertical driving circuit: water = moving the shift register is too long, and increase the complexity of the design, and can smoothly enter the two-way broadcast. Another object of the present invention is to provide a control ship of a plant of age, a raw circuit and a generating method, which directly uses an input signal as a vertical timing control signal or a horizontal timing to reduce power consumption. The control gamma number generating circuit of the display device of the present invention comprises a material generator, and the generating method is received by the county device - the external signal source - the input signal, the _ second control signal is generated, and the signal is transmitted The horizontal crane is placed, and the input is transferred to the horizontal driving circuit 1 to control the horizontal driving pure road. Furthermore, the generating method of the present invention can also generate the vertical timing sounding by using the timing generator to receive the input simplified. And transmitted to the display device - vertical drive circuit, _ input signal is also transmitted to the horizontal crane circuit, to straight
雷 1。 WJ 【實施方式】 兹為使責審查委員對本發明之結構特徵及所達成之功效有更進一步 之瞭2與職，謹佐啸狀實補及配合詳細之姻，綱如後：乂 明參閱第二圖，其為本發明之一較佳實施例之方塊圖。如圖所示，本 舍明之顯讀置包含-時序產生㈣，—水平驅動電路2q、—垂直驅動電 路30與-顯示區域4〇。時序產生器1()、水平驅動電路⑼、垂直驅動電路 7 200847111 30與顯示區域40皆位於顯示裝置之一顯示面板（圖未繪），顯示面板即為 玻璃基板。水平驅動電路2〇與垂直驅動電路30皆耦接於顯示區域4〇。 時序產生器10接收外部系統（例如電腦系統）所傳送之一外部訊號源 之一輸入訊號，產生一第一控制訊號並傳送至一驅動電路，同時輸入訊號 亦傳送至驅動電路，以控制驅動電路，其中驅動電路用於控制顯示裝置顯 不畫素，該驅動電路包括一水平驅動電路20與一垂直驅動電路30。時序產 生器ίο所接收之輸入訊號可為外部訊號源之一水平同步訊號Hsync與一垂 直同步訊號Vsync，而分別產生一水平輸入時脈訊號脱與一垂直輸入時脈 • 訊號VST ’並分別傳送至水平驅動電路2〇與垂直驅動電路洲，此外，時序 產生器10更依據外部系統所傳送之外部訊號源之一主時脈訊號紙尤分別產 生一水平移位時脈訊號HCK與一垂直移位時脈訊號VCK。在上述中，第一控 制Λ號包含一水平控制訊號與一垂直控制訊號，以分別控制水平驅動電路 2〇與垂直驅動電路3〇，水平控制訊號包含水平輸人時脈訊號脱與水平移 位時脈訊號HCK，垂直控制訊號包含垂直輸入時脈訊號VST與垂直移位時脈 訊號VCK。 水平驅動電路20，其包括一移位暫存器22、一問鎖模組24以及一數 位類比轉換電路26。移位暫存器22依據時序產生器1〇產生之水平輸入時 • 脈訊制ST與水平移位時脈訊號HCK產生-取樣時脈訊號。移位暫存器22 係依據水平移位時脈訊號Μ移位水平輸入時脈訊號厭，而產生取樣時脈 f簡驗24依據取樣時脈訊號取樣外㈣統所傳送之—影像資料而 ，生複數取樣貝料’並依據時序產生器1〇所接收之輸入峨，直接傳送至 ㈣旧_該棘樣倾，也就是鎌水稍步減脚此而保 拉=二取樣貝料。閃鎖模組24係包括一取樣問鎖電路卻與一保持閃鎖電 媒次441’取樣閃鎖電路240係依據取樣時脈減取樣影像資料，產生該些取 跑^;而保持閂鎖電路242則依據水平同步訊號Hsync ，保持取樣閃鎖電 麵之4些取樣資料。數位類比轉換器洲，轉換保持之該些取樣資料 類比之顯示訊號，並傳送至顯示裝置之顯示區域40之資料線（圖树）: 8 200847111 以顯示影像。 «轉 30包括-移鱗赫32，移轉彻32絲垂直輸入 時脈訊號VST與垂直移位時脈訊號VCK產生—垂直選擇訊號，用於選擇顯 示區域40之垂直掃描線（圖未繪），即控制顯示區域仙之垂直掃描線（圖 未緣）’腦使顯示區域40顯示影像。由上述可知，顯示面板之顯示區域 40可藉由水平驅動電路20與垂直驅動電路3〇傳送之垂直選擇訊號與顯示 峨罐示影像。此外’本發明之時敍生㈣會直接傳送輸人訊號至垂 直驅動電路30以控制驅動電路30，也就是傳送垂直同步訊號Vsync至垂直 φ 鶴電路30。例如欲在某一期間進行局部顯示模式時，即可發送垂直同步 訊號VsyncS垂直驅動電路30，以控制垂直驅動電路3〇在此某一期間進行 局部顯示模式。另’上述财平邮赠Hsyne _直畔緘㈣此作 為輸入訊號縣本發攸-健f侧’料肖限本發社輸錢號為水 平同步訊號Hsync與垂直同步訊號vsync。 本發明由於直接依據輸人訊號產生時序控制訊號，所以不需如同習用 技術般_計數H，或者水平驅動電路20或者垂直驅動電路3()之移位暫 存器22、32，如此可減少硬體複雜度而降低設計複雜度及功率消耗，此外 可避免水平驅親路20與垂直驅動f路3G之移位暫存器22、32因增加級 φ 數而導致長度過長，而增加設計之複雜度，且可順利進行雙向掃描。 請一併參閱第四圖，其為本發明之另一較佳實施例，如圖所示，本實 施例與第三圖之實施例不同之處在於本發明之顯示裝置更包括一控制單^ 50。控制單元50接收輸入訊號，產生一第二控制訊號並傳送至水平驅動電 路20與垂直驅動電路30,以分別控制水平驅動電路2〇與垂直驅動電路 並第二控制訊號之頻率同於輸入訊號之頻率，但是脈衝寬度不一定相同。 由於水平驅動電路20與垂直驅動電路30分別有多種不同設計方式， 所以用於控制不同設計之水平驅動電路20與垂直驅動電路3〇之時序抑制 訊號的脈波寬度與時序係有所差異。所以本發明之控制單元5〇係依據^同 需求之控制訊號而有多種設計。請參閱第五A圖與第五b圖，其為本發明 200847111 之，制單元之一較佳實施例之方塊圖與所對應之輸入訊號和時序控制訊號 的晗序圖。如圖所示，控制單元50包含有一延遲單元500與一反相器502， 延遲單το 500延遲輸入訊號，再經由反相器5〇2反相經延遲後之輸入訊號， 以產生第—控制訊號。如第五β圖所示，控制訊號之頻率_輸入訊號。 本發明之控鮮元5〇亦可僅包含有延遲單元5⑼或反相器 502，而產生第 二控制訊號。 明參閱第六Α圖，其為本發明之時序產生器之另一較佳實施例之方塊 圖與所對應之輸入訊號和控制訊號的時序圖。如圖所示，控制單元㈤包含 • 延遲單元500與一及閘504，延遲單元圖延遲輸人峨，而及閘5〇4接收 輸入訊號與延遲單元_輯後之輸入訊號，產生第二控制訊號。如此， 所產生之控制訊號將如第五B圖所示，其頻率同於輸入訊號且脈波寬度大 於輸入訊號之脈波寬度。上述之兩實施例彳ns本發㈤之兩實施例，本發明 之控制單7G 50係依騎需之時雜制截而有不同之設計。此外，控制單 元50亦可設置於時序產生器10内。 、、示上所述，本發明之顯示裝置之控制訊號產生電路包括時序產生器， 本發明之產生方法係由時序產生器接收輸人喊，據輸人訊號產生第 -控制訊號，並傳送至齡裝置之，_電路，同時輸人觸祕送至驅動 • 電路’以控制驅動電路，如此可減少硬體複雜度而降低設計複雜度及功率 消耗，且可順利進行雙向掃描。 以上所述僅為本發明之較佳實施例，並非用來限定本發明之範圍，舉 凡依本發辦請專利麵所述之形狀、構造、特徵及精神所為之均等變化 與修飾，均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 第一圖為習知液晶顯示器之方塊圖。 第二圖為另一習知液晶顯示器之方塊圖。 第三圖為本發明之一較佳實施例之方塊圖。 200847111 f四圖為本發敗另-難實補之方顧。 =A圖為本發明之時序產生器之—_實麵之方塊圖。 望圖“五A圖之輸人訊號與時控制訊號之時序圖。 第^圖為第六A圖之輸人訊號與時控制訊^^之方塊圖 之4序圖。Ray 1. WJ [Embodiment] In order to make the reviewer's structural features and the effects achieved by the reviewer, there are two more tasks. I would like to sum up and cooperate with the details of the marriage. Figure 2 is a block diagram of a preferred embodiment of the present invention. As shown, the display of the present invention includes - timing generation (4), - horizontal drive circuit 2q, - vertical drive circuit 30 and - display area 4 。. The timing generator 1 (), the horizontal driving circuit (9), the vertical driving circuit 7 200847111 30 and the display area 40 are all located on one display panel (not shown) of the display device, and the display panel is a glass substrate. The horizontal driving circuit 2 and the vertical driving circuit 30 are both coupled to the display area 4A. The timing generator 10 receives an input signal of an external signal source transmitted by an external system (for example, a computer system), generates a first control signal and transmits the signal to a driving circuit, and the input signal is also transmitted to the driving circuit to control the driving circuit. The driving circuit is configured to control the display device, and the driving circuit includes a horizontal driving circuit 20 and a vertical driving circuit 30. The input signal received by the timing generator ίο can be one horizontal sync signal Hsync and one vertical sync signal Vsync of the external signal source, and respectively generate a horizontal input clock signal and a vertical input clock signal VST 'and respectively transmit The horizontal driving circuit 2 is parallel to the vertical driving circuit. In addition, the timing generator 10 further generates a horizontal shifting clock signal HCK and a vertical shift according to one of the external clock signals transmitted by the external system. Bit clock signal VCK. In the above, the first control signal includes a horizontal control signal and a vertical control signal to respectively control the horizontal driving circuit 2 and the vertical driving circuit 3, and the horizontal control signal includes the horizontal input clock signal and the horizontal shift. The clock signal HCK, the vertical control signal includes a vertical input clock signal VST and a vertical shift clock signal VCK. The horizontal drive circuit 20 includes a shift register 22, a lock module 24, and a digital analog conversion circuit 26. When the shift register 22 is based on the horizontal input generated by the timing generator 1 •, the pulse signal ST and the horizontal shift clock signal HCK generate a sample clock signal. The shift register 22 is based on the horizontal shift clock signal Μ shift level input clock signal anger, and the sampling clock pulse f is generated 24 according to the sampled clock signal sample (4) transmitted by the image data, The raw and sampled shellfish 'is according to the input 接收 received by the timing generator 1 峨, directly transmitted to (4) the old _ the ratchet-like tilt, that is, the drowning step slightly reduces the foot and the zipper = two sampled shell material. The flash lock module 24 includes a sample lock lock circuit and a hold flash lock electrical medium 441' sampling flash lock circuit 240 according to the sampling clock minus sample image data, generating the take-ups; and maintaining the latch circuit 242, according to the horizontal synchronization signal Hsync, keeps the sampling data of the sampling flash lock electrical surface. The digital analog converter converts the sampled data to be displayed analogously to the display signal and transmits it to the data line (picture tree) of the display area 40 of the display device: 8 200847111 to display the image. «Turn 30 includes -shift scale 32, shifting through 32-line vertical input clock signal VST and vertical shift clock signal VCK generation-vertical selection signal for selecting the vertical scan line of display area 40 (not shown) That is, the vertical scanning line (not shown) of the display area is controlled. The brain causes the display area 40 to display an image. As can be seen from the above, the display area 40 of the display panel can display the image by the vertical selection signal and the vertical display signal transmitted by the horizontal driving circuit 20 and the vertical driving circuit 3. Further, the present invention (4) directly transmits the input signal to the vertical drive circuit 30 to control the drive circuit 30, that is, the vertical sync signal Vsync to the vertical φ crane circuit 30. For example, when the partial display mode is to be performed for a certain period, the vertical sync signal VsyncS vertical drive circuit 30 can be transmitted to control the vertical drive circuit 3 to perform the partial display mode during this period. In addition, the above-mentioned Caiping mailed Hsyne _ Straight 缄 (4) as the input signal county county hairpin - health f side 'Material limited to the hair loss of the horizontal synchronization signal Hsync and vertical synchronization signal vsync. In the present invention, since the timing control signal is directly generated according to the input signal, it is not necessary to count H as in the prior art, or the shift register 22, 32 of the horizontal drive circuit 20 or the vertical drive circuit 3 (), thereby reducing the hard The complexity of the body reduces the design complexity and power consumption. In addition, the shift register 22 and 32 of the horizontal drive path 20 and the vertical drive f path 3G can be prevented from being too long due to the increase of the number of stages φ, and the design is increased. Complexity and smooth two-way scanning. Please refer to the fourth figure, which is another preferred embodiment of the present invention. As shown in the figure, the embodiment is different from the embodiment of the third figure in that the display device of the present invention further includes a control unit. 50. The control unit 50 receives the input signal, generates a second control signal and transmits it to the horizontal driving circuit 20 and the vertical driving circuit 30 to respectively control the horizontal driving circuit 2 and the vertical driving circuit, and the frequency of the second control signal is the same as the input signal. Frequency, but the pulse widths are not necessarily the same. Since the horizontal driving circuit 20 and the vertical driving circuit 30 have different designs, respectively, the pulse width and timing of the timing suppression signals for controlling the horizontal driving circuit 20 and the vertical driving circuit 3 of different designs are different. Therefore, the control unit 5 of the present invention has various designs according to the control signals of the same requirements. Please refer to FIG. 5A and FIG. 5b, which are block diagrams of a preferred embodiment of the manufacturing unit of the invention 200847111 and a sequence diagram of the corresponding input signal and timing control signals. As shown in the figure, the control unit 50 includes a delay unit 500 and an inverter 502, delaying the single το 500 delay input signal, and then inverting the delayed input signal via the inverter 5〇2 to generate the first control. Signal. As shown in the fifth β diagram, the frequency of the control signal_input signal. The control unit 5 of the present invention may also include only the delay unit 5 (9) or the inverter 502 to generate a second control signal. Referring to the sixth diagram, which is a block diagram of another preferred embodiment of the timing generator of the present invention and a timing diagram of the corresponding input signal and control signal. As shown in the figure, the control unit (5) includes a delay unit 500 and a gate 504, the delay unit map delays the input, and the gate 5〇4 receives the input signal and the input signal after the delay unit _, generating a second control. Signal. Thus, the generated control signal will be as shown in Figure 5B, with the same frequency as the input signal and the pulse width being greater than the pulse width of the input signal. In the two embodiments of the above two embodiments, the control unit 7G 50 of the present invention has different designs depending on the time of the ride. Further, the control unit 50 can also be disposed in the timing generator 10. The control signal generating circuit of the display device of the present invention includes a timing generator. The generating method of the present invention receives the input and shout by the timing generator, generates a first control signal according to the input signal, and transmits the signal to the control signal. The age device, the _ circuit, and the input to the drive • circuit 'to control the drive circuit, which can reduce the hardware complexity and reduce the design complexity and power consumption, and can smoothly perform two-way scanning. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the equivalent changes and modifications of the shapes, structures, features and spirits described in the patent application should include Within the scope of the patent application of the present invention. [Simple description of the drawing] The first figure is a block diagram of a conventional liquid crystal display. The second figure is a block diagram of another conventional liquid crystal display. The third figure is a block diagram of a preferred embodiment of the present invention. 200847111 f Four pictures are the other side of the failure - hard to make up the square. =A is a block diagram of the real-time timing generator of the present invention. Look at the timing diagram of the input signal and the time control signal of the five-figure diagram. The second figure is the sequence diagram of the block diagram of the input signal and the time control signal of the sixth picture A.
【主要元件符號說明】 10, 時序產生器 12， 第一計數器 14， 第二計數器 20， 垂直驅動電路 22， 移位暫存器 30， 水平驅動電路 32， 移位暫存器 45， 顯示區域 10 時序產生器 20 水平驅動電路 22 移位暫存器 24 閂鎖模組 240 取樣閂鎖電路 242 保持閂鎖電路 26 數位類比轉換器 30 垂直驅動電路 32 移位暫存器 40 顯示區域 50 控制單元 500 延遲單元 200847111 502 反相器 504 及閘[Main component symbol description] 10, timing generator 12, first counter 14, second counter 20, vertical drive circuit 22, shift register 30, horizontal drive circuit 32, shift register 45, display area 10 Timing generator 20 horizontal drive circuit 22 shift register 24 latch module 240 sample latch circuit 242 hold latch circuit 26 digital analog converter 30 vertical drive circuit 32 shift register 40 display area 50 control unit 500 Delay unit 200847111 502 inverter 504 and gate