TW200843075A - Circuit component structure - Google Patents

Abstract

A circuit component includes a first chip having a first semiconductor substrate, at least one first metal pad over the first semiconductor substrate, a first passivation layer over the first semiconductor substrate, at least one first opening in the first passivation layer exposing the first metal pad. The first chip further includes a first metal layer over the first passivation layer and connected to the first metal pad through the first opening. The circuit component further includes a second chip over the first chip. The second chip has a second semiconductor substrate over the first chip, a second metal pad over the second semiconductor substrate, and a second passivation layer over the second semiconductor substrate, at least one second opening in the second passivation layer exposing the second metal pad. The circuit component further includes a first wire connecting a first wire bonding pad of the first metal layer to an external circuit, and a second wire connecting the second metal pad to a second wire bonding pad of the first metal layer.

Description

200843075 . . . . . . Description of the Invention: [Technical Field] The invention relates to a circuit component structure and a process thereof, and more particularly to a wafer structure and a process for performing a double-wire process in a wafer. [Prior Art] In recent years, with the continuous development and development of semiconductor process technology, various high-performance products have continued to evolve, and the integrated circuit (Integrated Circuit, 1C) component integration has also been continuously improve. In the packaging process of integrated circuit components, IC Packaging plays a very important role, and the integrated circuit package type can be roughly divided into wire bonding packages (WB) and stickers. ▼Tape Automatic Bonding (TAB) and Flip Chip (FC), and each package has its particularity and application. ^ However, when the size of the integrated circuit is further miniaturized, when the metal connection structure on the integrated circuit is connected to other circuits or systems, the circuit performance will gradually become an adverse impact, especially the metal connection structure. When parasitic capacitance and resistance increase, the performance of the wafer will be seriously degraded. For example, when the parasitic capacitance and resistance of the metal interconnection increase, it will mean a decrease in the performance of the wafer. Among them, the most concern is along the power bus and the ground bus (voltage drop between the four (4) and the resistance and capacitance delay of the key signal path (this (four)) In order to reduce the resistance, if a wide metal wire is used, the parasitic capacitance of these wide metal wires will increase.

In view of this, the process of the circuit components and its considerations, the present invention, have raised the problem of knowing the technology.

The product is reduced. Another object of the present invention is to provide r

The circuit structure and its manufacturing process replace the existing metal bumps with the bismuth bumps to reduce the material cost. a conductor substrate, the first semiconductor substrate has at least one first metal pad; a first protective layer on the first semiconductor substrate, the first protective layer having at least a mouth to expose the first metal pad; a first metal layer is disposed on the first protective layer and connected to the first protruding pad via the first opening, the first metal layer has a first bonding pad and a second bonding pad; a second semiconductor substrate, on the first semiconductor substrate, exposing at least one side of the first semiconductor substrate, the first bonding pad and the second bonding pad, and the second semiconductor substrate has a second metal connection a second protective layer is disposed on the second semiconductor substrate, and one of the second protective layers has at least one second opening exposing the second metal pad; a first wire bonding wire 5 is located at the first bonding wire The pad is connected to a first external circuit; a second wire is connected to the second metal pad of the second semiconductor substrate. For the above purpose of the present invention, a circuit component structure is proposed, which comprises a first half 200843075 conductor substrate, the first semiconductor substrate having at least one first metal interface, a first protective layer, in the first Counting county red, recording - dip layering at least - opening (four) the first metal joint; - the first metal layer, located on the first protective layer and electrically connected to the first metal joint, the first metal The layer has a -th-line hiding and a second wire bonding; - a first wire bonding wire, the bit is connected to a first external circuit on the first wire bonding port; and a second wire bonding wire is located in the second wire bonding wire The pad is connected to a second external circuit. In order to achieve the above object of the present invention, a circuit component structure is proposed, which includes a first semiconductor substrate, and - a plethora is on the bottom of the Na-Semiconductor County, and at least the first opening of the turn-bottom layer exposes the first Connecting the first pad via the first opening to the first protective layer of the semiconductor substrate, the first wiring substrate, the first semiconductor substrate, and the first semiconductor substrate is exposed on the first semiconductor substrate and exposing the first semiconductor substrate At least one side of the first bonding wires, and a second protective layer on the second semiconductor substrate, at least one second opening of the second protective layer exposing the second semiconductor substrate a pad, and a second metal layer is on the second protective layer and connected to the second pad via the second opening, the second metal layer includes a plurality of second bonding pads; a third semiconductor substrate is positioned Forming at least one side of the second semiconductor substrate on the first semiconductor substrate:: '. . . . . . . . . . . . . . The second line is miscellaneous, and the third county is on the scale three-turn base, the third V. . - '·; The at least one opening exposes a third pad of the third semiconductor substrate, and a third metal layer is disposed on the third protective layer and connects the third interface via the third opening, the third ' · ^ - * 1 ... the metal layer includes a plurality of third wire pads; a fourth semiconductor substrate on the third semiconductor substrate .....,: : and the second semiconductor is exposed At least one side of the substrate and the third bonding pads, and a 200843075 four protective layer is on the fourth semiconductor substrate, and at least one fourth opening of the fourth protective layer exposes one of the fourth semiconductor substrates a fourth pad, and a fourth metal layer is disposed on the fourth protective layer and connected to the fourth pad via the fourth opening, the fourth metal layer includes a plurality of fourth wire pads, a plurality of wire wires, and a plurality of wires And the first wire bonding pad and the second wire bonding pad, the second wire, the second wire bonding pads, the second wire bonding pads and the fourth wire bonding pads a wire bonding pad and the third wire bonding pad, the third wire bonding pad and the fourth wire bonding pad The wire bonding wires are connected to each other; an external circuit is connected to at least one of the first wire bonding pad, the second wire bonding pad, the third wire bonding pad and the fourth wire bonding pad via the wire bonding wires . For the above purpose of the present invention, a wiring element structure is provided, which includes a first semiconductor substrate having at least one first metal pad; a first protective layer on the first semiconductor substrate The first protective layer has at least one opening exposing the first metal pad; a composite metal layer is disposed on the first protective layer and electrically connected to the first metal pad, the composite metal layer has a first a first wire bonding wire and a second wire bonding wire; a first wire bonding wire connected to the first external circuit on the first wire bonding pad; and a second wire bonding wire connected to the second wire bonding pad A second external circuit. For the above purpose of the present invention, a wiring element structure is provided which includes a semiconductor substrate having at least one metal pad; a protective layer on the semiconductor substrate, the protective layer having at least one opening exposed a metal pad; a polymer bump on the protective layer; a metal layer on the protective layer, the polymer bump and the metal pad, the metal layer covering the polymer bump At least two surfaces are connected to an external circuit via the gold 200843075 genus layer on the polymer bump. For the above purpose of the present invention, a circuit component is provided, which comprises a semiconductor layer (four) t on the semiconductor substrate, the protective layer has at least two closed openings exposing the first metal junction layer, spines The bump layer and the metal layer cover the at least two surfaces of the polymer bump, the first metal layer includes a bonding pad on the polymer bump, and a second a metal layer is disposed on the protective layer and connected to the second metal pad. The second metal layer includes a wire bonding wire. The wire is disposed on the wire bonding pad and connected to a first external circuit. For the above purpose of the present invention, a wiring element structure is provided, which includes a semiconductor substrate having at least a “first metal pad” and a second metal contact; a protective layer is disposed on the semiconductor substrate. The protective layer has at least two openings exposing the first metal joint and the second metal joint; - polymer bumps respectively located on the protective layer; a first [metal layer, located in the protective layer, On the polymer bump and the first metal pad, the first metal layer covers at least two surfaces of the polymer bump, and the first metal layer comprises a bonding contact on the polymer bump; a second metal layer on the protective layer and connected to the second metal interface; a tin-containing metal layer connected to the second metal layer. The purpose, technical contents, features and effects achieved by the present invention will become more apparent from the detailed description of the embodiments and the accompanying drawings. 200843075 - ' . . . · [Real pain type] : ':, ; : - - -' _ . : Yue Yue (4) Miscellaneous road structure and its process, which is solved in this invention, _ not _ Wei ~ structure and • Cheng Fang: 3⁄4: After @细^Invented various rewards _ freshly said, before the explanation, the class #方" In the present invention, t means that it is located on and in contact with something, or: Chinese objects are in contact with them. ........,_.'. · · * ', , ,'."·- :^ :. ^ ' .': '.;'ν.': ; :'·;·; . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The substrate 1 is usually a silicon substrate, and the second substrate may be an intrinsic ruthenium, a P-type ruthenium substrate or a ni矽 substrate. For high-performance wafers, a silicon germanium (SiGe) or a silicon-on-insulator (SOI) substrate is used. Among them, the nightmare base includes '.一• . ;....... 』..",:. ;.. A stone 锗 锗 epithetical layer (epitaxial layer) on the surface of the stone slab base, another The overlying insulating substrate comprises an insulating layer (preferably an oxidized oxidized stone) on a substrate, and a stone or epiphytic layer is formed on the insulating layer. Next, a device layer 12 is formed on the substrate 1 as shown in FIG. 5b. The component layer 12 generally includes at least one semiconductor device (semicon device), and the device layer 12 is In the surface of the substrate 1 以及 and/or on the surface, wherein 5 11 200843075 semiconductor component may be a MOS transistor, such as N-type MOS transistor M (NM0S transistor' n- Channel MOS transistor) or P-type transistor transistor (P-channel MOS transistor), and the gold-gas semiconductor transistor μ includes a source 16, a drain 18 and a gate 20, and The gate 20 is often a polycrystalline dream (_ sUieon), a tungsten polycide, a tungSten silicide, a titanium silicide, and a cobalt ruthenium. Or a salicide gate. Alternatively, the abundance conductor element can also be a double carrier transistor.

(bipogr transistor), diffusion metal oxide semiconductor (Diffused MOS, DM0S sate oxide semiconductor (Lateral Diffused M〇S, LDMOS), charge coupled device (Charged-Coypled Device, CCD), mutual trapping metal An oxide semiconductor (CMOS) sensing element, a photo-sensitive diode, a resistive element (formed by a polysilicon layer or a diffusion region in a germanium substrate). Various semiconductor circuits can be used to form various circuits, such as complementary Metal-oxide-semiconductor (CMOS) circuit, N-type MOS circuit, P-type MOS circuit, bi-carrier complementary gold-oxide semiconductor (BiCM(6) circuit, complementary metal oxide, semiconductor sensor) , a metal oxide semi-metamorphic milli-source electric brigade, a laterally diffused metal oxide semiconductor circuit, etc. In addition, the component layer 12 also includes a reverse gate (N〇ij ga1 or a NAND gate) Beyond 'can also be an inverter (inverkr), one gate (and gate} ^ a lang lang gate), a static random access memory unit (SRAjj cel 丨), state random access cryptic body Unit (DR^M Cell), a non-volatile memory cell (ηΰη-g memory cell), a dynasty memory cell unit (7)-like bucking boat ^^ out of the read-only memory 先 single first (EPROM cell)---read-only memory unit (ROM cell), a magnetic with 12 200843075 · ' . Machine memory (magnetic RAM, MRAM) unit, a sense amplifier (sense amplifier), an op amp amplifier (〇perati〇nal amplifier, 〇p A is an adder, a multiplexer, a diplexer, a multiplier, and a type of this/digital converter (human/claw 6 6) , a digital/analog conversion ', '.' (D/A converter), a complementary metal oxide semiconductor sensing device unit (CM〇s sensor cell), a photosensitive diode (ph〇t〇-sensitive Diode), a complementary metal oxide semiconductor, a double-carrier complementary MOS, a double-carrier circuit (bip〇larcircui1:) or an analog circuit. Fine connection: See Ic As shown, a thin line structure 22 is formed on the substrate 1 and the element layer 12, and the thin line structure 22 includes a plurality of thin lines. Fine-Hne conductivity layer 24, a fine-line dielectric layer 26, and a plurality of conductive plugs in the opening 28 of the fine-line dielectric layer 26 and the opening 28 (fine-iine via plug) 30, in addition to the topmost thin circuit layer 24 may be at least one or a plurality of regions, these regions being defined as pads 32. The thin circuit layer 24 is selected from the group consisting of aluminum metal material, copper metal material, or more specifically, in this embodiment, and is formed by sputtering. Aluminum layer, or copper layer formed by mosaic. Therefore, .4 .... . . - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . All of the fine lines · ' . . . . . . . . . - - layer 24 are all copper layers; (3) the bottom layer of the fine circuit layer 24 is an aluminum layer, and the top layer of the thin circuit layer 24 is: .... Copper layer; or (4) The fine circuit layer 24 of the bottom layer is a copper layer, and the fine circuit layer 24 of the top layer is an aluminum layer. In addition, the thickness of each thin circuit layer 24 is between 〇· 〇 5 μm (egg) to 2 μm, ' .... . . . and between 0· 2 A thickness between micrometers and 1 micrometer is preferred, and if another fine wiring layer 24 is a line, 13 200843075 has a lateral design standard (width) of between 20 nanometers and 15 micrometers, and It is preferably between 20 nm and 2 microns. First, the thin circuit layer 24 is an aluminum layer, and the aluminum layer of the thin circuit layer 24 is usually formed by physical Vapor Deposition (PVD), for example, by sputtering, and then through The aluminum layer is patterned by depositing a photoresist layer having a thickness between 微米·[micron to 4 micrometers (preferably between 微米·3 micrometers and 2 micrometers), and then performing the layering A wet etching or a dry etching is preferably a dry plasma silver paste (usually comprising a gas plasma). In addition, an adhesion/barrier layer may be selectively formed under the layer, wherein the adhesion/barrier layer may be titanium, titanium tungsten alloy, titanium nitride or a composite layer formed by the above materials. An anti-reflective layer (such as nitriding) can also be selectively formed on the layer. In addition, the opening 28 can be selectively filled with chemicai vapor deposition (CVD) tungsten metal, and then the tungsten metal layer is polished by chemical mechanical polishing (CMP) to form a conductive plug. 30 〇% Next, it is explained that the thin circuit layer 24 is a copper layer, and the copper layer of the 钿 circuit layer 24 is usually formed by means of electroplating and a damascene process, which is described as follows: (1) depositing a copper. .·· * · Diffusion barrier layer (for example, a nitrogen oxide layer or nitride layer with a thickness between 〇·05 μm and 0·25 μm), and (2) plasma-assisted chemical vapor deposition (plasma) Enhanced CVD, PEGVD), · ' - ' .- . .- - spin-on coating or high-density plasma chemical vapor deposition (jjigh j) ensity plasma CVD (HDPCVD) 〇·1 micron to 2·5 micron between a thin line of the mesoporous layer 26' wherein the thin-line dielectric layer 26 is between 〇·3 micrometers to 1.5 micrometers 14 200843075 (3 minus the deposition thickness is between.) A light between micron and a micro Layer «2β , ^ , 3 2 « 彳 为 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Using a tin plating or chemical vapor deposition layer, 人#^, human "nitriding_, titanium, titanium or titanium tungsten alloy, or a composite formed from the above materials a copper layer, which may be formed by using gold ore, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper, copper The thickness of the steel layer is between 0.2 micrometers and 1 micrometer, and (6) is removed by the grinding (preferably 駄-type mechanical polishing) crystal riding method to remove the opening or groove not in the fine-line dielectric layer 26 The copper layer, the seed layer, and the brittle barrier layer are exposed to the thin-line dielectric layer under the adhesion/barrier layer. Only after the __ grinding 5, only the metal in the opening or the trench is left. And the remaining metal is used as 30 (a%#24) 〇, φ can be _-double (dQUble as seen) _, in the second-order system----------------------------------------- And the gold secret road or metal plane. Two times I shadow = h〇t〇llthography) process and two electroplating processes are applicable to the dual damascene process. The double inlay process in the above single damascene process - case - dielectric Step (3) and the deposited metal layer 2, () add more deposition and patterning of another dielectric layer. The receiver describes the fine-line dielectric layer 26, which is formed by chemical vapor deposition, electric 200843075 slurry transfer; {study vapor deposition, two-time plasma chemical vapor deposition or spin coating (Spin) -0JJ) is formed in a way. The material of the front layer food layer zero layer 26 includes silicon oxide, nitrite (sili item nitride), bismuth oxynitride (si 1 icon pxynitride), and plasma-assisted chemical system. (PECVD TEOS), Fluorinatpd Silicate Glass (F§G) or a low dielectric constant (field::, for example, Black Bay 薄 thin gland (Black Di_nd7,

Temple Division # named Explosive Materials Company}, ULLM

SiLKClBM company) low dielectric constant dielectric material. The oxidized dream formed by plasma-assisted chemical vapor deposition, the tetraethoxy oxane formed by the plasma-assisted chemical vapor deposition, or the oxide formed by the high-density plasma has a ratio of 3.5 to 4.5. The dielectric constant between the 矽; the fluorocarbon glass formed by the plasma-assisted chemical oxygen phase deposition or the bismuth glass formed by the high-density plasma has a dielectric constant value between 3. 〇 and 35, and The low dielectric constant dielectric material has a dielectric constant value between 丨·5 and & A low-k dielectric material, such as a black diamond film, is porous and contains #hydrogen, carbon, and second enthalpy, and has a molecular formula of HwGSiy0z. This "line dielectric layer I (four), inorganic _ (--ganic mater ial), used to reach the dielectric layer 26 _ win between 〇 · 05 micro

^ 28 M: m mkM is etched in the form of a dry name. The dry etching type includes fluorine plasma (flucrine), as shown in Fig. 1c, forming a protective layer 34 on the fine line structure, and this protection 34 plays a very important role in the present invention. Protective layer & In the integrated circuit industry is for the two 16 200843075. · ::..:... An important part, such as 1990 by S, Wolf, and by 1^1:1: 丨〇6? As described in the "Si 1 icon Processing in the VLSI era", Volume 2, the protective layer 34 is defined as a final layer in the integrated circuit process and deposited on the entire upper surface of the wafer. It is an insulating and protective layer that prevents mechanical and mechanical damage during assembly and packaging... _ ' ,. - Learn to damage. In addition to preventing mechanical scratches, the protective layer 34 also prevents mobile ions (mobile ion) ) 'For example, sodium ions, and transition metals, such as gold and copper, penetrate into the integrated circuit components below. In addition, the protective layer 34 can also protect the underlying components and connection lines (fine line metal structure and fine line dielectric layer) from moisture. .....;--:. . . - (moisture) Intrusion. The protective layer 34 usually comprises a silicon nitride layer and/or a silicon oxynitride layer, and the thickness is between 〇 2 μm and 1.5 μm, and A thickness between 0 and 3 micrometers to 1.0 micrometer is preferred. Other materials used in the protective layer 3〇〇 are oxidized by plasma-assisted chemical vapor deposition, and oxidized by plasma-enhanced tetraethyl orthosilicate (PETE0S). , phosphorosilicate (PSG), borophospho, silicate glass (BPSG), oxide formed by high density plasma (HDP). Next, describe: r. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <;7;·" . :; ^ ^ Some examples of the protective layer 34 consisting of a composite layer, the bottom to top order is: (1) thickness between 0_ 1 micron to 1.0 micron ( The preferred thickness is between 〇·3 μm and 〇·7 μm); Γ*' ;;' ·!;: ;; V : . ;'' ' : : ; ' : ; ' .· 〇-' :· :·· ;; / ;·: / , :;; The oxide / thickness is between 0 · 25 microns and 1.2 microns (preferably thickness is between 〇 · 35 microns to U) Tantalum nitride, this type of protective layer 34 is usually overlaid on a metal connection line formed of aluminum as '-\ '/ , :- - - ; , wherein the metal connection line formed of aluminum usually includes sputtering Aluminium and etch 17 200843075 Ming process; (2) NOx/thickness thickness between 〇·05 μm and 〇. 35 μm (preferably between 0·1 m and 〇·2 μm) Yu Yu. The oxide/thickness from 2 μm to 1.2 μm (preferably between 〇·1 μm and 〇·2 μm) is between 微米·2 μm and 1.2 μm (better thickness is between 〇 · 3 microns to 〇 · 5 microns) of nitride / thickness between 〇 2 microns to 1.2 2 槪 meters (preferably between 0.3 microns and 〇 · 6 microns) of oxide, which The type of edge-preserving layer 34 is typically overlaid on a metal connection line formed of copper, wherein the metal-connected green line formed of copper typically includes electroplating, chemical mechanical polishing, and damascene processes. In addition, the oxide layer in the above two examples may be a cerium oxide or a plasma-reinforced tetraethyl orthosilicate (plasma-enhanced tetrae) formed by plasma-assisted chemical vapor deposition (plasma-enhanced tetrae) Oxide, oxygen >fb formed by -density plasma. The above is applicable to all embodiments of the present invention. Referring to Figure Id, the protective layer 34 forms at least one opening 36, The opening 36 of the protective layer 34 is formed by wet etching or dry etching, wherein dry etching is preferred. Further, the opening 36 has a size of between 1 μm and 200 μm and is Preferably, the opening of the micro-port is between 1 micrometer or 5 micrometers to 3 micrometers, and the opening 3 (four) is shaped like a circle, a square, a rectangle or a polygon, so the size of the opening 36 is a circle. The diameter dimension, the length of the square, the longest diagonal dimension of the polygon, or the width dimension of the rectangle. The length dimension of the rectangle is between micron and i, and is between 5 micrometers and 200 micrometers. Good. Eight insured The opening 36 of the sigh layer 34 also has a different size for the components provided in the component layer 12. 'In general, the size of the opening 36 of the protective layer 34 is between 〇. 微米 micrometers to _micrometers, 18 200843075 and by means of 介3 micron to 30 micron is preferred; if the component layer 12 is provided with a voltage regulator 'V'. ' ':: - - . For the race, transformer and ESD protection circuit, the size of the opening 36 Larger, the range is from 1 micron to 15 〇 米 4 4 ' 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 。 。 。 。 。 。 。 。 。 。 。 。 。 Mat (metal (10)) 32, used for electric front. Factory '- . . 乂.'r.. to secure several layers of over-passivation lines or planes. Wafers 9 such as 矽 仏 仏 ^ ^ (10) 财 ^ ^ is manufactured using different generations of integrated circuit process technology, such as 丨 micron, 〇 8 microns, 〇 · 6 microns, (15 microns, 〇.35 microns 〇.25μm, North 18μm, (125μm, 〇.13μm, 丽奈米_, 65nm, 45奈求, Circuit Process Technology _ Generation is gold oxide semi-electric crystal The length of the body 14 or the length of the channel is defined by the length of the wafer. The dimensions of the wafer are, for example, 5 忖, 6 pairs, 8 pairs, 12 忖 or 18 忖, etc. Μ程丝作, this 郷 包含 contains _ ((10) ing), exposure (expQsing) and developing photoresist 'for the photoresist of the substrate 1 ,, the thickness is between 〇 1 micro-exposure wire resistance. 'Multiple of money exposure and weaving refers to the ratio of the pattern on the reticle on the wafer when the light is stretched and the solution is made on the wafer, and five times (5 χ) means The pattern on the reticle is five times the proportion of the pattern on the wafer. Scanners that use the advanced generation of integrated circuit process technology are usually four times smaller (cut size reduction to improve resolution. The beam wavelength used by the stepper or scanner is g_iine, Na^^(i-line): 248 ^^(mt,^ ,DUV),193^^(DUV) . 157^^(DUV) 19 200843075 影影--------------------------------- Road layer 24. (:c_ _ 录 。. _10 麈 麈 ^ ^ am ^ im 〇 gray body, containing greater than or equal to 〇. 3 microns of clothing dust particles _ _ too or equal to ◦ · 2 Micron gray de f no more than 75 sharp _ 灰 灰 捧 不 不 不 不 不 不 不 不 不 不 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 大于 大于 大于 大于 大于 大于 大于 大于 大于 大于 大于 大于 大于 大于 大于 大于 大于No more than 7 dust particles, containing more than or equal to 〇. i microns of dust particles no more than 35. When using copper as the fine circuit layer 24, you need to use a metal top layer (fat C is X | The pad 32 of the oil f exposed by the opening 34 of the tilting layer 34 is damaged by the pad 32 and can be used as a subsequent wafer layer including - aluminum layer 1 and _) layer, a gold ( Gol, one Titanium (Ti) layer, a titanium-tungsten alloy layer, a set of (five) layers of TaN layer or a recording (when Ni_ layer is formed), a barrier layer is formed between the copper pad and the metal top layer. The barrier layer includes titanium, titanium ▲ alloy, titanium nitride, group, nitride group 'complex (_ or ^ Guang A 〆 棒 为本 ^ ^ Ming semiconductor substrate 10, thin wire structure 22 and Bao 34, the explanation, The following is a description of the present invention, the real protection of the present invention, the P-protection layer 20 200843075, · . . . . . . . . . The structure on the protective layer in the present invention includes a stacked package, tape aut〇mated bonded (TAB), CQG (chip an glass), and tape-type die bonding. (Tape carrier package, TCP>, C0F (_p on f ilm) packaging method, and using polymer bumps to cover Chip, FC) technology is bonded to another external substrate, and the structures of the respective embodiments are respectively explained below. And the process described in the following examples of the sisters have many parts of the material and process phase, and therefore, the materials of the same components in the T examples and aspects And the system is not repeated, for example, the following pads in the real bee example 32. The aluminum material is used as the description 'but the pad, the material of 32 can also be copper, the difference is when the pad When the material of 32 includes copper metal, a metal top layer (for example, an aluminum layer) is used to protect the copper-containing pad 32 exposed by the opening 36 of the layer 34, so that the copper-containing pad 32 is protected from oxidation. Erosion damage. When the metal top layer is an aluminum layer, a barrier layer is formed between the pad 32 and the aluminum layer, and the barrier layer comprises tantalum, titanium alloy, titanium nitride, button, nitride boat, Chrome chrome (Cr) or nickel. The contents of the bottom are described in the case of a metal top layer, but those skilled in the art can be implemented by adding the metal top layer by the following examples. - · .. · · ........: . - ·. * · ... . - The first implementation lacks the first aspect: First, please refer to Figure 2a to form an adhesive barrier layer. (adhesi〇n/bari; ier iayei 〇 38 on the protective layer 34 and the pad 32 above the substrate 10; in the absence of this substrate 10 is a silicon wafer, and the adhesion barrier The material of the layer 38 may be titanium, crane, :.. 200843075 cobalt, nickel, titanium nitride, titanium alloy, bismuth, chromium, copper, chrome-copper alloy, button, tantalum nitride, formed by the above-mentioned germplasm The alloy is a composite layer composed of the above materials. Alternatively, the adhesion/barrier layer 38 may be electroplating, electr〇less plating, chemical vapor deposition or physical vapor deposition (for example, sputtering). And the thickness of the adhesion/barrier layer 38 is ^ 0. 02 0. 8 ^ 0. 05 2 degrees is formed by a method of forming a physical vapor deposition, for example, a metal sputtering process. Preferably, 2b 0. 005 2 The thickness of the strip 〇·1 to 〇·7 micro-milk-seed layer 4{) is adhering. The barrier layer 38 is formed by a method such as sputtering, steaming, physical vapor deposition, electro-mineralization or electroless galvanic. This seed layer is _ post = metal _ setting, the mouse seed (four) maid f will be under-conformed with the subsequent metal wire material. For example, when the seed layer 4 is plated to form a metal layer of copper material, the material of the seed layer is preferably made of steel; when the seed layer 40 is made of gold, the gold lion is made of gold material ^f 40 4〇^; 4〇40 The material of the shell is preferably molybdenum; when the metal layer of the button material is plated on the seed layer 40, the seed layer 40 is fine; when the layer 4G is on the Wei fiber, the seed layer 40 is made of ^ When the seed layer 4G is energized into the metal layer of the chain f, the material of the seed layer 40 is preferably a chain; when the seed layer 40 is plated to form a metal layer of nickel, the seed layer 4〇22 200843075 Referring to FIG. 2c, a photoresist layer 42 is formed on the seed layer 4, and the photoresist layer is patterned by an exposure and development process to form a photoresist layer opening 42a. In the photoresist layer 42 and exposing the seed layer 4 位 above the pad 32, the rain is performed in the process of forming the photoresist layer opening 42a, for example, by one time (10) exposure age __ or scanners. Exposure development. There are two types of the photoresist layer 42, which are: (1) liquid photoresist 'which is formed by single or multiple spin coating or printing ((4), (8), the method is formed. The thickness of the photoresist is between 3 microns and 6 microns, and preferably between 5 microns and 40 microns; and (dry film ph〇t〇resist) It is formed by a laminating method. The thickness of the dry film photoresist is between 3 Å and 300 μm, and preferably between 5 Å and 150 μm. The photoresist may be a positive-type or a negative-type, and a better-type thick ph〇t〇resist is preferred for obtaining a better resolution. An aligner or double (IX) stepper exposes the photoresist. This double (1χ) τ means that the beam is projected from a reticle (usually of quartz or glass) to the wafer. When on, the pattern on the reticle. _ ... is reduced on the wafer, and the pattern ratio on the reticle is plotted on the wafer. The proportion of the case is the same. The wavelength of the beam used by the aligner or double stepper is 436 g-line, 397 nm (h-line), 365 nm (i-line), g/ h line (in combination with g-iine and h-line) or g/h/i line (in combination with g-line, h-line and i-line). Use beam wavelengths of g/h line or g/h/i line Double stepper (or double aligner) provides greater light intensity over exposure to thick photoresist or thick photosensitive polymers (200843075 . . . . . . In addition, the shape of the opening 42a of the patterned photoresist layer 42 may also include a shape of a coil, a square, a circle, a polygon, or an irregular shape. ^ : . / ' · · , as shown in Figures 2d and 2e, a metal layer 44 is formed by electroplating on the seed layer .40 in the opening 42a. The metal layer 44 is, for example, gold, copper or silver. , palladium, platinum, rhodium, ruthenium, iridium or recorded single-layer metal layer structure or composite metal layer structure, the thickness of the metal layer 44 is between 1 micrometer and 20 micrometers, preferably the thickness can be between L 5 micrometers Between 15 microns, and complex The combination of the combined metal layer structure includes a combination of copper/nickel/gold, copper/gold, copper/nickel/palladium, and copper/nickel/turn, in which the metal layer 44 is a single layer and the metal layer 44 The material is gold. Two regions are defined on the surface of the metal layer 44. The two regions are respectively a wire bonding pad 44a and a wire bonding pad 44b. The wire bonding pads 44a and 44b can provide a wire bonding function in a subsequent process, and the wire bonding pad 4 4牝 Viewed from a top perspective view (Fig. 2e), the position of the wire bonding pads 44a, 44b is different from the position of the pad 32. The substrate 1 below the wire bonding pad 44a or the wire bonding pad 44b may be provided with at least An active component, which includes a diode, a transistor, etc. The active component has been described in detail in the above component layer 12, and will not be repeated here, and the position of the wire pad is used for her and her position. It can be placed above the interface 32. As shown in Figure 2f, the position of the wire and the lug can vary depending on the user's needs. Referring to the second figure, the patterned photoresist layer 42 is removed, wherein the patterned photoresist layer 42 can be removed by using an organic solvent, such as _, alcohol, etc., and can also be removed by using an inorganic solvent, such as sulfuric acid. And hydrogen peroxide (_4, flank), etc., and the patterned photoresist layer 42 can also be removed by high pressure oxygen (〇2) burning. Referring to FIG. 2h, the seed layer 4〇 under the metal layer 44, the adhesion barrier 24 200843075 i 38 /, and the material of the sub-layer 44 are metal enamel, and the iodine-containing _ can be used. The pain is removed, and the way to remove the adhesive barrier layer 38 is divided into a dry type 働-wet side, wherein the dry side is used to remove % by using hydrogen peroxide. Referring to FIG. 2i, a patch 44a, 44b on the raft layer 44 is formed to form an assembly 44 Ji ^ iiit «^(exp〇sur^ Λ «^Cdevelopment) t^^ 46 Π 46a π 46a, Then, the heat curing is performed to make the polymer layer 46 hard. The temperature of the hardening process is between (8) and 3 (8), and the material of the polymer layer 46 may be selected from the group consisting of polyimine. P〇lyimide, ρι), benzocyclobutene (BCB), parylene, epoxy-based material, such as epoxy resin or by Swiss ph〇t〇epoXy SU-8, elastomer, such as silicone, provided by Sotec Microsystems of Renens. When the polymer layer 46 is a photosensitive material, the polymer layer 46 can be patterned by using only a lithography process (without cutting to the process). Please refer to the figure 2j for the 2nd figure only the wire pads 44a, 44b and the 2i figure are not wide: v.: . ' '; . - ., ··· ::: -·;:· ν 卜—r. : Again, Figure 2j again shows that the position of the wire connectors 44a, 44b may vary depending on the user or product design needs. : . . / / _ - ' . , - - . , v Please refer to Figure 2b for the step of cutting the substrate 10 to produce a plurality of semiconductor wafers (chip) 48 ° 25 200843075 to complete the fabrication of the semiconductor wafer 48. The integrated circuit 49 underneath will represent the various structures below the pattern 34 to the second layer. That is, the integrated circuit 4 includes a base substrate, a germanium layer 12, a gold oxide semiconductor transistor 14, a source electrode 16, a drain electrode 18, a dummy electrode 2, a thin circuit structure 22, a thin circuit dielectric layer 26, and a conductive plug. 30 and so on. Referring to FIG. 21 and FIG. 2m, the semiconductor wafer 48 includes a first semiconductor wafer 48a and a second semiconductor wafer 48b. The first half wafer 48a and the second semiconductor wafer may be from the bottom of the county. 1〇 or different substrates 1〇, or the first semiconductor wafer and the second semiconductor wafer 48b may have the same or different structural design; and the first half-length wafer 48a is adhered by an adhesive (for example, epoxy resin). On a first external circuit 52, the first external circuit 52 includes a printed circuit board, a metal substrate, a glass plate, a flexible substrate, a ceramic substrate, and a substrate. In this embodiment, the external circuit 52 It is a printed circuit board, and the first external circuit 52 has a plurality of connection pads 52a. Similarly, the lower surface of the second semiconductor wafer is adhered to the polymer layer 46 on the first semiconductor wafer 48a by using an adhesive 50, wherein the first semiconductor wafer is at least 1% up to the area (the area is exposed, and the first The exposed area of the semiconductor wafer 48a includes the first rotating wafer of the first wire wafer 44a and the wire bonding pad 44b. Referring to the second FIG. 2', the same adhesive layer 5 () will be used - the second external secret % lower surface adhesion stack The second external circuit is disposed on the polymer layer 46 of the second semiconductor wafer 48b, and the second external circuit is selected from the group consisting of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a secret plate. The second external circuit 54 is a broken chip, and the second external circuit % has a plurality of connection pads 54a 〇 26 200843075. Please refer to FIG. 2 to form a plurality of wires 56 on the first semiconductor wafer 48a by a wire bonding process. The wire bonding pad 44a and the wire bonding pad 44b, the second semiconductor wafer nano wire bonding pad 44a and the wire bonding pad 44b, and the connection of the first external circuit 52 are connected, and the connection pad 54a of the second external circuit 54 is connected. on, The wire for tearing the first semiconductor wafer is connected to the connection pads 52& of the first external circuit 52, so that the wire bonding pads 44b of the first semiconductor wafer 483 and the second semiconductor wafer 481 are connected to each other. The connection between the bonding pads 44b of the second semiconductor wafer 48b and the second external circuit 54 is interconnected, wherein a portion of the second semiconductor wafer 48b is connected to the wire 44a and a portion of the second external portion. The connection pads 54a of the circuit 54 and the portion of the first external circuit 52 are connected to the pad (not shown). Referring to FIG. 2p, the first semiconductor wafer stealing, the second semiconductor wafer 48b, the first external circuit 52, and the second external circuit 54 of the wire bonding process are packaged to form a polymer protective layer 58. On the first semiconductor wafer 48a, the second semiconductor wafer nano, and the first outer cake 52, the reading layer 54 is made of epoxy L resin. The second bear of the first embodiment: the structure and manufacturing method of the second aspect and the first! The structure and manufacturing method of the aspect are quite similar, so the materials and processes of the same components in the following embodiments and aspects are not repeatedly described, wherein the integrated circuit 59 will represent the protection in the 3a to 3n. Layer 34 - various structures below. That is, the integrated circuit 22 includes the base 10, the element layer 12, the MOS transistor 14, 27 200843075 ... · * ·, ',:.'", .: .:;. ' ' ;: - ·· v :··^ ; , 琢 I6, 愚极 I8, 闸?_等丄.."Λ;" . · .•... -* · . . . . ·. . . '. . . . , . . . ' . . . . . . . Γ 第 第 , , , , , , , , , , 形成 形成 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物The polymer layer is 6〇, .....,. .八. .... The acid 212 is in the whole, the bottom of the 10 polymer layer of the Fengfang suppresses the word pad 324; the (four) shape scales the poor service 0Q5 Between micro# and transcripts (better than *.^micron to 〇. 7 micron milk about one kind of pre-layer (S眯d丨ayer) 64 on the entire _ _ / barrier layer 62. ; - , * . . . . , . . . ' - .3c ^ B 66 64 i / (exposure) and development process to pattern the photoresist layer 66 to form the photoresist layer opening 66a in the light The seed layer 64 is disposed in the resist layer 66 and is disposed above the pad 32, and in the process of forming the photoresist layer opening 66a, for example, a stepper or a scanner. Line exposure development. . . - . I Please refer to Figures 3d and 3e to form a metal layer 68 in the opening 66a . . . . . , inside and seed layer. The upper metal layer 68 is, for example, a single metal layer structure of gold, copper, silver, handle, turn, 姥, 舒, 銶 or nickel or a composite metal layer structure, the thickness of the metal layer 68 being between 丨 micron to 20 microns... preferably a thickness of between 15 microns and 15 microns, and a combination of composite metal layer structures including copper/nickel/gold, copper/gold, copper/nickel/copper/nickel/platinum, etc. In this embodiment, the metal layer 68 is a single layer, and the metal layer 68 is made of gold. The metal layer (10) defines two regions on the surface, and the two regions are a wire bonding pad 68a and a wire bonding pad (4). This line 28 200843075 (4) 8a, in the subsequent process can provide the line of riding, this line is connected to the café, from the perspective of the ugly, the line is connected to the 如6, the coffee position is different from the position of the pad 32, which is the line At least one active component can be placed on the base 1 below the pad or the wire, and the transfer is based on 12 k rotation. _Discussion. Please refer to the figure below to remove the pattern of the resist layer β6 and remove the seed layer 64 that is not under the metal layer 68, and the adhesive barrier layer 62 〇 The layer 70 is in the polymer layer 6〇 and the metal*,. >~: · · · · _ , , , ... layer 68 on the 'female overexposure (expos (10)), apparently difficult to win (10) The layer 70' causes the polymer layer 7 to form a plurality of openings, and the opening a7〇a is exposed. . . . 'the wire bonding pads 68a, 68b on the metal layer 68, followed by heat hardening, ^ 70 hardening. Referring to Figure 3h, the substrate 1 is subjected to a dicing step to produce a plurality of semiconductor chips 72. Referring to FIGS. 3ι and 3j, the semiconductor wafer 72 includes a first semiconductor wafer 72a gray-second half-wheel wafer 72b; wherein the first semiconductor wafer 72a and the second single-conductor-day sheet 72b匕 from the same substrate 10 or different substrates, or the second semiconductor worm chip 72a Friend second semi-conductive wafer 72b may be the same or different in structural design; reuse an adhesive 74 (such as epoxy resin) to win the first The special wafer 72a is projected on a first external circuit %, and this first '1 f ' .I. one by one ~ -, -v-. ··., . external % base 76; : ; ' ; The adhesive layer 74 is also used to stack the lower surface of the second semiconductor wafer on the first Fengqian body wafer 72a & the polymerization preparation layer 70, wherein the anode conductor wafer 72a has at least 1% to 1%. The area of the area of the semiconductor wafer 72a exposed by the area of the 200843075 includes the first semiconductor wafer 7 such as the bonding pad 68a and the bonding pad 68b. Ming Duo read the 3k figure, also using the second external circuit 78 lower surface 72b 70 k from the printing, private circuit board, metal substrate, glass substrate, flexible substrate, ceramic substrate and Shi Xi The substrate tt 78 a ^ , 78 has a plurality of connection pads 78a ., . . . . . . . ', ··,... Please refer to Fig. 31 to form a plurality of wires by a wire bonding process, such as the connection of the first external circuit 76 on the first semiconductor crystal A 72a 68b Ji > 72b pad 68a and the wire bonding pad 68b. On the pad, the connection pad 78a of the second external circuit 78, the bonding pad 68a of the first semiconductor wafer 72a and the connection pad 763 of the first external circuit 76 are connected to each other, so that the bonding pad 68b of the first semiconductor wafer 723 is connected. Connected to the bonding pads 68a of the second semiconductor wafer 72b, such that the bonding pads 68b of the second semiconductor wafer 72b and the connection pads of the second external circuit 78 are connected to each other, wherein there is a small portion of the second semiconductor wafer. The connection pads 78a of the second wiring circuit 78 of the 72b, the connection pads 78a of the second external circuit 78 are connected to the connection pads 76a of the first external circuit 76 (not shown). Referring to FIG. 3m, the first semiconductor wafer Wa, the second conductive conductor wafer 72b, the first external circuit 76, and the second external circuit 78 of the wire bonding process are packaged to form a polymer protective layer 80. On the first semiconductor wafer 72a, the second semiconductor wafer 72b, the first external circuit 76, and the second external circuit 78, each of the polymer protective layers 80 is, for example, an epoxy 30 200843075 resin. Example 1: Reconstruction of the structure: The structure and production method of the Fenix and the process are not repeated. The structure and production method of the third aspect are similar to the second aspect. Miscellaneous phase _ component material 0 0 2 __ 2 W café - 帛 - cut-off board, and another second external circuit is placed on the upper semiconductor wafer, through the plurality of wires to make 2 semiconductor wafers, - The external circuit board and the first: Lai Road are connected to each other. The structure of the third secret is composed of the first & ^ 4a 4 82a. 82b. 82〇 ^ ^ ^ board 84 and the second external circuit 86, wherein the fourth semiconductor wafer version, which, version, 82d process and material are like The process and material of the second aspect (as shown in the figure to the first cell diagram), the semiconductor wafer fabricated by the process of the second aspect has a wire bonding and wire bonding pad 88b' half V body wafer 82b The wiring board has a wire bonding terminal 9a and a wire bonding pad, the semiconductor wafer 82c has a wire bonding terminal (4) 2a and a wire bonding pad 92b, the semiconductor wafer 82d has a wire bonding terminal 94a rib wire pad 94b, and the first outer circuit board 84 has a connection. The pad 84a, the second external circuit 86 also has a connection pad 86a. In the process, the semiconductor wafer is first disposed on the first external circuit board by using an adhesive. Then, the semiconductor wafer 82b is sequentially stacked on the semiconductor wafer 82a by using an adhesive. The semiconductor wafer 82c is stacked on the semiconductor wafer 82b, the semiconductor wafer 82d is stacked on the semiconductor wafer 82c, and the second external circuit 86 is stacked on the semiconductor wafer 82d-soil, wherein the semiconductor 31 200843075 wafer 82a, semiconductor wafer 82b and semiconductor wafer At least 1% to 10% of the area of the 82c is exposed, and at least 1% to 70% of the semiconductor wafer and 82d are exposed, and the exposed surfaces of the semiconductor wafer 82a, the semiconductor wafer 82b, the semiconductor wafer 82c, and the semiconductor wafer 82d are also exposed. At the same time, the wire bonding pads 88a, 88b, the wire bonding pads 90a, 90b, the wire bonding pads 92a, 92b, and the wire bonding pads 94a, 94b are exposed. Referring to FIG. 4b, the plurality of wires 96 are formed by the wire bonding process on the semiconductor wafer 8 such as the bonding pad 88a and the bonding pad 881), the bonding pad 9 of the semiconductor wafer 821), and the bonding pad 90b. The connection between the bonding pad 92a of the semiconductor chip 82c and the bonding pad 92b, the bonding pad 94a of the semiconductor wafer 82d, and the bonding pad 94b, the connection terminal 84a of the first external circuit board 84, and the second external circuit 86 are connected. On the pad 86a, the bonding pads 88a of the semiconductor wafer 82a and the connection pads 84a of the first external circuit 84 are connected to each other, and the bonding pads 88b of the semiconductor wafer 82a and the bonding pads 90a of the semiconductor wafer 82b are connected to each other. The bonding pads 90b of the semiconductor wafer 82b and the bonding pads 92a of the semiconductor wafer 82c are connected to each other, and the bonding pads 92b of the semiconductor wafer 82c and the bonding pads 94a of the semiconductor wafer 82d are connected to each other to make the dummy pads 94b of the semiconductor crystal 82d and The connection pads 86a of the second external circuit 86 are connected to each other. The connection port 86a of the portion of the second external circuit 86 and the connection port 84a of the first external circuit board 84 are connected to each other. The wire bonding pad 90a of the semiconductor wafer 82c and the wire bonding pads of the partial semiconductor wafer and the connection wiring of the first external circuit board 84 are connected to each other (not shown). As shown in the figure, the semiconductor wafers 82a, 82b, 82c, 32 200843075 82d, the first external circuit board 84 and the second external circuit 86 which complete the wire bonding process are packaged to form a polymer money industry. The material of the layer 97 is as follows: the second embodiment of the second embodiment, _ see, _2 〇, fine _ structure 22, fine line Jiexian ^ ^ body: · '100 _, and the integrated circuit into each Structure and Process In the above implementation, it has been said that the various structures and processes in the integrated circuit 100 of the display system are not as good as those of Liu. Please: _ Figure 5a, forming - polymer is 12 The entire integrated circuit should be on the protective layer 34 and the pad 32. Please refer to Figure 5b, and through the exposure (e chature), Gu Ying (devel process and last name engraving process to pattern the polymer layer 112, The polymer layer 112 is formed into a plurality of openings n2a and a plurality of polymer bumps 114 (only one is shown in the figure) The opening 112a exposes the protective layer 34 and the pad 32, and then heat hardens to harden the polymer bump 114. The temperature of the hardening process is between 150 degrees (between 〇 and 300 degrees). The material of the polymer bump Π4 may be selected from the group consisting of polyiimide (PI), benzocyclobutene (BCB), parylene, and epoxy materials. · · - . . . One of the epoxy-based materials, such as epoxy resin or photoepoxy SU-8, elastic material (eiast〇mer) from Sotec Microsystems, Renens, Switzerland. For example, silicone. Where the polymer layer 112 is a photosensitive material, the polymer layer 112 can be patterned by a lithography process (without an etching process) only for 33-200843075, and the polymer bump 114 has a thickness of 5 micrometers to At 50 microns, the polymer bumps 114 have a maximum lateral dimension of between 1 micron and 60 microns. - · . .; , . . , ' ... . . . See the 5c chaos, forming an adhesive barrier layer (adhesion/barr cut r layer) 116 in the whole body mold road 1〇〇 The upper protective layer 34, the pads 32 and the polymer bumps 114. In addition, the adhesion/bile & layer 116 can be formed by electroplating, electroless electrolysis, chemical vapor deposition or physical vapor deposition (for example, splashing clock), wherein the heterogeneous gas phase The frequency is preferably formed, for example, the metal fiber is light. Further, the thickness of the adhesion barrier layer m is between 微米 2 μm and 〇. g μm, and the thickness between the 〇·撒微枣 is preferred. - '·. Months> See the picture shown in Figure 5d, and then form a seed with a thickness between 0·005 μm and 2 μm (between 〇·1 μm and 〇·7 μm) The seed layer 118 is on the adhesion/resist layer 116, and the seed layer ι8 is formed by, for example, inspection, steaming, physical vapor deposition: the electrician is unintelligible, for example, when the seed layer 118 When electroplating to form a metal layer of copper, the seed layer and the material are pleasing, and the remaining material is better; when the seed layer 11δ is plated to form the metal layer of the material, the seed layer 118 is privately inserted. It is better to use 糸 糸 ;; when the seed layer 118 is electrically broken, the metal layer of the white material is formed, and the seed layer ▲ is all turned into a hot recording system; when the seed layer 118 is plated to form a metal layer of the money material , seed layer 118 work 1 correction material t, when the seed layer m is charged to the metal layer of the material of 2008, 2008, 75, the material of the seed layer 118 is preferably ;; when the seed layer 118 is electroplated to form a metal layer of 銶 质The material of the layer 118 is preferably a chain; when the seed layer 118 is plated to form a metal layer of nickel, the species Sunburn layer 118 preferably nickel-based material. Referring to FIG. 5e, a photoresist layer 1 is formed on the seed layer 118, and the photoresist layer 12 is patterned by an exposure and development process to form a plurality of photoresist layers 120a. The photoresist layer 120 is exposed on the seed layer 118 above the pad 32 and the polymer bumps 114, and in the process of forming the photoresist layer opening 120a, for example, it is doubled (1χ). . , #的预机 (steppers) or scanners (scanners) for exposure and development. There are two types of the light sister layer 120, which are: (1) liquid photoresist, which is formed by single or multiple spin coating or printing. The thickness of the wet film photoresist is between 3 micrometers and 60 micrometers, and preferably between 5 micrometers and 40 micrometers; and (2) dry film photoresist, which utilizes stickers The laminating method is formed. The thickness of the dry film photoresist is between 3 〇 1 ' . . . . . . . between 300 μm and preferably between 5 μm and 150 μm. In addition, the photoresist can be positive-type or negative-type, and in obtaining a better ' _ . - . . . . . (p0Sitive-type thick photoresist) is preferably used to expose the photoresist by an aligner or a double (IX) stepper. This double (lx). · , · .. means that when the light beam is projected onto the wafer from a reticle (usually composed of quartz or glass), the reticle is ' ' . . . " ' . ... : The pattern of the image is reduced on the wafer, and the pattern ratio on the reticle is the same as the pattern on the wafer - ., - . . . . . . . . . The wavelength of the beam used by the aligner or double stepper is 436 nm... , . . . (g line), 397 nm (h-line), 365 nm (i- Line), g/h line (in combination with g-line 35 200843075 .-- ' : - · v * . · ... , · · .. .., . . . . . _ .... .. :. with h-line) or g/lj/i line (combined with g-line, h-line and i-line). Use a double-stepper (or double-aligner) with a beam wavelength of g/h line or 8/11/丨1 fat for exposure to thick photoresist or thick photosensitive polymer (photosenstive polymer) Providing a larger light intensity; in addition, the shape of the opening 12〇a of the patterned photoresist layer 120 may also include a coil shape, a square shape, a circular shape, a polygonal shape, or an irregular shape. Referring to FIG. 5f, a metal layer 122 is formed by electroplating on the seed layer 118 in the opening i2〇a, and the Jr layer 122 covers at least the seed r layer above the two surfaces of the polymer bump 114. 'The metal layer 122 is, for example, a single metal layer structure of gold, copper, silver, la, gu, ruthenium, iridium, or nickel or a composite metal layer structure having a thickness of 1 micron to 20 microliters, preferably between 1.5 microns and 15 microns thick, and the combination of composite metal layer structures includes copper/nickel/gold, copper/gold, copper/nickel/copper, and copper/nickel/platinum combinations. In this embodiment, the metal layer 122 is an early layer 'the metal layer 122 is made of gold, and the surface of the metal layer 122 located on the polymer bump H4 is a bonding interface 124.塾124 can be used to connect external circuits. (Refer to FIG. 5g, removing the patterned photoresist layer 120 and removing the seed layer 118 and the adhesion barrier layer 116 that are not under the metal layer 122. See the 5th figure of the brothers. Performing a dicing step to produce a plurality of semiconductor chips 126 'the bonding pads 124 on the semiconductor wafer 126 can be via tape automated bonded (TAB), COGC chip on glass) 6 . - · .-.. .... ' ;

The carrier package (TCP) or C0F (chip on film) is connected to an external circuit 128 having at least one bonding metal layer 129 to which the bonding pads 124 are connected to the bonding 36 200843075 metal layer 129. As shown in Fig. 5, the present embodiment is connected to the external circuit 128 in a C0G manner, and the bonding pads 124 on the semiconductor wafer 126 are bonded to the bonding metal layer 129 of the external circuit 128 by the anisotropic conductive pads 130. Referring to FIG. 51, if the embodiment is connected to the external circuit 128 by the cop method, the bonding of the semiconductor wafer 126 is also performed by the anisotropic conductive paste 130. The pad 124 is bonded to the bonding metal layer (2) of the external terminal 128, and the other mode of bonding is shown in the drawing, which is a method of bonding the semiconductor chip 126 by thermal compression bonding. Bonded to the tin-containing outer boundary circuit 128, the gold on the bonding interface 124 and the tin layer 132 on the bonding metal layer 129 are thermally bonded to form a tin residual alloy layer 134, which is thermally bonded. The bonding method can also be applied to tape automated brace (TAB) and roll Y-type die bonding (TCP). .. , _ . - . . . The second bear description of the IH embodiment: v The structure and manufacturing method of the second aspect are quite similar to the structure and manufacturing method of the first aspect, so the following embodiments and aspects The material and process of the same components in the middle are not repeated. - - , , . . . , . . . . . . . . . . . . . . . See the picture shown in Figure 6a, the second aspect and the first The difference in the aspect is that the bumping circuit 100 of the second aspect has two pads 32, 32, and the protective layer of the polymer layer 112 on the entire integrated circuit 100 is also formed on the pads 32, 32. . . ; : * * _ Please refer to Figure 6b and pattern the polymer layer 112 by exposure, development, and the process of etching. The layer 112 forms a polymer bump (polymer b_) 114 (only i is shown in the drawing), the opening 112a exposes the protective layer and the pads 32, 32', and then heat hardens to make the polymer The bump 114 is hardened. When the polymer bump 114 is a photosensitive material, the polymer bump 114 can be patterned by using only a lithography process (without an etching process), and the thickness of the polymer bump 4 is between 5 micrometers and 5 turns. The micron, polymer bumps 114 have a maximum lateral dimension of from 1 micron to 6 microns. As shown in FIG. 6c, the adhesion barrier layer iayer) is formed on the protective layer 34, the pads 32, 32, and the polymer bumps ι14 on the entire integrated circuit 100, and the adhesion barrier layer 110 is formed. The thickness is preferably between 微米·〇2 μm and 〇·8 μm, and is preferably between 〇5 μm and 0.2 μm. Referring to Figure 6d, a seed layer 118 having a thickness between 0.95 μm and 2 μm (preferably having a thickness between 0.1 μm and 〇·7 μm) is formed. On the barrier layer 116. Referring to FIG. 6e, the photoresist layer 120 is formed on the seed layer 118, and the photoresist layer 120 is patterned by an exposure and development process to form a plurality of photoresist layer openings 120a, 120b. A seed layer 118 is disposed within the photoresist layer 120 and overlying the pads 32, 32, and the polymer bumps 114, respectively. . . . . . ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The layer 122 covers at least the seed layer 118' above the two surfaces of the polymer bumps 114, and the metal layer 122 is a single metal layer structure or composite of gold, copper, silver, palladium, ruthenium, iridium, ruthenium, iridium or nickel. a metal layer structure having a thickness of 1 micron 38 200843075 to 20 micrometers, preferably between 1.5 micrometers and 15 micrometers thick, and a composite metal layer structure comprising copper/nickel/ Gold, copper/gold, copper/nickel/copper, and copper/nickel/turned combination. In this embodiment, the metal layer 122 is a single layer, and the metal layer 122 is made of gold and is located on the surface of the metal layer 122. The two regions are defined as a bonding pad 124 and a wire bonding pad 136. The bonding pad 124 is fastened on the polymer bump 114, and the wire bonding pad 136 is located on the pad 32. The bonding pad 124 and the bonding wire are defined. The pads 136 can be used to connect external circuits. Referring to FIG. 6g, the patterned photoresist layer 12 is removed and the seed layer 118 and the adhesion barrier layer 116 that are not under the metal layer 122 are removed. Referring to FIGS. 6h and 6i, the integrated circuit 1 is subjected to a dicing step to generate a plurality of semiconductor chips 126. The bonding pads 124 on the semiconductor wafer 126 can be flipped (Flip Chip, FC). The technology is bonded to another external substrate 138, such as a germanium semiconductor wafer. When the external substrate 138 is a semiconductor wafer, the external substrate 138 has a plurality of bonding pads 140 having a bonding gold on the bonding pads 140. The bismuth layer 142, the material of the bonding metal layer 142 comprises a single metal layer of gold, copper, silver, free, turned, bismuth, bismuth, antimony, tin or nickel: a composite or a composite metal layer structure, the bonding metal The layer 142 will change with the material of the metal layer 122. For example, the material of the Jinlin 122 is gold, and the metal of the Jinlin 142 is a metal layer of gold or tin, and then the chip is laminated (10) P, P, FC The technique is to be disposed on the semiconductor wafer 126, wherein the bonding is performed by means of thermal fusion bonding, such that the bonding metal layer 142 and the metal layer 122 are fused or alloyed (gold/gold bonding or gold-tin alloy). And ^m^ l38 126 144 , , b encapsulation layer 144 material A polymer-based material, such as an epoxy resin. In addition, the wire bonding pad (10) 39 200843075 .... eight ':·. · ;, v - · . . . Μ is formed by the wire-making process - the wire I46 is connected to another external paper _ not shown. Read the reference list, in addition to the wire connection _6 in addition to _ wire ^ winter wire 146 connection $ another - external circuit, φ can be connected to the outer circuit of the solder ball 147, the thickness of the tin bar W is different Between micron and _ micro-depletion, the film connection can be joined by the way of the green. The third state of the second embodiment: the structure and manufacturing method of the 笫3 aspect and the second aspect and the second aspect The structure and manufacturing method are quite similar, so the materials and processes of the same elements in the following embodiments and aspects are not repeated. Referring to FIGS. 7a and 7b, the difference between the third aspect and the second aspect is only that the position of the wire bonding pad 136 is different, and the position of the wire bonding pad 136 of the third aspect is from a top perspective view. 9b)), the position of the wire bonding pad 136 is different from the position of the pad 32', wherein at least one active component may be disposed on the substrate 1 in the integrated circuit 100 below the wire bonding interface 136, and the active component includes The 'active elements of diodes, transistors, etc. have been described in detail in the above-mentioned element layer 12 and will not be repeated here. The fourth aspect of the second embodiment: The structure and manufacturing method of the fourth aspect are quite similar to those of the third aspect and the first aspect, and therefore the same components in the following embodiments and aspects The materials and processes are not repeated. 200843075 V ·- · · ·' ·: . V ' . ' . * ' . / ' ·· . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . / . *; - ·. : . i · _.:.; ' , - , please refer to the appearance of the post-fermentation, the same shape of the literate layer 112 on the full-width flag body t road lOQ. ' 1 广··..," . . : Guarantee layer 34 and money pad 3; and selection pad 32, on. Read.: 8b _ (four) shows, and led the exposure, display the curtain release plowing map game bjfc complex layer 1 丨 2 into this gathering layer 112 shape ...- * - : ; ; . . . . . ; : · '* ^ " - 4 v^ ,"; - ' - "- . . , * ·. - . · - , - :' . . .. "...· ·,. The long-numbered polymer island road ^ (four): and the selection of the calendar Θ Θ 热 热 热 热 热 热 热 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物 聚合物❻度彳^冬间^真聚聚物块丨复义神^ ^ I from I Liang 舜 release (poly(五)♦ 'PI), phenylcyclobutene i (fylene + (parylene), epoxy One of the base materials (ep0Xy-based material), such as cycline yttrium is from, dry, i, Renens: Sot printed Micfosystenis, provided photoepoxy SU-8, elastic material (elastomer) 'eg seconds Silicone, wherein when the polymer layer 112 is a photosensitive material, the polymer layer 112 can be patterned using only a lithography process (without an etching process), and the polymer block 148 has a thickness of 5 micrometers to 50 degrees. Micron. ·: .. . . . . . . . . . .: " ., 5 Fen sees the younger 8c figure and the younger 8d figure does not 'then form another polymer layer 150 in the polymer. VV · ; ; . . . ; ; - - ... :;·;::, ··: : ^ ; C : 148 and the opening 112a, the polymer layer ί5 〇 is the same material as the polymer layer 112, and is transparent: .... %, /: , .: , . . . . :. :-- 1. Overexposure, development ((16¥61〇?1116111:) process and etching process patterning the polymer layer 150 to form a plurality of polymer bumps 152 (only shown in the figure) When the polymer layer 150 is a photosensitive material, the polymer layer 150 can be patterned by using only a microfabrication process (without an etching process), and the thickness of the polymer bump is between 5 micrometers and 50 degrees. The micron, polymer bumps 152 have a maximum lateral dimension of between 10 microns and 60 microns. :: :· Λ V ' · . , . _ , .: » . , , ' . · . : · ;'· ... ^ : : : : . ' ; :v- , , ' . . " . V. :- ' : Please refer to Figure 8e to form an adhesion/barrier layer 116 200843075 throughout the integrated circuit 100 Upper pad 32, pad 3 2, polymer convex 148 on. ”Opening Figure 81, Figure 0. Then forming a seed layer with a thickness between 〇〇〇5 μm and 2 μm (between 0.1 micron and 7 μm) (see6_^ barrier layer) 116 & read as shown in Figure Sg, forming a light spleen layer, then cutting the soil layer, and patterning the photoresist layer 120 by exposure (-〇'e) and development process to form a plurality Light, take the Espresso Resist and remove the seed layer 118 above the pad bump 152 and the polymer block _, while forming the photoresist layer opening 12〇a. .. - / . . · · * In the know, for example, the exposure machine (steppers) or scanners (X) are used for exposure and development. Please refer to Figure 8h to form a metal layer by electroplating. 122, on the seed layer 118 in the opening 120a, the metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bump 152, and the metal layer 122 is, for example, gold, copper, silver, palladium, platinum, rhodium, iridium. , single-layer gold v-layer structure of chain or nickel or composite Yitai genus structure, the thick skin of this 浚13⁄4 is between 1 micron and 20 辗, which is thicker than Cui's thickness _#1:5 Micron to 15 microi, and composite 1 genus subtractive group consists of steel/巍73⁄4, :/gold, copper/nickel/palladium, and copper/nickel/platinum. This metal is used in the i itb example. Xiu Zhao 2 series 'single layer, and the metal layer 12f is rich in gold, _ in the polymer *, *. _ , , ' · · · - '. , * *, > χ * _., * metal The layer 122 defines an area as a joint pad 24, and the joint pad 1 is green spear-heating #, and the surface of the metal layer I22 located on the layer 148 is taken as a line connection #136 The 耔 接 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 The thinner substrate ίο has sufficient buffering effect, so that the substrate iq of the integrated circuit (10) and the active component of the component layer 12 are damaged in the wire bonding, and the embodiment is connected by the upper perspective view. The position of the pad I48 is different from that of the interface 32, but the wire connection can also be located at the top of the connection, and will not be repeated here. As shown in Fig. 8i, the patterned photoresist layer is removed. 12〇 and removing the seed layer 118 and the adhesion barrier layer ιι6 which are not under the metal layer eg. Referring to Fig. 8j, the integrated circuit 100 is subjected to a step of generating a plurality of semiconductor chips 126. 8k is similar to the above-mentioned 6i, and the semiconductor wafer 126 is bonded to another external substrate via Flip Chip (FC) technology, as explained in the above-mentioned 6th. So I won't repeat it here. The second state of the embodiment is: • * . · · · · · · . . . . . . . . . . . . . . . . The method is quite similar to the structure and manufacturing method of the fourth aspect, - · :·,. ' - ' , . . . The structure of the fourth sample is the change of the first aspect, so in the following embodiments and aspects The materials and processes of the same components will not be repeated. • , ; . - . · - : : ... . , please refer to Figure 9a. 'The difference between the first and the first aspect is that the exposure is Deng (10), the development, and the silver engraving process pattern. The step of forming the polymer layer 丨12 and heat hardening 'in the fifth aspect, the two steps simultaneously form the polymer block 148 and the polymer bump 114, that is, the thickness of the polymer block 148 and the polymer bump 114. The same, and the polymer block 148 and the polymer 43 200843075 bump 114 have a thickness between 5 microns and 50 microns. Please refer to FIG. 9b to form an adhesive barrier layer (adhesi〇n/barrier layer) 116 and a thickness between 0 and 005 micrometers to 2 micrometers (preferably thickness is between 〇·i micron to 0). A seed layer 118 of between 7 microns is on the entire integrated circuit 1 , 32 , pads 32 ′ , polymer bumps 114 , and polymer blocks 148 . Referring to FIG. 9c, the photoresist layer 120 is formed in the seed layer 118 (exposure) and development process to pattern the photoresist layer 12A to form a plurality of photoresist layer openings 120a in the photoresist layer 120. And exposing the seed layer 118 above the interface 32, the mattress 32, the polymer bump 114 and the polymer block 148, and in the process of forming the fine layer Zheng, for example, an exposure machine of - (IX) Steppers) or scanners are used for exposure development. Referring to FIG. 9d, a metal layer 122 is formed on the seed layer 118 in the opening 12A by electroplating. The metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bump 114. The metal layer 122 For example, a single-layer metal of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel, and the structure of the structure is a composite metal layer structure. The thickness of the metal layer 122 is between 1 micrometer and 20 micrometers. , . . . ' , the preferred thickness can be between 1.5 microns and 15 microns, and the composite metal layer structure combination includes copper / nickel / gold, copper / gold, copper / nickel / K and copper / nickel In this embodiment, the metal layer 122 is a single layer 'the metal layer 122 is made of gold, and the surface of the metal layer 122 located on the polymer bump μ defines a region as a bonding interface 124. The bonding interface 124 can be used to connect the external circuit. The surface of the metal layer 122 on the polymer block 148 defines a region as a wire bonding pad 136. The bonding wire 136 is connected to the external circuit via a wire bonding process. The wire block 136 under 44 200843075 of the polymer block 148 is hitting the green copper # + 4 crack length & The stress generated by the punching line has sufficient buffering effect on the thinner substrate 10, which can prevent the active components of the substrate 10 and the component layer 12 of the integrated circuit 100 from being wire-bonded and p' In addition, the position of the wire bonding pad 1 is different from the position of the pad 32: the wire bonding pad 136 can also be located on the pad 32, above, in this embodiment. I don’t repeat it. Referring to Fig. 9e, the patterned photoresist layer 12 is removed and the seed layer 118 which is not under the metal layer 122 is removed, and the barrier layer m is attached. Referring to Fig. 9, the integrated circuit m is subjected to a dicing step to generate a plurality of semiconductor wafers (chjp) 126. Referring to the % diagram, the 9th figure is similar to the above-mentioned 6i, in which the semiconductor wafer machine is bonded to the other external substrate 138 via Flip Chip (FC) technology, wherein the description of the bonding is as described above. The 6i diagram is the same, so it will not be repeated here. The sixth example of the embodiment can be: v 苐6 aspect structure and manufacturing method are quite similar to the structure and manufacturing method of the first aspect, : . . . . . . . Therefore, the materials and processes of the same elements in the following embodiments and aspects are not repeated. This embodiment is connected to the fifth aspect of the first aspect, and after the completion of the fifth embodiment, as shown in FIG. 10a, a seed layer of a metal layer 154 in the opening i2〇a is formed by electroplating. The 'metal layer 154' is, for example, copper, and the metal layer 154 has a thickness of from 1 micrometer to 2 micrometers, and preferably has a thickness of between 1.5 micrometers and 15 micrometers. 45 200843075 : ' ' ... - . - , ' Please refer to Figure l b, and then electroplating a metal layer 156 on the metal layer 148, the material of the metal layer 156 is nickel, the metal layer 156 The thickness ranges from 〇·i to 2 μm, and preferably from 1 μm to 15 μm. Referring to FIG. 10c: FIG. 10, another photoresist layer 158 is formed on the photoresist layer 12, the metal layer 156 . . . . . . . . . . . . . . . . And patterning the photoresist layer 158 through an exposure and development process to form a plurality of photoresist layer openings 158 & within the photoresist layer 158 and exposed over the polymer bumps 114 The metal layer 156 is exposed in the process of forming the photoresist layer opening 158a, for example, by an exposure machine (German rs) or a scanner (scanners). development. The other material forming the photoresist layer 158 may also first remove the original photoresist layer 12 (), then the resist layer 158 on the seed layer 40 and the metal layer 156, and expose (exp__e) and develop. The silk layer 158 is placed in the photoresist layer 158 and exposed to the metal layer 156 above the polymer bumps 114, as shown in FIG. L〇e 160 158a (^ 156 i ^ 160 ^#f . . tin-silver-copper alloy layer 'error-free solder, etc., the thickness of the metal layer 16〇 is between 1 micron and 3 micron, preferably thickness Between 5 μm and 2 μm. i58^i2〇^ The seed layer 118 is not under the metal layer 156, and the barrier layer is adhered. Please show the 'GG' as shown in the 1GG® reheating process to make the metal layer (10) It reaches the melting point and cohesively forms a sphere.

46 200843075 Referring to the figure ih, the substrate 10 is subjected to a dicing step to produce a plurality of semiconductor wafers (chiP) 126, and the metal layer 160 on the semiconductor wafer 12 can be bonded to the other substrate. The description of the present invention is made by way of example only, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to apply only to the scope of the invention, and not to limit the scope of the invention. Equivalent modifications or modifications made by the spirit of the present invention should still be included in the scope of the claims described below. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to _ are schematic views showing the formation of a thin wiring structure and a protective layer in the present invention. 2a to 2p are schematic views of the first embodiment of the first embodiment of the present invention. 3a to 3m are schematic views showing a second aspect of the first embodiment of the present invention. 4a to 4c are schematic views showing a third aspect of the first embodiment of the present invention. 5a to 5k are schematic views showing a second aspect of the second embodiment of the present invention. 6a to 6 are schematic views showing a second aspect of the second embodiment of the present invention. 7a to 7b are schematic views showing a third aspect of the second embodiment of the present invention. 8a to 8k are schematic views showing a fourth aspect of the second embodiment of the present invention. 9a to 9g are schematic views showing a fifth aspect of the second embodiment of the present invention. Figures 1 through l〇h are schematic views of a sixth aspect of the second embodiment of the present invention. Figure No.: 47 200843075 10 Substrate 12 Component Layer - . 14 14 Gold Oxide Transistor 16 Source 18 Deuterium. 20 Gate / 22 Fine Front Structure 24 Thin Circuit Layer 26 Thin Line Dielectric Layer 28 Opening 30 Conductive Plug 32 pad 34 protective layer 36 opening 38 adhesive barrier layer 40 seed layer 42 photoresist layer 42a photoresist layer opening 44 metal layer 44a wire bonding pad 44b wire bonding pad 46 polymer layer 46a opening 48 semiconductor wafer 49 integrated circuit 48a First semiconductor wafer 48b Second semiconductor wafer 50 Adhesive 52 First external circuit 52a Connection pad 54 Second external circuit 54a Connection pad 56 Conductor 58 Polymer protective layer 59 Integrated circuit 60 Polymer layer 60a Opening 62 Adhesive Barrier layer 64 seed layer 66 photoresist layer 66a photoresist layer opening 68 residual layer 48 200843075 68a wire bonding pad 70 polymer layer 72 semiconductor wafer 72b second semiconductor wafer 76 first external circuit 78 second external circuit 80 polymer Protective layer 82b semiconductor wafer 82d semiconductor wafer 86 second external circuit 88 b wire bonding pad 90b wire bonding pad 92b wire bonding pad 94b bonding pad 80a Pad 9f polymer protective layer 112a opening 116 adhesion/barrier layer 120 photoresist layer 122 metal layer 126 semiconductor wafer 68b wire bonding pad 70a opening 72a first semiconductor wafer 74 adhesive 76a connection pad 78a connection pad 82a semiconductor wafer 82c semiconductor wafer 84 first outer circuit board 88a wire bonding pad 90a wire bonding pad 92a wire bonding pad 94a wire bonding pad 84a connection pad 96 wire 112 polymer layer 114 polymer bump 118 seed layer 120a photoresist layer opening 124 bonding Pad 128 External Circuit 49 200843075 129 Bonding Metal Layer 130 132 Tin Layer 134 32, Pad 120b 136 Wire Bonding Pad 138 140 Bonding Pad 142 144 Package Layer 146 147 Tin Ball 148 150 Polymer Layer 152 154 Metal Layer 156 158 Light Resistive layer 158a 160 metal layer anisotropic conductive adhesive tin gold alloy layer photoresist layer opening external substrate bonding metal layer wire polymer block polymer bump metal layer photoresist layer opening 50

Claims (1)

200843075 X. Patent application garden: 1. A circuit component, including: a wide semiconductor substrate 'the semiconductor substrate has at least one metal interface; ·; ''' ... ' . . . : ' a protective layer on the semiconductor substrate, the protective layer having at least one opening exposing the metal pad; . . . - ' - · · · · *, +. ^ ? - . . . ... a polymer bump, Positioned on the protective layer; and a metal layer V is located on the protective layer, the polymer] [7] and the metal interface, the metal layer ... covers at least two surfaces of the polymer bump, via The metal layer on the polymer bump is connected to an external circuit. 2. If the scope of the patent application is wrong! I am not referring to the source. The circuit component of item, wherein the semiconductor substrate comprises seconds. 3. If the scope of the patent application is wrong, the reference source cannot be found. The circuit component of the present invention, wherein the semiconductor substrate comprises a thin wiring structure, the thin wiring structure comprises: a plurality of dielectric layers having a thickness of less than 3 micrometers, on the semiconductor substrate, and the dielectric layers have a plurality of via holes; and _. _ . . . a plurality of thin circuit layers having a thickness of less than 3 microns, and the thin circuit layers are located on one of the dielectric layers, wherein the thin circuit layers are The channel holes are electrically connected to each other. 4. The circuit component of claim 3, wherein the thin circuit layer comprises an aluminum layer having a thickness between 0. 05 microns and 2 microns. 5. The circuit component of claim 3, wherein the thin circuit layer comprises a copper layer having a thickness between 0.05 microns and 2 microns. 6. If the scope of the patent application is wrong, the reference source cannot be found. The circuit component of the item, wherein: 51 200843075 The material of the protective layer comprises a nitrogen hydrazine compound. 7. If the scope of the patent application is wrong, you cannot find the reference source. The component of claim 1, wherein the material of the protective layer comprises a phosphorous glass (PSG). ... · · · : : 8 · If the scope of the patent application is wrong! I am not referring to the source. The circuit component according to the invention, wherein the material of the ruthenium protective layer comprises an oxonium compound. 9. If the scope of the patent application is wrong, the circuit component described in the reference source may not be found, wherein the material of the protective layer comprises a oxynitride compound. 1〇·If the scope of the patent application is wrong! The reference source could not be found. The circuit component of the item, wherein the material of the carrier layer comprises a bismuth phosphorite glass (BPSG). U·If the scope of the patent application is wrong! The circuit component described in the reference source is not found, wherein the material of the metal layer includes gold. 12·If the scope of the patent application is wrong! The reference source could not be found. The circuit component of the item, wherein the material of the metal layer comprises copper. 13·If the scope of the patent application is wrong! .. . * The material of the metal layer includes silver. .. .. ' ‘ 14· If the scope of the patent application is wrong! The material of the metal layer includes platinum. - ’.. ,,-.. 15·If the scope of the patent application is wrong! The material of the metal layer includes palladium. 16·If the scope of the patent application is wrong! The material of the metal layer includes nickel. The reference source could not be found. The line component 5 described in the item, where :::;·.;-.eight. I am not referring to the source. The line component described in the item, wherein the reference source is not found. The line component described in the item, where: - - - ' -. • - · . . . , - - . . Item; the line component, its one, 52 200843075 17·If the scope of the patent application is wrong, the reference source cannot be found. The circuit component of the item, wherein the metal layer has a thickness of between 1 micrometer and 20 micrometers. 18. If the scope of the patent application is incorrect, the reference source cannot be found. The circuit component of item, wherein the metal layer has a thickness of between 1.5 microns and 15 microns. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2〇·If the scope of the patent is wrong, the reference source cannot be found. The circuit component of the present invention, further comprising a -adhesive/barrier layer between the metal layer and the metal pad. 21. The circuit component of claim 20, wherein the first adhesion/barrier layer comprises a titanium tungsten alloy layer having a thickness between 0. 02 microns and 〇 8 microns. 22. The circuit component of claim 4, wherein the first adhesion/barrier layer comprises a titanium metal layer having a thickness between 0.02 microns and 〇8 microns. The circuit component of claim 20, wherein the first adhesion/barrier layer comprises a titanium nitride layer having a thickness between 〇·02 μm and 〇·8 μm. The first adhesive/barrier layer comprises the first adhesive/barrier layer package. The circuit component of claim 2, wherein the thickness is between 0. 02 micrometers and 〇 8 micrometers. A layer of metal. 25. The circuit component according to claim 20, wherein the nitride layer is one of a thickness of from 0. 02 micrometers to 〇. 8 micrometers. The first adhesive/barrier layer comprises the first adhesive/barrier layer package. The circuit component according to claim 20, wherein the thickness is between 0. 02 micrometers and one of 8 micrometers. Chrome metal layer. 27. The circuit component of claim 2, wherein 53 200843075 comprises a layer of chrome-copper alloy having a thickness between 0. 02 microns and 〇 8 microns. 28. The circuit component of claim 2, further comprising a sub-layer between the first adhesion/barrier layer and the metal layer. ^ 29 The circuit component of claim 28, wherein = the seed layer is of the same material as the metal. 30' If the patent is illegal, the source of the reference cannot be found. The circuit component of claim 7, wherein the semiconductor substrate includes an active component underlying the polymer bump. 3U is the circuit component of claim 30, wherein the active component comprises a diode. 32. The circuit component of claim 3, wherein the active component comprises an electro-optic. 33. If the scope of the patent application is wrong, you cannot find the reference source. The circuit component of the item, wherein the external circuit comprises a printed circuit board. 34. If the scope of the patent application is wrong, the reference source cannot be found. The circuit component of the item, wherein the external circuit comprises a metal substrate. 35. If the scope of the patent is wrong, the reference source cannot be found. The circuit component of the item, wherein the external circuit comprises a glass substrate. 36. If the scope of the patent is wrong, the reference source cannot be found. The circuit component of the item, wherein the external circuit comprises a flexible substrate. 37. If the scope of the patent application is wrong! The reference source could not be found. The circuit component of the item, wherein the external circuit comprises a ceramic substrate. 54 200843075 * - ' 38 · If the scope of the patent application is incorrect, the circuit component described in the reference source may not be found, wherein the polymer bump comprises a polyimine compound. 39. If the scope of the patent application is incorrect, the reference source cannot be found. The circuit component of the item, wherein the hydrate bump comprises the substrate compound. 40. If the scope of the patent application is wrong! The circuit component described in the reference to the source is not found, wherein the polymer bump comprises a parylene polymer compound. 41. If the scope of the patent application is wrong, the reference source cannot be found. The circuit component of item, wherein the polymer bump comprises an epoxy resin. From the wrong side of applying for a patent! The reference source could not be found. The circuit component of item wherein the polymer bump has a thickness between 5 microns and 5 microns. 43. If the scope of the patent application is wrong, the reference source cannot be found. The circuit component of item wherein the polymer bump has a maximum lateral dimension of between 1 μm and 6 μm. The dielectric constant of the dielectric constant 44. The circuit component of claim 3, wherein the value is between 1 and 3. 45·—a kind of circuit components, including a semiconductor substrate having at least one first metal interface and a contact; a protective layer is disposed on the semiconductor substrate, the protective layer has at least two open metal pads and the second metal interface; exposing a read polymer bump on the protective layer; a metal layer on the protective layer, the polymer bump and the first metal pad 55 200843075 ..Ή'....^ V &quot; '.· - :./; , . - , ·. ' I ' The first layer of the cladding layer covers at least two surfaces of the polymer bump, the first metal layer includes a joint, and the dance mat is on the polymer as a block; One--::. ' '.r; ' * ;;.. ...: ';&quot;·, a + metal layer 'on the protective layer and connected to the second metal pad, the first The two metal layer soap comprises a dozen wire mats with a V. . . . . . . . , , , -〆: ' ' ' : : . . » ' · · · · · - . - . · · · · -.,····· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . For the seven Shen, the special spears to identify the missing circuit components in the 45th item, among them The conductor substrate is a circuit component as described in claim 45, wherein the semiconductor substrate comprises a fine structure, and the dream connection structure comprises: '-v_' vr . . ' ! ' -', -'- a plurality of dielectric layers having a thickness less than 3 lions, recorded on the bottom of the county, and the dielectric layers have a plurality of channel holes; and a plurality of thin circuit layers having a thickness of less than 3 microns. The thin circuit layer is located on the dielectric layer, and the fine circuit layer includes the thickness system 4&amp; the circuit component according to claim 3, An aluminum layer between 0. 05 micrometers and 2 micrometers. The thin wiring layer includes a dielectric constant 49 of the dielectric layers, as described in claim 3 A circuit component, wherein a copper layer is between 0. 05 micrometers and 2 micrometers. 50. The circuit component of claim 3, wherein the value is between 1 and 3. The material of the protective layer includes 51. The circuit component as described in claim 45, 52. The circuit component of claim 45, wherein the material of the protective layer comprises 56 200843075 a scale dream glass (PSG) 〇 __ material, including 53 · as claimed The line component of item 45, wherein one oxygen dream compound. % The circuit component of claim 45, wherein: the material of the protective layer comprises - a nitrogen oxide second compound. The circuit component of claim 45, wherein the material of the protective layer comprises a borophosphonium porphyrin. A circuit component according to claim 45, wherein the material of the first metal layer comprises metal 〇* · , t . , - .... * * , D? · The circuit component of claim 45, wherein the material of the first metal layer comprises steel. 58. The circuit component of claim 1, wherein the material of the first metal layer comprises silver. The circuit component of claim 45, wherein the material of the first metal layer comprises platinum. 6〇···································· The circuit component of claim 45, wherein the material of the first metal layer is the circuit component of claim 45, wherein the first metal layer has a thickness of 1 micron to 20 microns. The circuit component of claim 45, wherein the first metal layer has a thickness of between 1.5 μm and 15 μm. 64. The circuit component of claim 45, wherein the material of the second metal layer comprises gold. The circuit component of claim 45, wherein the material of the second metal layer comprises copper. 66. The circuit component of claim 45, wherein the material of the second metal layer comprises silver. 67. The circuit component of claim 45, wherein the reading of the second metal layer comprises turning. 68. The circuit component of claim 45, wherein the material of the second metal layer comprises a handle. 69. The circuit component of claim 45, wherein the material of the second metal layer comprises nickel. The circuit component of claim 45, wherein the second metal layer has a thickness of from 1 micrometer to 20 micrometers. The circuit component of claim 45, wherein the second metal layer has a thickness of from 1.5 μm to 15 μm. 72. (4) The circuit component described in Item 45 of the patent scope, the towel, which is viewed from a top perspective view, is not disposed. 73. The circuit component of claim 1, wherein the first wire conductor material 58 200843075 comprises gold. The circuit components as described in claim 45 of the patent scope include copper. In the middle, the material of the first wire is 5. The circuit component described in claim 45 of the patent scope, the dragon includes gold. ^ ^ 〜 'The second wire of the wire I, as described in the patent application, item 45, includes the steel ^^ ^ ^, the second wire of the wire 77. As described in claim 45 The circuit component is further composed of ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ T ' and includes a first cage and an early P layer between the first metal layer and the first metal pad.爪 肀 肀 肀 肀 肀 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利The circuit component of claim 20, wherein the first adhesion/barrier layer comprises a titanium metal layer having a thickness of between 0.02 micrometers and U 8 micrometers. The circuit component of claim 20, wherein the first adhesion/barrier layer comprises a titanium nitride layer having a thickness of from 0.02 nm to 0.8 μm. 81. The circuit element of the present invention, wherein the first adhesive barrier layer comprises a button metal layer having a thickness of from 0.02 micrometers to 0.8 micrometers. 82. The circuit component according to claim 20, wherein the first component The etched/barrier layer comprises a nitriding button layer having a thickness of between 0.02 μm and 8. 8 μm. 83. The circuit component according to claim 20, wherein the first adhesive/blocking layer The layer comprises a chrome metal layer having a thickness of from 0.02 micron to 0.8 micron. 59 200843075 .· . . , , .- . . . . , _ 8 For example, Shen Yuan; the line element dance described in the second paragraph of the patent scope, wherein the first adhesive/barrier layer has a thickness of chrome-copper alloy of 0'02 micron to 〇g micrometer. 85. The circuit component of claim 2, further comprising a first seed layer in the first viewing layer (the barrier layer 舆 the first metal layer 。. / 11:86.: ^, a metal layer is the same material. The circuit component of claim 45, further comprising a second adhesion/barrier layer in the second metal layer Between the second metal pads, the circuit component of claim 87, wherein the second adhesive/barrier layer comprises a thick germanium of 0. 02 micrometers. To a &lt;8 micron one titanium-tungsten alloy layer, the circuit component according to claim 87, wherein the second adhesive/barrier layer comprises a thickness of from 0.02 micrometers to 〇·8 micrometers. The second adhesive layer includes a thickness of 0. 02. The second adhesive layer includes a thickness of 0. 02.微米至〇. 8 micron nitride layer / 91. The circuit component of claim 87, wherein the second adhesion/barrier layer comprises a thickness between 0·〇2 μm and 〇· 8 micro-finish one metal layer. Pyr is as claimed in claim 87, wherein the second adhesion/barrier layer comprises a nitride layer having a thickness of between 0.02 micrometers and 0.8 micrometers. The circuit component as claimed in claim 87, wherein the second adhesive/blocking sound comprises a thickness of pure 02 «domain 8 reddish-silk. The circuit element as described in claim 87, wherein the second adhesion/barrier layer ^ 200843075 comprises a layer of chrome-copper alloy having a thickness of between 0.02 μm and 8 8 μm. • '95. The circuit component of claim 87, further comprising two second seed layers between the second adhesion/barrier layer and the first metal layer. For example, the circuit component described in claim 95, wherein the second seed layer is discussed; the metal layer is the same material. The circuit component of claim 45, wherein the semiconductor substrate comprises an active component standing under the wire bonding tab or the bonding pad. ί 98. The circuit component of claim 30, wherein the active component comprises a diode. 99. The circuit component of claim 3, wherein the active component comprises an electro-optic. 100. The circuit component of claim 45, wherein the first external circuit comprises a semiconductor wafer. 101. The circuit component of claim 45, wherein the first external circuit \ comprises a printed circuit board. The circuit component of claim 45, wherein the first external circuit comprises a metal substrate. , V. 乂.: 103. The circuit component of claim 45, wherein the first external circuit comprises a glass substrate. The circuit component of claim 45, wherein the first external circuit comprises a flexible substrate. The circuit component of claim 45, wherein the first external circuit comprises a ceramic substrate. '. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ^ ^ ^ ^ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The circuit component of claim 106, wherein the second external circuit comprises a printed circuit board. 109. The circuit component of claim 1, wherein the second external circuit comprises a metal substrate. 110. The circuit component of claim 106, wherein the second external circuit comprises a glass substrate. 11L. The circuit component of claim 106, wherein the second external circuit comprises a flexible substrate. The circuit component of claim 1, wherein the second external circuit comprises a ceramic substrate. 113. The circuit component of claim 45, further comprising a first polymer layer having a thickness between 2 microns and 1 micron between the protective layer and the second metal layer. 111. The circuit component as claimed in claim 45, further comprising a layer of a polyamidene compound having a thickness between 2 micrometers and 100 micrometers between the protective layer and the second metal layer. 115. The circuit component of claim 45, further comprising a layer of a phenylcyclobutene compound having a thickness between 2 micrometers 62 200843075 and 100 micrometers in the protective layer and the second metal layer between. 116. The circuit component of claim 45, further comprising a parylene polymer layer having a thickness between 2 micrometers and 100 micrometers between the protective layer and the metal layer . 117. The circuit component of claim 45, further comprising an epoxy layer having a thickness between 2 microns and 100 microns between the protective layer and the second metal layer. 118. The circuit component of claim 113, wherein the first polymer layer differs from the polymer bump by a thickness of between 1 micrometer and 10 micrometers. The circuit component of claim 45, wherein the polymer bump comprises a polyimine compound. The circuit component of claim 45, wherein the polymer bump comprises a phenylcyclobutene compound. The circuit component according to claim 45, wherein the polymer bump comprises a p-toluene polymer compound. The circuit component of claim 45, wherein the polymer bump comprises an epoxy resin. 123. The circuit component of claim 45, wherein the polymer bump has a thickness between 5 microns and 50 microns. The circuit component of claim 45, wherein the polymer bump has a maximum loose dimension of between 1 μm and 60 μm. 63. The circuit component of claim 45, further comprising a second polymer layer having a thickness between 2 microns and 100 microns on the second metal layer. 126. The circuit component of claim 45, further comprising a layer of a polyamidene compound having a thickness between 2 micrometers and 100 micrometers in the second metal layer. ... &amp;; · ' ... ^ -1 - 127 · The circuit components as described in claim 45, including a layer of phenylcyclobutadiene compound having a thickness of between 2 μm and 100 μm You are on the second metal layer. 128. If the circuit component of the bee of the patented Fanjue 45 is applied, a polyparaxylene polymer layer having a thickness of between 2 micrometers and 100 micrometers is disposed on the second metal layer. 129. The circuit component of claim 45, further comprising an epoxy layer having a thickness between 2 micrometers and 100 micrometers on the second metal layer. A circuit component comprising: a semiconductor substrate having at least a first metal pad and a second metal pad; a protective layer disposed on the semiconductor substrate, the protective layer having at least two openings Exposing the first metal pad and the second metal pad; a polymer bump respectively located on the protective layer; and a first metal layer disposed on the protective layer, the polymer bump, and the On the first metal pad, the first metal layer covers at least two surfaces of the polymer bump, the first metal layer includes a bonding pad on the polymer bump; and a second metal layer is located on the first metal pad. The protective layer is connected to the second metal pad; and a tin-containing metal layer is connected to the second metal layer. The circuit component of claim 130, wherein the semiconductor substrate comprises germanium. The circuit component of claim 130, wherein the semiconductor substrate comprises a thin wiring structure, the thin wiring structure comprising: - a one-to-one reduction m soft dielectric layer, 働 ^ On the bottom of the county, the dielectric layer has a plurality of via holes; and a plurality of thin circuit layers having a thickness of less than 3 micrometers, and the germanium circuit layers are located on one of the dielectric germanium layers. The circuit layers are electrically connected to each other by the channel holes. 133. The circuit component of claim 3, wherein the thin circuit layer comprises an aluminum layer having a thickness between 0. 05 micrometers and 2 millimeters. 134. The circuit component of claim 3, wherein the thin circuit layer comprises a copper layer having a thickness between 0. 05 microns and 2 microns. 135• The circuit components of the third item of the patent scope, wherein the dielectric layers have a dielectric constant value between 1 and 3. The circuit component of claim 13, wherein the material of the protective layer comprises a nitrogen breaking compound. 137. The circuit component of claim 13, wherein the material of the protective layer comprises a phosphorous glass (PSG) 〇f V .. · -;·. :..'.,.'.一广..·:...'广广' 138·, as described in claim 13 of the patent scope, wherein the protective layer The material includes an oxygen compound. 139. The circuit component of claim 13 wherein the material of the protective layer 65 200843075 comprises an oxynitride compound. 14 (h) The circuit component of claim 130, wherein the material of the protective layer comprises a borophosphorus bismuth glass (BPSG) 〇 141. The circuit component according to claim 130 of the patent application The material of the first metal layer comprises copper. The material of the first metal layer comprises copper. I. 143. The line element of the item, wherein the first metal layer of /. . . . . : : . The material comprises silver. 144. The circuit component of claim 130, wherein The material of the first metal layer comprises a turn. 145. The circuit component of claim 130, wherein the material of the first metal layer comprises 1 bar. 146. The line according to claim 130 The device of claim 1, wherein the material of the first metal layer comprises nickel. The circuit component of claim 130, wherein the first metal layer has a thickness of between 1 micrometer and 20 micrometers. Line described in item 130 of the patent scope The element, wherein the first metal layer has a thickness of from 1.5 micrometers to 15 micrometers. 149. The circuit component of claim 130, wherein the second metal layer comprises gold. 66 200843075 . The circuit component of claim 13 wherein the material of the second metal layer comprises copper....^ — - ' .. . '* . . - · · - · ' , - 151 · Face reading special spear _ surrounding material including silver. _ , Guang.-; .. I. - - ..... .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... The circuit component of claim 130, wherein the material of the second metal layer comprises: i . . . . . : : : V _ . . . . . . . . , . . . The circuit component of claim 13, wherein the material of the second metal layer comprises a brocade. 155. The circuit component of claim 130, wherein the thickness of the second metal layer is between 1 micro 156. The circuit component of claim 130, wherein the second metal layer has a thickness of between 1.5 and 15 micrometers. ^ 157. The circuit component, wherein the tin-containing metal layer is in a different position from the second metal pad as viewed from a top perspective view. 158. The circuit component of claim 130, further comprising a first adhesion/barrier layer between the first metal layer and the first metal pad. 159. The circuit component of claim 2, wherein the first adhesion/barrier layer comprises a titanium-tungsten alloy layer having a thickness between 〇·02 μm and 〇·8 μm. 160. The circuit component of claim 20, wherein the first adhesion/barrier 67 200843075 layer comprises a titanium metal layer having a thickness between 0. 02 microns and 〇 8 microns. 161. The circuit component of claim 2, wherein the first adhesion/barrier layer comprises a thickness strip G·〇2 microfilament 鄕·8 鄕-gas reduction layer. 2. The circuit component of claim 2, wherein the first adhesive/barrier layer comprises a button metal layer having a thickness between 〇2 至2 μm and 0.8 μm. The circuit component of claim 20, wherein the first adhesion/barrier layer comprises a thickness strip G·G2 micron to 〇·8 micron-nitride. The circuit component of claim 2, wherein the first adhesion/barrier layer comprises a chrome metal layer having a thickness ranging from 〇·02 μm to 〇·8 μm. The circuit component of claim 2, wherein the first adhesive/barrier layer comprises a chrome-copper alloy layer having a thickness of from 0.02 micrometers to about 8 micrometers. 166. The circuit component of claim 20, further comprising a first seed layer between the first adhesion/barrier layer and the first metal layer. The circuit component of claim 28, wherein the first seed layer and the first metal layer are the same material. 168. The circuit component of claim 130, further comprising a second adhesion/barrier layer between the second metal layer and the second metal pad. 169. The circuit component of claim 87, wherein the second adhesion/barrier layer comprises a titanium tungsten alloy layer having a thickness between 0. 02 microns and 〇 8 microns. The circuit component of claim 87, wherein the second adhesive/barrier layer comprises a titanium metal layer having a thickness of from 0.02 micron to 〇·8 micron. 68 200843075 As the key line of the 87th job of the bond paste, the second layer of the barrier layer includes a titanium nitride layer with a thickness ranging from 〇·02 μm to 〇·8 μm. The circuit component of claim 87, wherein the second adhesive layer comprises a metal layer having a thickness of from 0.02 micrometers to 〇8 micrometers. The circuit component of claim 87, wherein the second adhesive layer comprises a layer of nitriding layer having a thickness of from 0.02 μm to 〇·8 μm. 174. , : The layer consists of a chrome metal layer with a thickness ranging from 〇·02 μm to 〇·8 μm. 175. The circuit component of claim 87, wherein the second adhesion/barrier layer comprises a chrome-copper alloy layer having a thickness between 0. 02 microns and 〇. 8 microns. 176. The circuit component of claim 87, further comprising a second seed layer between the second adhesion/barrier layer and the second metal layer. 177. The circuit component of claim 95, wherein the second seed layer and the second metal layer are of the same material. The circuit component of claim 130, wherein the semiconductor substrate comprises an active component under the tin-containing metal layer or the bonding pad. 179. The circuit component of claim 30, wherein the active component comprises a diode. The circuit component of claim 30, wherein the active component comprises a transistor. The circuit component of claim 130, wherein the first metal layer is connected to a first external circuit via the bonding pad via 69 200843075. 182. The circuit component of claim 181, which comprises a semiconductor wafer. 183. 'The circuit component as described in claim 181, which includes a printed circuit board. I84. The circuit component of claim m, wherein the metal substrate is included. 185. A circuit component as recited in claim 181, which includes a glass substrate. 186. The circuit component of claim 181, wherein the flexible substrate is included. 187. The circuit component according to claim 8 wherein the ceramic substrate is included. • A line component as described in Section 13G of the claim life, wherein connected to a second external circuit. 189. The circuit component of claim 1, wherein the semiconductor component comprises a semiconductor wafer. 190. The circuit component of claim 10, wherein the circuit component comprises a printed circuit board, and the circuit component of claim 1, wherein the circuit component comprises a metal substrate. The first external circuit, the first external circuit, the first external circuit, the first external circuit, the first external circuit, the first external circuit, the tin-containing metal layer, the second external circuit, the second external circuit, the second external Circuitry 200843075 192. The circuit component of claim 106, wherein the second external circuit comprises a glass substrate. [ 193. The circuit component of claim 106, wherein the second external circuit comprises a flexible substrate ^ ^ _ 194. The circuit component of claim 106, wherein the second The external circuit includes a ceramic substrate. 195. The circuit component of claim 130, further comprising a polymer layer having a thickness between 2 micrometers and 100 micrometers between the protective layer and the second metal layer. 196. The circuit component of claim 130, further comprising a layer of a polyamidene compound having a thickness between 2 microns and 100 microns between the protective layer and the second metal layer. 197. The circuit component of claim 130, further comprising a layer of a phenylcyclobutene compound having a thickness between 2 microns and 100 microns between the protective layer and the second metal layer. 198. The circuit component of claim 130, further comprising a parylene polymer layer having a thickness between 2 micrometers and 100 micrometers between the protective layer and the second metal layer . 199. The circuit component of claim 130, further comprising an epoxy layer having a thickness between 2 micrometers and 100 micrometers between the protective layer and the second metal layer. 200. The circuit component of claim 113, wherein the polymer layer differs from the polymer bump by a thickness of between 0.01 μm and 1 μm. The circuit component of claim 113, wherein the polymer layer differs from the thickness of the 71 200843075 polymer bump by between 0.1 μm and 1 μm. 202. The circuit component of claim 130, wherein the polymer bump comprises a polyimine compound. 2〇3β ^ 130 ^ includes a phenylcyclobutene compound. The circuit component of claim 130, wherein the polymer bump comprises a parylene-based south molecular compound. The circuit component of claim 130, wherein the polymer bump comprises epoxy wax. 206. The circuit component of claim 130, wherein the polymer bump has a thickness between 5 microns and 50 microns. 207. The circuit component of claim 130, wherein the polymer bump has a maximum lateral dimension of between 10 microns and 60 microns. 208. A circuit component comprising: a semiconductor substrate having at least one metal pad; a protective layer on the semiconductor substrate, the protective layer having at least one opening exposing the metal pad; a polymer bump on the protective layer; and a first metal layer on the protective layer, the polymer bump and the metal pad; and a second metal layer on the first metal layer And a tin-containing metal layer on the second metal layer above the polymer bump, connected to an external circuit via the 72 200843075 tin metal layer. 209. The circuit component of claim 2, wherein the semiconductor substrate comprises germanium. The circuit component of claim 2, wherein the semiconductor substrate comprises a thin wiring structure, the thin wiring structure comprising: a plurality of dielectric layers having a thickness of less than 3 μm, located in the semiconductor On the substrate, the dielectric layers have a plurality of via holes; and a plurality of thin circuit layers having a thickness of less than 3 micrometers, and the thin circuit layers are located on one of the dielectric layers, wherein the fine circuit layers are The channel holes are electrically connected to each other. 211. The circuit component of claim 3, wherein the thin circuit layer comprises an aluminum layer having a thickness between 0.05 and 2 microns. The circuit component of claim 3, wherein the thin circuit layer comprises a copper layer having a thickness between 0. 05 microns and 2 microns. 213. The circuit component of claim 2, wherein the material t of the protective layer comprises a nitrogen hydrazine compound. 214. The circuit component of claim 208, wherein the material of the protective layer comprises a phosphorous bismuth (PSG) 〇 215. The circuit component according to claim 208, wherein the protection The material of the layer includes a monoxide compound. 216. The circuit component of claim 208, wherein the material of the protective layer comprises a oxynitride compound. The circuit component of claim 208, wherein the material of the protective layer comprises a borophosphorus ruthenium (BPSG). 218. The circuit component of claim 208, wherein the material of the first metal layer comprises copper. 219. The circuit component of claim 208, wherein the material of the second metal layer comprises nickel. 220. The circuit component of claim 2, wherein the first metal layer has a thickness ranging from 1 micron to 2 micron. 221. The circuit component of claim 208, wherein the first metal layer has a thickness of between 1.5 and 15 microns. 222. The circuit component of claim 208, wherein the second metal layer has a thickness of from 1 micron to 2 micron. 223. The circuit component of claim 208, wherein the second metal layer has a thickness of from 1 micron to micrometer. 221. The circuit component of claim 208, wherein the polymer bump is not earned by a top perspective view. 225. The circuit component of claim 2, further comprising an adhesive/transfer layer between the first metal layer and the metal pad. 226. The circuit component of claim 20, wherein the adhesion/barrier layer comprises a thickness ranging from 〇·G2 county to 〇·8 micro-alloy layer. 227. The circuit component of claim 20, wherein the adhesion/barrier layer package 74 200843075 comprises a titanium metal layer having a thickness between 0. 02 microns and 〇 8 microns. The circuit component of claim 2, wherein the adhesion/barrier layer comprises a titanium nitride layer having a thickness between 0. 02 micrometers and 〇 8 micrometers. The circuit component of claim 2, wherein the adhesive/barrier layer comprises a button metal layer having a thickness of between 0.02 μm and 8·8 μm. The circuit component of claim 20, wherein the adhesion/barrier layer comprises a tantalum nitride layer having a thickness of from 0.02 micron to 〇.8 micron. The circuit component of claim 20, wherein the adhesion/barrier layer comprises a chrome metal layer having a thickness of from 0.02 micrometers to 〇8 micrometers. 2. The circuit component of claim 2, wherein the adhesion/barrier layer comprises a chrome-copper alloy layer having a thickness between 0. 02 micrometers and 〇 8 micrometers. 233. The circuit component of claim 2, further comprising a sub-layer between the adhesion/barrier layer and the metal layer. 234. The circuit component of claim 28, wherein the seed layer is the same material as the metal layer. 2359. The circuit component of claim 2, wherein the semiconductor substrate comprises an active component positioned below the polymer bump. 236. The circuit component of claim 30, wherein the active component comprises a pole body. 237. The circuit component of claim 30, wherein the active component comprises a transistor. The circuit component of claim 2, wherein the external circuit comprises a printed circuit board. 239. The circuit component of claim 2, wherein the external circuit comprises a metal substrate. 240. The circuit component of claim 2, wherein the external circuit comprises a glass substrate. 241. The circuit component of claim 2, wherein the external circuit comprises a flexible substrate. 242. The circuit component of claim 208, wherein the external circuit comprises a ceramic substrate. 243. The circuit component of claim 208, wherein the polymer bump comprises a polyamidene compound. 244. The circuit component of claim 2, wherein the polymer bump comprises a phenylcyclobutene compound. 245. The circuit component of claim 208, wherein the polymer bump comprises a poly(p-phenylene terphenyl) polymer compound. 246. The circuit component of claim 2, wherein the polymer bump comprises an epoxy resin. 247. The circuit component of claim 208, wherein the polymer bump has a thickness between 5 microns and 50 microns. 248β. The circuit component of claim 208, wherein the polymer bump is at most 76 200843075 having a large lateral dimension of between 10 micrometers and 60 micrometers. 249. The circuit component of claim 3, wherein - the dielectric layer has a dielectric constant between 1 and 3. 250. The circuit component of claim 208, wherein the tin-containing metal layer has a thickness of between 1 micrometer and 300 micrometers. 251. The circuit component of claim 208, wherein the tin-containing metal layer has a thickness of between 5 microns and 200 microns. 77