200843065 九、發明說明： 【發明所屬之技術領域】 本發明涉及半導體封裝技術’特別涉及一種小尺寸之 半導體封裝結構。 【先前技術】 半導體封裝結構主要包括晶片及封裝外殼，封裝外殼 封裝晶片，以髓晶片，避免其受到機械損害及電氣侵擾。 另外，半導體封裝結構通常還包括電阻、電容、電感等被 動元件，以配合晶片構成完整之電子系纟先。 、 請參閱圖1，典型之半導體封裝結構馳包括晶片 lla、被動元件12a及基板i3a。晶片Ua及被動元件12& 設置於基板13a上並與基板i3a電連接，其中，晶片Ua 没置於基板13a中心處，被動元件12a繞設於晶片Ua周 圍l'隹’被動元件12a如此設置不利於半導體封裝結構1〇〇a 之小型化，且對晶片11^佈線之空間造成限制。 【發明内容】 有鑒於此，有必要提供一種可縮小尺寸之半導體封裝 結構。 一種半導體封裝結構，其包括一基板、至少一被動元 件、一絕緣填充材料及一晶片。所述基板包括一封裝面， 所述封裝面開設有一凹槽，所述至少一被動元件設置於所 述凹槽内並與所述基板電性連接，所述絕緣填充材料填充 於所述凹槽内並覆蓋所述至少-被動元件，所述晶片設置 於所述絶緣填充材料上並與所述基板電性連接。 6 200843065 一種半導體封裝結構，其包括·· 一基板，所述基板開設有凹槽； 至少-被動元件，所述被動元件絕緣封裝於 槽 内並與所述基板電性連接；及 一晶片’所述晶片設置於所述至少—被動树上方並 與所述基板電性連接。 所述半導體封裝結構將所述至少—被動元件收容於所 „凹槽内，可提高所述半導體封裝結構之空間利用 率，鈿小所述半導體封裝結構之尺寸。 【實施方式】 弟一實施例 7關2 ’本實_之半導體輕結構·包括一 片\〇所=、一被動元件20、—絕緣填充勵及-晶 Γ凹二T板10包括一封裝面11，所述封裝面霉 内且與;ΑΠ少—被動元件20設置於所述凹槽12 於所ΐ =土反10,電性連接。所述絕緣填充材料30填充 片40=曰12内亚覆蓋所述至少一被動元件20。所述晶 連接又置於所述絕緣填充材料3〇上且與所述基板10電性 盤及第二料1 路電性連接之第一浮 還形赤古从1" /、體地，所述基板10之下表面15 接。所、^:、ί.三谭盤，，用於與外部電路(圖未示)電連 处二焊盤可以係球柵陣列(Bail Grid Array，JBGA)、 7 200843065 無引線晶片載體(Leadless Chip Carrier，LCC)或引線樞 (Leadframe)。 "所述基板10可採用塑膠、陶兗或玻璃材料製成，本實 知例之基板10採用塑膠製成。具體地，塑膠材料可採用摻 有玻璃纖維之魏脑、摻有有财之魏齡或摻有 曰ife胺之衩氧樹脂製成，本實施例之基板由摻有有 矽之環氧樹脂製成。 所述凹槽12開設於所述封裝面n之中央，其尺寸大 於所述晶片40之尺寸，其深度大於所述絕緣填充材料％ 之厚度。即，所述絕緣填充材料3〇填充於所述凹槽12後 形成之上表面31低於所述封裝面u。如此，所述晶片4〇 可收容於或部純容於所述凹槽U内，降低所述半導體封 裝結構100之高度。 ' 本實施例之晶片40部分收容於所述凹槽12内，以霖 出其上表面41，方便所述晶片4〇之佈線作業。 所述凹槽12可為方形凹槽、圓形凹槽或其它形狀之凹 槽’本實施例採用方形凹槽。 所述至少一被動元件2〇為多個表面貼裝元件②瓜以⑶ Mounted Device，SMD)，其通過表面貼裝技術(細咖 Mounted Technology, SMT)焊接於所述複數第一焊盤13上。 本貫施例之絕緣填充材料3〇採用可固化接著劑，如 此，所述晶片40可直接接著於所述絕緣填充材料3〇，進 而固定所述晶片40。所述可固化接著劑可採用熱固化接著 劑或紫外光固化接著劑，並採用相應之熱熟化或紫外熟化 8 200843065 工藝固化所述可固化接著劑。 所述晶片4〇通過多條引線42電性連接至所述複數第 一;^盤14，從而實現與所述基板電連接。所述弓丨線A]可200843065 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor package technology', and more particularly to a small-sized semiconductor package structure. [Prior Art] The semiconductor package structure mainly includes a wafer and a package casing, and the package casing encapsulates the wafer to protect the core wafer from mechanical damage and electrical intrusion. In addition, the semiconductor package structure usually includes passive components such as resistors, capacitors, and inductors to match the wafer to form a complete electronic system. Referring to FIG. 1, a typical semiconductor package structure includes a wafer 11a, a passive component 12a, and a substrate i3a. The wafer Ua and the passive component 12& are disposed on the substrate 13a and electrically connected to the substrate i3a, wherein the wafer Ua is not placed at the center of the substrate 13a, and the passive component 12a is disposed around the wafer Ua. The semiconductor package structure 1A is miniaturized, and the space for wiring the wafer 11 is limited. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a semiconductor package structure that can be downsized. A semiconductor package structure comprising a substrate, at least one passive component, an insulating filler material, and a wafer. The substrate includes a package surface, the package surface defines a recess, the at least one passive component is disposed in the recess and electrically connected to the substrate, and the insulating filling material is filled in the recess And covering the at least-passive component, the wafer is disposed on the insulating filler material and electrically connected to the substrate. 6 200843065 A semiconductor package structure comprising: a substrate, the substrate is provided with a groove; at least a passive component, the passive component is insulatively packaged in the slot and electrically connected to the substrate; and a wafer The wafer is disposed above the at least-passive tree and electrically connected to the substrate. The semiconductor package structure accommodates the at least one passive component in the recess, which improves the space utilization ratio of the semiconductor package structure and reduces the size of the semiconductor package structure. 7 off 2 'the actual semiconductor light structure · including a piece of \ 〇 =, a passive component 20, - insulation filling and excitation - the wafer concave two T plate 10 includes a package surface 11, the package surface mold and And the passive component 20 is disposed on the recess 12 and electrically connected to the ground. The insulating filler 30 fills the sheet 40=曰12 to cover the at least one passive component 20. The first connection of the crystal connection is placed on the insulating filler material 3 and electrically connected to the substrate 10 and the second material, and the first floating shape is from 1" The lower surface 15 of the substrate 10 is connected. The ^:, ί. San Tan disk is used for electrically connecting with an external circuit (not shown). The second pad can be a Bail Grid Array (JBGA), 7 200843065 Leadless Chip Carrier (LCC) or Leadframe. The board 10 can be made of plastic, ceramic pot or glass material, and the substrate 10 of the present invention is made of plastic. Specifically, the plastic material can be made of glass fiber-containing Wei brain, mixed with wealth, or mixed with The substrate of the present embodiment is made of epoxy resin doped with antimony. The recess 12 is formed in the center of the package surface n and has a larger size than the wafer 40. a dimension having a depth greater than a thickness of the insulating filler material. That is, the insulating filler material 3 is filled in the recess 12 to form an upper surface 31 lower than the package surface u. Thus, the wafer 4〇 can be accommodated or partially contained in the recess U to lower the height of the semiconductor package structure 100. The wafer 40 of the embodiment is partially received in the recess 12 to lend the upper surface thereof. 41. Facilitating the wiring operation of the wafer 4. The groove 12 may be a square groove, a circular groove or a groove of other shapes. The embodiment adopts a square groove. The at least one passive component 2〇 Mounting components for multiple surface mounts (3) Mounted Device, SMD), Soldering on the plurality of first pads 13 by surface mount technology (SMT). The insulating filler material 3 of the present embodiment employs a curable adhesive, so that the wafer 40 can be directly followed by The insulating filler material 3 is further fixed to the wafer 40. The curable adhesive may be a heat curing adhesive or an ultraviolet curing adhesive, and cured by a corresponding thermal curing or UV curing 8 200843065 process. The wafer 4 is electrically connected to the plurality of first wires through a plurality of leads 42 to electrically connect to the substrate. The bow line A] can
採用金線、銀線、銅線等良導體線材，本實施例之弓丨線I 採甩金線。 具體地，本實施例之半導體封裝結構励還包括一封 裝層50，其包覆於所述晶片40及引線幻上，以保護所述 晶片4〇及引線42 ’避免其受到機械損害及電氣侵擾。本 實施例之封裝層50採騎氧樹脂材料，其可通過轉送成型 ^(Transfer Molding)iUt ^(Injecti〇n M〇lding)^^ 型方法成型’本實關_魏成魏形賴麟裝層5〇。 所述半導體封裝結構100在所述基板ι〇之封裝面n 開設所相槽12收容所述至少i動元件2Q，如此，可 提高所述半導體封裝結構1⑻之”_率，縮小所述半 導體封裝結構1〇〇之尺寸，方便所述晶片4〇之佈線作業。A good conductor wire such as a gold wire, a silver wire or a copper wire is used, and the bow wire I of this embodiment picks a gold wire. Specifically, the semiconductor package structure of the embodiment further includes an encapsulation layer 50 covering the wafer 40 and the leads to protect the wafers 4 and the leads 42 from mechanical damage and electrical intrusion. . The encapsulating layer 50 of the embodiment adopts an oxygen resin material, which can be formed by a transfer molding method (Transfer Molding) iUt ^ (Injecti〇n M〇lding) ^^ type forming '本实关_魏成魏形赖麟装Layer 5〇. The semiconductor package structure 100 is provided with a phase groove 12 on the package surface n of the substrate ι to accommodate the at least i-moving element 2Q, so that the semiconductor package structure 1 (8) can be increased and the semiconductor package can be reduced. The size of the structure is one, which facilitates the wiring operation of the wafer.
另外’所述凹槽尺寸大於所述晶片40之尺寸，深度大 ⑽述絕緣填充材料30之厚度，使得所述晶片40部分收 合於所相槽12 Θ，更進—步縮小所 结構 100之尺汁。 弟一貫施例 ==例之晶U騎像感測晶片，本實施例之半導 -考=彳2GG與第—實施例之半導體封I 〇不同 之處包括： 本男％例之絕緣填充材料⑽採用環氧樹脂，其通過射 9 200843065 出成型/去寺成型方法填充於所述凹槽12内，並形成一平整 表面61。所述晶片40通過一接著層70設置於所述平整表 面61上。所述接著層7〇可採用可固化接著劑或雙面膠墊， 本實施例採用可固化接著劑。 所述半導體封裝結構200包括一可固化接著劑8〇及一 透明板90，所述可固化接著劑8〇包覆於所述引線42與所 述第二焊盤14，所述透明板9〇覆蓋於所述影像感測晶片 並接著於所述可固化接著劑80上。 綜上所述，本發明確已符合發明專利要件，爰依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式’舉凡热悉本案技藝之人士，於援依本案發明精神所作 之等效修飾或變化，皆應包含於以下之申請專利範圍内。 【圖式簡單說明】 圖1為典型半導體封裝結構之俯視示意圖；In addition, the groove size is larger than the size of the wafer 40, and the depth is (10) the thickness of the insulating filler material 30, so that the wafer 40 is partially folded into the phase groove 12 Θ, and the structure 100 is further reduced. Ruler juice. The consistent application of the example == example of the crystal U riding image sensing wafer, the semi-conductive test of the present embodiment - 彳 2GG and the semiconductor sealing I 第 of the first embodiment include: the male insulating material of the example (10) An epoxy resin is used which is filled in the recess 12 by a shot forming method, and forms a flat surface 61. The wafer 40 is disposed on the flat surface 61 by an adhesive layer 70. The adhesive layer 7 can be a curable adhesive or a double-sided rubber pad. In this embodiment, a curable adhesive is used. The semiconductor package structure 200 includes a curable adhesive 8A and a transparent plate 90. The curable adhesive 8 is coated on the lead 42 and the second pad 14. The transparent plate 9〇 Overlying the image sensing wafer and then on the curable adhesive 80. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only the preferred embodiment of the present invention. Any modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top plan view of a typical semiconductor package structure;
圖2為本發明第一實施例之半導體封裝結構之剖面示意 圖； u =3為本翻第二實關之㈣體縣結構之剖面示意 【主要組件符號說明 100、200絕緣填充材料 30、60 10 絕緣填充材料上表面 31、61 11 晶片 40 12 晶片上表面 41 121 引線 42 基板 封裝面 凹槽 凹槽底面 200843065 第一焊盤 第二焊盤 基板下表面 第三焊盤 被動元件 13 封裝層 50 14 接著層 70 15 可固化接著劑 80 16 透明板 90 20 112 is a schematic cross-sectional view showing a semiconductor package structure according to a first embodiment of the present invention; u=3 is a schematic cross-sectional view of the structure of the body of the second county (the main component symbol description 100, 200 insulating filler materials 30, 60 10 Insulating filling material upper surface 31, 61 11 wafer 40 12 wafer upper surface 41 121 lead 42 substrate packaging surface groove groove bottom surface 200843065 first pad second pad substrate lower surface third pad passive component 13 encapsulation layer 50 14 Next layer 70 15 curable adhesive 80 16 transparent plate 90 20 11