TW200841317A - Source driver, electro-optical device, and electronic instrument - Google Patents

Abstract

A source driver that drives a plurality of source lines of an electro-optical device includes a grayscale voltage generation circuit that outputs first and second grayscale voltages corresponding to grayscale data, and a source line driver circuit that drives a source line among the plurality of source lines based on the first and second grayscale voltages. The source line driver circuit includes a flip-around sample/hold circuit that outputs an output grayscale voltage between the first and second grayscale voltages to the source line.

Description

200841317 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a source driver, a photoelectric power device, an electronic device, and the like. [Prior Art] A liquid crystal panel previously used for an electronic device such as a mobile phone (the photoelectric device is well known as a liquid crystal panel of a simple matrix type, and an active component using a switching element such as a thin film transistor (hereinafter referred to as TFT). Matrix-type liquid crystal panel. The advantage of the simple matrix method is that it is easier to consume than the active matrix method, and the disadvantage is that it is difficult to display multi-color and dynamic display. In addition, the advantage of the active matrix method is that it is suitable for multi-colorization and dynamics. Display, and the disadvantage is that it is difficult to reduce power consumption. In recent years, portable electronic devices such as mobile phones have increased the demand for multi-color and dynamic display in order to provide high-quality images. The liquid crystal panel replaces the liquid crystal panel of the simple matrix method used in the past. The active matrix liquid crystal panel changes the transmittance of the pixel by writing a signal to the source line in the pixel selected through the gate line. In recent years, with the increase in the size of the surface of the liquid crystal panel and the increase in the number of pixels, the number of source lines of the liquid helium panel has increased. In addition, it is required to provide the same accuracy to the voltage of each source line. Further, as the battery drive for mounting the liquid crystal panel and the electronic device are required to be miniaturized, the source driving of the source line for driving the liquid crystal panel is required to be The power consumption is reduced and the size of the wafer of the source driver is reduced. Therefore, the source driver must be simple in structure and high in function. 127200.doc 200841317 As disclosed in Patent Document 1 and Patent Document 2, a driving source can be disclosed. The guide rail of the output line of the source line of the driver is operated by the guide rail, and the voltage is supplied to the source line in a high-precision manner. [Patent Document 1] JP-A-2005-175811 (Patent Document 2) [Invention] [Problems to be Solved by the Invention] However, the techniques disclosed in Patent Document 1 and Patent Document 2 are that the respective turn-off circuits are controlled by driving an auxiliary circuit to realize the guide rails. Therefore, it is necessary to mount an auxiliary circuit as an additional circuit, and the circuit scale of the source driver becomes large. The variation of the voltage of the line causes the size of the transistor to become larger. Furthermore, in order to supply the voltage to the source line with high precision, it is necessary to reduce the voltage from the DAC which generates the tone voltage, which is cheaper than the tone data. Supply to the source line. Therefore, when the number of tones increases, the number of tone voltage signal lines must also increase, and the size of the chip becomes larger. In addition, the general operational amplifier needs to consider the variation of the output voltage. The size of the transistor constituting the operational amplifier is used to suppress the variation of the output voltage. One aspect of the present invention provides a small-scale circuit, and the source driver of the source line can be supplied with high precision by the action of the rail to the rail. In addition, the other aspects of the present invention provide a small-scale circuit that can suppress fluctuations in the power-out and high-precision supply voltage to the source driver of the source line, 127200.doc 200841317 Devices and electronic machines. In other cases, the source device, the photoelectric device, and the electronic device that supply the electric power to the source line with positive accuracy even when the number of tones is increased, is 4" in the number of lines. [Technical means for solving the problem] In order to solve the above problem, the source driver of the present invention is used to drive the source line of the photovoltaic device, and includes

a weekly voltage generating circuit for outputting respective tone voltages of the first and second tone voltages corresponding to the tone data; and a source line driving circuit for driving the source according to the first and second tone voltages The source line driving circuit includes a flip type sample-and-hold circuit that outputs an output tone voltage between the rain-first color tone voltage and the second color tone voltage to the source line. Here, the source driver may also output a voltage of the same potential as the first tone voltage, and may also output a voltage of the same potential as the second tone voltage as the output tone voltage. According to the present invention, since the output tone voltage between the first and second tone voltages is generated by the flip type sample-and-hold circuit, the structure is very simple, and the output circuit can generate a complex tone voltage. As a result, the type of tone voltage to be produced can be drastically reduced. Thereby, the number of tone voltage signal lines can be reduced, and the circuit scale of the tone voltage generating circuit can be greatly reduced. In general, the tone voltage generating circuit needs to increase the size of the transistor in order to supply a high voltage, and the circuit scale of the tone voltage generating circuit is reduced, which is large, and contributes to the wafer size of the source driver. Reduced. Further, by the flip type sampling and holding circuit, the rail-to-rail operation can be performed without the addition of an auxiliary circuit or the like, and it is not necessary to increase the size of the crystal in order to suppress the variation. Therefore, it contributes to the reduction of the size of the wafer of the source driver. Further, by the present invention, it is not necessary to output the tone voltage generated by the tone voltage generating circuit to the source #, line' in order to set the tone voltage applied to the source line. The structure of the tone voltage generating circuit can be miniaturized. Further, with the present invention, the tone voltage can be generated with high accuracy only by the output circuit. As a result, the structure of the tone voltage generating circuit can be simplified. In addition, in the source driver of the present invention, the flip type sampling and holding circuit includes: an operational amplifier circuit; and a plurality of electrical TL devices connected to one end of the input of the operational amplifier circuit; ❿, during the sampling period In the state in which the output of the operational amplifier circuit and the source line are interrupted, the input and output of the operational amplifier circuit are electrically connected to each of the capacitive elements of the plurality of capacitive elements, corresponding to the first or second a charge of a tone voltage; ^ electrically interrupting the input and output of the operational amplifier circuit during the hold period after the sampling period, and supplying an output of the operational amplifier circuit stored in the complex capacitor element The output voltage of the operational amplifier circuit is output to the source line. Further, in the source driver of the present invention, 127200.doc 200841317 The above-mentioned flip type sample-and-hold circuit includes a large open circuit which supplies a voltage on a non-inverted input terminal; The reverse rotation terminal 〇刖'l of the operational amplifier circuit is open between the outputs of the large circuit; the - terminal is connected to the first to the first brain of the reverse input terminal; the switch is switched to use =Off' is the circuit that turns the third (1^Ρ幻'p is an integer) to the circuit: between the other end of the P-capacitor element and the output of the aforementioned operational amplifier circuit; One end of the p input switch is connected to the other end of the pth command 70仵; and the output switch is connected between the L^ pole lines; ..., the output of the operational amplifier circuit and the aforementioned source are in the other The other end of each input switch of the j-input switch is supplied with a tone voltage before the λ ΒΒ ; ;; during the sampling period, the feedback switch of the age & With the switch, the state of the other: before and after the capacitor is turned on: Next, in the first one, the end supply, the first and second tone voltages are in the first to the jth flip switch after the sampling period, and the p: month may be turned on by the first The first open feedback switch obtained in the above manner is turned on, and the source of the print source between the color-off voltage and the second tone voltage is turned on. ^272〇〇t(j〇c -9. 200841317 When using any domain-invention, because it is stored in a complex capacitive element = electrical structure that moves to the output side of the operational amplifier circuit, it is not affected by the amplifier circuit. With the influence of the input offset voltage, the tone voltage can be output with high precision. In addition, according to the present invention, the first and second tone voltages can be supplied to the first to the sth capacitance elements in a simple structure. In the source driver of the present invention, when the minimum output voltage of the output tone voltage ratio to the voltage of the source line is close to the last potential voltage of the power output to the source line, the tone voltage generating circuit follows the potential network. The first and second tone voltages are sequentially outputted; when the output tone voltage is closer to the lowest potential voltage than the highest potential voltage, the tone color generating circuit can output the first and second tone voltages in order of low potential Further, in the source driver of the present invention, when the output tone voltage is closer to the highest potential voltage than the lowest potential voltage, In the first and first tone voltages, in a state in which the tone voltage on the high potential side is supplied to any one of the first to the seventh magnetic devices, the color voltage on the low potential side can be supplied to the first one. And switching the first to the jth input switches in a manner of any one of the jth capacitive elements. Further, the source driver of the present invention is when the output tone voltage is closer to the lowest potential voltage than the same potential voltage In a state in which the tone voltage on the low potential side is supplied to any one of the first to jth valley elements in the first and first color burst voltages, the color voltage on the high potential side can be supplied to the aforementioned Switching control of the first to jth input switches is performed by any one of the first to jth capacitive elements. 127200.doc 200841317 By any of the above inventions, a line leakage is generated, so that it is possible to prevent... ~ Brother _ switch to open situation. This is to avoid the voltage level change of the output tone voltage, in addition, the source driver of the present invention, etc. The output capacitance of the first and second tone voltages can be accurately and easily generated. The source driver of the present invention can be included at one end of the supply. The auxiliary capacitance element of the inverting input terminal of the operational amplifier circuit is connected to the other end. The invention can suppress the electric U-turn of the input terminal of the reverse polarity of the circuit and realize the output tone voltage. Further, in the source driver of the present invention, the auxiliary capacitance element may also be used as a dummy capacitance element in the formation region of the capacitor element. Further, in the source driver of the present invention, Each of the source driver blocks of each of the source lines of the optoelectronic device includes: a plurality of source driver blocks comprising: the tone voltage generating circuit and the source line driving circuit; each of the source driver blocks is in a plurality of The direction in which the source driver blocks are arranged in the direction of the direction of the opening, the 卞& The capacitive element forming region of the auxiliary capacitive element; the auxiliary capacitive element may also be formed along a boundary of the boundary between the capacitive element forming regions 127200.doc 200841317 along a direction intersecting the direction in which the array direction intersects. According to the present invention, the capacitance values of the first to _th capacitive elements can be accurately formed, and the auxiliary capacitance elements can be formed without wasting the layout area. Further, in the source driver of the present invention, the differential amplifier circuit can perform the A-stage amplification operation during the sampling period and the AB-level amplification operation during the sustain period.

In addition, in the source driver of the present invention, the operational amplifier circuit may include: an amplification factor that amplifies a difference value between an input of the operational amplifier circuit and an output of the operational amplifier circuit; a first drive of the first conductivity type a transistor, which is disposed on the first power supply side, controls a gate electrode according to a voltage of an output node of the operational amplifier; and a second driving transistor of the second conductivity type is connected in series with the first driving transistor It is disposed on the second power supply side; the electric device is configured to perform capacitance coupling between the gate electrode of the first driving and the second driving transistor and the opening electrode of the second driving transistor, and And a charge supply circuit that supplies electric charge to the gate electrode of the first two driving transistors during the sampling period, and stops supplying the electric charge to the gate electrode of the two driving transistor during the holding period. Further, in the source driver of the present invention, the charge supply circuit includes: a current generating circuit; and 127200.doc 12-200841317 a switching circuit 'inserted into the aforementioned/Wangtu Electric Tower Xingshuo Lei Xuan-End and the aforementioned Between the gate electrodes of the two driving transistors; the aforementioned switching circuit of the pirates can also be turned on during the sampling period before (1), and the mode of disconnection during the previous period is controlled by the switches. In addition, in the source driver of the present invention, the current generating circuit includes a current source transistor for supplying a heart, a y, a, and a port motor to the poleless and diode vehicle;

The foregoing switching circuit may also be inserted into one end of the capacitor of the gate electrode pad of the current source transistor and the idle electrode of the second driving transistor: between 0 and 'the general flip type sampling and holding circuit, regardless of the During the sampling period or during the holding period, (4) there is no change in the load. And any of the above-mentioned sources of invention: in the driver: the load of the source line of the photovoltaic device needs to be driven during the holding period. Thus, with any of the above inventions, since the flip type sample hold: the path drives the output of the low load during the sampling period and drives the output of the high load during the sustain period, the source driver can be provided with the optimum source line driving circuit. Without affecting the function of the flip-type sample-and-hold circuit, the circuit scale of the flip-flop sample-and-hold circuit can be greatly reduced. In addition, the photovoltaic device of the present invention comprises: a plurality of scanning lines; a plurality of source lines; and a plurality of pixels, wherein the pixels are specified by respective scanning lines of the plurality of scanning lines and respective source lines of the plurality of source lines; Driving any of the above-described source drivers for a plurality of source lines. 127200.doc -13- 200841317 The invention can provide an optoelectronic device comprising a small-scale circuit, a source-driven cymbal that can supply a voltage to a source line with high precision by guiding to a rail action, by means of the invention An optoelectronic device comprising a source driver having a small circuit scale, omitting an input offset voltage, and supplying a voltage to a source line with high accuracy is provided. Further, according to the present invention, it is possible to provide an optoelectronic device including a source driver which can supply a voltage to a source line with a high degree of accuracy even when the number of hue numbers is increased. Furthermore, the electronic machine of the present invention comprises any of the above-described source drivers. Further, the electronic apparatus of the present invention comprises the above-described photovoltaic device. According to any of the above inventions, it is possible to provide an electronic device which can set a tone voltage with high accuracy on a source line and which is lightweight and miniaturized. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail using the drawings. Further, the embodiments described below are not intended to unduly limit the scope of the invention described in the claims. Further, all the configurations described below are not limited to the essential constituent elements of the present invention. 1. Liquid crystal device Fig. 1 shows a schematic configuration of an active matrix type liquid crystal device of the present embodiment. Here, the active matrix type liquid crystal device will be described, but the display driver of this embodiment can be applied to other liquid crystal devices. The liquid day device 10 includes a liquid crystal display (LCD) panel (in a broad sense, a display panel, and more generally, an optoelectronic device). The LCD panel 20 is an amorphous germanium liquid crystal panel, for example, formed on a glass substrate. 127200.doc -14- 200841317 The glass substrate is arranged with a plurality of gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) which are arranged in the Y direction and extend in the χ direction, respectively, and in the X direction. A plurality of source lines (data lines) SL1 to SLN (N is an integer of 2 or more) extending in the γ direction are arranged. Further, a pixel region (pixel) is provided corresponding to the intersection position of the gate line GLm (1SmSM, m is an integer, the same applies hereinafter) and the source line SLn (l gn$N, η is an integer, the same below). A thin film transistor (Thin_Film Transistor: hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region. The gate of the TFT 22 mn is connected to the gate line GLn. The source of the TFT 22 mn is connected to the source line SLn. The drain of the TFT 22 mn is connected to the pixel electrode 26 mn. A liquid crystal (generally, a photovoltaic device) is formed between the pixel electrode 26 mn and the counter electrode 28 mni opposed thereto to form a liquid crystal capacitor (in a broad sense, a liquid crystal element) 24 mn. The transmittance of the pixel changes depending on the applied voltage between the pixel electrode 26 mn and the counter electrode 28 mn. The counter electrode voltage Vcom is supplied to the counter electrode 28 mn. The LCD panel 20 is formed by laminating a first substrate on which a pixel electrode and a TFT are formed and a second substrate on which a counter electrode is formed, and sealing a liquid crystal as a photovoltaic material between the substrates. The CD panel 20 may include a pixel electrode connected to the source line via a TFT as a switching element. Further, the LCD panel 20 may include a plurality of source lines, a plurality of switching elements, and a plurality of pixel electrodes each of which is connected to each of the switching elements via the respective source lines. The liquid helium coat 10 includes a display driver (broadly speaking, a drive circuit) 90 that drives the LCD panel. Display driver 90 includes a source driver 3〇. Source 127200.doc 15 200841317 The polar driver 30 drives the source lines of the source lines SL1 SLSLN of the lcd panel 20 in accordance with the tone data corresponding to the respective source lines. The display driver 9A can include a gate driver (broadly speaking, a scan driver) 32. The gate driver 32 scans the gate line of the LCD panel 2 for a vertical scanning period (31^~1%). The display driver 90 may be configured by omitting at least one of the source driver 30 and the gate driver 32. The liquid crystal device 10 can include a power supply circuit 94. The power supply circuit 94 generates a necessary voltage when driving the source line, and supplies the source driver 30. The power supply circuit 94 generates a source line that drives the source driver 3 The power supply voltages VDDH, VSSH, and the voltage of the logic portion of the source driver 30 are required. Further, the power supply circuit 94 generates a voltage required for scanning the gate line and supplies it to the gate driver 32. Further, the power supply circuit 94 The counter electrode voltage Vc 〇 m is generated. The power supply circuit 94 periodically repeats the high potential side voltage ¥(:〇]^11 and the low potential side in cooperation with the timing of the polarity inversion signal p〇L generated by the source driver 3〇. Voltage • VCOML's relative electrode voltage Vc〇m is output to the LCD panel 2's opposite electrode 0. The liquid day is set to 1 0. The display controller 38 can be included. The display controller 3 8 is processed by the central unit (not shown). Device (Central Processing Unit: The contents of the host (H_) such as CPU are controlled by the CPU, etc., and the source driver 卯30 gate driver 32 and the power supply circuit 94 are controlled. If the display controller 38 is connected to the source driver 30 and the gate The driver 32 sets the operation mode and supplies the vertical synchronizing signal and the horizontal synchronizing signal generated internally. In addition, FIG. 1 includes the power supply circuit 94 or the display control 127200.doc -16-200841317 controller 38 in the liquid crystal device 1 . However, at least one of these may be provided outside the liquid crystal device 10. Alternatively, the host device may be included in the liquid crystal device 10. In addition, the source driver 30 may also include a gate driver 32. And at least one of the power supply circuits 94. Further, part or all of the source driver 30, the gate driver 32, the display controller 38, and the power supply circuit 94 may be formed on the LCD panel 20. As shown in FIG. The display driver 9 is formed on the panel 20 (the source driver 30 and the gate driver 32). Thus, the LCD panel 20 can include: a plurality of source lines, a plurality of gate lines, and each of the switching elements is connected to each of the plurality of gate lines. Gate The plurality of switching elements of the source lines of the line and the plurality of source lines and the source driver for driving the plurality of source lines are formed. A plurality of pixels are formed in the pixel formation region 80 of the LCD panel 20. FIG. 3 shows FIG. An example of the structure of the gate driver 32 of Fig. 2. The gate driver 32 includes a shift register 4A, a level shifter 42 and an output buffer 44. The shift register 40 includes gate lines corresponding to the gates. And each of the flip-flops is arranged, and the plurality of flip-flops are sequentially connected. The shift register 4〇 is synchronized with the clock signal CPV, and the start pulse signal STV is held in the flip-flop, and is sequentially and clocked. The signal CPV synchronization shifts the start pulse signal STV to the adjacent flip-flop. Here, the input clock signal CPV is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal. The level shifter 42 shifts the voltage level from the shifting moment to the moment of crying (2), and the voltage level of the liquid crystal element corresponding to the liquid crystal element of the LCD panel 20 127200.doc -17 - 200841317. The voltage level requires a high voltage level of 20 V to 50 V. The output buffer 44 buffers the scan voltage shifted by the level shifter 42. The gate line is output to the gate line to drive the gate line. The high potential side of the pulsed scan voltage is selected voltage, and the low potential side of the scan voltage is a non-selected voltage. In addition, the gate driver 32 is not shown in FIG. The shift gate is used to scan the gate line, and the gate line is scanned by selecting the gate line corresponding to the decoding result of the address decoder. Figure 4 shows the source driver of Figure 1 or Figure 2. Block diagram of the configuration example of 30. The source driver 30 includes: 1/〇 buffer 5〇, display memory 52, line latch 54, tone voltage generation circuit 58, DAC (digital/analog converter) (generalized In other words, the tone voltage generating circuit) 6〇 and the source line driving circuit 62 In the actuator 30, for example, the tone data D is input from the display controller 38. The color faded material D is input in synchronization with the dot clock signal DCLK, and is buffered in the ι/〇 馨 冲 〇 。 5 〇. The signal DCLK is supplied from the display controller 38 to the 0 buffer 50 by the display controller 38 or a host not shown. The tone data buffered by the U buffer 50 is written into the display memory 52. The tone data read by the memory 52 is buffered by the 1/〇 buffer 5〇, and is output to the display controller 38. The display memory 52 includes the output lines corresponding to the respective source lines. There are multiple memory cells of each memory cell. Each memory cell is specified by a column address and a row address. In addition, each memory cell of one scan line portion is specified by a line address of 127200.doc -18-200841317. The address control circuit 66 generates a column address, a row address, and a line address for the memory cells in the specific display memory 52. The address control circuit 66 generates a column bit when the tone data is written to the display memory 52. Address and row address, that is, the tone data buffered by the I/O buffer 50 is written by the column And a row address of the display memory and Cloth Laid memory cell 52 in. Column address decoder 68 will be decoded column address, the column corresponding to the selected

The memory of the memory 52 is displayed in the address. The row address decoder 70 decodes the row address, and selects the memory cell 0 of the display memory 52 corresponding to the row address to read the tone data from the display body 52 and output it to the line latch 54. The address control circuit 66 generates a line address. That is, the line address decoder 72 decodes the line address and selects the memory cell of the display memory corresponding to the line address. Then, the tone data of the horizontal scanning portion read from the memory cell specified by the line address is output to the line latch 54. When the address control circuit 66 reads the tone data from the display memory 52 and outputs it to the I/O buffer 50, a column address and a row address are generated. That is, the color of the memory cell of the display memory 52, which is held by the column address and the row address, is read by the I/O buffer 50. The tone data read by the 1/0 buffer 5 is taken out by the display controller 38 or a host not shown. The column address decoder 68, the row address decoder 7A, and the address control circuit 66 in FIG. 4 function as a write control circuit for controlling the writing of the tone data to the display memory 52. In addition, in FIG. 4, the line address decoder 行, the row address decoder 7G, and the address control secret function function as a read control circuit for controlling the color tone data from the display memory (2) to sell 127200.doc -19-200841317. . The line locker 54 latches the tone data of the horizontal scanning portions read from the display memory 52 by the timing of the change of the lock pulse Lp during the i horizontal scanning periods. The line locker 54 includes a plurality of temporary storages of the color data of each of the registers. The temporary storage of the plurality of registers of the line latch 54 is read from the display memory 52! The color data of the dots. The tone voltage generating circuit 58 generates a complex tone voltage corresponding to each tone data for each tone voltage (reference voltage). More specifically, the tone voltage generating circuit 58 generates a complex tone voltage corresponding to each tone data for each tone voltage in accordance with the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH. Each source output of the DAC 60 produces a tone voltage corresponding to the tone data of the "horizontal horizontal scanning portion of the line latch". More specifically, the Dac 58 is derived from the complex tone voltage generated by the tone voltage generating circuit 58. Among them, the tone data of the one line portion selected from the line latcher 54 corresponds to the tone voltage of the tone data corresponding to each source line, and outputs the selected tone voltage. Such DAC 60 includes each The source output sets the voltage selection circuits DECI to DECN. Each of the voltage selection circuits outputs i tone voltages corresponding to the respective tone data from the complex tone voltages from the tone voltage generation circuit 58. The source line driver circuit 62 includes an output circuit. 〇Pi~〇Pn. The output circuits of the output circuit 包含^ΟΡν include an operational amplifier circuit, and impedance conversion is performed using the output tone voltages of the voltage selection circuits of the DAC 60 to drive the source lines. 127200.doc -20- 200841317 2 · Structure example of source driver This embodiment is designed to reduce the circuit scale of the source driver block set for each source output, and drive the source line. A flip-type sample-and-hold circuit is provided in each of the output circuits of the circuit 62. Then, the flip-type sample-and-hold circuit is provided for: [to the source line. More specifically, the first and the first output by the DAC 60 are received. The two-tone voltage 'flip type sample-and-hold circuit outputs the output tone between the first tone voltage and the second tone voltage to the source line. Here, the source line driver circuit 62 including such a flip type sample-and-hold circuit will be described. Figure 5 shows a circuit diagram of a configuration example of the output circuit of the source line driver circuit 62. Figure 5 shows the structure of the output circuit 〇Ρι, but the other output circuits OP2 〇 PN also have an output circuit In addition, FIG. 5 shows an example in which two kinds of output tone voltages between the first and second tone voltages are generated, but the present invention is not limited in terms of the type of output tone voltage. 60 supplies the first and second tone voltages as the input voltage Vin, and supplies the output tone voltage to the source line. The type of the output tone voltage generated in the output circuit is a number • The type of tone voltage generated by the tone voltage generation circuit 58 can be deleted. Because of this, the number of tone voltage signal lines can be greatly reduced, and the scale of the DAC60i can be greatly reduced. For example, the source driver 3 is based on 6 When the tone data of the bit drives the source line, the original tone voltage generating circuit needs to generate 64 (=26) kinds of tone voltages. However, since the source line driving circuit shown in FIG. 5, each output circuit can generate two kinds of tone voltages. Therefore, the tone voltage generation circuit 127200.doc -21 - 200841317 58 only needs to generate 32 kinds of tone voltages, that is, the amount only needs to be 32"P can be 〇 and the tone signal line number is Deng, h can be Jiang Duo domain halved. In addition, Fen, °. The wiring area of the 仏旎 line is the first and the 裳 际 ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ”

Thunder 1 out circuit pack 3 flip type sample-and-hold circuit. The flip type sampling guarantee (4)' is different between the first half of the horizontal scanning (four) (1H) and the holding period of the second half. That is, the flip type sample holding circuit supplies the charge stored during the sampling period to the output side thereof during the holding period. The output circuit includes an operational amplifier circuit, and a -4 is connected to the operation of the "complex capacitive element of the input of the circuit. Then, the output circuit is in the sampling period" to electrically interrupt the output of the operational amplifier circuit and the state of the source line. The electrical input is connected to the input and output of the operational amplifier circuit, and the electric charge corresponding to the first or second hue voltage is stored in each of the electric valley elements of the plurality of capacitors, that is, the voltage of the source line is not made during the sampling period. And electrically interrupting the output of the operational amplifier circuit and the source line. Then, the charge corresponding to any one of the first and second tone voltages is stored at the end of the plurality of capacitive elements, and is operated by the operational amplifier circuit. The driving part of the output section is supplied with charge at the other end of the plurality of capacitive elements. During the subsequent holding period, the output circuit electrically blocks the input and output of the operational amplifier circuit, and is stored in the complex capacitive element. The charge is supplied to the rotation of the operational amplifier circuit. At this time, the output of the operational amplifier circuit is electrically connected to the source line, that is, during the hold period, in order to be in the source line. Supply 127200.doc -22- 200841317 output tone voltage, and electrically connected to the output of the operational amplifier circuit and the source line. Then, the input and output of the electrical interrupting operation amplifier circuit will be stored in the charge supply of the complex valley element. The output of the operational amplifier circuit is such that the charge and discharge of the driving portion of the operational amplifier circuit is performed by the virtual short-circuit function of the input side of the operational amplifier circuit whose input voltage and output voltage are equal to each other, so that the output tone voltage can be changed. .

More specifically, the output circuit OP1 may include: an operational amplifier circuit opq, a jth (j is an integer of 2 or more) capacitive elements cn to cj, and first to jth flip switches S3 -1 to S3 -j And output switch S4. An analog ground agnd (specified voltage) is supplied to the non-inverting input terminal of the operational amplifier circuit OPC!. When the high-potential side power supply voltage of the operational amplifier circuit 0PC1 is VDD and the low-potential side power supply voltage is vss, the analog ground agnd can be (VDD + VSS)/2. The first to jth capacitive elements C1 to _ are connected to an operational amplifier circuit 〇PCli inverting input terminal. The capacitance values of the first to jth capacitor elements C1 to Cj are equal. The p is an integer). The switch S3.P is inserted between the other end of the capacitive element of the pth and the output of the operational amplifier circuit OPCA. The output switch S4 is inserted between the output of the operational amplifier circuit ο% and the output line electrically connected to the source line SL1. By supplying the first and second tone voltages to the first to jth capacitive elements C1 to cj, a 2ϋ-υ output tone voltage between the first and second tone voltages can be generated. Alternatively, the output circuit OP1 may further include an input switch of the first to the ninth input switch p (l = p^j'p is an integer), and one end of the input switch is connected to the other end of the p-th capacitive element. Then, the first or second tone voltage is supplied time-divisionally at the other end of each of the input switches of the first to the jth input switches. 127200.doc -23· 200841317 Next, the more specific structure and operation will be described by taking the case of Fig. 5 as an example. Figure 5 shows the situation of the system 2. The first input switch is controlled by the switch control signal SCO. The second input switch is controlled by the switch control signal SC1. The feedback switch is controlled by the switch control signal SC2. And the first: the flip switch is called, the 仏 2 is controlled by the switch control signal SC3. The output switch is switched by the switch control (four) f tiger SC4 (four). The switch control signal SCO ~ SC4 is output without a picture Fig. 6 is an explanatory diagram showing a first operation example of the output circuit OP1 of Fig. 5. During the sampling period, the first tone voltage Vini and the second tone voltage Vin2 are time-divisionally supplied. During the period of one tone voltage Vin1, the first input switch S0 is turned on, and the subsequent sampling period is switched off from the holding period. Further, the second input switch S1 is at least during the supply of the second tone voltage Vin2. The switching control is performed in a manner of being turned on. Further, the second input switch S1 is switched on during the sampling period and is turned off during the holding period. The feed switch S2 is switched on during the sampling period and is turned off during the hold period. The first and second inversion switches S3_1, S3-2 are turned off during the sampling period and are turned on during the holding period. Controlling. The switch S4 is turned on to switch off during the sampling period, and the switching control is performed in the manner of turning on during the holding period. That is, during the sampling period, the first to the jth turning switches are turned off, and the feedback switch S2 is turned on. And disconnecting the output switch S4, supplying the first and second tone voltages at the other ends of the first and second capacitive elements C1, C2 127200.doc -24 - 200841317

One of Vinl, Vin2. a μ and then, during the hold period after the sampling period, by turning on the first switch, the feedback switch S2 is turned off, and the output switch S4 is turned on, and The younger one tone voltage Vinl and the second color tone Vin2 are turned out to be the output of the tone voltage V〇ut to the source line. More specifically, in FIG. 6, during sampling, the first tone voltage is stored at one end of the first cell 70 C1 via the first input switch so.

The charge of Vml. In addition, via the second wheel switch si, in the second capacitor

One end of the piece C2 stores a charge corresponding to the second tone voltage vin2. During this period, since the feedback switch S2 is turned on, the voltage of the node NEG of the inverting input terminal of the amplifying circuit (4) is operated and the output voltage of the operational amplifying circuit ο% is operated by the virtual short circuit function of the operational amplifying circuit Ο%! Become analog to ground AGND. Therefore, during sampling, the charge Qs represented by the following formula is stored on the node NEG. At this time, since the output switch 84 is turned off, the voltage of the source line sli does not change.

Qs=Vinl xC+Vin2xC · (1) Here, Vinl is the first tone voltage, vin2 is the second tone voltage, and the capacitance values of the capacitance elements of the first and second cell elements C1 and C2 are c. Next, during the hold period, the first and second input switches, S1 and the feedback switch S2 are turned off, and the first and second inversion switches S3-1 and S3_2 are turned on. As a result, the voltage corresponding to the charge stored in the first and second capacitive elements C1, C2 is output, and the tone voltage is output as the operational amplifier circuit 0PCli. At this time, since one ends of the first and second capacitive elements C1, C2 are short-circuited, the output tone voltage v〇ut is expressed by the following formula. 127200.doc -25- 200841317

Vout=(Vinl+Vin2)/2 (2) FIG. 7 is an explanatory diagram showing a second operation example of the output circuit 〇Pi of FIG. 5. 6 is supplied to the first and second capacitive elements in the order of the high potential of the first and second hue voltages. However, FIG. 7 is supplied to the first and second colors according to the first and second hue. Second capacitive element. Also in this case, similarly to Fig. 6, the first and second input switches S0 and S1, the feedback switch S2, and the first and second inversion switches are controlled by the switches of ", S3_2, and the output switch S4. Money, during the hold period, outputs the output tone voltage v〇ut expressed by the formula (2). The output circuit of Figure 5 is shown in Figure 8. An explanatory diagram of the third operation example. 6 and 7 show an example in which the voltage between the first tone voltage vin1 and the second tone voltage Vm2 is output and the output tone voltage Vout is output, but the present invention is not limited thereto. By setting the first and second tone voltages Wn J and Vin2 to the same potential voltage, the output tone voltage % can be added to the same potential as the first and second tone voltages Vin1 and Vin2. # In this case, similarly to Fig. 6, the first and second input switches S0 and S1, the feedback switch S2, and the first and second inversion switches 83_丨, S3-2 and the output switch S4 are switched. As a result, according to the formula (2), the output tone voltage Vout becomes the electric potential of the same potential as the first and second tone voltages vin1, vin2, and the output tone voltage Vout is output during the sustain period. Since the flip-type sample-and-hold circuit described above is used to drive the source line, it is possible to have a very simple structure to generate a complex tone voltage from the output circuit. As a result, the type of the color voltage to be generated by the tone voltage generating circuit 58 can be greatly reduced. In this way, the number of tone voltage signal lines can be reduced, and the DAC (10) circuit scale can be greatly reduced by 127200.doc -26-200841317. In other words, since the DAC 60 is required to increase the transistor size by supplying a high voltage, the circuit size of the DAC 6() is reduced to greatly contribute to the reduction in the size of the wafer of the source driver 30. Further, by using the above-described flip type sampling and holding electric material, it is possible to carry out the guidance to the guide rail operation without adding an auxiliary circuit or the like, and it is not necessary to increase the size of the transistor in order to suppress the variation. Thus, it contributes to the reduction in the size of the wafer of the source driver 3. Furthermore, since the above-described flip type sample-and-hold circuit moves the charges stored in the first and second capacitive elements C1 and C2 to the output side of the operational amplifier circuit 〇pCi, it is not required to be operated by the operational amplifier circuit. The influence of the input offset voltage can produce an output tone voltage v〇j with high accuracy. Furthermore, the above-described flip type sample-and-hold circuit does not need to output the tone voltage generated by the DAC 60 to the source line for high-precision setting of the tone voltage applied to the source line, and only the output circuit can generate the tone voltage with high precision. Therefore, it is not necessary to generate the tone voltage with high precision by the DAC 60, which simplifies the structure of the DAC 60 and reduces the circuit scale of the DAC 60. 2 · 1 Comparative Example Further, the inverted type sample-and-hold circuit having the configuration of the present embodiment is required to have the order of the switching control of the first to j-th input switches during the sampling period and the level of the tone voltage input to each of the input switches. as follows. That is, the output tone voltage VoiU is the lowest potential voltage than the voltage output to the source line, and is close to the highest potential voltage of the voltage output to the source line, as shown in FIG. 6, the DAC 60 (tone voltage generation circuit) The first and second tone voltages must be output in the order of the high potential. Here, as for 64 kinds of tone voltages v〇~V63, the lowest is 127200.d〇c -27- 200841317: when the bit voltage is vo, the highest potential electric dust is state, and the lowest potential electric power is V63, the highest potential voltage is For v〇. The buzzer tone voltage Vout is close to the lowest potential voltage than the highest potential voltage: the DAC 60 (tone voltage generation circuit) must output the first and second tone voltages in order of low potential. Therefore, in the case where the other end of each of the first to the jth input switches is supplied to the second or second color electric house, the output tone voltage is biased to the lowest electric power: when the electric power is close to the highest potential electromigration, at the And in the second tone voltage, the tone voltage on the high potential side is confessed to 5^. In the state of any one of the capacitor elements C1 to Cj of the electric source, the mouth to the first to the jth, the low potential side is required. The switching of the first to jth input switches is performed in such a manner that the color dust is supplied to any one of the first to the jth capacitive elements C1 to cj. /b external 丄 When the other end of each input switch of the first to jth input switches is supplied with the first or _th color for 5 weeks, the output tone dust is closer to the lowest potential voltage than the highest potential, at the nth tone In the voltage, the tone of the low-potential side is supplied to the first to the ninth capacitive element, and any one of the capacitors is supplied to the first to the jth. The switching control of the first to jth input switches is performed in the manner of any one of the capacitor elements C1 to Cj. The reason described below will be described in comparison with the comparative example of the present embodiment. Fig. 9 is an explanatory view showing an operation example of the output circuit 叱 in the comparative example of the embodiment. In Fig. 9, the same portions as those in Figs. 6 to 8 are denoted by the same reference numerals, and the description will be omitted as appropriate. This comparative example is in the first half of the sampling period, in the state where the first input -28·127200.doc 200841317 is switched on, and the 篦-confident-wheel-in switch S1 is turned off, the first color is set.

The voltage Villi is supplied to one end of the first electric macro-V, and then in the second half of the sampling period, in the state of disconnecting the switch, the input switch so, and the second input switch, The second color bar voltage Vm2 is supplied to one end of the second capacitive element C 2 . The potential of the color tone voltage Vin1 of the purple > of the comparative example is a potential lower than the potential of the second tone voltage Vin2. Fig. 1A shows an operation explanatory diagram of the comparative example.

The same portions as those in Fig. 5 in Fig. 10 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. Fig. 10 shows a state in which the first input switch s is turned off and the second input switch S1 is turned on during sampling. When the first input switch so is turned on and the second input switch S1 is turned off, the first tone voltage Vml (SQ1) of Fig. 9 is supplied to the first capacitive element C1*. At this time, the electric charge corresponding to the first tone voltage Vin1 is stored in the first capacitive element C1. Next, as shown in FIG. 1A, in a state where the first input switch so is turned off and the second input switch S1 is turned on, the second tone voltage vin2 of FIG. 9 is supplied to the second capacitive element C2 (vinl < vin2^ SQ2). At this time, the electric charge corresponding to the second tone voltage MM is stored in the second capacitive element C2. Here, with the application of the tone voltage Vin2, the voltage level fluctuation of the node NEG (the other end of the second capacitive element C2) corresponding to the charge of the first tone voltage Vin1 is stored. Because the first capacitive element is electrically connected. The other end of the first capacitive element C2 communicates with the fluctuation of the voltage level of the node NEG as a change in the voltage level of the first capacitive element of the capacitive coupling. 127200.doc •29· 200841317 At this time, the voltage fluctuation of the node NEG is transmitted through the first capacitive element as a fluctuation of the voltage level at one end of the first inversion switch Μ-1, which is higher than the power supply voltage VDD. The potential (SQ4). This indicates that leakage occurs because the source (drain) of the p-type MOS transistor forming the switch and the diode connection portion between the substrates forming the transistor are in the positive direction. Therefore, the voltage level of the output tone voltage Vout which should be output during the hold period fluctuates. Therefore, in the present embodiment, the first tone voltage Vin2 on the low potential side is supplied to the second capacitance element after the first tone voltage Vin 1 on the first potential side in the second capacitance element C2. Switching control is performed in the mode of C2. Thereby, it is possible to avoid the case where the fluctuation of the voltage level of the second capacitive element is transmitted to the node NEG. That is, when the output tone voltage Vout is closer to the highest potential voltage than the lowest potential voltage, the first and second tone voltages are In the state in which the tone voltage on the high potential side is supplied to any one of the capacitance elements C1 to Cj of the first to the jth, the color tone voltage on the low potential side is supplied to the first to the sixth capacitive elements C1 to Cj. The switching control of the first to the ninth input switches is performed in any one of the capacitive elements. In addition, FIG. 9 and FIG. 10 illustrate the case where the output tone voltage Vout is closer to the highest potential voltage than the lowest potential voltage, but even if it is output When the tone voltage Vout is closer to the lowest potential voltage than the highest potential voltage, the bubble of the input switch is similarly generated. Therefore, when the output tone voltage V〇ut is closer to the lowest potential voltage than the highest potential voltage, the first and second are In the tone voltage, the tone voltage on the low potential side is supplied to any one of the capacitance elements C1 to Cj of the first to the jth, With the high-potential side color 127200.doc -30- 200841317 voltage supply to the _th. Brother] capacitive element C1 ~ Cj any of the Ray-cross components, who 耔筮 j 调 调 调 叮 叮 〜 〜 The input control of the input switch of the j input switch. Here, in order to judge the output of the hue electric hue voltage with a simple structure, the most close to the thunder device + r, if it is close to the smart potential voltage or close to the lowest potential voltage, it can also be based on the highest order of the tone data. The determination is made by the element." The explanation of the output order of the tone voltage in the present embodiment is shown in Fig. 11.

For example, the hue voltage corresponding to the hue data I μ卩 ratio _ 枓 枓 枓 最 最 , , , , , , , , , , 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调 色调The uppermost bit is "〇"_, and the tone voltage on the high potential side of the first and second tone voltages is supplied to the first capacitance element C1, and the tone voltage on the low potential side is supplied to the second capacitance element C2. In addition, the uppermost bit of the tone data is Γ1" Riji, and the tone voltage on the low potential side of the first and second tone voltages is supplied to the first capacitive element C1, and the tone voltage on the high potential side is supplied to The second capacitive element C2 can thereby prevent the output of the tone voltage Vout from generating the target voltage without causing leakage in the first and second inversion switches S3_i, S3_2. 2.2 Structure of Important Portion of Source Driver Next, a configuration example of an important portion of the source driver 3A in the present embodiment will be described. Fig. 12 is a block diagram showing a configuration example of a source driver block of the source driver 3A in the present embodiment. The same portions as those in Fig. 4 in Fig. 12 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. In addition, the following tone data is 6 bits. 127200.doc -31 - 200841317 Figure 12 shows only the structure of the source driver block of the source line SL1. The source driver block for driving the source line SL1 includes: an adding circuit 8 (^, an addition control logic 82!, a voltage selection circuit DEC1, and an output circuit 〇Ρι. The present embodiment is first and second for time division. The tone voltage is supplied to the output circuit OPi, and the tone data D[5:0] is output from the display memory 52, and the tone data and the data of the tone data are incremented to the voltage selection circuit DEC!. At this time, the addition circuit 8〇1 is controlled according to the addition control signal ADD_BIT from the addition control logic 82, and can output the data of the incremental tone data, or output the tone data without change. More specifically, the tone data D[5] :〇] The upper-order 5-bit data D[5:l] is input to the addition circuit 8〇ι. In addition, the data of the top-order bit D[5] in the tone data D[5:〇] is compared with the lowest order. The bit element just inputs the addition control logic 82. The addition control logic 821 inputs the addition timing signals AD1, AD2 generated in the control circuit not shown, and according to the tone data d[5], D[〇] The data and the addition timing signal 〇1, AD2 generate the addition control signal add Fig. 13 is an explanatory diagram showing the addition timing signals AD1, AD2 of Fig. 12. The period of the addition timing signal level corresponds to the first input switch for supplying the tone voltage in the first capacitance element C1 of the output circuit 〇p丨. During the turn-on period of the s〇, the addition timing signal AD2 is the Η level period @, corresponding to the ON period of the second input switch S 1 for supplying the tone voltage in the second capacitive element ^ of the output circuit 0-1. 14 shows the action description of the addition control logic 82 of Fig. 12. In the figure, when the tone data [5:0] is "〇〇〇〇〇〇", the color tone is 127200.doc -32- 200841317 When the tone data [5:0] is "lllm", the color tone is the lowest potential. y, and the control logic 821 is the data of the topmost bit D[5] of the tone data is "0", , , , , , The addition circuit 8〇1 is controlled and controlled by the timing of the addition timing signal AD2. At this time, the data of the lowest order bit D[0] of the tone data is the addition circuit 8〇1, and the tone data D is unchanged. [5:l] data voltage selection circuit DEC1. In addition, the lowest level of tone data protection [〇] The bedding system "in the case of lj, the addition circuit 80! adds the information of "1" to the tone data D[5:1]) to the voltage selection circuit DEC i. The addition control logic 82l adds the power at the timing of the addition timing signal AD1 when the lean material "1" of the uppermost bit d[5] of the tone data is called the addition control. (4), the lowest order of the tone data. In the case of Yuan Gang and 'Department 0', the addition circuit 80 outputs the data of the tone data D[5:1] to the voltage selection circuit DECI without change. Further, in the lowermost bit D of the color tone, the addition circuit 801 outputs the data of the increased color w week D[5:1] to the voltage selection circuit dec!. The output of the adder circuit 1, which is controlled by the addition control logic 821, is input to the voltage selection circuit prison 1 as tone data. The voltage selection circuit DEC τ outputs any of the tone voltages v 〇 v v32 generated by the tone voltage generating circuit 58 to the output circuit OP1 in accordance with the tone data from the adding circuit 80!. The output circuit Oh has a pattern 0 2 · 3 auxiliary capacitance element 127200.doc -33 - 200841317 In this embodiment, as shown in Fig. 5, the auxiliary capacitance element ccs is connected to the node NEG. One end of the auxiliary capacitive element ccs is connected to the grounding power supply voltage vss or the analog grounding AGND, and the other end is connected to the node. Thereby, the voltage change of the inverting input terminal of the transport amplifier circuit OPC! can be suppressed, and the output tone voltage Vout can be further stabilized. Further, since the auxiliary capacitance element CCS is intended to suppress potential fluctuation, it is not necessary to compare the first and second capacitance elements C1 and C2 to accurately form a capacitance value. Therefore, in the capacitive element forming region where the auxiliary capacitive element ccs and the first and second valley elements C1 and C2 are formed, the auxiliary capacitive element CCS must be formed in the first and second capacitive elements ci, C2, etc. A difficult area to control when forming a capacitive element. Therefore, the auxiliary capacitance element CCS must be used as a dummy capacitance element formed in the capacitance element formation region in the source driver. 15(A) and 15(B) are explanatory views showing the storage capacitor element CCS. FIG. 15(A) shows a layout image of the source driver 30. The source driver 3 aligns the source driver blocks SB 1 to SBN in the direction in which the output pads (Pads) of the source lines are arranged. Each of the source driver blocks includes a tone voltage generating circuit, a voltage selecting circuit, and a source line driving circuit, and the layout configuration of each source driver block is the same. Fig. 15(B) shows an image of the capacitance element forming region of the source driver block SBn. The source driver block SBn has a first capacitive element C1 and a second capacitive element C2 in a direction perpendicular to the direction in which the source driver blocks SB 1 to SBN are arranged (the direction in which the output pads are arranged). The capacitive element of the auxiliary capacitive element CCS forms a region CEA. At this time, the auxiliary capacitor 127200.doc -34 - 200841317 element CCS shall be in the boundary of the capacitive element forming region CEA along one of the two boundary portions opposed to the direction perpendicular to the above-described arrangement direction (the direction of intersection) Formed by the Ministry. In general, a virtual capacitive element in the region where the capacitor element is formed is formed in the boundary portion. 15(B), when the arrangement direction of the source driver blocks SB1 to SBN is referred to as DR1, two of the boundary portions of the source driver block SBn which are opposed to the direction DR2 which is perpendicular to the arrangement direction DR1 are formed. One side of the side EDn forms the auxiliary capacitive element CCS, whereby the edges (ends) of the first and second capacitive elements C1, C2 and the edge of the auxiliary capacitive element CCS of the source driver block, and the adjacent source The edges of the first and second capacitive elements C1, C2 of the pole driver block are adjacent. Therefore, since the gaps Δdl to Δ (14) between the respective edges can be formed at substantially the same etching speed, the first and second capacitive elements C1 and C2 can be formed with high precision. In addition, the edges of the auxiliary capacitive element ccs are not the same as the other The edges of the capacitive element are adjacent to each other. Therefore, regarding the edge of the auxiliary capacitive element ccs, such as the etching speed from the output pad arrangement region side, since the etching speeds from the first and second capacitive elements C1, C2 are different, the first Compared with the second capacitive elements C1 and C2, the capacitive elements cannot be accurately formed. As shown in Fig. 15(B), by forming the respective capacitive elements, the capacitances of the first and second capacitive elements C1 and 〇2 can be accurately formed. The value, in addition, does not waste the layout area, but can form the auxiliary capacitance element CCS. 2.4 Operation and amplification circuit The circuit scale of the flip type sample-and-hold circuit in this embodiment must be small. Therefore, the flip (4) (4) in the present embodiment (4) holds the circuit in focus. Sampling 127200.doc -35- 200841317 During the period and the holding period, the operation of the discrete ant note, the operational amplifier circuit suitable for the flip type sample-and-hold circuit shall be adopted. In the flip-type sample-and-hold circuit of the present embodiment, the output switch S4 is turned off during the sampling period, the output of the low load is driven, and the output switch S4 is turned on during the sustain period to drive the output of the high load. In addition, in the operational amplifier circuit of the flip-type sample-and-hold circuit of the present embodiment, the A-stage amplification operation can be performed during the sampling period, and the AB-level amplification operation can be performed during the sustain period. Therefore, the local-shaped L-shaped differential amplification The circuit OPCI to 〇PCn can adopt the following structure: Fig. 16 is a circuit diagram showing a configuration example of the operational amplifier circuit 〇PCi of Fig. 5. Fig. 16 is a view showing an operational amplifier circuit 〇]? (1), but other operations are enlarged. The circuit OPC: 2 to 〇 PCN has the same configuration. The operational amplifier circuit opq includes a differential amplifier 11 〇 (in general, an operational amplifier), an output unit 120, a capacitor CCP, and a charge supply circuit 13 〇. 110 amplifies a difference value between the input voltage VIN and the output voltage VOUT. The output unit 120 includes: a p-type driving transistor (first driving transistor of the first conductivity type) PTR1, which is According to the voltage of the output node NDD of the differential amplifier 11A provided on the first power supply side of the analog power supply voltage AVDD, the gate electrode is controlled; and the N-type driving transistor (the second driving transistor of the second conductivity type) NTR1 is provided in series with the p-type driving transistor pTR1 on the second power supply side of the analog grounding AGND. The capacitor CCP is connected to the gate electrode and the n-type driving transistor of the P-type driving transistor PTR1. The gate electrode of NTR1 is set in. The charge supply circuit 130 supplies charge to the gate electrode of the n-type driving transistor 127200.doc -36- 200841317 NTR1 during sampling, and stops the gate of the N-type driving transistor NTR1 during the holding period. The pole electrode supplies a charge. Thereby, during the sampling period, the P-type driving transistor PTR1 and the N-type driving transistor NTR1 are operated in accordance with the voltage of the output node NDD of the differential amplifier 110, so that the output voltage VOUT of the operational amplifier circuit 100 can be made to the high potential side. Or the low potential side changes. Further, during the sustain period, the output voltage VOUT is output depending on the voltage of the gate electrode of the P-type driving transistor PTR1. Therefore, the A-stage amplification operation during the sampling period can be simplified, and the operational amplifier circuit 0 of the AB-stage amplification operation is performed during the hold period (:1). Fig. 17 is a circuit diagram showing a configuration example of the operational amplifier circuit OPPi of Fig. 16. The same portions as those in Fig. 16 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. The differential amplifier 110 includes a current mirror circuit CM1, a differential pair DIF1, and a current source CS1. The current mirror circuit CM1 is included in its source. The P-type transistors PTR10 and PTR11 of the analog power supply voltage AVDD are supplied to the pole, and the gate electrode of the P-type transistor PTR10 and the gate electrode of the P-type transistor PTR11 are connected. The P-type transistor PTR11 is connected to the gate electrode and the drain. The differential pair DIF1 includes N-type transistors NTR10 and NTR11. The source of the N-type transistor NTR10 is connected to the source of the N-type transistor NTR11. The drain of the N-type transistor NTR10 is connected to the drain of the P-type transistor PTR10. The drain of the N-type transistor NTR11 is connected to the drain of the P-type transistor PTR11. The analog ground AGND is supplied to one end of the current source CS1, and the other end of the current source CS1 is connected to the source of the N-type transistors NTR10 and NTR11. 127200.doc - 37- 200841317 The differential amplifier 110 supplies an input voltage VIN to the gate electrode of the N-type transistor, and supplies an output voltage νουτ to the gate electrode of the N-type transistor >11111. Then, the p-type transistor is connected. 1> The connection node between the drain of the D1 111 and the drain of the 1^-type transistor NTR10 becomes the output node NDD of the differential amplifier 11. The output node is connected to the P-type drive transistor PTR1 of the output portion 12 The gate electrode 13 includes a current source transistor CTR that supplies a current to the diode of the drain thereof, and a gate electrode that connects the current source transistor CTR at one end thereof, and the other end is connected One end of the capacitor cep and the switch circuit swT of the gate electrode of the type transistor 160. The switch circuit S WT is controlled by the switch control signal STC. The charge supply circuit 130 may further include a current source transistor ctr. The drain current generates a current source CS2 of a constant current. Fig. 18 is a view showing the operation of the switch control signal of the sample-and-hold circuit to which the operational amplifier circuit of Fig. 17 is applied. Fig. 18 is the first and second input switches SO. , S1, feedback switch S2, first and first inversion switches S3-1, S3-2 and output switch S4 together to display the operation example of the switch circuit SWT of Fig. 17. As shown in Fig. 18, the switch of Fig. 17 The switch SWT is controlled by a switch control signal STC generated by a control circuit (not shown) to be turned on during sampling and turned off during the hold period. The operational amplifier circuit 〇PC1 of Fig. 17 changes the gate electrode of the n-type drive transistor NTR1 in response to the change of the gate electrode of the p-type drive transistor PTR1 via the capacitor cep. The charge supply circuit 13 is tied to 127200.doc -38 - 200841317

During the sample period, the switching circuit SWT is turned on, and the electric current transistor ctr is used to store the electric charge in the gate electrode of the N-type driving transistor, and the electric energy of the gate electrode of the radiation driving transistor PTR1 is transmitted. To the gate electrode of the N-type driving transistor NTR1. Further, the charge supply circuit (10) disconnects the switch circuit SWT' during the hold period and the voltage change of the gate electrode of the injection drive transistor (4) is transmitted to the N-type drive transistor NTRR gate electrode. In the differential amplifier 110 of the operational amplifier circuit 0PCI having such a configuration, the case where the input voltage VIN is higher than the output voltage ν 〇υ τ is considered. At this time, the voltage of the output node NDD drops, and the drain voltage of the 电-type transistor NTR11 increases. As a result, the voltage of the gate electrode of the 驱动-type driving transistor PTR1 drops, and the P-type driving transistor PTR1 faces the direction of turn-on. Here, when the voltage of the gate electrode of the p-type driving transistor PTR1 drops, the voltage of the gate electrode of the N-type driving transistor NTR1 also drops. Further, the case where the input voltage VIN is lower than the output voltage VOUT is considered in the differential amplifier 110. At this time, the voltage of the output node NDD rises, and the voltage of the N-type transistor NTR11 decreases. As a result, the voltage of the gate electrode of the p-type driving transistor PTR1 rises, and the p-type driving transistor PTR1 faces the direction of the disconnection. Here, when the voltage of the gate electrode of the P-type driving transistor PTR1 rises, the voltage of the gate electrode of the N-type driving transistor NTR1 also rises. As a result of the above operation, the operational amplifier circuit is shifted to an equilibrium state in which the input voltage VIN and the output voltage VOUT are substantially the same potential. The operational amplifier circuit OPQ of FIG. 16 is not limited to the configuration of FIG. Consider that the first power supply is analogous to the power supply of the grounded AGND, and the second power supply is the power supply of the analog power supply voltage AVDD. The first 127200.doc •39· 200841317 conductivity type is N type, and the second conductivity type is P type, such as Fig. 19 is a circuit diagram showing another configuration example of the operational amplifier circuit of Fig. 16. At this time, the output unit 120 includes an N-type drive transistor NTR2, which is based on the differential amplifier 110 provided on the first power supply side. The voltage of the output node controls the gate electrode; and the P-type driving transistor PTR2 is disposed in series with the N-type driving transistor NTR2 on the second power supply side. The difference of the operational amplifier circuit shown in FIG. The dynamic amplifier 110 includes a current mirror circuit CM10, a differential pair DIF10, and a current source CS10. The current mirror circuit CM1 0 includes N-type transistors NTR40 and NTR41 which are supplied with an analog ground AGND in their sources. The gate electrode of the body NTR40 and the gate electrode of the N-type transistor NTR41 are connected to the gate electrode and the drain of the N-type transistor NTR41. The differential pair DIF10 includes the P-type transistor PTR40 and PTR41. The source of PTR40 and the source of P-type transistor PTR41. The drain of P-type transistor φ body PTR40 is connected to the drain of N-type transistor NTR40. The drain of P-type transistor PTR41 is connected to N-type transistor NTR41 The analog terminal supply voltage AVDD is supplied to one end of the current source CS10, and the other end of the current source 10 is connected to the source of the P-type transistors PTR40 and PTR41. The differential amplifier 110 is in the P-type transistor PTR40. The input voltage VIN is supplied to the gate electrode, and the output voltage VOUT is supplied to the gate electrode of the P-type transistor PTR41. Then, the connection node between the drain of the N-type transistor NTR40 and the drain of the P-type transistor PTR40 becomes The output node NDD of the differential amplifier 110. The output node is connected to the gate electrode of the N-type driving transistor 127200.doc -40- 200841317 NTR2 of the output portion 120. The charge supply circuit 130 includes: a current source transistor CTR10, which is Supplying current on its bungee The pole body is connected; and the switch circuit SWT is connected at one end thereof to the gate electrode of the current source transistor CTR10, and the other end thereof is connected to one end of the capacitor CCP and the gate electrode of the p-type drive transistor PTR2. The charge supply circuit 130 can also A current source CS20 is provided which is connected to the drain of the current source transistor CTR1 , to generate a steady current. Since the operation of the operational amplifier circuit 〇pCl of the configuration shown in Fig. 19 is the same as that of the operational amplifier circuit OPC1 shown in Fig. 18, the description will be omitted. 2 _ 5 Output Circuit Modifications In the present embodiment, the output circuit of the source line drive circuit 62 generates two kinds of tone voltages between the first and second tone voltages. However, the variation of the embodiment is generated. Four color tone voltages between one and two tone voltages. That is, in the description of Fig. 5, the configuration example in which j is 4 is the configuration of the present modification. Fig. 20 is a circuit diagram showing an example of the configuration of the output circuit 〇P i of the source line driving circuit 62 according to the modification of the embodiment. The same portions as those in Fig. 5 in Fig. 20 are denoted by the same reference numerals, and the description is omitted as appropriate. Further, Fig. 20 sets the first to fourth input switches sn to SI4, and sets the first to fourth inversion switches δ3_υ3-4. The capacitance values of the first to fourth capacitor elements C1 to C4 are equal. 21(A) and 21(B) are explanatory views showing a first operation example of the output circuit ◦匕 of Fig. 2A. 127200.doc •41 · 200841317 Fig. 21(A) and Fig. 21(B) show the data of the order 2 Bytes as the tone data D[5:〇] 〇[1:〇] is “ An example of the output tone voltage between the first and second tones of 〇 ^ 00 00. As shown in Fig. 21 (A), in the sampling period: the first-tone electric house is given 4·0ν, and the second-tone electric calendar is given to 3·8 V, and the switches SI1 to SI4 are input via the first-in-one four-in-one. All of the first to fourth capacitive elements C1 to C4 are supplied with 4 〇 ν ^ I 伢 , , and port 4.0 v. Then, as shown in Fig. 21(B), during the hold period, the switches S3-1 to S3 are turned over via the first brother.

4 ' Output tone voltage of 4·〇 V by supplying charge to the wheel

Voub Fig. 22(A) and Fig. 22(B) are diagrams showing a second operation example of the output circuit 〇Ρ of Fig. 2A. 22(4) and 22(B) show an example in which the output η5 v is used as the tone data D[5:〇]^TPt2^it^ t#D[l:〇]^r〇lj tones. As shown in Fig. U(4), during the sampling period, 'the first tone voltage Vin1 is given 4g v, and the second tone voltage is given to 3·8 V, via the first to fourth input switches sn to si4, and the fourth is Three of the capacitive elements C1 to C4 are supplied with 4 〇 v, and 3·8 V is supplied to the remaining one of the capacitive elements. Then, as shown in Fig. 22(B): 'In the holding period, the first to fourth inversion switches are called ~(1), #"charge to the output side, according to the law of charge storage, the output of (10) can be outputted to the tone voltage bias. Output ^ (Α) Figure 23 (B) shows the output circuit of Figure 20: the description of the private example. Le-Xun Figure 23 (A), Figure 23 (B) shows the output 3 · 9 〇 V as Tone data 127200.doc •42- 200841317 The lower-order 2 bits of the capital _] is "1." When the first and the -tone voltages are turned out to be the color of the thunder like ^ shooting period door ~ Figure 23 (A) shows that when the pumping voltage is given to 4. 〇V, and the second tone 璧Vin2 is given 3 8 乂, one._ by the younger brother four rounds into the switches SI1 to SI4, and ^ Two of the four capacitor elements C1 to C4 are supplied with 4.0 V, and 3 8 v is supplied to the remaining two capacitor elements. Then, as shown in Fig. 23 (8): during the holding period, via the first to fourth inversion switches Μ·] 』]],

Hunting supplies charge to the output side, and according to the law of charge preservation, it can output an output tone voltage v〇ut of 3.90 V. 24(A) and 24(B) are explanatory views showing a fourth operation example of the output circuit 图 of Fig. 20. Θ 24(A) and Fig. 24(B) show the first and second when the output D[1:0] of the lower-order 2-bit data of 3.85 V is the tone data D[5·0] is "11" An example of the output tone voltage between color and voltage. As shown in Fig. 24(A), during the sampling period, the first tone voltage Vin1 is given 4·0 V, and the second tone battery Vm2 is given to the 3·8 ^ temple via the first to fourth input switches SI1 to SI4. On the other hand, one of the first to fourth capacitive elements C1 to C4 is supplied with 4.0 V, and the other three of the capacitive elements are supplied with 3.8 V. Then, as shown in FIG. 24(B), during the holding period, the first to fourth inverting switches S3-1 to S3-4 are supplied to the output side via the first to fourth inverting switches S3-1 to S3-4, and can be output according to the law of charge storage. Output tone voltage %扒 of 85 V. 3. Modification of the source driver The flip-type sample-and-hold circuit of the present embodiment can also be applied to an output circuit of a so-called multi-drive source driver. 127200.doc -43 - 200841317 Fig. 25 is a block diagram showing a configuration example of a source driver in a modification of the embodiment. In FIG. 25, the same portions as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be appropriately omitted. The source driver in the present modification differs from the source driver in the present embodiment shown in FIG. 4 in that a multiplexer circuit 56 and a separation circuit 64 are provided, and a voltage selection circuit and a configuration constituting the DAC 60 are provided. In the output circuit of the source line driving circuit 62, each source output is time-divisionally supplied with tone data and tone voltage. In Fig. 25, the multiplexing circuit 56 is provided between the line latches. The separation circuit 64 is provided on the output side of the source line drive circuit 62. The multiplexer circuit 56 includes a multiplexer MPXrMPXJk which is a positive integer), and each multiplexer generates a tone of a horizontal scanning portion to be latched by the line latch 54 to q (q is a positive integer, wherein qXk=N) Each source of the strip takes turns to divide the time and multiplex the multiplexed data. FIG. 26 is a view showing the operation of the multiplexer circuit 56 of FIG. 25. • The k in Figure 26 is 24〇. At this time, each of the multiplexers generates multiplexed data in which the tone data corresponding to each source output is time-division multiplexed for each of the 240 source outputs. The first to the 24th source outputs are placed by the line locker 54. The tone data GDi to GD24〇 are used, and the multiplexer is multiplexed by the multiplexer circuit 56. The multiplex control signals SEL1 to SE24 are input to the multiplexers of the multiplexers MPXi to MpXk at predetermined time division timings. Such a kiln control k number SEL1 to SEL240 are generated in a control circuit (not shown) of the source driver 3A. The control circuit is in the horizontal scanning period, for example, any one of the multiplex control signals SEL1 to SEL240 is in the order of 127200.doc -44 200841317, and the control signal is SEL1 ~ SEL240. During each multiplex control signal, the gradation data corresponding to the source output of the multiplex control signal is output as the multiplexed data. Such a multiplexing circuit 56 may also have a plurality of pixels of a plurality of pixels in the early position of the plurality of pixels. The color data may be time-division multiplexed, or may constitute a complex point unit of the same color component of each pixel. . When the pixel is composed of three points, it is possible to generate multi-edition data in which the RGB color data of the two pixel portions are time-divided and multiplexed. this

In addition, if the pixel is composed of three points, it is also possible to generate the multiplexed data of the color data of the pixel MM, the multiplexed data of the color data of the G component, and the color data of the B component. Multi-guard data. The separation circuit 64 of Fig. 25 includes a plurality of detectors X1 to DMPXk, and each of the multiplexers performs an operation opposite to the multiplexer of the multiplexer circuit 56 corresponding to the multi-touch state. That is, the multiplexed resolution Is separates the multiplexed tone voltages from the output circuits of the source line driving circuit 62 and outputs them to the q source outputs. The separation operation timing of the multiplexer is synchronized with the time division timing of each of the multiplexers of the multiplexer circuit 56. 4. Electronic device Fig. 27 is a block diagram showing a configuration example of the electronic device in the embodiment. Here, the electronic device system displays a block diagram of a configuration example of a mobile phone. The same portions as those in Fig. 2 or Fig. 2 are denoted by the same reference numerals, and the description is omitted as appropriate. The mobile phone 900 includes a camera module 91A. The camera module 9 〇 includes (10) a camera, and (10) the image captured by the camera is supplied to the display 127200.doc -45- 200841317 controller 38 in a clear format. The mobile phone 900 includes an LCD panel 20. The LCD panel 20 is driven by a source driver 30 and a gate driver 32. The LCD panel 20 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels. • The display controller 38 is connected to the source driver 30 and the gate driver 32, and supplies the source driver 30 with tone data in RGB format. The power supply circuit 94 is connected to the source driver 30 and the gate driver 32, and supplies a power supply voltage for driving to each of the drivers. Further, a counter electrode voltage VC0m is supplied to the opposite electrode of the LCD panel 20. Host 940 is coupled to display controller 38. The host 94 controls the display controller 38. Further, the host 940 can demodulate the tone data received via the antenna 960, and demodulate it by the modulation/demodulation unit 950, and supply it to the display controller 38. The display controller 38 is displayed on the LCD panel 20 by the source driver 3 and the gate driver 32 in accordance with the tone data. The host 940 can instruct the tone data generated by the camera module 91 to be modulated by the modulation and modulation unit 950, and then transmitted to other communication devices via the antenna 96. The host computer 940 performs transmission and reception processing of color tone data, imaging of the camera module 91, and display processing of the LCD panel based on the operation information from the operation input unit 97. Further, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention. The present invention is not limited to the driver applied to the liquid crystal display panel described above, and is also applicable to the driving of electroluminescence or a plasma display device. In addition, the present invention towel, the date of issue of the dependent request item, may also omit part of the constituent elements of the dependent item of the 127200.doc -46-200841317 sub-image. In addition, important parts of the invention of one independent claim of the present invention may also be subordinate to other independent claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an example of the configuration of a liquid crystal device according to this embodiment. Fig. 2 is a view showing another example of the configuration of the liquid crystal device of the embodiment. Fig. 3 is a block diagram showing a configuration example of the source driver of Fig. 。. 4 is a block diagram showing a configuration example of the source driver of FIG. 1 or 2. Fig. 5 is a circuit diagram showing an example of the configuration of an output circuit of the source line driving circuit of Fig. 4. Fig. 6 is an explanatory diagram showing a first operation example of the output circuit of Fig. 5. Fig. 7 is an explanatory diagram showing a second operation example of the output circuit of Fig. 5. Fig. 8 is an explanatory diagram showing a third operation example of the output circuit of Fig. 5. Fig. 9 is an explanatory diagram showing a fourth operation example of the output circuit of Fig. 5. Fig. 1 is a diagram showing the operation of this comparative example. Fig. 11 is an explanatory diagram showing the output order of the tone voltage in the embodiment. Fig. 12 is a block diagram showing a configuration example of a source driver block of a source driver in the embodiment. Figure 13 is an explanatory diagram of the addition timing signal of Figure 12. Fig. 14 is a view showing the operation of the addition control logic of Fig. 12. 15(A) and 15(B) are explanatory views of the auxiliary capacitance element CCS. Fig. 16 is a circuit diagram showing a configuration example of the operational amplifier circuit of Fig. 5. Fig. 17 is a circuit diagram showing a configuration example of the operational amplifier circuit of Fig. 16. Fig. 18 is a diagram showing the operation of the sampling and holding circuit of the operational amplifier circuit of Fig. 17 127200.doc • 47· 200841317. Fig. 19 is a circuit diagram showing another configuration example of the operational amplifier circuit of Fig. 16. Fig. 20 is a circuit diagram showing a configuration example of a wheel circuit of a source line driving circuit according to a modification of the embodiment. 21(A) and 21(B) are explanatory views showing a first operation example of the output circuit of Fig. 20. 22(A) and 22(B) are explanatory views showing a second operation example of the output circuit of Fig. 20. 23(A) and 23(B) are explanatory views showing a third operation example of the output circuit of Fig. 20. 24(A) and 24(B) are explanatory views showing a fourth operation example of the output circuit of Fig. 20. Fig. 25 is a block diagram showing a configuration example of a source driver in a modification of the embodiment. Fig. 26 is a view showing the operation of the multiplexer circuit of Fig. 25. Fig. 27 is a block diagram showing a configuration example of an electronic device in the embodiment. [Main component symbol description] 10 LCD device 20 LCD panel 30 Source driver 32 Gate driver 38 Display controller 50 I/O buffer 52 Display memory 127200.doc -48- 200841317

54 Line Latch 58 Tone Voltage Generation Circuit 60 DAC 62 Source Line Driver Circuit 66 Address Control Circuit 68 Column Address Decoder 70 Line Address Decoder 72 Line Address Decoder 801 Addition Circuit 821 Addition Control Logic 90 Display Driver 94 Power supply circuit AGND Analog grounding Cl First capacitive element C2 Second capacitive element CCS Secondary capacitive element DECI ~ DECn Voltage selection circuit GL1 ~ GLM Gate line NEG Node OP i ~ OPn Output circuit opc! Operational amplification circuit so first input Switch SI Second input switch S2 Feedback switch 127200.doc • 49· 200841317 S3-1 First flip switch S3-2 Second flip switch S4 Output switch SCO~SC4 Switch control signal SL1~SLN Source line Vout Output tone Voltage

127200.doc 50-

Claims (1)

200841317 X. Patent application scope: 1 · Kind of source driver, which is characterized by being used to drive the source line of the optoelectronic device, and includes: a color = electric dust generating circuit, which corresponds to the tone data, and the output And a source line driving circuit for driving the source line according to the first and second tone powers t′; the source line driving circuit includes flipping (Flip eight) (7) a fairy-type sample-and-hold circuit that outputs an output tone voltage between the first tone voltage and the second tone voltage to the source line. 2. The source driver of the present invention, wherein the flip type The sample-and-hold circuit includes: an electric operation amplifying circuit; and a plurality of capacitive elements connected to the input of the operational amplifier circuit at one end; ▲ electrically interrupting the output of the operational amplifier circuit and the rain source line during the sampling period a state in which the wheel of the operational amplifier circuit is electrically connected: and the wheel of the plurality of capacitive elements of the plurality of capacitive elements is stored corresponding to the first or The charge of the two-tone voltage; during the hold period after the sampling period, the current interrupted output = output 'will be supplied to the second circuit of the complex capacitors (4) (4) The output voltage is output to the source line. • If the source driver of the item 1 is specified, the pot Φ 铪, the cutting tool is used for the inverted type sampling and holding power 127200.doc 200841317 Road includes: It is connected to the non-inverting input terminal The supply is turned on, and is inserted between the reverse wheel terminal of the operational amplifier circuit and the output of the operational amplifier circuit; one end is connected to the anti-Korean wheel. (j is an integer of 2 or more) capacitive element; The first to the jth flip switch, the 1st eight-series brother p (l SpSj, P is an integer), the flip switch is inserted between the other end of the aforementioned step P electric grid element and the output of the operational amplifier circuit; The jth input switch is issued in Chu; k/v _ eight-phase P-wheel switch is connected at one end of the P-th power switch to the other end; and the output switch is spoofed between the two source lines; ... the output of the operational amplifier circuit and the foregoing Computing the amplifying circuit voltage; supplying the two-tone voltage to the other end of each of the input switches of any one of the first to jth capacitive voltages of the first to the jth capacitors of the feedback switch during the first or the first sampling period; In the state in which the first to the jth inversion switches are turned on and the above-described turn-off switch is turned on, the first and second color tones J to the image phase are supplied to the other end of the π-piece. During the hold period of the captive*~jth flip switch, the first switch is turned on, the P# switch is turned off, and the feedback switch is turned on, and the output is turned on, and only the first output tone is given. The tone voltage and the aforementioned second tone voltage are pulsed out to the aforementioned source line. 127200.doc >2- 200841317 4. The source driver of claim 3, wherein the aforementioned (4) lowest potential electric power to the aforementioned source line is close to the output of the highest potential electric material, the aforementioned color electric circuit 2 The potentials are sequentially outputted to the first and second tone voltages; the output tone voltage is lower than the last potential potential "±▲ K" potential voltage is close to the minimum power C, and the tone voltage generating circuit has a low potential The sequence outputs the first and second tone voltages. "', the source drive 15 of item 4, wherein the output tone voltage is closer to the highest potential power (four) than the above-mentioned = low potential voltage, and the tone voltage on the potential side is supplied to the aforementioned first in the first first tone voltage - in the state of any one of the J-capacitor elements, the tone voltage on the low potential side is supplied to any of the first -1 (1) capacitive elements - the manner of each of the seven elements is 'the first to the first input' Control of the switch. W ^ The source driver of claim 4, wherein the output tone voltage is closer to the lowest potential voltage than the potential potential voltage, and in the first and the first color 5 weeks, the low potential side In the state in which the tone is supplied to any one of the first to the Jth capacitive elements, the color tone voltage on the high potential side is supplied to the 钕, +, + electric socket for the ν' mouth to the month U 4 first~ The method of any one of the capacitive elements of the jth capacitive element, the switching of the first to the jth input switch can be described as follows. 7. The source driver of any of claims 3 to 6, wherein the foregoing the first~ The capacitance values of the capacitive elements of the j-valley element are equal. 8. The source driver of any of the items 2 to 6 is included in the - terminal 127200.doc 200841317. The voltage of the voltage is in the other The auxiliary capacitor element is connected to the inverting input terminal of the operational amplifier circuit. The source driver of claim 8, wherein the auxiliary capacitor element is used as a dummy capacitor element formed in the capacitor element forming region. The source driver of claim 8, wherein each of the source driver blocks driving the source lines of the optoelectronic device comprises a plurality of source driver blocks, wherein the tone voltage generating circuit and the source line driving circuit are included Each source driver block has a capacitive element forming region forming the first j-th capacitive element and the auxiliary capacitive element in a direction intersecting with the discharge of the plurality of source driver blocks; the auxiliary capacitive element is The boundary between the capacitive element forming regions is formed along a boundary opposite to the direction in which the arrangement direction is intersected. a source driver of the source device, wherein each of the source lines of the respective optoelectronic devices driving the source line 11 comprises a plurality of source driver II blocks, wherein the tone voltage generating circuit and the source line driving circuit are included; The 纟 source driver block has a capacitive element forming region forming the first to jth capacitive elements and the auxiliary capacitive element in a direction intersecting the row 2 direction of the plurality of source driver blocks; the auxiliary capacitive element In the boundary of the aforementioned capacitive element forming region, a source driver is formed along the boundary opposite to the direction in which the foregoing arrangement direction intersects. 12. The source driver according to any one of claims 2 to 6, wherein the aforementioned operation The amplifier circuit performs an A-stage amplification operation during the sampling period, and performs an AB-stage amplification operation during the holding period. The source driver of any one of claims 2 to 6, wherein the operational amplifier circuit comprises: an operational amplifier that amplifies a differential value between an input of the operational amplifier circuit and an output of the operational amplifier circuit; a first driving transistor, which is disposed on the first power supply side, controls the closed electrode according to the voltage of the output node of the operational amplifier; and a second driving transistor of the second conductivity type, which is the first The driving transistor is disposed in series on the second power source side; the capacitor is used for the capacitor to consume the gate electrode of the first (four) transistor and the gate electrode of the second driving transistor; and 14. The source driver of claim 13 a current generating circuit; and a switching circuit, which is inserted into the line, and is inserted before the Φ, and goes to the female. 丨 1 The manner in which the capacitors are disconnected can be controlled by switches. 15. The source driver of claim 14, wherein the current generating circuit includes a current source transistor that supplies current to the drain and the diode is connected; and the switch circuit is inserted as described above. An optoelectronic device of the gate electrode of the current source transistor and the terminal of the capacitor and the gate electrode of the second driving transistor, characterized in that: a plurality of scanning lines; a plurality of source lines; each of the plurality of scanning lines of the plurality of source lines; and the plurality of pixels of the plurality of source lines; and the plurality of source lines of the plurality of source lines The source driver for the plurality of source lines is driven. 17. An electronic machine characterized by a source driver. 18. An electronic machine characterized by a setting. Contains any of the items 1 to 15 as contained in claim 1 and 127200.doc