200830082 determine the charge time of the voltage source to shift the voltage of the control node of the first transistor pair. 七、 指定代表圖： (一) 本案指定代表圖為：第（5 )圖。 (二) 本代表圖之元件符號簡單說明： 500 電壓調整電路 501、503 電壓提升單元 502、504 控制電路 510 交錯耦合式拾鎖電路200830082 determines the charge time of the voltage source to shift the voltage of the control node of the first transistor pair. VII. Designated representative map: (1) The representative representative map of the case is: (5). (2) Brief description of the component symbols of this representative diagram: 500 voltage adjustment circuit 501, 503 voltage boosting unit 502, 504 control circuit 510 interleaved coupled pickup circuit
511、512 PMOS 513、514 NMOS 540 反向器鏈 八、 f案若有化學式時，請揭示最能顯示發明特徵的化學 (無） 九、 發明說明： 【發明所屬之技術領域】 本發明係關於一種電壓調整電路以及其控制方法，特別是 指-種具有預充祕，使得交_合雜鎖電 latch)能有更快的反應時間將輸出電壓調整至所需電位的一種 電壓調整電路以及其控制方法。 【先前技術】 200830082 電路系統中，針對不 級電路需要推動負载而需要大:丰:=;電_ ’例如後 晶片（1C)而言，則必 羊的電源荨荨，對於積體電路 在習知技術十通常六、不同電縣位的訊號做電>1轉換， latch)來達到調整電屋準;式麵電路（咖㈣_d 考電_ 含有-。型金氧半二== 對中PMOS_# (gate)為該電晶 =對中嶋卿皆耗合至另一電晶趙對之二：， 圖斤不之又錯轉合式拾鎖電路100為例，電晶體對ι〇ι包含有 PMOS110 ’其源極轉合至一高電麼源vddh，沒極則盥 NMOS130·極轉合形成節點1〇3，應〇813〇的源極則麵合^ 地’電aB體對102包含有PMOS120，其源極搞合至一高電壓源 VDDH，汲極則與NMOS140的汲極耦合形成節點1〇4， NMOS140的源極則耦合至地。其中？河〇811〇的閘極為電晶體 對101的控制節點，搞合至節點104形成交錯耦合式拴鎖電路1〇〇 的電壓輸出端’而PMOS120的閘極為電晶體對1〇2的控制節 點’躺合至郎點103 ’交錯搞合式拾鎖電路1〇〇另包含有一反相 器150，輸入電壓Vin耦合至NMOS130的閘極，另一方面經由反 相器150反向後耦合至NMOS140的閘極。 反相器150的操作電壓與輸入電壓Vin準位皆為VDD，當輸 200830082 入電壓Vin為VDD時NMOS130會導通（turn on)而NMOS140 不導通（turnoff)，所以節點1〇3電壓為〇使得PM〇S12〇導通， 將節點104的輸出電壓Vout提升到較高的電壓值VDDH，因此 PMOS110不導通，節點103電壓仍維持在〇。當輸入電壓乂出為❹ a寺NMOS130不導通而NMOS140導通，節點1〇4的輸出電壓v〇ut 會被降到0V，因此PMOS110導通，節點103電壓值被提升到 VDDH使得PMOS120不導通，輸出電壓v〇ut維持0V。 然而，由於PMOS110、PMOS120的閘極電壓取決於 NMOS130、NMOS140導通與否，亦即考慮暫態時，NM〇S13〇、 NMOS140必須在PMOS110、PMOS120之前動作，因此在設計 時NMOS130、NMOS140的寬長比（aspect ratio)必須較大以使 得其與PMOS110、PMOS120相比之下較有主控性（str〇nger)， 如此一來，交錯耦合式拴鎖電路1〇〇才能正常工作。不過，這同 時也造成輸出電壓Vout在由0 V提升至VDDH的上升時間（rising time)與從VDDH下降至0V的下降時間（faUing time)並不相 等，也就是說輸出電壓對比於輸入電壓會有一定量的失真，若 輸入電壓為一脈衝寬度調變（PWM)訊號，在考慮製程誤差的 情況下此失真會更加嚴重。另外，雖然輸出電壓v〇ut會隨著輸 入電壓Vin的電壓準位改變而改變，然而在轉換時因為pM〇s的 主控性比較弱（weaker)，節點靠PMOS提升電壓的速度會比 NMOS導通的速度慢，因此會發生同一電晶體對的pM〇s尚未 元全不導通日寸NMOS即已導通的情形’造成在輸入電壓的電 壓準位改變時會有大電流流經電晶體對而形成功率損耗。 請參考第2圖，第2圖為另一習知技術交錯耦合式拴鎖電路 200830082 可輕易得知其作用與第j圖之交錯轉 時也具有相同的缺點，在此不再贅述。M電路100相同’同 【發明内容】 由是，本發明之主要目的，即在於 的電壓調整電路及其控制方法，你尸甘=I、有預充功月b ^之敎，且其上升_ (risingtime)及下降咖（髓ng time)不致失真太嚴重，以解決上述問題。 根據本發明-實補，其係龍—種具有預充魏的電壓 »周正電路，其包含有一交錯轉合式射貞電路（__ latch) ’其具有連接方式互相對稱之一第一、第二電晶體 一電晶體對皆接收該輸人龍且每—電晶體對之—輸出端皆互 她合至另-電晶體對之-控制節點，其中該第二電晶體對之 輪出端電壓即為該輸出電壓電壓提升單元，合至一電源 1、/亥第電晶體對之s亥控制節點，用來提升該控制節點之電 左，以及控制電路，搞合至该電壓提升單元與該輸入電壓， 可偵測該輸入電壓之變化以提供一脈衝（pulse)，該脈衝可控 制該電壓提升單元以決定該電源對該第一電晶體對之該控制節 點之充電時間。 根據本發明另一實施例，其係揭露一種調整電壓的控制方 法，用來將一輸入電壓轉換至具有較高電壓值之一輸出電壓， 200830082 其包含有提供連接方式互相對稱之一第一、第二電晶體對，每 一電晶體對皆接收該輸入電壓且每一電晶體對之一輪出端皆互 相耦合至另一電晶體對之一控制節點，其中該第二電晶體對之 輸出端電壓即為該輸出電壓；偵測該輸入電壓之變化以提供— 第一脈衝；以及根據該第一脈衝來控制一電源對該第一電晶體 對之該控制節點之充電時間。 【實施方式】 由上所述，習知技術的缺點在於當一電晶體對中 不導通時，其輸出電壓必須由該電晶體對中的PM〇s來往 VDDH提升’而該PMOS在設計上較弱（weaker)(亦即寬長比 (aspectratio)較小，電流流通能力較弱）；而在1^]^1〇8導通時， 該PM0S的控制節點（即PM0S的閘極）電壓必須由另一電晶體 對中同樣較弱的PM0S將該控制節點的電壓提升後才能=該 PM0S關閉，此一現象導致輸出電壓Vout不論從0V到VDDH^ 是由VDDH到0V都需要-段轉換時間，而這段轉換時間並不對 稱而造成電壓訊號失真，而且會造成功率損耗。 率損耗 於是本發明提供一種電壓調整電路及其控制方法，可以在 輸入電壓Vin改變時預先將控制節點t電，使得輸出電壓ν⑽ 的改變更似及上升時間與下降時間更加對顯減少失真及功 首先凊參考第3®，第3圖為本發财電駿升單元观 制電路3G2之電路圖，在本實施例中，提升單元則為二^ 極搞合至高電_VDDH的Ρ型金氧半電晶體（pM〇s)训'，、 200830082 但是也可以用其他不同的電路來實施，PMOS310的汲極可耦合 至前述習知技術中所提到的交錯耦合式拴鎖電路100、200中的 控制節點，當PMOS310導通時，便可以將控制節點的電壓往 VDDH提升，加速控制節點的電壓到達預定的電壓值，而當 PMOS310不導通時，則可視為與交錯耦合式拴鎖電路1〇〇、2〇〇 間斷路。PMOS310導通與否係由控制電路3〇2來控制，控制電 路302包含有一PMOS320、兩NMOS330與340、一延遲單元350 以及一反向器360。PMOS320耦合至高電壓源VDDH，由於其 閘極接地，故PMOS320可視為一電阻；一互相串聯並分別耦合 至PMOS320與地之間的NMOS330與NMOS340，其作用類似於 一反及閘（NAND gate )，當此二NMOS的閘極（亦即NAND gate 的二輸入端）電壓為電壓準位”1”時（亦即電壓VDD)NMOS330 與NMOS340會導通，於是NMOS330與PMOS320的耦合接點p 電壓為0，該耦合接點P電壓即為PMOS310的閘極電壓，因此使 得PMOS310導通。輸入電壓Vin經由延遲單元350延遲一預定時 間後輸入NMOS330的閘極，同時輸入電壓Vin亦經由反向器360 反向後輸入NMOS340的閘極’如第4圖所示，當輸入電壓vin 由電壓準位’Τ’改變至電壓準位，，〇，，時，在該預定時間内 NMOS330與NMOS340的閘極電壓皆為VDD，導致PMOS310的 閘極電壓為一脈衝，其脈衝寬度可由延遲單元35〇來控制，在該 脈衝寬度時間内PMOS310導通，將交錯耦合式拴鎖電路1〇〇、 200中的控制節點的電壓往VDDH提升，加速控制節點的電壓到 達預定的電壓值，由此可知，當輸入電壓Vin沒有發生改變時摩馬 合接點P電壓為VDDH，PMOS310不導通。 200830082 明參考第5圖，第5圖為本發明電壓調整電路5〇〇第一實施例 的電路圖’電壓調整電路包含有—交錯輕合式拾鎖電路 510、兩電壓提升單元501與5〇3、兩控制電路5〇2與5〇4以及一反 =器鏈540。其中交錯耦合式拴鎖電路51〇的結構與運作原理與 前述之交錯耦合式拴鎖電路100相同，而電壓提升單元5〇1與5〇^ 的結構與運作原理與前述之電壓提升單元301相同，控制電路 502與504的結構與運作原理則與前述之控制電路3〇2相同，反向 器鏈540則作為反向功能與延遲功能，現詳述其工作原理如下。 當輸入電壓Vin為電壓準位”1”（即VDD)時，節點b、d電壓皆 為VDD，節點a、c電壓則為〇,因此節點e、f電壓為vddh，電 壓提升單元501與503皆不導通，節點b電壓為VDD使得 NMOS513導通，控制節點g電壓為〇，使得PM〇S512導通，另 外因為節點c電壓為0使得NMOS514不導通，因此輸出電壓v〇ut 為VDDH ’ PMOS511不導通。當輸入電壓vin由電壓準位，，i”改 變至電壓準位（即電壓〇)時，節點a電壓由〇變至VDD，但 郎點d此時尚未改變（因為節點a至節點d間相隔三個反向器，因 此造成一延遲時間），電壓值仍是VDD，因此節點e電壓迅速被 拉至0導至電壓提升單元501導通，因此節點g的電壓被高電源 VDDH預充，其預充時間可藉由反向器鏈54〇的反向器數目來調 整，節點b電壓變為0後NMOS513不導通，控制節點g的電壓值 藉由預充迅速提升至VDDH，使得PMOS512不導通，當節點〇 電壓變為1時NMOS514導通，輸出電壓Vout為〇，PMOS511導 通，最後節點d電壓變至〇，節點e電壓恢復至VDdh，預充過程 結束，整個電壓調整電路500恢復穩態操作。另一方面，當輸入 200830082 包壓\^1由電壓準位”〇”改變至電壓準位”丨，，（即電壓VDD)時， :點c此時尚未改變（因為輸入電壓端至節點c間相隔三個反向 态’因此造成一延遲時間），電壓值仍是VDD，因此節點[電壓 ，速被拉至0導至電壓提升單元5〇3導通，因此輸出電壓v—被 而電源VDDH預充，其預充時間可藉由反向器鏈54〇的反向器數 目來調整，輸出電壓Vout可藉由預充迅速提升至VDDH，當節 點c電壓變為〇後NMOS514不導通，輸出電壓v〇ut固定為 VDDH，節點f電壓恢復至VDDH，預充過程結束，整個電壓調 整電路500恢復穩態操作。 請參考第6圖，第6圖為本發明電壓調整電路6〇〇第二實施例 的電路圖，其與第5圖之電壓調整電路500的不同處在於將電壓 調整電路500中的交錯轉合式拾鎖電路51〇替換成類似前述之交 錯耦合式拴鎖電路200的結構，當輸入電壓Vin為電壓準位，τ， (即VDD)時，節點b電壓為VDD，NM〇S613不導通，節點c 電壓為0，NMOS614導通，導致PMOS612導通，輸出電壓v〇m 為VDDH。當輸入電壓Vin由電壓準位”丨，，改變至電壓準位，，〇，， (即電壓0)時，控制電路602使得電壓提升單元6〇1將控制節點 g的電壓值預充至VDDH，PMOS612不導通，此時因為節點匕的 電壓變為0 ’ NMOS613導通，所以輸出電壓被拉至〇。當輸入電 壓Vin由電壓準位，，〇，，改變至電壓準位”r，（mVDD")時， NMOS613不導通而NMOS614導通，控制電路6〇4使得電壓^升 單元603將輸出電壓v〇ut預充至VDDH。 请參考第7圖，第7圖為本發明電壓調整電路第三實施例 的電路圖，其中的交錯耦合式拴鎖電路為前述之交錯耦合式拴 11 200830082 鎖電路100與200的混合使用，其功能與操作原理與交錯柄合式 拴鎖，路100、200完全相同’因此電翻整電路7〇〇與前述之第 一:第二實酬的功能與操作原理亦相似，習知技藝者可輕易 推論得之，在此不予贅述。 二 請參考第8圖，第8圖為本發明電麼提升單元謝與控制電路 80^之電關，電壓提升單元謝與㈣·8()2與麵之電壓提 升單7L3G1與控制電路302在使用元件與電路上非常相似，唯一 不同在於NMOS830的閘極_合至輸出電壓ν_，而不是像第 3圖之控制電路302般耦合至一延遲後之輸入電壓，但是由於輸 出麵Vin與輸出電壓Vout間本來就存在有時間延遲，因此可以 達到與控制電路302類似的效果。 明參考第9圖’第9圖為本發明電壓調整電路9〇〇第四實施例 的電路圖’電壓碰電路議包含有—交錯搞合式拾鎖電路 910、兩電壓提升單元9〇1與9〇3、兩控制電路9〇2與9_及一反 =器鏈。其中交錯輕合式拾鎖f路910的結構與運作原理與 則述之交錯#合式拾鎖電路100相同，而電顧^升單元刪與则 的結構與運作原理與前狀電壓提升單元_目同，控制電路 902與904的結構與運作原理則與前述之控制電路8〇2相同，反向 器鏈940則作為反向功能，現詳述紅作原理如下。當輸入電壓 Vm為電壓準位，’Γ (即VDD)時，節點b電壓為vdd，節點&、 c電壓則為0 ’因此節點e、f電壓為VDDH，電壓提升單元9⑴與 903皆不導通，節點b電壓為VDD使得雇〇8913導通，控制^ 點g電壓為〇，使得PMOS912導通，另外因為節點c電壓為〇使得 NMOS914不‘通，因此輸出電壓v〇i^vddh，pm〇S911不導 12 200830082 通。當輸入電壓Vin由電壓準位”1”改變至電壓準位，，〇，，（即電壓 〇)時，節點a電壓由0變至VDD，但輸出電壓VouU(；4時尚未改變， 電壓值仍是VDDH，因此節點e電壓迅速被拉至〇導至電壓提升 單元901導通，因此節點g的電壓被高電源VDDH預充，節點b 的電壓變為0後NMOS913不導通，控制控制節點g的電壓值可藉 由預充迅速提升至VDDH，使得PMOS912不導通，當節點£電 壓變為1時NMOS914導通，此時輸出電壓v〇ut才變為〇， PMOS911導通，節點e的電壓也恢復svDDH，預充過程結束， 整個電壓調整電路900恢復穩態操作。當輸入電壓乂匕由電壓準 位”0”改變至電壓準位”1”（即電壓VDD)時，控制節點g的電壓 值此時尚未改變，電壓值仍是VDDH，因此節點『電壓迅速被拉 至〇導至電壓提升單元903導通，因此輸出電壓v〇ut被高電源 VDDH預充，當節點c電壓變為(^NM〇S914不導通，輸出電壓 Vout固定為VDDH，節點f電壓恢復至VDDH，預充過程結束， 整個電壓調整電路9〇〇恢復穩態操作。 请參考第10圖，第10圖為本發明電壓調整電路第五實 施例的電路圖，其與第9圖之電壓調整電路9〇〇的不同處在於將 電壓調整電路900中的交錯耦合式拴鎖電路91〇替換成類似前述 之父錯耦合式栓鎖電路2〇〇的結構，當輸入電壓▽匕為電壓準 位”1”（即VDD)時，節點b電壓為VDD，NM〇sl〇13f導通， 節點c電壓為〇，NMOS1014導通，導致PMOS1012導通，輸出 電壓Vout為VDDH。當輸入電壓yin由電塵準位”1”改變至電壓 準位”0”（即電壓〇)時，控制電路1〇〇2使得電壓提升單元1〇〇1 將控制節點g的電壓值預充至VDDH，PM〇S1〇12不導通，此時 13 200830082 因為郎點b的電壓變為0，NMOS1013導通，所以輸出電壓被拉 至〇。當輸入電壓Vin由電壓準位”〇”改變至電壓準位，，ι，，（即 VDD)時’NMOS1013不導通而NMOS1014導通，控制電路1〇〇4 使得電壓提升單元1003將輸出電壓Vout預充至VDDH。 睛參考第11圖’第11圖為本發明電壓調整電路H00第六實 施例的電路圖，其中的交錯耦合式拴鎖電路為前述之交錯耦合 式拾鎖電路100與200的混合使用，其功能與操作原理與交錯麵 合式拴鎖電路100、200完全相同，因此電壓調整電路11〇〇與前 述之第四、第五實施例的功能與操作原理亦相似，習知技藝者 可輕易推論得之，在此不予贅述。 請注意，實施例一到實施例六中雖然都使用兩組電壓提升 單元與兩組控制電路，但是實際應用上可視需求而只使用一組 電壓提升單元與控㈣路，也就是說，可視需要選擇性地只預 充控制節點或者輸出端的電壓其中之一。 、 雖然本發明已揭露較佳實施例揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不麟本發明之精神和範圍 内田可作些許之更動與潤飾，因此本發明之保護範圍當視德 附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖為習知技術交錯轉合式拾鎖電路之電路圖。 第2圖為另_f知技術交錯#合式栓鎖電路之電路圖。 第3圖為本發明中電顧升單元與控制電路之電路圖 _為第3圖中輸入電壓Vin、延遲輸入電壓、反向輸入電壓以 14 200830082 及接點p電壓之波形圖。 第5圖為本發明電壓調整電路第一實施例之電路圖。 第6圖為本發明電壓調整電路第二實施例的電路圖。 第7圖為本發明電壓調整電路第三實施例的電路圖。 第8圖為本發明電壓提升中單元與控制電路之電路圖。 弟9圖為本發明電壓調整電路第四實施例的電路圖。 弟10圖為本發明電壓調整電路第五實施例的電路圖。 第11圖為本發明電壓調整電路第六實施例的電路圖。 【主要元件符號說明】 100'200、510、910 交錯耦合式拴鎖電路 101 ^ 102 電晶體對 103、104 節點511, 512 PMOS 513, 514 NMOS 540 reverser chain VIII, f If there is a chemical formula, please disclose the chemical that best shows the characteristics of the invention (none) IX. Description of the invention: [Technical field of the invention] The present invention relates to A voltage adjusting circuit and a control method thereof, in particular, a voltage adjusting circuit having a pre-filling secret so that a cross-locking latch can have a faster reaction time to adjust an output voltage to a desired potential and Control Method. [Prior Art] In the circuit system of 200830082, it is necessary to push the load for the non-level circuit and need to be large: abundance: =; electricity _ 'For example, after the chip (1C), the power supply of the sheep must be used for the integrated circuit. Know the technology ten is usually six, the signal of different electricity county level to do electricity > 1 conversion, latch) to achieve adjustment of the electricity house standard; surface circuit (coffee (four) _d test _ contains -. type gold oxygen half two == PMOS _ # (gate) is the electric crystal = the pair of Zhongqing is consumed to another electric crystal Zhao to the second:, the figure is not wrong and the wrong type of lock-up circuit 100 as an example, the transistor pair ι〇ι contains PMOS110 'The source is turned to a high-voltage source vddh, the 没 130 130 130 130 130 130 130 130 130 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 电 电 电 电 电The source is coupled to a high voltage source VDDH, the drain is coupled to the drain of the NMOS 140 to form a node 1 〇 4, and the source of the NMOS 140 is coupled to ground. The gate of the 〇 〇 〇 is extremely transistor pair 101 The control node is coupled to the node 104 to form a voltage output terminal of the interleaved shackle circuit 1 而 and the PMOS 120 gate is electrically The control node of the body pair 1 〇 2 is slid to the lap point 103 'the interleaved latching circuit 1 〇〇 further includes an inverter 150 , the input voltage Vin is coupled to the gate of the NMOS 130, and the inverter 150 is coupled via the inverter 150 The NMOS 130 is turned on and the NMOS 140 is turned off when the input voltage Vin is VDD. Therefore, the voltage of the node 1〇3 is 〇 such that the PM〇S12〇 is turned on, and the output voltage Vout of the node 104 is raised to a higher voltage value VDDH, so the PMOS 110 is not turned on, and the voltage of the node 103 is maintained at 〇. When the input voltage is turned off, ❹ a Temple NMOS130 is not conducting and NMOS140 is turned on, the output voltage v〇ut of node 1〇4 will be reduced to 0V, so PMOS110 is turned on, the voltage value of node 103 is raised to VDDH so that PMOS120 is not turned on, and the output voltage v〇ut is maintained at 0V. However, since the gate voltages of PMOS110 and PMOS120 depend on whether NMOS130 or NMOS140 is turned on or off, that is, when transients are considered, NM〇S13〇 and NMOS140 must operate before PMOS110 and PMOS120, so NMOS is designed. 130. The aspect ratio of the NMOS 140 must be large so that it is more mastered than the PMOS 110 and the PMOS 120, so that the interleaved coupled latch circuit can be used. normal work. However, this also causes the output voltage Vout to rise from 0 V to VDDH and the faing time from VDDH to 0V, which means that the output voltage is compared to the input voltage. There is a certain amount of distortion. If the input voltage is a pulse width modulation (PWM) signal, the distortion will be more serious considering the process error. In addition, although the output voltage v〇ut will change with the change of the voltage level of the input voltage Vin, in the conversion, because the main control of pM〇s is weak, the node will increase the voltage by PMOS than the NMOS. The conduction speed is slow, so the pM〇s of the same transistor pair may not be fully turned on. The case where the NMOS is turned on' causes a large current to flow through the transistor pair when the voltage level of the input voltage changes. Form power loss. Please refer to FIG. 2, which is another conventional technique of the interleaved shackle circuit 200830082. It can be easily seen that the function has the same disadvantages as the interleaving of the j-th diagram, and will not be further described herein. M circuit 100 is the same 'same content', the main purpose of the present invention is that the voltage adjustment circuit and its control method, you are guilty = I, there is a pre-charged power b ^, and its rise _ ( Rising time) and falling ng time are not too severe to solve the above problem. According to the present invention, the squadron has a pre-charged voltage » Zhou Zheng circuit, which includes a staggered turn-on type 贞 circuit (__ latch) 'which has one of the connection modes symmetrical to each other, the first and second The crystal-transistor pair receives the input transistor and each of the transistor pairs-output terminals are coupled to the other-transistor pair-control node, wherein the voltage of the second transistor pair is The output voltage and voltage boosting unit is coupled to a power supply 1, a second transistor pair shai control node for boosting the power left of the control node, and a control circuit to engage the voltage boosting unit and the input voltage The change in the input voltage can be detected to provide a pulse that can control the voltage boosting unit to determine the charging time of the power supply to the control node of the first transistor pair. According to another embodiment of the present invention, a method for controlling voltage adjustment is disclosed for converting an input voltage to an output voltage having a higher voltage value, and 200830082 includes one of providing a connection mode that is symmetrical to each other. a second pair of transistors, each of the pair of transistors receiving the input voltage and one of the turns of each pair of transistors is coupled to one of the control nodes of the other transistor pair, wherein the output of the second transistor pair The voltage is the output voltage; detecting the change in the input voltage to provide a first pulse; and controlling a power source to charge the control node of the first transistor pair based on the first pulse. [Embodiment] As described above, a disadvantage of the prior art is that when a transistor pair is not turned on, its output voltage must be boosted by the PM 〇s of the transistor pair to VDDH, and the PMOS is designed. Weaker (that is, the aspect ratio is small and the current flow capacity is weak); and when 1^]^1〇8 is turned on, the voltage of the control node of the PM0S (ie, the gate of the PM0S) must be The other weaker POM in the other transistor pair raises the voltage of the control node before the PM0S is turned off. This phenomenon causes the output voltage Vout to be converted from VDDH to 0V from 0V to VDDH. This conversion time is asymmetrical and causes voltage signal distortion, and will cause power loss. The present invention provides a voltage adjustment circuit and a control method thereof, which can electrically control the control node t when the input voltage Vin changes, so that the change of the output voltage ν(10) is more like the rise time and the fall time, and the distortion and the work are significantly reduced. First, refer to the 3®, and the 3rd figure is the circuit diagram of the 3G2 circuit of the power supply unit. In this embodiment, the lifting unit is a 金-type MOS half that is connected to the high voltage _VDDH. Transistor (pM〇s) Training, 200830082, but can also be implemented with other different circuits, the drain of PMOS 310 can be coupled to the interleaved shackle circuits 100, 200 mentioned in the prior art. The control node, when the PMOS 310 is turned on, can raise the voltage of the control node to VDDH, accelerate the voltage of the control node to reach a predetermined voltage value, and when the PMOS 310 is not turned on, it can be regarded as an interleaved coupled shackle circuit. , 2 breaks between the roads. Whether the PMOS 310 is turned on or not is controlled by the control circuit 312. The control circuit 302 includes a PMOS 320, two NMOSs 330 and 340, a delay unit 350, and an inverter 360. The PMOS 320 is coupled to the high voltage source VDDH. Since its gate is grounded, the PMOS 320 can be regarded as a resistor; an NMOS 330 and an NMOS 340 connected in series to each other and coupled between the PMOS 320 and the ground, respectively, function like a NAND gate. When the voltage of the gate of the two NMOSs (ie, the two input terminals of the NAND gate) is the voltage level "1" (that is, the voltage VDD), the NMOS 330 and the NMOS 340 are turned on, so that the voltage of the coupling junction of the NMOS 330 and the PMOS 320 is 0. The voltage of the coupling contact P is the gate voltage of the PMOS 310, thus turning on the PMOS 310. The input voltage Vin is delayed by the delay unit 350 for a predetermined time and then input to the gate of the NMOS 330, and the input voltage Vin is also inverted by the inverter 360 and then input to the gate of the NMOS 340 as shown in FIG. 4, when the input voltage vin is from the voltage When the bit 'Τ' is changed to the voltage level, 〇, ,, the gate voltages of the NMOS 330 and the NMOS 340 are both VDD, and the gate voltage of the PMOS 310 is a pulse, and the pulse width thereof can be delayed by the delay unit 35. To control, during this pulse width time, the PMOS 310 is turned on, and the voltage of the control node in the interleaved coupled shackle circuits 1 〇〇, 200 is raised to VDDH, and the voltage of the acceleration control node reaches a predetermined voltage value, thereby knowing that when When the input voltage Vin is not changed, the voltage of the Moma junction P is VDDH, and the PMOS 310 is not turned on. 200830082 Referring to FIG. 5, FIG. 5 is a circuit diagram of the voltage adjustment circuit 5 of the first embodiment of the present invention. The voltage adjustment circuit includes a staggered light-weight pickup circuit 510, two voltage boosting units 501 and 5〇3, Two control circuits 5〇2 and 5〇4 and a reverse=chain 540. The structure and operation principle of the interleaved shackle circuit 51A are the same as those of the interleaved shackle circuit 100 described above, and the structure and operation principle of the voltage boosting units 5〇1 and 5〇^ are the same as those of the voltage boosting unit 301 described above. The structure and operation principle of the control circuits 502 and 504 are the same as those of the aforementioned control circuit 3〇2, and the inverter chain 540 functions as a reverse function and a delay function. The operation principle is as follows. When the input voltage Vin is the voltage level "1" (ie VDD), the voltages of the nodes b and d are all VDD, and the voltages of the nodes a and c are 〇, so the voltages of the nodes e and f are vddh, and the voltage boosting units 501 and 503 Nb is not turned on, the voltage of node b is VDD, so that NMOS 513 is turned on, the voltage of control node g is 〇, so that PM〇S512 is turned on, and because the voltage of node c is 0, NMOS514 is not turned on, so the output voltage v〇ut is VDDH ' PMOS511 is not conducting. . When the input voltage vin is changed from the voltage level to the voltage level (ie, voltage 〇), the voltage of node a changes from 〇 to VDD, but the point d has not changed at this time (because node a to node d are separated) The three inverters, thus causing a delay time), the voltage value is still VDD, so the node e voltage is quickly pulled to 0 and the voltage boosting unit 501 is turned on, so the voltage of the node g is precharged by the high power supply VDDH, which is The charging time can be adjusted by the number of inverters in the inverter chain 54〇. After the voltage of the node b becomes 0, the NMOS 513 is not turned on, and the voltage value of the control node g is rapidly boosted to VDDH by precharging, so that the PMOS 512 is not turned on. When the node 〇 voltage becomes 1, the NMOS 514 is turned on, the output voltage Vout is 〇, the PMOS 511 is turned on, and finally the node d voltage is changed to 〇, the node e voltage is restored to VDdh, the precharge process is ended, and the entire voltage adjustment circuit 500 resumes the steady state operation. On the other hand, when the input 200830082 packet voltage \^1 is changed from the voltage level "〇" to the voltage level 丨, (ie, the voltage VDD), the point c has not changed at this time (because the input voltage terminal to the node c) Three opposite states Therefore, causing a delay time), the voltage value is still VDD, so the node [voltage, the speed is pulled to 0 to the voltage boosting unit 5〇3 is turned on, so the output voltage v- is precharged by the power supply VDDH, and its precharge time can be By adjusting the number of inverters of the inverter chain 54〇, the output voltage Vout can be quickly boosted to VDDH by precharging, and when the voltage of the node c becomes 〇, the NMOS 514 is not turned on, and the output voltage v〇ut is fixed to VDDH. The node f voltage is restored to VDDH, the precharge process ends, and the entire voltage adjustment circuit 500 resumes steady state operation. Please refer to FIG. 6. FIG. 6 is a circuit diagram of a second embodiment of the voltage adjusting circuit 6 of the present invention, which is different from the voltage adjusting circuit 500 of FIG. 5 in that the interleaved switching in the voltage adjusting circuit 500 is performed. The lock circuit 51 is replaced by a structure similar to the aforementioned interleaved shackle circuit 200. When the input voltage Vin is a voltage level, τ, (ie, VDD), the voltage of the node b is VDD, and NM 〇 S 613 is not turned on, the node c When the voltage is 0, NMOS 614 is turned on, causing PMOS 612 to be turned on, and the output voltage v 〇 m is VDDH. When the input voltage Vin is changed from the voltage level "丨" to the voltage level, 〇, (ie, voltage 0), the control circuit 602 causes the voltage boosting unit 6〇1 to precharge the voltage value of the control node g to VDDH. PMOS612 is not turned on. At this time, since the voltage of the node 变为 becomes 0 ' NMOS 613 is turned on, the output voltage is pulled to 〇. When the input voltage Vin is changed from the voltage level, 〇, to the voltage level "r, (mVDD" When the NMOS 613 is not turned on and the NMOS 614 is turned on, the control circuit 6〇4 causes the voltage boost unit 603 to precharge the output voltage v〇ut to VDDH. Please refer to FIG. 7. FIG. 7 is a circuit diagram of a third embodiment of the voltage adjustment circuit of the present invention, wherein the interleaved coupling type shackle circuit is a hybrid use of the aforementioned interleaved coupling type 200811 200830082 lock circuit 100 and 200, and its function Compared with the principle of operation and the interlocking shank, the roads 100 and 200 are identical. Therefore, the electric turning circuit 7 is similar to the first one: the second real paying function and operating principle are similar, and the skilled artisan can easily infer In this case, I will not repeat them here. Please refer to FIG. 8 , which is the electrical switch of the electric lifting unit and the control circuit 80 ^ of the present invention. The voltage boosting unit Xie and (4)·8() 2 and the surface voltage boosting unit 7L3G1 and the control circuit 302 are The components used are very similar to those on the circuit. The only difference is that the gate of the NMOS 830 is coupled to the output voltage ν_ instead of being coupled to a delayed input voltage like the control circuit 302 of FIG. 3, but due to the output surface Vin and the output voltage. There is a time delay between Vouts, so that similar effects to the control circuit 302 can be achieved. Referring to FIG. 9A, FIG. 9 is a circuit diagram of a fourth embodiment of the voltage adjustment circuit 9 of the present invention. The voltage touch circuit includes a staggered latching circuit 910 and two voltage boosting units 9〇1 and 9〇. 3. Two control circuits 9〇2 and 9_ and a reverse=acter chain. The structure and operation principle of the interlaced light-weight pick-up f-way 910 is the same as that of the interleaved pick-up circuit 100, and the structure and operation principle of the electric-powered unit is the same as that of the front voltage boosting unit. The structure and operation principle of the control circuits 902 and 904 are the same as those of the aforementioned control circuit 8〇2, and the inverter chain 940 is used as a reverse function. When the input voltage Vm is the voltage level, 'Γ (ie VDD), the voltage of the node b is vdd, and the voltage of the node & c is 0 'so the voltage of the node e, f is VDDH, and the voltage boosting units 9(1) and 903 are not Turn on, the voltage of node b is VDD, so that the employee 8913 is turned on, the voltage of the control point g is 〇, so that the PMOS 912 is turned on, and because the voltage of the node c is 〇, the NMOS 914 is not 'passed, so the output voltage v〇i^vddh, pm〇S911 Do not guide 12 200830082 pass. When the input voltage Vin changes from the voltage level "1" to the voltage level, 〇,, (ie, voltage 〇), the voltage of node a changes from 0 to VDD, but the output voltage VouU (; 4 has not changed, the voltage value Still VDDH, so the node e voltage is quickly pulled to the voltage boosting unit 901 to be turned on, so the voltage of the node g is precharged by the high power supply VDDH, the voltage of the node b becomes 0, and the NMOS 913 is not turned on, and the control node g is controlled. The voltage value can be quickly boosted to VDDH by pre-charging, so that the PMOS 912 is not turned on. When the node £ voltage becomes 1, the NMOS 914 is turned on, and the output voltage v〇ut becomes 〇, the PMOS 911 is turned on, and the voltage of the node e is also restored to svDDH. When the precharge process ends, the entire voltage adjustment circuit 900 resumes the steady state operation. When the input voltage 改变 is changed from the voltage level "0" to the voltage level "1" (ie, the voltage VDD), the voltage value of the control node g is The fashion has not changed, the voltage value is still VDDH, so the node "voltage is quickly pulled to the voltage boosting unit 903 is turned on, so the output voltage v〇ut is precharged by the high power supply VDDH, when the node c voltage becomes (^NM〇 S914 does not conduct, output power The voltage Vout is fixed to VDDH, the node f voltage is restored to VDDH, the precharge process is completed, and the entire voltage adjustment circuit 9 is restored to the steady state operation. Referring to FIG. 10, FIG. 10 is a fifth embodiment of the voltage adjustment circuit of the present invention. The circuit diagram is different from the voltage adjustment circuit 9A of FIG. 9 in that the interleaved shackle circuit 91〇 in the voltage adjustment circuit 900 is replaced by a structure similar to the aforementioned parent-missing coupling type latch circuit 2〇〇. When the input voltage ▽匕 is the voltage level “1” (ie VDD), the voltage of the node b is VDD, NM〇sl〇13f is turned on, the voltage of the node c is 〇, and the NMOS 1014 is turned on, causing the PMOS 1012 to be turned on, and the output voltage Vout is VDDH. When the input voltage yin is changed from the electric dust level "1" to the voltage level "0" (ie, voltage 〇), the control circuit 1 使得 2 causes the voltage boosting unit 1 〇〇 1 to pre-control the voltage value of the node g When charging to VDDH, PM〇S1〇12 is not turned on. At this time, 13 200830082, because the voltage of the point b becomes 0, the NMOS1013 is turned on, so the output voltage is pulled to 〇. When the input voltage Vin is changed from the voltage level “〇” to Voltage level, ι,, ( VDD) 'NMOS1013 is not turned on and NMOS1014 is turned on, and the control circuit 1〇〇4 causes the voltage boosting unit 1003 to precharge the output voltage Vout to VDDH. The eleventh figure is the sixth implementation of the voltage adjusting circuit H00 of the present invention. The circuit diagram of the example, wherein the interleaved coupling type shackle circuit is used in combination with the aforementioned interleaved pickup type latch circuits 100 and 200, and its function and operation principle are completely the same as those of the interleaved surface-type shackle circuits 100 and 200, and thus the voltage adjustment circuit 11 is similar to the functions and operating principles of the fourth and fifth embodiments described above, and can be easily inferred by those skilled in the art and will not be described herein. Please note that although the two sets of voltage boosting units and two sets of control circuits are used in the first embodiment to the sixth embodiment, only one set of voltage boosting units and control (four) paths are used for practical applications, that is, visually needed Optionally, only one of the voltages at the control node or the output is precharged. The present invention has been disclosed in the above preferred embodiments. However, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements within the spirit and scope of the present invention. The scope of protection shall be subject to the definition of the scope of patent application attached to the Vision. BRIEF DESCRIPTION OF THE DRAWINGS The figure shows a circuit diagram of a conventional technique for interleaved switching pickup circuits. Fig. 2 is a circuit diagram of another type of interlocking circuit. Fig. 3 is a circuit diagram of the power-up unit and the control circuit of the present invention. _ is a waveform diagram of the input voltage Vin, the delayed input voltage, and the reverse input voltage of 14 200830082 and the contact p voltage in FIG. Fig. 5 is a circuit diagram showing a first embodiment of the voltage adjusting circuit of the present invention. Fig. 6 is a circuit diagram showing a second embodiment of the voltage adjusting circuit of the present invention. Fig. 7 is a circuit diagram showing a third embodiment of the voltage adjusting circuit of the present invention. Figure 8 is a circuit diagram of a unit and a control circuit for voltage boosting of the present invention. Figure 9 is a circuit diagram of a fourth embodiment of the voltage adjustment circuit of the present invention. Figure 10 is a circuit diagram of a fifth embodiment of the voltage adjusting circuit of the present invention. Figure 11 is a circuit diagram of a sixth embodiment of the voltage adjusting circuit of the present invention. [Main component symbol description] 100'200, 510, 910 interleaved coupling shackle circuit 101 ^ 102 transistor pair 103, 104 nodes
110、120、310、320、5H、512、6n、612、911、912、1011、 1012 PMOS 130、140、330、340、513、514、613、614、830、913、914、 1013、1014 NMOS 150、360 反向器 3(U、5(H、503、6(H、603、801、901、903、10(H、1003 電 壓提升單元 302、502、504、602、604、802、902、904、1002、1004 控 制電路 350 延遲單元 500、600、700、900、1000、1100 電壓調整電路 15 200830082 540、940 反向器鏈 十、申請專利範圍： 1· 一種電壓調整電路（level shifter)，用來將一輸入電壓轉換至 具有較高電壓值之一輸出電壓，其包含有： 一交錯|馬合式栓鎖電路（cross-coupled latch)，其具有〆第 一、第二電晶體對，用來接收該輸入電壓且每一電晶體對之 一輸出端皆互相耦合至另一電晶體對之一控制節點； 一第一電壓提升單元，耦合至一電源與該第一電晶體對之 該控制節點，用來提升該控制節點之電壓；以及 一第一控制電路，耦合至該第一電壓提升單元與該輸入電 壓，可偵測該輸入電壓之變化以提供一脈衝（pulse)，該脈 衝可控制該第一電壓提升單元以決定該電源對該第一電晶體 對之該控制節點之充電時間。 2·如申請專利範圍第1項所述之電壓調整電路，豆 式拴鎖電路之第-與第二電晶體對互相對稱連接，'皆:為至 少一P型金氧半電晶體（PM0S)與一N型金氧半電晶體# (NM0S)串聯而成，其串聯節點即為該輸出端，該:型金 半電晶體之閘極（gate)即為該控制節％ 合至顧型金氧半電·之_。]卩上雜人電壓係柄 3·如申請專利範圍第1項所述之電壓調整電 ^ ^ 丨人β · 电路其中邊苐一電壓 k升早兀係為-Ρ型金氧半電晶體，其源級（s_e)搞合至 16110, 120, 310, 320, 5H, 512, 6n, 612, 911, 912, 1011, 1012 PMOS 130, 140, 330, 340, 513, 514, 613, 614, 830, 913, 914, 1013, 1014 NMOS 150, 360 reverser 3 (U, 5 (H, 503, 6 (H, 603, 801, 901, 903, 10 (H, 1003 voltage boosting unit 302, 502, 504, 602, 604, 802, 902, 904, 1002, 1004 control circuit 350 delay unit 500, 600, 700, 900, 1000, 1100 voltage adjustment circuit 15 200830082 540, 940 reverser chain ten, the scope of patent application: 1 · a voltage shifter (level shifter), An output voltage for converting an input voltage to a higher voltage value, comprising: a cross-coupled latch having a first and second transistor pairs, Receiving the input voltage and one output of each transistor pair is coupled to one of the other transistor pairs; a first voltage boosting unit coupled to a power source and the first transistor pair a node for boosting the voltage of the control node; and a first control circuit coupled Up to the first voltage boosting unit and the input voltage, detecting a change in the input voltage to provide a pulse, the pulse controlling the first voltage boosting unit to determine the power source to the first transistor pair The charging time of the control node. 2. The voltage adjusting circuit according to the first aspect of the patent application, the first-and second-electrode pairs of the bean-type shackle circuit are symmetrically connected to each other, 'all: at least one P-type gold The oxygen semi-transistor (PM0S) is formed in series with an N-type gold-oxygen semi-transistor # (NM0S), and the series node is the output terminal, and the gate of the gold-type semi-transistor is the control. Section % is combined with the type of gold oxide and semi-electricity. _] The voltage of the hybrid system is 3. The voltage adjustment electric power as described in the first paragraph of the patent application ^ ^ β人β · The circuit of which is a voltage k The early 兀 is a Ρ-type MOS transistor, and its source level (s_e) is integrated to 16