TW200820426A - Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states - Google Patents

Abstract

A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic ''00'' state, a logic ''01'' state, a logic ''10'' state and a logic ''11'' state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic ''0'' is represented by a mathematical expression (1+f)R. The logic ''1'' state is represented by a mathematical expression (n+f)R. The logic ''2'' state is represented by a mathematical expression (1+nf)R. The logic ''3'' state is represented by a mathematical expression n(1+f)R.

Description

200820426

The invention relates to a high-density memory device based on a programmable resistive memory material, comprising a metal oxide substrate and other materials, wherein the invention relates to a high-density memory device based on a programmable resistive memory material. And the method of manufacturing the device. [Prior Art] A read/write optical disc is widely used as a memory material in which phase change is dominant. The ginseng material contains at least two solid phases, for example, a general amorphous solid phase and a generally crystalline stationary phase. The laser pulse enables the reading/writing of the optical disc to be phase-switched and the material of the optical characteristic read after the phase change. Phase change basic memory materials, such as chalcogenide base materials and similar materials, can be phase changed by applying a suitable current level to the integrated circuit. Generally, the amorphous state has a higher resistance coefficient than the general crystalline stationary phase, and can immediately sense and indicate the data. Because of these characteristics, φ creates the interest of using a programmable resistor material to form a non-volatile circuit that can be read and written with random access. The amorphous state is generally changed to a crystalline state by a low current operation. Changing from crystalline to amorphous, referred to herein as reset, is typically operated at a high current that includes an instantaneous high-density current pulse to melt or break the crystalline structure, while The phase change material can be rapidly cooled by a cooling phase change procedure and at least a portion of the phase change structure is stabilized in an amorphous state. It is desirable to minimize the reset current intensity that causes the phase change material to change from a crystalline state to an amorphous state. Reduce the reset power required for the reset action 200820426

蔑— TW2958PA / Flow intensity can be achieved by reducing the size of the phase change material and the electrode and the contact area between the phase change material and the electrode. The phase change material achieves a higher current density with a small absolute current value. . One direction of development is to create small holes in the integrated circuit and to fill the small holes with a small amount of programmable resistive material. The patents that point to the development of small holes include: U.S. Patent No. 5, 687, 112 published by 〇vshinsky on U.S., 1997. Multi-bit single memory cell memory element with sharp contact points (MuiHbit) Single Cell Memory 10 Element Having Tapered Contact); Method of Making Chalogenide [sic] in U.S. Patent No. 5, 789, 277, issued on August 4, 1998, by Zahorik et al. A memory-controlled two-way phase-change semi-conducting memory device and method of manufacture (Control 1 able Ovonic Phase-Change Semiconductor Memory Device, US Patent No. 6,150,253, issued November 21, 2000). And Methods of Fabricating the Same)”. The problems caused by the manufacture of such devices, such as the need for very small sizes of devices, and the need to adapt to the rigorous specifications of large-sized devices, require changes to the process. , each memory layer that needs phase change memory stores multiple bits ^ [Summary] A bistable random access memory Contains a plurality of programmable resistive random access memory cells, where each programmable resistive random access

PW2958PA 200820426 Memory cells have multiple layers of memory layers. Each memory layer stack includes a conductive layer overlying a programmable resistive random access memory layer. According to a first aspect of the invention, a first memory layer stack covers a second memory layer stack, and a second memory layer stack covers a third memory layer stack. The first memory layer stack includes a first conductive layer overlying a first programmable resistive memory layer. The second memory layer stack includes a second conductive layer overlying the second programmable resistive random access memory layer. The third memory layer stack includes a third conductive layer overlying a third programmable resistive random memory layer. The 10th programmable resistive random access memory layer has a memory area and is larger than a memory area of the second programmable random access memory layer. The second programmable random access memory layer has a memory area and is larger than the memory area of the first programmable random access memory layer. Each programmable resistive random access memory layer has a multi-level memory state, for example, the first bit is used to store the first state and the second bit to store the second state. The first memory stack is connected in series with the second memory stack, and the second memory stack is in series with the third memory stack. The memory cell has three memory stacks and provides eight logic states (2k), where k represents the number of memory layers or memory stacks. For example, the number of billions of stacks can be reduced to two memory stacks per cell, or to four memory stacks per cell, looking at the memory design. Suitable materials for the first programmable resistive device, the second programmable resistive random memory layer or the third programmable resistive random memory layer may include, but are not limited to, metal oxides and giant magnetoresistance materials. (Colossal magnetoresistance, CMR), ternary oxide (three-element

rW2958PA 200820426

Oxide), phase change materials and polymer materials. The resistive random access memory (RRAM) may be the same or different material used for the first programmable resistive random access memory layer and the first programmable resistive random access memory layer. The resistive random access memory (RRAM) is used for the third programmable resistive random access memory layer and the material of the first programmable resistive random access memory layer may be the same or different. Resistive random access memory (RRAM) is in the third programmable resistive random access memory layer and the second programmable resistive random access memory

The materials of the layer may be the same or different. The thickness between the first, second, and third programmable resistive random access memories is, for example, about 丨 nanometers (nm) to 200 nanometers (nm). 〇 Broadly speaking, the memory device includes a first a conductive member covers a first programmable resistive random access memory device, and the first programmable resistor access memory member has an area representing a first resistance value, the first electrical component and the first programmable resistor The random access memory has a side; and the second conductive member covers the second programmable resistor & random, memory, member, and the first programmable resistance random access memory component The component 'the first programmable resistive random access memory component is connected in series with the second resistive random access memory component, and the second programmable resistive random access memory has a second electrical The area of the value 'and the area of the second programmable random access memory component is greater than the area of the first programmable random access memory component. A method of fabricating a bistable resistive random access memory and having multiple memory layer stacks is described herein. - a first-memory layer stack comprising Ί - a conductive layer overlying - a first programmable resistive random access memory

200820426TW2958PA ▲ The material and the second memory layer stack comprise a second conductive layer covering a m second programmable resistive random access memory layer, and the first memory layer stack is stacked on a second memory layer stack. . A mask is disposed on a portion of the first conductive layer in a dry or wet etch chemistry. The first conductive layer and the left side and the right side of the first programmable resistive random access memory layer are etched to the top surface of the second conductive layer, thereby generating a first conductive member and a first programmable resistive memory Take the memory component. A dielectric sidewall is disposed on the left and right sides of the first conductive member and the first programmable resistive random access memory device. The thickness of the dielectric sidewalls affects the area dimensions of both the second conductive member and the second programmable resistive random access memory device. For example, if the critical dimension (CD) of the mask is assumed to be about 0.15 micrometers (/zm), and the thickness of the dielectric sidewalls is about 31 nanometers (nm), that is, The area of the two programmable resistive random access memory components is approximately twice the area of the first programmable resistive random access memory component. This area is inversely proportional to the resistance value and is expressed in a mathematical relationship of ΟΛ4), where J represents the length of the programmable resistive random access memory component and 4 represents the programmable resistive random access memory component. area. In this example, the resistance of the second programmable resistive random access memory component is approximately one-half the resistance of the first programmable resistive random access memory component. The ideal resistance difference between the first and second programmable resistors . . . , the random access memory components is determined by the SET/RESET resistance window of the programmable resistive random access memory component. (resistance window) (which is defined by the resistance ratio of one state to another state 200820426). The left and right sides of the second conductive layer and the second programmable resistive random access memory m' layer are etched to form a second conductive member and a second programmable resistive random access memory device. The left and right sides of the second conductive layer and the second programmable resistive random access memory layer are etched to the next layer or through the next layer. A via plug is placed below the next layer. According to a second aspect of the present invention, a resistive random access memory for operating a stack of two memory layers arranged in series is disclosed. The first memory 10 stack includes a first conductive layer overlying a first programmable resistive random access memory layer, and the second memory layer stack includes a second conductive layer overlying the second programmable resistive random Access to the memory layer. A first bit line voltage Vw is coupled to the top surface of the first conductive layer and a second bit line voltage Vb2 is coupled to the bottom surface of the second programmable resistive random access memory. A programmable resistive random access voltage VmM has a first end coupled to the first conductive member and a second end coupled to the first programmable resistive random access memory layer member. The second programmable resistance random access voltage VmAM is generally connected to the first programmable resistive random access memory device by a first end and the second and second programmable resistive random access memory Connect the pieces. There are two important variables that affect how a bistable programmable resistive random access memory changes from one logic state to another. The first variable is represented by the symbol/2 to indicate the selected memory material characteristics. The second variable is represented by the symbol / to indicate the thickness (or width) of the dielectric sidewall. This variable f can be selected or adjusted to change with the resistance

200820426TW2958PA m • There is a large enough operation window to perform a multi-bit resistive random access memory (RRAM). In a bistable random access memory, each memory cell has a rain memory layer stack, and the bistable resistive random access memory operates in four logic states, and the logic state is "〇〇" (or logic state) "〇"), logic state "01" (or logic state "1"), logic state "ίο" (or logic state "2"), and logic state "n" (or logic state "3"). The relationship between these four different logic states can be mathematically represented by two variables /3, / and _ resistance value i?. The logic state, 〇" is expressed in mathematical form. Logic state" Γ is expressed in mathematical form. The logical state '' 2 ' is expressed in a mathematical expression. The logical state, 3' is represented by a mathematical expression. An advantage of the present invention is to increase the overall childhood of a bistable resistive random access memory by using multiple memory layers for each memory cell. The present invention also provides a three-dimensional bistable random access memory design and manufacturing scheme. The present invention is more capable of reducing the resistance change of the bistable electric P-type random access memory. The structures and methods of the present invention are disclosed in detail later. The summary herein is not intended to define the invention. The invention is defined by the patent application range i. To make the embodiments, features, aspects and advantages of these and other techniques more apparent, the following description of the preferred embodiment and the accompanying drawings are set forth in detail below:

rW2958PA 200820426 [Embodiment] For describing the structural embodiments and methods of the present invention, please refer to the provided i-th to 17th. It is to be understood that the specific embodiments of the present invention are not to be construed as limited. The same elements are shared by the same reference numerals in the different embodiments. Figure 1 is a schematic diagram showing a memory array 1 实施 implemented in the manner described herein. In the first! As shown in Fig., a common source line (c〇m(4)^ source line) 128, a word line 123, and a word line 12 4 are generally arranged in parallel in the Y-axis direction. One bit line 141 and 142-f are arranged in parallel in the X-axis direction. Thus, a gamma-decoder and a word line driver 145 are coupled to word lines 123 and 124. An X-decoder and a set of sense amplifiers 146 are coupled to bit lines 141 and 142. The common source line 128 is coupled to the source terminals of the access transistors 15A, 151, 152, and 153. A gate of the access transistor 150 is coupled to the word line 123. The gate of the access transistor 151 is coupled to the word line 124. The gate of the access transistor 152 is coupled to the word line 123. The gate of the access transistor 153 is coupled to the word line 124. The drain of the access transistor 150 is turned by the sidewaU pin memory cell 135 and the lower electrode member 132, and the sidewall pin 135 has the upper electrode member 134 and the lower electrode member 132. This upper electrode member 134 is coupled to the split line 141. The common source line 128 can be viewed as being shared by two columns of memory elements, and the column referred to herein refers to the unintended Y direction. In other embodiments, the access transistor may be replaced by a diode, or other means for selecting a device to control current flow may be

TW2958PA 200820426 Array used to read and write data. Fig. 2 is a block diagram showing an integrated circuit 2 of a resistive random access memory structure in accordance with a preferred embodiment of the present invention. The integrated package 275 includes a memory array that uses a side active pin bistable resistive Ik to access the memory cells to one half of the conductive substrate. A column of decoders 26^ is coupled to the plurality of sub-element lines 262 and arranged along the columns of the memory array 260. The pin decoder 263 is coupled to the plurality of bit lines 264 and extends over the pin arrangement of the memory array 260 for reading and programming the side pin memory element data in the memory array. The address provided by a bus 265 is provided to the pin decoder 263 and the column decoder 261. The sense amplifier and data input structure 266 is coupled to the pin hopper 263 via a data sink 267. The data is supplied from the input/output port located at the integrated circuit 275 or from another data source located inside or outside the integrated circuit 275 via the data-in line 271 to the sense amplifier and data input structure. 266 data input structure. In the description of this embodiment, other circuit diagrams are also included in the integrated circuit, such as a general purpose processor (genera) or a special purpose application circuitry, or by a thin film bistable resistor. A random access memory cell array provides a modular system-on-a chip module combination. The data is provided by a data-out line 272, from the sense amplifiers located in the sense amplifier and data input structure 266 to the input/output interface on the integrated circuit 275, or to other internal data destination units or external products. The body circuit 275 〇 200820426 祖 此 in this example the controller uses a bias arrangement state machine 269 to control the bis arrangement supply voltage 268, such as reading, stylizing, erasing, wiping In addition to verification and program verification voltage. This controller can be implemented using conventional special purpose logic circuits. In an alternate embodiment, the controller includes a multi-purpose multi-processor that can execute the same integrated circuit and can also execute a computer program to control the operation of the device. In another embodiment, a combination of special purpose logic circuits and multiple processors for multiple uses is also available for controller implementation. Figure 3 is a simplified schematic diagram showing the steps of the deposition and lithography techniques for fabricating two programmable resistive random access memory layers of a bistable resistive random access memory layer in accordance with the present invention. The bistable resistive random access memory 300 includes a first programmable resistive random access memory layer 31 and a second programmable resistive random access memory layer 320. Each of the first programmable resistive random access memory layer 310 and the second programmable resistive random access memory layer 320 provides a capacity to store two sets of information states. The first and second programmable resistive random access memory layers 310, 320 provide a total of four sets of logic states in the bistable resistive random access memory 300: the first logic replies "00" (or "〇") The second logic state "01 j (or "1"), the third logic state "1" (or "2"), and the fourth logic state "11" (or "3"), . · · * . In an embodiment, the first programmable resistive random access memory layer 310 and the second programmable resistive random access memory layer 320 are the same material. In another embodiment, the first programmable resistive random access memory 15

rW2958PA 200820426 Second: the program resistive random access memory layer 32 is transmitted as a different material = the brother-programmable resistive random access memory layer _ = a β-type resistive random access memory layer 310戋:= (Electricity, access record (4) k 1 not (nm) to 200 nm (nm). Each of the programmable resistive memory layers 310, 320 formed by the same material

There are at least two steady state resistance levels, meaning resistive random access memory materials. In subsequent follow-up __material-regulated random access memory is beneficial. The term "bistable resistive random access memory" means the control of a resistance level and has the following meanings: voltage amplitude, current amplitude or polarity. The state of the phase change memory is by voltage amplitude, Current amplitude or pulse time is controlled. The polarity of the bistable resistive random access memory does not affect the stylization of the bistable resistive random access memory. The short summary describes four types of resistive memory materials suitable for resistive random access memory. The first memory material suitable for use in the examples is a giant magnetoresistance (CMR) material such as barium-calcium-manganese oxide. (PrxCayMn〇3) wherein x:y=〇·5:0· 5 or x:〇~1; y ··〇~1 to form CMR' wherein oxidized (optional xide) can be selectively used. A method of forming a CMR material is, for example, using a physical vapor deposition (PVD) sputtering or a magnetro-sputtering method, and using argon (Ar), nitrogen 16

200820426一A

A TW2958PA (N2), oxygen (〇2), and either helium (1^) are used as source gases, and the enthalpy is between 1 and 100 millitorres (mTorr). The deposition temperature ranges from room temperature to 600 ° C depending on the conditions of the subsequent deposition process. A collimator with an aspect ratio of 1 to 5 can be used to improve fill-in performance. In order to improve the filling performance, the DC bias voltage can be used from tens of times the voltage to hundreds of times. On the other hand, it can be used in combination with a DC bias and a collimator. A magnetic field from tens of times Gauss to a Tesla (10, OOOGauss) can also be applied to • Improve the magnetic crystalline phase. A post-deposition annealing treatment can be selected for use in a vacuum or in a nitrogen or nitrogen/oxygen mixed environment to improve the crystalline state of the CMR material. The annealing temperature is between 400 ° C and 600 ° C and the annealing time is at least 2 hours. The thickness of the CMR material depends on the design of the memory cell structure. For example, a CMR having a thickness of 10 to 200 nanometers (nm) can be used as a core material. A buffer layer of Lu-Cu oxide (YBaCu〇3 is a high temperature superconductor material) is also commonly used to improve the crystallization state of CMR materials. The second YBC0 system is deposited in front of the CMR material, and the thickness of YBC0 ranges from 3〇2 to 2 nanometers (nm). The first type of compound is a compound of two elements, such as nickel oxide (ΝιΑ). Titanium oxide (Tix〇y), aluminum telluride to do octa tungsten oxide (10) y), zinc oxide (Znx0y) '# oxide (Zrx〇y), copper oxide (CuA), etc. 'where x: y=〇. 5:0. 5 or X:(M ; y:(M ... formation method is, for example, using PVD 贱 clock or magnetron splatter method and reactive gas 17

TW2958PA 200820426 Gas (Ar), nitrogen nitrogen (N2), oxygen (〇2) and or helium (He), etc., pressure between 1~100 mTorr (mT〇rr), using oxidized metal as dry material , such as nickel oxide (Nix〇y), titanium oxide (Tix〇y), aluminum oxide (Aix〇y), tungsten oxide (Wx〇y), zinc oxide (Znx〇y), tantalum oxide (zrx〇y), copper oxide (Cux〇y), and the like. The deposition is usually formed at room temperature. A collimator having a longitudinal rod ratio of 1 to 5 can be used to improve the filling performance. In order to improve the filling performance, the DC bias voltage can be used from tens to hundreds of times. The DC bias can also be used simultaneously with the collimator if required. A post-deposition annealing treatment can be selected to be used in a vacuum or in a nitrogen or nitrogen/oxygen mixed environment to improve the oxygen distribution of the metal oxide. The annealing temperature is between 400 ° C and 600 ° C and the annealing time is less than 2 hours. An alternative formation method can use PVD sputtering or magnetron sputtering methods with reactive gases argon/oxygen (Ar/〇2), argon/nitrogen/oxygen (Αγ/Ν2/〇2), pure oxygen (〇2) a gas such as helium/oxygen (He/〇2), helium/nitrogen/oxygen (He/N2/〇2), having a pressure of 1 to 100 milliTorr (mTorr), using a metal tantalum such as nickel (Ni), Titanium (Ti), Ming (A1), tungsten (W), zinc (Zn), zirconium (Zr), copper (Cu), and the like. Its deposition is usually performed at room temperature. A collimator with aspect ratio 5 can be used to improve fill performance. In order to improve the filling performance, a DC bias voltage of tens to hundreds of times can be used. The DC bias can also be used simultaneously with the collimator if required. ^ A post-deposition annealing treatment can be used to improve the oxygen distribution of the metal oxide in a vacuum or in a nitrogen or nitrogen/oxygen mixed environment. Its annealing temperature is at 4 〇〇. 〇 to 600 ° C, the annealing time is less than 2 small

TW2958PA 200820426 Time 0 Another method of formation is oxidation by a high temperature oxidation system, such as a furnace or a rapid thermal pulse (RTP) system. The temperature is 200~7〇 (Tc and pure oxygen (〇2) and the nitrogen gas has a pressure of several millitorr (mT〇rr) to 1 atmosphere (atm), and the time ranges from several minutes to several hours. Another oxidation The method is plasma oxidation. The RF or DC source plasma is a mixture of pure oxygen (〇2), argon mixed gas or argon/nitrogen/oxygen (Ar/〇2/〇2) at a pressure of 1 Torr. (mTorr) is used to oxidize a metal surface, and the metal is, for example, nickel (Ni), titanium (Ti), aluminum (A1), tungsten (W), zinc (Zn), lead (Zr), copper (Cu), or the like. The oxidation time ranges from a few seconds to a few minutes. The oxidation temperature ranges from room temperature to 3 〇〇. (: It depends on the degree of plasma oxidation. The two types of materials are a polymeric material such as cyano. For the tetracyquinodimethane (TCNQ) doped copper (Cu), carbon 60 (C6.), silver (Ag), etc. or phenyl C61-butyric acid methyl ester (phenyl C61-butyric acid methyl ester, PCBM)-Cyano-p-dioxane® complex (TCNQ) mixed polymer. It can be formed by thermal evaporation, electron beam evaporation (e-beam evaportation). ) or vapor deposition by a m〇iecuiar beam epitaxy (MBE) system, etc. The solid state TCNQ and the doped granules are co-evaprated in a single tank. , TCNQ and granular doping are placed in a tungsten boat (w-boat) or a group of boats (Ta-boat) or a pottery boat. A high current or electron beam is applied to the melting source material for material mixing and deposition. Non-reactive chemicals on the wafer 19

TW2958PA 200820426 Quality and gas. The deposition is at pressure 1 (Γ4~1 (T1Q Toll (70 ti)). The temperature of the wafer ranges from room temperature to 2 (10). 后. Post-deposition annealing can be used for vacuum or gas (10) In the environment to improve the composition of the polymer (4). The temperature of the fire is 300 ° C, and the annealing time is less than 1 hour. Another technique used to form a polymer-based memory material is a solution doped with TCNQ. Spin coating at a speed of less than 1 rpm. After spin coating, the wafer is placed for a period of time until a solid state is formed (typically at room temperature or below 2 〇 (in rc). The time range is from ^ minutes to several days, depending on the temperature and formation state. The fourth type is a chalcogenide material such as GexSbyTez where x:y:z=2:2:5 or It is composed of χ:〇~5, y:〇~5, ζ:〇~ι〇. GeSbTe can be doped with nitrogen (N-), 矽 (si〇, 锑(Sb-) or selective 杂 other The method for forming a sulfide material can be, for example, a PVD ruthenium plating or a magnetron sputtering method with a source gas of argon (red), nitrogen (NO). / or 氦 (以) and other gases in the appearance of 1 to 100 torr (inTorr). Deposition is usually formed at room temperature. A collimator with an aspect ratio 丨 ~ 5 can be used to improve the filling performance. To fill the performance, the DC bias voltage can be used from tens to hundreds of times. If necessary, the DC bias can also be used simultaneously with the collimator. A post-deposition annealing treatment can be used for vacuum or nitrogen. The environment is used to improve the crystal state of sulfides. The annealing temperature is generally between 1 ° C and 400 ° C, and the annealing time is less than 30 minutes.

TW2958PA 200820426 has a thickness greater than 8 nanometers (nm) and can have a phase change characteristic to allow the material to exhibit two stable resistance states. In the embodiment, the memory cell of the bistable resistive random access memory 300 may include a phase change-based memory material, including a sulfide-based material and other materials, as the first programmable resistance random memory. The memory layer 310 and the second programmable resistive random access memory layer 320 are taken. The chalcogen element contains the sixth group of the periodic table and any of the four elements oxygen (Oxygen), sulfur (Sulfer), selenium (Selenium) and ti (Tellurium). The sulfide contains a chalcogen element compound having a more electropositive element or radical. Chalcogenide alloys contain chalcogenides and other materials such as transition metals. Chalcogenide alloys usually contain one or more elements from the sixth block of the periodic table elements such as germanium and tin. Typically, the chalcogenide alloy comprises a combination comprising one or more of antimony, gallium, indium, and silver. Many phase change basic memory materials have been described in scientific publications, including alloys · gallium / germanium (Ga / Sb), indium / germanium (In / Sb), indium / selenium (In / Se), 锑 /碲(Sb/Te), 锗/碲 (Ge/Te), 锗/锑/hoof (Ge/Sb/Te), indium/锑/碲 (In/Sb/Te), gallium/selenium/碲 (Ga/ Se/Te), tin / 锑 / 碲 (Sn / Sb / Te), indium / 锑 / 碲 (In / SbMe), silver / indium / 锑 / 碲 (Ag / In / Sb / Te), 锗 / tin /锑/碲 (Ge/Sn/Sb/Te), 锗/锑/Selenium/碲丨仏/邰/and/彡 and 碲/锗/锑/Sulphur (Te/Ge/Sb/S). In the family of 锗/锑/碲 (Ge/Sb/Te) alloys, the range of alloys that can be used is large. The composition can be characterized by a hoof-missing compound (TeaGebStMOiMa+lO). A researcher has described the most useful alloy 21 200820426. The average concentration of strontium (Te) in the deposited material is preferably less than 70%, generally less than 60%, and the general range is from 23% to 58% Te, and Preferably it is about 48% to 58% Te. The concentration of germanium (Ge) is greater than about 5% and averages from about 8% to an average of 30% in the material, typically less than 50%. The main constituent element remaining in this compound is bismuth (Sb). These percentages are atomic percentages, and the total amount of constituent element atoms is 100%. (Ovshinsky,, 112patent, cols 10-11·). The special alloys evaluated by another investigator include 碲-锑-gallium compounds (GeaSbzTes, GeSb2Te4 with 10 and GeSbVTe?) (Noboru Yamada," with gallium-germanium-germanium (Ge-Sb-Te) as the south rate data. The possibility of phase change disc", Sp IE ν· 3109 ' ρρ· 28-37 (1997)). More broadly, a transition metal such as chromium (Cr), iron (iron), nickel (nickel, Ni), sharp (niobium, Nb), palladium (Pd), platinum (platinum, Pt) and mixtures thereof or alloys thereof may also be combined with 锗/锑/碲 (Ge/sb/Te) to form a phase change alloy to have programmable resistance characteristics. Winning Ovshinsky 112 patent at columns 11 -13 Special examples of memory materials may also be useful, examples of which are included in the reference material. The phase change alloy can be switched between the first structural state and the second structural state, wherein the first structural state is that the material is located in the general amorphous solid phase and the second structure is in the general crystalline solid phase. It is the local order in the active channel area of the memory run. These alloys are at least bistable. Amorphous refers to a relatively disordered structure that is less ordered than a single crystal and has detectable properties compared to crystalline states such as higher 22 200820426

. —: 〇 〇 - [W2958PA - resistivity. The crystalline state refers to its relatively ordered structure (ordered compared to the amorphous structure), which has a spreadable property such as a lower electrical resistance coefficient than the amorphous phase. In general, the phase change material can be electrically switched to each other in a detectable state between the range of completely amorphous and crystalline states of the local order. Other material properties are also affected by the phase changes in amorphous and crystalline, including atomic order, free electron density, and activation energy. The material can be switched to a different solid phase or two or more solid mixed phases to provide a gray scale between completely amorphous and fully crystalline states. The electronic properties in the material will change accordingly. Phase change alloys can be changed from one phase to another by the application of electronic pulses. It can be observed that a shorter, higher amplitude pulse tends to change the apparent material to a general amorphous state... longer, lower amplitude pulses tend to change the phase change material to the general crystal state. The energy of the short, higher amplitude pulses is high enough to cause the crystal bonds to be broken, and because the pulses are short enough to avoid rearranging the atoms into a crystalline state. It is not necessary to go through an excessive experiment to determine the appropriate pulse waveform for a particular phase change alloy. = The phase change material disclosed in the following sections refers to 锗_锑_碲 (GST), and it can be understood that other phase change materials can also be used. The material described herein that is useful for completing the phase chage random access memory (PCRAM) is the GezSbzTes. Other programmable resistive memory materials can also be used in other embodiments of the invention, including different crystals of yttrium-niobium-tellurium (GST) doped nitrogen (仏), 锗1 (GexSby), or other materials. The change of phase depends on 23

200820426TW2958PA determines its resistance; 镨H巍 oxide (PrxCayMn〇3), 镨-Ming-Chal oxide (PrSrMnO3), yttrium oxide (ZrOx), tungsten oxide (WOx), titanium oxide (Ti〇x), Aluminium oxide (Al〇x) or other materials use electronic pulses to change their resistance state; 7, 7, 8, 8-cyano-p-dimethyl cyanomethane, TCNQ Methanofullerene 6,6-phenyl C61-butyric acid ester, PCBM, TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, CtTCNQ, TCNQ doped with other metals, or any other that can be controlled by electronic pulses and has bistable Or a polymer material in the state of multiple steady state resistance. The first conductive layer 312 is overlying the first programmable resistive random access memory layer 310 and is a conductive element. The second conductive layer 322 is disposed between the first programmable resistive random access memory layer 31 and the second programmable resistive random access memory layer 320. The first conductive layer 312 is a conductive element connected to the first programmable resistive random access memory layer 31. The second conductive layer 322 is a conductive element connected to the second programmable resistive random access memory layer 320. Suitable materials for the first conductive layer 312 and the second conductive layer 322 include: titanium (Ti), nitrogen north titanium (1^1^), gasification/tungsten/titanium nitride (TiN/W/TiN), Titanium nitride/titanium/aluminum/titanium nitride (141^/14/eight-1/141^), 11+ polycrystalline stone eve (11 〇 13^11 [〇: 〇11), nitrous oxide (Tl0N) , group (Ta), nitride button (TaN), nitrogen oxide group (TaON) and other materials. In one embodiment, the first conductive layer 312 and the second conductive layer 322 are the same material. In yet another embodiment, the first conductive layer 312 and the second conductive layer 322 are different materials. The first conductive layer 312 and the second conductive layer 200820426 may have the same or different thicknesses. The thickness of the first conductive layer 312 or the second conductive layer 322 ranges, for example, from about 1 Å to about 2 Å. A mask 330 is formed on the first conductive layer 312. This mask 33 contains a photoresist, a hard mask such as a telluride (salt), a tantalum nitride (Sil), and a tantalum oxynitride (Si0xNy). This mask can be trimmed to a critical dimension (CD) by picking a technique that is suitable for the mask. If the mask 33 is a light group, a reactive ion etching machine mainly composed of chlorine (CL) and hydrogen bromide (HBr) is used to trim the photoresist. If the mask 330 is a hard mask, wet trimming with a suitable solvent can be used to trim the hard mask. In particular, a dilute hydrogen fluoride (dilute HF, DHF) can be used for a hard mask made of oxidized stone (Si〇x). Hot phosphoric acid (ΗΡΑ) is used for hard masks made of nitrogen oxide (SiNx). 4 is a schematic diagram showing a step of fabricating a bistable resistive random access memory 300 according to the present invention, etching to a second conductive layer having a second conductive layer adjacent to the first conductive member 412 and the first A dielectric sidewall is deposited by the resistive random access memory device 410. As shown in FIG. 3, the first conductive layer 312 and the first programmable resistive random access memory layer 310 are etched to the top surface of the second conductive layer 322 to form the first conductive member 412 and the first programmable resistor. Random access memory component 410. The etching process using the first conductive layer 312 and the first programmable resistive random access memory layer 310 may be a single non-isotropic etching, or a two-stage process, first, etching the first etching chemistry first Conductive layer 312; second 'etching first programmable resistive random access 25 with a second etching chemistry

TW2958PA 200820426 ii: The etching chemistry can be selected according to a single-material or a plurality of materials. If the first conductive member 412 uses titanium nitride (TiN) and - electrically shunt random surface memory member 41 (10), Then the two-stage side navigation ^ "the first step of the embossing crane is to complete the chlorine (cl2); and the second step is to vaporize the sulfur (10) to the private resistive random access memory layer 31〇 . The first dielectric sidewall 430 is deposited on the first programmable resistor 410 material and the first conductive structure II, & machine access memory Zhao component „ 43〇:::::« 繁繁...w 7 The surface is suitable for (SN; Ί 430 material comprising yttrium oxide (10) 0 and the thickness of tantalum nitride 30 affects the second conductive member 512 (as shown in Figure 5) with the second programmable resistance random access The memory member 51q (such as the area of the fifth dry. For example: if the mask has a critical dimension of about 0.15 microseconds (four), and the thickness of the dielectric sidewall can be about ^ nanometer (nm)' So that the area of the second programmable resistive random access memory component 510 is approximately the same as the first programmable resistive random access memory component; that is, in the same logic state (such as SET or RESET). The second programmable resistive random access memory device 51 has a resistance of approximately the first programmable resistance random access memory component, and the second +: the first programmable resistive random access memory The resistance difference θ of the component 4in is a private-resistive random access memory component 51() According to the resistance-based random access memory, the SET/R 窗 window of the material assumes that the SET/RESET window is approximately 1G times an order of magnitude ((10) 26 200820426

For the "TW2958PA ribs HMe", the difference between the first programmable resistive random access memory component 410 and the second programmable resistive random access memory component 51 is approximately twice as appropriate. Figure 5 is a block diagram 500 showing the next step of fabricating a bistable resistive random access memory in accordance with the present invention, etched through a second electrical mode to access the memory layer. 322 and the second programmable resistor 2 memory access memory layer 320 (as shown in FIG. 3) is etched to the top surface of the underlying layer by a reactive ion etch or etched through a bottom layer 61 〇 (eg, FIG. 6 The second conductive member 512 and the second programmable resistive random access memory device 510 are formed. The last program can be used to the second conductive layer 322 and the first programmable resistive random access memory layer 320. A single non-isotropic phase bites a two-stage procedure, first, the first etch chemistry etches the second conductive layer 322; second, the second etch etch etches the second programmable resist & machine access memory Layer 320. The etch chemistry can be selected based on the material or material. For example, if The second conductive member 512 uses titanium nitride (TiN) and the second programmable resistive random access memory member 510 uses tungsten germanium (W〇x), and the two-stage etching process uses chlorine (C12) to the second. The conductive layer 512 performs the first etching, and the second programmable resistive random access memory device 510 is etched with the sulfur fluoride (SR). FIG. 6 is a diagram showing the bistable according to the present invention. A simplified schematic diagram of a resistive random access memory of a programmable resistive random access memory. The cell structure 600 illustrates that the bottom layer 610 has been etched through, as described in Figure 5 above. The program resistive random access memory 600 includes a bottom layer 610 disposed on the second programmable resistive random access memory structure.

200820426TW2958pA piece 510. The etching process of the bottom layer 610 is stopped at the top surface of the intermediate dielectric layer 630. The bottom layer 610 is connected to the contact hole 620 and is disposed under the bottom layer 610 and surrounded by the intermediate dielectric layer 630. Embodiments of the contact hole 620 include a tungsten plug (W_plug) or a poly-si plug. The polycrystalline germanium plug can be composed of a polycrystalline germanium (p〇ly-Si diode) or an NP diode. Figure 7 is a diagram showing a current-voltage curve of a bistable resistive random access memory having a resistive random memory layer according to the present invention. The X-axis is voltage 710 and the y-axis is current. 720. In a RESET state 730, the resistive random access memory layer is low. In a set (SET) state 740, the resistive random access memory layer is at a high resistance. In this example, the set/reset window of the resistive random access memory layer is approximately one order of magnitude of read voltage 750. This read voltage, shown as a dashed line 752, exhibits a significant gap between the high current state (high logic state) and the low current state (low logic state). From reset state 730, after the voltage stress, the current in reset state 730 rises to a high current. From the set state 740, the current in the set state is lowered. When the current stops, the large swing from low state to high state or from high state to low state makes it difficult to control different logic multiple states with voltage. Therefore, the different resistive random access memory layers are connected in series, and each of the resistive random access memories has its own area or its own resistance for the bistable resistive random access memory. Implement different logic states. FIG. 8A is a simplified diagram showing a bistable process 28 ΓΨ 2958 ΡΑ 200820426 type resistive random access memory 600 having two resistive random access memory devices each located in a RESET state according to the present invention. . When the first critical resistive random access memory component 410 and the second programmable resistive random access memory component 510 are in a reset state, the bistable programmable resistive random access memory 600 operates on Logic state, 〇〇,,. The second programmable resistive random access memory device 510 has a resistor i? 810 and the first programmable resistive random access memory device 41 has an electrical barrier /?? Here, the variable ί is greater than 1, because the area of the first programmable resistive random access memory member 410 is smaller than the area of the second programmable resistive random access memory member 510. The total resistance of this bistable programmable resistive random access memory 600 is approximately (1 + /) feet. For example, assume that the variable / is equal to 2, and the total resistance can be calculated as a mathematical expression as (1 + 2 / 〇 = 3i?. Figure 8B shows two settings (SET > and reset according to the present invention) A simple schematic diagram of a bistable programmable resistive random access memory 600 of a (RESET) state resistive random access device. When the first programmable resistive random access memory component 410 is in a set state and a second The program resistive random access memory device 510 is in a reset state, and the dual Rustable programmable resistive random access memory 600 operates in a logic state "01", and the second programmable resistance type here The random access memory component 510 is still in a reset state or is not charged. The second programmable resistive random access memory component 510 has a resistive rib 1 and a first programmable resistive random access memory. The member 410 has an electrical; 7 fj? 8 3 0, where the variable /3 is greater than 1. The total resistance of the bistable programmable resistive random access memory 600 is approximately (i + j3 /) i For example, if the variable f is equal to 2 and the variable is equal to 1〇 While the total resistance was calculated to be the number 21i ?, 29

20082Pi26TW2958PA The expression is as ugly as (l〇+2i)i^3i. FIG. 8C is a diagram showing a bistable programmable electrical I1 and a random access memory device having two resistive random access memory components in a set (SET) and reset (RESE1T) state according to the present invention. A simple schematic. When the first resistive random access memory material component 410 is in a reset state and the second programmable resistive random access memory component 51 is in a set state, the bistable programmable resistive random access memory The body 600 operates in a logic state ''10'' where the first programmable memory random access memory component is still in a reset state or charged. The second programmable resistive random access memory component 510 The resistor and the first programmable resistive random access memory device 410 have a resistor / / 86 〇, where the variable /2 is greater than 1. The bistable programmable resist random access memory 6 〇〇 The total resistance is approximately for example, assuming that the variable / is equal to 2 and the variable η is equal to 10 'the total resistance can be calculated as l2i?, and its mathematical expression is expressed as (10 + 2) i? = 12i?. Figure 8D A simplified schematic diagram of a bistable programmable resistive random access memory 600 having two resistive random access memory components in a set (SET) state in accordance with the present invention. When the first programmable resistive random access is performed The memory member 410 is in a set state The second programmable resistive random access memory 51〇 member in a set state, then the bistable electrically programmable random access memory 600 Er operating state "1Γ in a logic. The second programmable resistive random access memory device 510 has a resistor and the first resistive random access memory 41 has a resistor ii/i?880. The bistable programmable resistive random access memory 30

The total resistance of the FW2958PA 200820426 600 is approximately /2 (1 + /)]?. For example, assuming the variable / is equal to 2 and the variable /] is equal to 10, the total resistance can be calculated as 30i?, and the mathematical expression is expressed as 10(l+2)i?=30i?. FIG. 9 is a diagram showing the mathematics of four logic states of the bistable programmable resistive random access memory 600 connected in series by two resistive random access memory components connected in series according to the present invention. Relationship, and each memory cell stores two dollars. The three variables i?, /] and ί use the equation of the resistance relationship, where the variable i? represents the reset of a memory component, the electrical group, the variable/2 is related to the characteristics of the resistive random access memory material, and The variable is related to the thickness of the dielectric sidewall. In other words, the variable Ώ depends on the material properties. The variable f can be controlled by the thickness of the dielectric sidewalls. In logic state "0" 910, the total resistance of the bistable programmable resistive random access memory 600 is approximately (l+/)i?. In logic state "1" 920, the total resistance of the bistable programmable resistive random access memory 600 is approximately (n + /) i?. In logic state "2" 930, the total resistance of the bistable programmable resistive random access memory 600 is approximately (l+/3/)i?. In the logic state "3" stomach 940, the total resistance of the bistable programmable resistive random access memory 600 is approximately the adjustment variable f to conform to the resistance transformation, so that there is sufficient operation window in the bistable programmable resistance random The two-bit operation is performed in the access memory 600. For example, the above two-bit operation window is represented by the following resistances: 3i?, to 30i?. If the variable /2 = 100, and the variable P2, and the two-bit operation window will be calculated as 3i?, 102i?, 201i? and 300i? Figure 10 shows the multiple resistance type 31 connected in series according to the present invention. TW2958pa A schematic diagram of a bistable resistive random access memory 1000 that provides random access memory components such that each memory cell provides multiple bits. Multiple Resistive Random Access Memory Components connect each memory cell in series to provide multiple bits. The bistable resistive random access memory 1000 includes a multi-resistive random access memory layer connected in series, in other words, a first programmable resistive random access memory layer 310 and a second programmable resistive random access The access memory layer 320 is connected in series, and the second programmable resistive random access memory layer 320 is connected in series with the third programmable resistive random access memory layer 1〇1〇,..., • (nl)th programmable resistive random The memory layer 1020 is connected in series with the nth programmable resistive random access memory layer 1030. In the embodiment, each of the first, second, third, ... (n-1 wide, Z programmable resistive random access memory layers 310, 320 '1010, 1〇2, 1030 respectively provides storage of two logic states In another embodiment, each of the first, second, third, (η - l)th, nth programmable resistive random access memory layers 310, 320, 1010, 1020, 1030 provides storage, respectively. The ability to be greater than two bits of information. In other embodiments, each of the first, second, third (nl)th, nth programmable resistance singular random access memory layers 310, 320, 1010, 1020 1030 provides information capabilities for storing two or more bits, each of which has the ability to store multiple pieces of information. The total number of logic states of the bistable resistive random access memory 1000 is determined by resistors. The number of Xs of the random access memory layer is determined by: - and the number of layers y per bit, expressed as the mathematical formula ZX*y, and the symbol Z represents the total number of total resistive random access memory layers. For example, if The bistable resistive random access memory (10) has eight resistive random memories The memory layer, where each resistive access memory layer can store the i-bits of 32 2 〇〇 82 mw · and the mother bit stores two logic states or current levels, and the total number of logic states can be calculated as 81 *2 or 64 kinds of logic states. Each of the first, second, third... (nl)th, nth programmable resistive random access memory layers 310, 320, 1010, 1〇20, 1030 materials may be the same respectively Or different, or some resistive random access memory layer makes the same material, part of the other resistive random access memory layer uses another material. In addition, the first, second, third... (nl) Th, nth programmable resistive random access memory layers 310, 320, 1010, 1020, 1030 thickness may be the same or different from each other, or some resistive random access memory uses the same thickness, some other resistive random memory Taking different thicknesses of the memory layer, the first, second, third, ... (nl)th, programmable resistive random access memory layers 310, 320, 1010, 1020, 1030 have a thickness ranging, for example, from about 1 nm. Between (nm) and 2 nanometers (nm). The resistive random access memory layers are all connected to a conductive layer. In addition to the first and second conductive layers 312, 322 described above, the third conductive layer 1Q? 12 is disposed on the third resistive random access memory layer 1 The nth conductive layer 1022 is disposed on the (nl)th resistive random access memory layer. The nth conductive layer 1032 is disposed on the first programmable resistive random access memory layer 1030. 11 is a diagram showing an etch process for the first and second programmable resistive random access memory devices 41, 510 and the first and second dielectric sidewalls 430, lio bistable according to the present invention. Schematic diagram of resistive random access memory 1000. The etching process can be further performed on the first and second programmable resistive random access memory components 410, 51〇 33

200820426 XW2958PA ♦ and subsequent resistive random access memory layers, such as the third resistive random access memory layer 1010. In this example, the third conductive layer 1012 is simultaneously etched in the third resistive random access memory layer 1010. The same dielectric sidewalls are also disposed on the subsequent conductive layer and the resistive random access memory layer. In an embodiment, the area of the second programmable resistive random access memory device 510 is primarily determined by the first dielectric sidewall 430. Similarly, the area of the third resistive random access memory device 1010 is also primarily determined by the second dielectric sidewall 1110. Therefore, each of the resistive random access memory layers has its own respective area and is mainly defined by the thickness of the dielectric sidewalls. Thus, the resistive random access memory layers have their respective resistances. 12 is a schematic diagram of a bistable resistive random access memory 1200 having multiple resistive random access memory components and multiple conductive members after removing dielectric sidewalls in accordance with the present invention. The bistable resistive random access memory 1200 includes a first conductive member 412 disposed on the first removable resistive random access memory component 410, and a first programmable resistive random access memory component 410 disposed. On the second conductive member 512, the second conductive member 512 is disposed on the second programmable resistive random access memory device 510, and the second programmable resistive random access memory member 510 is disposed on the third conductive member 1220. The upper and third conductive members 1220 are disposed on the third programmable resistance random access memory device 1210 . . . , and the nth conductive member 1040 is disposed on the nth programmable resistive random access memory layer 1030. In an embodiment, the first conductive member 412 has the same width as the first programmable resistive random access memory member 410, and 34

TW2958PA 200820426 is smaller than the width of the second conductive member 512 and the second programmable resistive random access memory member 510. The second conductive member 512 has the same width as the second programmable resistive random access memory member 510 and is smaller than the width of the third conductive member 1220 and the third programmable resistive random access memory member 1210. The width of the first/conductive member 1〇4〇 and the nth programmable resistive random access memory layer 1030 is wider than the width of the previous resistive random access memory member and the conductive member. As shown in Figures 12 and 13, the bit line voltage is applied to the bistable programmable resistive random access memory 600 to achieve different logic states. The structure 500 as shown in Fig. 5 can be imagined in Fig. 13 with the same circuit diagram. In this case, in the embodiment, two programmable resistive random access memories are described; |, , and additional additional memory layers and corresponding bit line voltages. The first resistor Rd310 of the circuit 1300 represents the resistance of the first programmable resistive random access memory component 410, and the second resistor H312 represents the resistance of the second programmable resistive random access memory component 510. The first bit line BLd340 having the first bit line voltage VmI320 is connected to the second bit line BL21342 having the second bit line voltage Vb21330. The first bit line voltage Vm1320 is connected to the top surface of the first conductive layer member 412 and the second bit line voltage Vb2l330 to the bottom surface of the second programmable resistive random access memory device 510. In this embodiment, the bistable resistive random access memory 500 includes two 4s resistive random access memory layers having two separate and first programmable resistive random access memory components 410 and The second programmable resistive random access memory component 510 is connected to the voltage, wherein the first voltage to the first programmable resistive random access memory 35 ΓΨ 295 δ ΡΑ 200820426 body member 410, represented by the symbol v1rram 1312 and the second voltage to the second The resistive random access member 510' is represented by a symbol. The first programmable resistive random access voltage 11313 has a first end spot electrically connected to the conductive member 412 and a second end connected to the first programmable resistive random access memory member 410. The second programmable resistive random access memory voltage VmM 1314 has a first end generally connected to the first programmable resistive random access memory component 410 and the first programmable resistive random access voltage Vi_l 313, and A second end is connected to the second programmable resistive random access memory component 510, and another programmable resistive random access memory voltage such as V3m»il316 and a third programmable resistive random access memory The bodies 1210 are connected and can be applied to the programmable resistive random access memory components of the subsequent performance. When the bistable resistive random access memory 500 is in a reset state, that is, a reset state, the bistable programmable resistive random access memory 600 has a logic state of "〇" (or state "00" )set up. The bistable programmable resistive random access memory 600 can be programmed from a logic state "B" to a logic state "1" (or state "01"), or from a logic state "0" to a logic state. Sad "2" (or state "10"), or logical state "〇" to logic state "3" (or state "11"). In the process of programmable bistable resistive random access memory 500 from logic, state "〇〇" to logic state "10", the -th voltage is applied to the first bit line to reach the first bit line voltage Vbil 320 and a second voltage are applied to the second bit line up to the second bit line voltage 1^1330. The voltage applied to the first bit line voltage U320 can be a chirp voltage or a small negative voltage.

200820426TW7O

,,...—TW2958PA • Pressure. The voltage difference applied between the first bit line Vbil320 and the second bit line voltage U330 is equal to the sum of the first resistive access memory voltage 1_1313 and the second resistive random access memory voltage V2_13u If expressed mathematically: Vb2-Vbi=V2mM+V1R_=: VK initial programmable resistive random access memory component 410 and second programmable resistive random access memory structure 51〇 initial The state is a reset state, that is, a low resistance state. In this embodiment, the area of the first programmable resistive random access memory component 410 is smaller than the area of the second programmable resistive memory access memory 510. Therefore, the resistance of the first programmable resistive random access memory component 410 is higher than the resistance of the second programmable resistive random access memory structure 510. This means that the value of the first resistive random access memory voltage VuRAM 1313 is larger than the second resistive random access memory voltage V2miil 314, and if expressed in a mathematical relationship, it is VlRRAM &gt; V2RRAM. Assuming that the first resistive random access memory voltage 1313 is greater than a reset voltage (VurAVset), the first programmable resistive random access memory component 410 is changed from a reset state to a set state (ie, High resistance). If the second resistive random access memory voltage V2RRAM1 314 is less than the set voltage (V2RRAM < VsET), the second programmable resistive random access memory component 510 remains in the reset state. The resistance of the first programmable resistive random access memory component 410 has a (1+/) allowable resistance value dependent state "0" (or state "00") changed to a state with an electrical drop. 2" (or status "10"). For example, if the variable /=2, the variable, and the second programmable resistive random access memory member 510 have a reset resistance equal to [and the total resistance will change from 3]?

TW2958PA 200820426 to 21i? In the process of bistable programmable resistance with state "0" (or state "00") program 1 access memory 600 from logic state "11"), the first power 2 ^ to Logic state "3" (or a bit line voltage Vm1320, and the second f = applied to the first bit line reaches the second bit line voltage Vbd330. Apply a voltage that is farther than the second bit line The memory device 41G and the second second can be randomly connected to a zero voltage or a small ^-bit line voltage ^1320. The initial state of the first-programmable resistive memory member 51 is: resistive random storage Take the state. Between the first bit line voltage v ^ &quot; also a low resistance V 1QQO ^ ^ Vbll32 〇 and the second bit line voltage

Vb2l330 voltage difference is high enough (v,,, exempt from; r) enough to make the second ^ resistive random access device voltage V_m1313 and the first - Leiyang 4 Λ &gt; 广ΤΓ 10_ 禾 resistance random access The memory voltage ν_1314 is higher than the first programmable resistive random access memory component 41 〇 = the second programmable resistive random access memory component 51 () &amp; The resistance state of the first programmable resistive random access memory component and the second programmable resistive random access memory component 510 is changed from a reset state to a set state. The resistances of the first and second programmable resistive random access memory components 410, 510 are changed from the logic state "〇" (state "00") of the resistance value (1 + f) i? to the logic state of the resistance value. 3" (status "11"). For example, if the variable is 2, the variable /2 = 10, and the reset resistance of the second programmable resistive random access memory device 51 is equal to 芡, the total resistance is changed from 3i? to 30J?. In the bistable programmable resistive random access memory 6_ from the logic state "〇" (or state "00") to the logic state "!" (or shape 38 200820426

During the meal FW2958PA (state "01"), the bistable programmable resistive random access memory 600 firstly changes from the logic state "〇" (or the state "〇〇") to the browse state "3". (or state "η"), and the first and second squeezing resistors § 己, 51 〇 are also changed from the reset state to the set state. The voltage supplied to the second bit line voltage Vb2133〇 may be zero power or a small negative voltage, expressed mathematically as: vb2-Vf Vw&lt;o. The first bit line voltage Vbll32() provides a positive voltage. In the set state, the surface area of the first programmable resistive random access memory component is smaller than the area of the second programmable resistive random access memory structure 510, so that the first programmable resistive random access memory The member has a higher resistance than the second programmable resistive random access memory member 51. This represents a high voltage drop through the first programmable resistive random access memory member 410' which is mathematically represented as 丨v1R_|>| If the absolute value of the first resistive k-machine access § memory voltage V1RRAM1 3 is greater than the reset voltage (丨ViR_ | &gt; VRESET), then the first programmable resistive random access memory: body member 410 changes to heavy Set state (low resistance). If the absolute value of the second resistive random access memory voltage VmAM1 314 is less than the reset voltage (丨Vmu | &lt; VRESET), the second programmable resistive random access memory device 510 remains in the set state. The resistances of the first and second programmable resistive random access memory components 410, 510 are changed from the resistance value 〆1+/) and the logic sorrow 3 (or state "11") to the resistance value ( Add/Leave logic state 1 (or state "〇1"). For example, if the variable /=2, the variable /3-10 and the second programmable resistive random access memory component 51〇 reset resistance Equal to friend, when from logic state, 0" to, 3", total 39

200820426TW2958PA The resistance changed from 3i? to 30i?, when the logic state changed from "3" to "1", the total resistance changed from 30i? to 12i?. Two resistors M310 and R21312 are connected in series between the two bit lines BL1I34O and BLd342. The voltages supplied to the bit lines are denoted as Vw 1320 and Vd21342, respectively, and the voltage drops across the two resistors are respectively Vimd 313 and V^RAIll 3 1 4 'The voltage bubble drop between the two lines is Vb2~ Vbl equal to VlRRAM + V2HM. As shown in FIG. 5, FIG. 6, FIG. 8A to FIG. 8B, and FIG. 12, the area of the first programmable resistive random access memory device 410 is larger than that of the second programmable resistive random access. The area of the memory member 510 is small, and thus the resistance Ri is larger. The state of the combined resistive random access memory and the resulting cell value are shown in Table 1. This cell value corresponds to the relative overall resistance value. Table 1 status / value

Ri r2 cell reset reset 0 ("00") reset setting Κ "or ) set reset 2 ("10") set δ again 疋 3 ("11") It is worth noting that the embodiment of the first table According to the structure of a small-endian (that is, the last component is the least significant digit (LSD) and the maximum 40

rW2958PA 200820426 Most significant digit (MSD). Other embodiments follow the big-endian mode, that is, the number system is saved, and the starting program is the same program, but the two memory units are reversed. The relationship of the mathematical derivation showing the state of each memory cell is described as shown in Figs. 8A to 8D. FIG. 8A illustrates that the memory cell having the first memory component 包1 includes the first programmable resistive random access memory component 41A and the first conductive member 420. And the second memory component 吣 includes a second programmable resistive Ik machine access memory structure 51〇 and a second conductive member 52〇. Here, both components have a low resistance in a reset state. If R can be regarded as the resistance of the larger second programmable resistive random access memory 51 (), then the resistance of the other first programmable resistive random access memory component 41 is the second The fixed value/correlation of the program resistive random access memory structure 510. This embodiment shows that the resistance of the first programmable resistive random access memory device 410 is higher than that of the second programmable resistive random access memory structure 510, so the constant f is known to be greater than 丨, but Other embodiments are semantically described as being reversed from the above. The difference in resistance exhibited by the 8A to 8D drawings of this embodiment is due to the different sizes of the two-resistance random access memory members. The smaller resistive random access memory device has a higher resistance value. In another embodiment (not shown), different materials are used by the two components to achieve the same operating resistance difference. The difference in structure between the two embodiments is obtained in the % of the case, and the two resistive random access memory members have approximately the same thickness (described in detail below), but the widths thereof are different to cause a difference in resistance. 41

200820426 TW2958PA The two resistive random access memory components are arranged in series, and thus the resistance of the memory cells can be expressed in all or. The lower order component M2 is switched to a set state having a relatively high resistance level as shown in Fig. 8B. The resistance level increases in proportion to the constant /]. Different materials have different constants depending on the characteristics or approval of a particular compound, but the relationship between the reset and set states of a given material can be represented by a relationship R + nR as shown in Figure 8B. Thus, the state illustrated in Fig. 8B can be mathematically or described. • Similarly, Figure 8C shows the result of switching the resistive random access memory device 2 to the set state, leaving it in the reset state. In this embodiment, two members are formed in the same village material. This constant/2 describes the difference between the setting and the reset, and allows the resistance value to be described in jl/i?. Derived a complete mathematical formula to describe the resistance of the memory cell. Finally, in Fig. 8D, the transition rram components Mi, M2 are set to a set state, and a transient state of transition and //?+/](|〇1%) is generated. This state can be expressed as or /2(1+/)/?.肇. The semantic relationship of the four cell values can be as follows in the second table. The second table cell value relationship cell value 0 ("00") 1 ("01") 2 ("10") 3 ("11") 42 2〇〇82〇426_ _ An example of a sensing operation window can be Set parameter values, / and implementation. False^, β=1〇 and /=2, the resistance values of the four states can be expressed as 3χ104Ω, ι·2χΐ〇5Ω, 2·1&gt;&lt;1〇5〇 and 3x1〇5q. A detection voltage (read voltage) is 120 mV, and the induced currents of the four states are 4 //A, 1/z A, 0.6# A, and 0.4# A, respectively.区别 The difference between multiple levels of operation can be set to 2.5/ζΑ, 0·8/ζΑ and 0.5/U. For induced currents above 2·5 μΑ, a minimum resistance state can be defined as the state “〇” (or “00”). For an induced current less than 〇·5 with a, a maximum resistance _ state can be degraded to state "3" (or state "11"). For an induced current above 0.8 //A but less than 2·5/z A, a low resistance state can be defined as state "1" (or state "01"). For detecting an induced current greater than 0.5# a but less than 0·8μ A, a high resistance state can be defined as state "2" (or state "10"). The change in induced current is based on changes in the manufacturing process and changes in the nature of the material. For example, the change in the thickness (or width) of the dielectric sidewall determines the area of the second programmable resistive random access memory device, and the thickness and area determine the second programmable resistive random access memory component. The resistance. Therefore, the operation of a high quality multi-bit resistive random access memory requires a wide operating window. A higher constant Π and a higher coefficient / can provide a wide operating window, thus avoiding product status confirmation errors. A voltage is applied across the bit lines BLi and BL2 to set the memory to a desired value. The total value of the four voltages is sufficient to complete all possible values as shown in Table 1. Those skilled in the art will recognize that there are some actual voltages available. In one embodiment, two positive voltages are used (here exactly 2 measurements at 43 2〇〇82^^6TW2958paf) and two results are shown as v_,. characteristic. The absolute value of the applied voltage depends on the memory component k I including the material and size. In this embodiment, it is indicated. (4) and - the low voltage value is the reset of the body H-order. That is, the drive resistance is stored randomly == the piece to the reset state' to generate the cell value. This procedure is as follows: Table 3 overall reset transition process 2 (Vb2-Vbl) = — Vhigh)

As indicated above, the appropriate transition region voltage is _1, and the value of each of the pair of values V_#V2_, such as a shallow drop in voltage, exceeds the reset value. The value of the whole of the memory cell is 〇 as the two-resistance random sub-body member is in the reset state. The reset state is the starting point of the in-step operation. Because the unpredictable transition of the financial shame g, it is better to use the pure phase change operation Τ 以 T to lower the unit to the reset state as the first step. In its opposite state, the -cell value is 3, as shown in Table 4 below. 44

200820426 TW2958PA Transition of Table 4-3 (Vb2~Vbl)=Vhigh Component Status Cell Value Action Element Status Cell Value Μι 0 0 Vi&lt;Vset 1 3 M2 0 ¥2&gt;VsET 1 Apply a VhUh high voltage, enough to generate more than two The voltage drop of the VSET of the component. This cell value is 11 or 3 of the binary as the two components are in the set state. To generate a cell value of 2, the procedure is as shown in Table 5 below. Transition of Table 5-2 (Vb2-Ybl)=Vlow Element State Cell Value Action Element State Cell Value Μι 0 0 Vl&gt;VsET 1 2 M2 0 Y2&lt;YsET 0 In this setting, this voltage bleed Vi is greater than one Set the state of demand, so Ri is the set state, but this voltage drop V2 is less than the set demand. This result causes the 匕 to be in a set state and R2 to be in the reset state, resulting in a cell value of two bits 01 or 2. The way to generate a cell value of 1 is shown in Table 6. It is more difficult to reach the value of 1 than other transitions. Obviously, if the two components start from the reset state, applying a voltage sufficient to generate the set state at V2 will inevitably be set at V!, resulting in a value of 3. Not 1. The solution is to first make the memory cells all set, as shown in the previous table. Then, from a value of 45 2〇〇82^£g6TW29, the application of the -v_ voltage is sufficient for I instead of R to generate a reset state to produce a binary value of 01 or 1. Transition of Table 6 3-1 (Vb2 - Vbl) = - Vlow Component Status Cell Value Action Element Status Cell Value Μι 1 3 I Vl | &gt; Vreset 0 1 Ϊ 2 1 1 V2 1 &gt; Vreset 1 Figure 14 According to the present invention, the flow of the bistable programmable resistive random access memory 600 from the logic state "〇〇" to the other three logic states, the logic state "01", the logic state "10", and the logic state "11" is illustrated. Figure 1400. In step 1410, the bistable programmable resistive random access memory 600 can be programmed from a logic state "〇〇" to a three logic state, a logic state "01", a logic state "10", and a logic state "11". In step 1410, the bistable programmable resist random access memory 600 is in a logic state "00". If the bistable programmable resistive random access memory 600 is programmed from the logic state "00" to the logic state "〇1", in step 1420 the bistable programmable resistive random access memory 600 first The logic state "00" is programmed to the logic state "11", and then the logic state "11" is programmed to the logic state "01" in step 1430. In step 142 0, the bistable process: the resistive random access memory 600 is programmed from the logic state "00" to the logic state "11", and the first bit line voltage Vm1320 and the second bit The voltage of the line voltage - the difference between the voltages of 1330 is equal to &quot;the power of the waste Vhigh' is expressed in the mathematical form as Vbl-Vb2:=Vhigh, this brother 46

200820426TW2958PA ▲ The resistive random access memory voltage V2mM1314 is greater than the Vset voltage, and the first resistive random access memory voltage V1RRAM 1313 is greater than the VSET voltage. In step 1430, the bistable programmable resistive random access memory 6 is programmed from the logic state "11" to the logic state "〇1", and the first bit line voltage Vm1320 and the second bit line voltage The voltage difference between Vb21330 is specific to a negative low voltage -VlQW 'calculated as Vb2_Vbi=-Vi〇w, and the absolute value of the first resistive random access memory voltage V2miil3l4 is less than the absolute value of the Vreset voltage. And the first resistive random access memory voltage 10 Virram 1313 is greater than the absolute value of the Vreset voltage. In step 1440, the bistable programmable resistive random access memory 600 is programmed from a logic soft state "〇〇" to a logic state "10" at a first bit line voltage Vm1320 and a second bit line voltage Vb2l330. The voltage difference between the two is equal to a low voltage Vb, and is expressed by the mathematical expression as Vb2-Vbl=Vw, the second resistive random access memory voltage V2R_1314 is smaller than the Vsn voltage, and the first resistive random access memory voltage V1RRAM 1313 is greater than the Vsn voltage. In step 1450, the bistable programmable resistive random access memory 600 is programmed from the gastric logic state "〇〇" to the logic state "11", and the first bit line voltage Vbil320 and the second bit line voltage Vb2l330 The voltage difference between them is equal to the high voltage Vhigh, which is expressed by the mathematical expression as Vbl-Vl&gt; 2 = Vhigh, the second resistive random access memory voltage V2MAM 1314 is greater than the Vset voltage, and the first electric, .... resistive random Access memory voltage 1313 nine final vsn voltage. 15 is a diagram showing the bistable programmable resistive random access memory 600 from a logic state "〇1" to three other logic states, a logic state "00", a logic state "10", and a logic state according to the present invention. 47 of "11"

TW2958PA 200820426 Flowchart 1500. In step 1510, the bistable programmable resistive random access memory 600 is in a logic state "01". In step 1520, the bistable resistive random access memory 600 is programmed from a logic state "〇1" to a logic state "00" between the first bit line voltage Vbi 1320 and the second bit line electric dust Vb21330. The voltage difference is equal to a negative high voltage -Vhuh, expressed by the mathematical expression as VM_Vb2=-Vhigh, and the absolute value of the second resistive random access memory voltage V2R_1314 is greater than the Vresh voltage, and the first resistive random access memory The absolute value of the bulk voltage VurAM1313 is greater than the Vreset voltage. If the bistable programmable resistive random access memory 600 is programmed from the logic state "01" to the logic state "10", the bistable programmable resistive random access memory 300 is first logiced in step 1530. The state "01" is programmed to the logic state "〇〇", followed by the logic state "00" to the logic state "1" in step 1540. In step 1530, the bistable programmable resistive random access memory 600 is programmed from a logic state "01" to a logic state "00", between the first bit line voltage Vbl1320 and the second bit line voltage Vb21330. The voltage difference is equal to a negative high voltage -Vhigh, expressed as Vm-Vb2=-Vhigh in mathematical expression, and the absolute value of the second resistive random access memory dust VmAiil314 is greater than Vreset electric waste' and the first one is resistive The absolute value of the random access memory Vi_d313 is greater than the VRESET voltage. In step 1540, the bistable programmable resistive random access memory 600 worm logic state "〇〇" is programmed to a logic state "10", and the first bit line voltage Vm1320 and the second bit line voltage ^330 The voltage difference between them is equal to a low voltage Vw, expressed as Vbl-Vb2=Vi in mathematical expression. , 'the second resistive random access memory voltage V2RRAMi314 is greater than the Vreset voltage, and the 48th

TW2958PA 200820426 A resistive random access memory voltage Virram1313 is less than the Vreset voltage. In step 1550, the bistable programmable resistive random access memory 600 is programmed from a logic state "〇1" to a logic state "11", and the first bit line voltage Vbl1320 and the second bit line voltage Vt&gt The voltage difference between 21330 is equal to a high voltage Vhuh, expressed as Vbi-VfVhuh in the mathematical expression. The second resistive random access memory voltage VmAiil314 is greater than the Vset voltage, and the first resistive random access memory voltage ViRRAM1313 Greater than the Vset voltage. Figure 16 is a diagram showing a bistable programmable resistive random access memory 600 programmed from a logic state "1" to three other logic states, a logic state "(10)", a logic state "〇1" according to the present invention. And the flow chart 1600 of the logic state "11". In step 1610, the bistable programmable resist random access memory 600 is in a logic state "10". In step 1620, the bistable programmable resistive random access memory 600 is programmed from a logic state "10" to a logic state "00", between the first bit line voltage Vbl1320 and the second bit line voltage Vb21330. The voltage difference is equal to a negative high voltage • -Vhuh, expressed in the mathematical form as Vm-V^-Vhigh, the absolute value of the second resistive random access memory voltage 1314 is greater than the WmT voltage, and the first resistive random The absolute value of the access memory voltage ν1 Κ ω1313 is greater than the Vreset voltage. If the bistable wide resistive random access memory 600 is programmed from the logic state "10" to the logic state "01", the bistable programmable resistive random access memory is accessed in step 1630. 600 is first programmed from the logic state "10j to the logic state "11", followed by the logic in step 1640.

200820426 TW2958PA 麝 _ Status ’ n” is programmed to logic state “01”. In step 1630, the bistable programmable resistive random access memory 6 is programmed from a logic state "10" to a logic state "11", and the first bit line voltage Vm1320 and the second bit line voltage Vb21330 The voltage difference is equal to the high voltage (10), expressed as Vb2=Vhigh in the mathematical expression, the second resistive random access memory voltage V2md314 is greater than the Vsn voltage, and the first resistive random access memory voltage Virram1313 is greater than Vset Voltage. In step 1640, the bistable sorrow-stable resistive random access memory 600 is programmed from the logic state "11" to the logic state "10", and the first bit line voltage Vbl1320 and the second bit line voltage VmI330 The voltage difference is equal to the negative low voltage - expressed as Vbl-VfVlmr in the mathematical expression, the absolute value of the second resistive random access memory zero voltage VmAM 1314 is greater than the absolute value of the Vreset voltage, and the first resistive random access The absolute value of the memory voltage V1R_1313 is less than the absolute value of the Vresh voltage. In step 1650, the bistable programmable resistive random access memory card 6 is programmed from a logic state "10" to a logic state "11", and the first bit line voltage Vbl1320 and the second bit line The voltage difference of the voltage vbd330 is equal to the high voltage vhigh, expressed as vbl-Vb2=Vhigh in the mathematical expression, the second resistive random access memory voltage V2RRAM1314 is greater than the Vsrr voltage, and the first resistive random access memory voltage Virram1312 Greater than Vsn voltage. Figure 17 is a diagram illustrating the bistable programmable resistive random access memory 600 from the logic state "1" to the other three logic states, the logic state "〇〇J, logic state" Flowchart 1700 for 1" and logic state "10". In the step ΠΙΟ bistable programmable power 50

2〇〇82〇426TW2958PA Resistive random access memory 600 is programmed from logic state "11" to logic state "00", which is the voltage difference between the first bit line voltage Vbil320 and the second bit line voltage Vb21330 The value is equal to the negative high voltage -Vhigh, expressed as Vbl-VbZ111-Vhigh in the mathematical formula. 'The second resistive random access memory voltage 1 finds that the absolute value of 1314 is greater than the Vresh voltage, and the first resistive random access memory The absolute value of the bulk voltage VimMl313 is greater than the Vreset voltage. In step 1730, the bistable programmable resistive random access memory 600 is programmed from a logic state "11" to a logic state "〇1", and its first bit_yuan line voltage Vbl1320 and second bit line voltage Vbd330 The voltage difference between them is equal to the negative low voltage -View, expressed as Vbl-Vb2=-Vi in mathematical form. The absolute value of the second resistive random access memory voltage hmd 314 is greater than the absolute value of the Vresh voltage, and the absolute value of the first resistive random access memory voltage Virram 1313 is less than the absolute value of the Vreset voltage. If the bistable programmable resistive random access memory 600 is programmed from the logic state "11" to the logic state "10", in step Π40 the bistable programmable resistive random access memory 600 is first determined by the logic state. 11" _ is programmed to the logic state "00", followed by the logic state "00" in the step Π50 to the logic state "1". In step Π40, the bistable programmable resistive random access memory 600 is programmed from a logic state "11" to a logic state "〇〇", the first bit line voltage Vbl1320 and the second bit. The voltage difference between the line voltages Vb2l330 is equal to the negative high voltage -Vhigh, expressed as a mathematical expression of VM-VbF-Vhigh. The absolute value of the second resistive random access memory voltage V2_1314 is greater than the V_T voltage, and the first resistance The absolute value of the random access memory voltage V1RRAM 1313 is greater than the Vreset dust. At 51

200820426 TW2958pA » In step 1750, the bistable programmable resistive random access memory 600 is programmed from a logic state "00" to a logic state "10", the first bit line voltage Vbd320 and the second bit line The electrical waste difference between the voltages Vb21330 is specific to the negative low voltage -Vlow, and the mathematical expression is Vbl-Vb2=: -, the second resistive random access memory voltage V2md314 is greater than the Vset voltage, and the first resistor The random access memory voltage is less than VSET;

For additional information on the fabrication, material composition, use, and operation of phase change random access memory devices, see U.S. Patent No. 11/155, 067 &quot; Thin Film Fuse Phase Chang RAM and

Manufactured by the assignee of the application, which is hereby incorporated by reference in its entirety in its entirety in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire As disclosed above, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains may have various modifications and refinements in the spirit and scope of the invention in the (four) county. Therefore, the scope of protection of this judgment is deemed to be attached to the application. The scope is defined as the finale. 52 200820426

2: 3⁄4 class m · TW2958PA 2 [Simple description of the drawing] Fig. 1 is a schematic view showing a bistable resistive random access memory array according to the present invention. 2 is a simplified block diagram of an integrated circuit diagram of a resistive random access memory structure in accordance with a preferred embodiment of the present invention. Figure 3 is a simplified diagram showing the steps of the deposition and lithography techniques for fabricating a two-program resistive random access memory layer of a bistable resistive random access memory. Figure 4 is a schematic diagram showing a step under the fabrication of a bistable resistive random access memory according to the present invention, etching to a second conductive layer, the second conductive layer being deposited adjacent to the first conductive member and the first programmable A dielectric sidewall of a resistive random access memory device. Figure 5 is a block diagram showing a step under the fabrication of a bistable resistive random access memory in accordance with the present invention, etched through a second resistive random access memory layer. Figure 6 is a simplified schematic diagram showing the structure of a resistive random access memory cell in accordance with the bistable resistive random access memory of the present invention. Figure 7 is a diagram showing an example of a current-voltage (I-V) curve of a bistable resistive random access memory having a resistive random access memory layer in accordance with the present invention. Figure 8A is a simplified schematic diagram showing a bistable resistive random access memory having two resistive random access memory components each located in a RESET state in accordance with the present invention. Figure 8B illustrates two settings (SET) 53 in accordance with the present invention.

2〇〇82_0426TW2958PA and reset (RESET) state resistive random access device bistable resistive ^ random access memory simple schematic. Figure 8C is a simplified schematic diagram of a bistable resistive random access memory having two resistive random access memory components in a set and reset state in accordance with the present invention. Figure 8D is a simplified schematic diagram of a bistable resistive random access memory having two resistive random access memory components in a set (SET) state in accordance with the present invention. Φ Figure 9 is a diagram showing the mathematical relationship of four logic states of a bistable resistive random access memory in which two resistive random access memory components are connected in series to provide four logic states in accordance with the present invention. Figure 10 is a schematic illustration of a bistable random access memory in which multiple resistive random access memory components are connected in series to provide multiple bits per memory cell in accordance with the present invention. 11 is a schematic diagram of a bistable resistive random access memory having an etch process on the first and second resistive random access memory layers and a deposited dielectric sidewall according to the present invention. Figure 12 is a schematic diagram showing a bistable resistive random access memory having a multi-resistive random access memory device and a plurality of conductive members after removing the dielectric sidewalls according to the present invention. Figure 13 is a diagram showing a bistable resistive random access memory device for applying a voltage in accordance with the present invention to have a resistive random access memory device. Figure 14 is a diagram showing the bistable resistive random access 54 200820426T W295 8Ρ 记忆 memory is programmed from the logic state "00" to the other three logic states, the logic state "01", the logic state" according to the present invention. 10" and the flow chart of the logic state "11". Figure 15 is a diagram showing the bistable resistive random access memory from the logic state "01" to the other three logic states, the logic state "00", the logic state "10", and the logic state "11" according to the present invention. Flowchart ^ Figure 16 illustrates the bistable resistive random access memory from the logic state "10" to the other three logic states, logic state "00", logic state "01" according to the present invention. And the flow chart of the logic state "11". Figure 17 is a diagram showing the bistable resistive random access memory from the logic state "11" to the other three logic states, the logic state "00", the logic state "01", and the logic state "10" according to the present invention. Flow chart. • [Main component symbol description] 100: Memory array 123, 124, 262: Word line 128: Common source line. 132, 133: Lower electrode member, 134: Upper electrode member 135: Side wall pin memory cell 141 , 142, 264: bit line 55

rW2958PA 200820426 145: Y-decoder and a word line driver 146: X-decoder and a set of sense amplifiers 150, 151, 152, 153 :: access transistor 200, 275: integrated circuit 260: memory array 261: column decoder 263: pin decoder 2 6 5 · bus bar 266: sense amplifier and data input structure 267: data sink drain 268: bias arrangement supply voltage 269: bias arrangement state machine 271: data input line 272: data output line 274: other circuits® 300, 1000, 500: bistable resistive random access memory 310: first programmable resistive random access memory layer 312: first conductive layer 320: second Program resistive random access memory layer 322: second conductive layer 330: mask 410: first programmable resistive random access memory device 412, 420: first conductive member 56

200820426TW2958PA 430 ·• First dielectric sidewall r 510 ·•Second programmable resistive random access memory component 512, 520: second conductive member 600: bistable programmable resistive random access memory 610 : bottom layer 620: contact hole 630: intermediate dielectric layer 700: current-voltage curve example diagram • 710: voltage 720: current 730: reset state 740: set state 750: read voltage 752: dashed line 810: resistance i? 820 860 ··Resistance/i? _ 830,880: Resistor/] 850, 870: Resistor/li? 910: Logic state "0" 920: Logic state "1" 930: Logic state "2" &lt; : - · .* * ' 940 : Logic state "3" 1010 : Third resistive random access memory layer 1012 : Third conductive layer 57 20082 〇 426_ 1020: (η - 1)th programmable resistive random memory layer 1022 : (nl)th conductive layer 1030: nth programmable resistive random access memory layer 1032: nih conductive layer 1110: second dielectric sidewall 1200: bistable programmable resistive random access memory 1210 : third programmable resistance random access memory member 1220 : third conductive member 13 0 0 : circuit system 1310: A resistor Ri 1312: second resistor R2, 1313: first programmable resistance random access voltage Vmam 1314: second programmable resistance random access memory voltage V2Rrm 1316: additional programmable resistance random memory Taking the memory voltage 1320: the first bit line voltage Vm 1330: the second bit line voltage Vb2 • 1340: the first bit line 1342: the second bit line BL2 1400, 1500, 1600, 1700: flowchart 58

Claims (1)

200820426 祖祖10, the scope of application for patents: 1. A method of operating a resistive random access memory device, having a first conductive member, located on a first programmable resistive random access memory device, The first programmable resistive random access memory component is located on a second conductive member, and the second conductive component is located on a second programmable resistive random access memory component. The method comprises at least: The first programmable resistive random access memory component is connected in series with the second programmable resistive random access memory component, and the first programmable resistive random access memory component has a first representation The area of the resistance value, the second programmable resistive random access memory module has an area representing a second resistance value R, and the second programmable resistive random access memory component has the area larger than the area a first programmable resistive random access memory component, the first programmable resistive random access memory component having a first logic state ("00" shape And a second logic state ("0 state"), the second programmable resistive random access memory member has a third logic state ("10" state) and a fourth logic state ("11") a second dielectrically resistive random pattern is deposited on both sides of the first conductive member and the first programmable resistive random access memory device and on the surface of the second conductive member 妁h The access memory member has an area which is a function of the thickness of the first dielectric sidewall; and the first and second programmable resistive random access memory 59 fW2958PA 200820426 is changed to a material coefficient a function of the logic state of the component to another logic state, the logic state η and the thickness f of the dielectric sidewall. wherein the first one of the second ones of the third one is as described in claim 1 The logic state is based on the mathematical formula (1+/) friend operation. 3. The method described in claim 1 of the patent scope, the logic state is operated according to the mathematical formula (correction/)]. 4. If the method described in claim 1 is applied, the logic state is based on the mathematical formula (1+/2/) and the operation. 5. The method of claim 1, wherein the fourth logic state operates according to a mathematical formula. 6. The method of claim i, further comprising: connecting a first bit line voltage Vbl to a top surface of the first conductive hiring; connecting a second bit line voltage Vm to the first a bottom surface of the second programmable resistive random access memory device; generating a first resistive random access memory voltage between the first conductive member and the first programmable resistive random access memory device; A second resistive random access memory voltage V2RRAJ is generated between the first programmable resistive random access memory component and the second programmable resistive random access memory component. 7. The method of operating a resistive random access memory device according to claim 6, wherein the first and second programmable resistive random access memory components are in a RESET state. The method of claim 6, wherein the memory device changes from the first logic state to the second logic state from the first logic state, such that the transition from the first logic state to the transition In the state, Vbl-Vb2=Vhigh, V2RRAM&gt;VsET and Vu_&gt;VsET, and when changing from the transition state to the first logic state, 'set Vb2 — Vbl = -Vlow<0, I VmAM I &lt; I Vseset I And 丨V1RRAM 丨&gt; I Vreset I. 9. The method of claim 6, wherein the memory device is changed from the first logic state to the first by setting Vb2-Vm=Vi〇w, V2r_&lt;VW and Vl&_&gt;vSET Three logic states. 10. The method of claim 6, wherein the memory device changes from the first logic state to the fourth logic state by setting Vbi-Vb2 = Vhigh, V2R_&gt; Vsrr and V^AVsn. 11. The method of operation of claim 6, wherein the memory device is changed from the second logic state by setting Vbi-Vb2: -Vhigh, |V2rram|&gt;Vreset and |VlRRAM丨>VrESET The first state. 12. The method of claim 6, wherein the memory device device is set from the second logic state to the third state, such that when the first state is changed to the transition state, the setting is Vt&gt;rVb2=-Vhigh,|V2_(|&gt;VRESET and 丨Vi_H&gt;V_T, and when changing from the transition state to the third state, Vbl-Vb2=Vi〇w 'V2mM&gt;Vsn and VlRRA«<VsET are set. 13. The method of operation of claim 6, wherein the memory device changes from the second logic state to the fourth logic state by setting h_&gt;Vsn and V1R_&gt;VSn. 61 TW2958PA 200820426 14· The operating method of claim 6, wherein the memory device changes from the third logic state to the v3 by setting vbl-vb2 bis-Vhigh, |V2_|&gt;Vreset and 丨VlRRAM I &gt;VrESH The operating method of claim 6, wherein the memory device changes from the third logic state to the second logic state via the transition state, such that the third logic state Change to the transition In the state, Vbi-Vb2=Vhigh, 72_&gt;1^ and Vi_&gt;Vsn, and when changing from the third logical cancer to the second logic state, 'set Vbl-Vb2 = -Vlow ' | V2RRAM 丨>丨VrESET The method of claim 6, wherein the memory device: from the third logic state to the fourth logic state, VbleVb2:=Vhigh J The method of claim 6, wherein the memory device is set by Vm-VbF-Vhigh, 丨V2RRAM 丨&gt;VrESET and 丨VlRRAM I &gt;VrESET The method of claim 6, wherein the memory device is set by Vbl-Vb2 = - Viow, |V2RRAm|&gt;|VrESEt| And 丨||Vreset I changes from the fourth logic state to the second logic state. The method of claim 6, wherein the memory device transitions from the fourth logic state The state changes to the first logic state, so When the fourth logic state is changed to the excited state transition, setting 11 ^ 1-? &2 = -¥咖, |¥21^丨&gt;1^°£1' and |^_1>1^咖*1' and when changing from the transition state to the fourth logic state, setting VbrVb2=Vb , V2R_&gt;VsET and VlRRAM&lt;VsET. 62