200818450 九、發明說明： 【明 屬 3 發明領域 本發明一般地係有關於疊積晶粒，更特定延之，係有 5 關於執行疊積具有不同熱特性的晶粒。 C先前技術2 發明背景 電路設計需有複數之不同的考量。於多數的應用中， 笔路的實體尺寸係為關鍵性的。例如，可攜式裝置，諸如 10行動電話、個人數位助理(pda)、遊戲裝置及音樂播放哭， 在相同或是減小的實體形狀因素下漸增地需要更多的功 性。對於該等可攜式裝置的一解決方案係使用疊積式晶2 積體電路(1C)。疊積式晶粒積體電路提供的益處在於容許二 晶粒配置在辣而不需在1C之佔用面積或高 15 度上有顯著的增加。 於特定的疊積式晶粒積體電路中，就其之熱特性而 口 9θ粒具有顯著的差異性。例如，晶粒於其之介電常數 (k)上顯現充分的不同，在其之熱膨脹係數(tce)上亦具有差 異性。具有較大TCE的材料係受限於一具較小TCE的材料 2〇而無法膨脹，從而對具較小TCE的材料施加—力量，造成 膨脹更甚於其之TCE預測值。因此，介於晶粒間的互連因 不同的熱性質而承受應力。由於會對晶粒或其之互連造成 破4或其他方式的損害，所以此應力會減少IC的使用壽命 並導致1C結構上的破壞。 200818450 已试圖於晶粒間使用矽、鐵氟龍(Teflon®)及黏著劑薄 膜，用以減小晶粒間的熱應力；然而，該等方法係為昂貴 的’難以執行’並仍承受一不符合要求之程度的熱破壞。 其中该一嘗試係於2003年2月18日頒佈授與Su、Spencer 5專人心通為多晶片封裝(Multi-chip package)’’的台灣專利 第TW504818B號中有所說明。此專利講授使用二界接探測 器（interposer)而於界接探測器之間具有一間隔，但仍有改 良空間。 該等與其他的限制對疊積式晶粒K：之應用具挑戰性。 10 【發明内容】 發明概要 本务明之不同觀點係針對用以完成滿足及克服上述議 題的方法及配置。 與一示範具體實施例一致，本發明係針對一疊積式晶 !5粒積體電路配置，其具有-第-石夕晶粒，承受因:熱變: 而在實體尺寸所造成的第一變化。電路配置亦包含一第一 矽晶粒，承受因一熱變化而在實體尺寸所造成的第二變 化。實體尺寸所造成的變化在積體電路配置上產生一力 量。此外，該電路配置包括接合至每一晶粒的_支撐姅構， 2〇並實質上與一界面區域外切。界面區域與每一晶粒之一部 分接觸並具有一較支撐結構為大的可彎性係數。該可彎性 係數係為實體尺寸上第一變化與第二變化之間的一差異性 的一函數。 與一進一步的示範具體實施例一致，使用一方法用以 6 200818450 產生具有一第一及第二矽晶粒的一疊積式晶粒積體電路配 置。對於一界面區域所確定的可彎性係數係為介於第一與 第二晶粒TCE間差異性的函數。針對該可彎性係數，選定 在界面區域中使用的一材料。第一石夕晶粒係黏合至一支樓 5結構。該支撐結構實質上與該界面區域外切。第二晶粒係 黏合至支樓結構致使界面區域接觸每一晶粒之一部分，並 且晶粒相互垂直。200818450 IX. INSTRUCTIONS: [Ming 3] Field of the Invention The present invention relates generally to stacked grains, and more particularly to grains having different thermal characteristics for performing lamination. C Prior Art 2 Background of the Invention Circuit design requires a plurality of different considerations. In most applications, the physical size of the stroke is critical. For example, portable devices, such as 10 mobile phones, personal digital assistants (PDAs), gaming devices, and music playback, are increasingly requiring more functionality under the same or reduced physical form factor. One solution for such portable devices is to use a stacked crystal 2 integrated circuit (1C). The stacked die integrated circuit provides the benefit of allowing the two die configuration to be spicy without a significant increase in the 1 C footprint or height 15 degrees. In a particular stacked-type grain integrated circuit, there are significant differences in the thermal properties of the 9θ particles. For example, the crystal grains exhibit a sufficient difference in the dielectric constant (k) thereof, and also have a difference in the coefficient of thermal expansion (tce) thereof. Materials with larger TCEs are limited to a smaller TCE material and cannot expand, thereby applying a force to the material with a smaller TCE, causing the expansion to be more pronounced than its TCE prediction. Therefore, the inter-grain interconnections are stressed by different thermal properties. This stress reduces the lifetime of the IC and causes damage to the 1C structure due to damage to the die or its interconnections. 200818450 Attempts have been made to use tantalum, Teflon® and adhesive films between grains to reduce thermal stress between grains; however, these methods are expensive 'difficult to perform' and still withstand A thermal damage that does not meet the requirements. One of the attempts was described in Taiwan Patent No. TW504818B, which was issued on February 18, 2003, and issued to Su, Spencer 5, and the multi-chip package. This patent teaches the use of a two-interconnect detector with an interval between the boundary detectors, but there is still room for improvement. These and other limitations are challenging for the application of the stacked die K:. 10 SUMMARY OF THE INVENTION The present invention is directed to methods and arrangements for accomplishing and overcoming the above problems. Consistent with an exemplary embodiment, the present invention is directed to a stacked crystal!5-grained body circuit configuration having a -D-Silver grain, with a heat-resistant: first in physical size Variety. The circuit configuration also includes a first germanium die that withstands a second change in physical size due to a thermal change. The change in physical size creates a force on the integrated circuit configuration. In addition, the circuit configuration includes a _support structure bonded to each die, and is substantially circumscribed with an interface region. The interface region is in contact with one of the portions of each of the dies and has a greater bendability factor than the support structure. The bendability factor is a function of a difference between the first change and the second change in the physical size. Consistent with a further exemplary embodiment, a method for 6 200818450 to produce a stacked die integrated circuit configuration having a first and second germanium die is used. The bendability coefficient determined for an interface region is a function of the difference between the first and second die TCE. For this bendability factor, a material used in the interface region is selected. The first Shixia crystal system is bonded to a building 5 structure. The support structure is substantially circumscribed with the interface region. Bonding the second die to the branch structure causes the interface region to contact a portion of each die and the grains are perpendicular to each other.
本發明之上述摘要並不意欲說明每一具體實施例或是 本發明之每-應用。藉由參考以下結合伴隨圖式所作的詳 細說明及中請專職圍，對益處及目標，連同對本發明之 更為完整的瞭解，將為顯而易見並察知的。 圖式簡單說明 15 弟2圖係為本發明之一厂# 晶粒配置產生方法；以及範具體實施例的多重疊積式 第3圖係為-視圖，圖示用' 2〇實施例的-疊積式晶教 Μ產生本發明之-示範具體 、一示範方法。 較佳實施例之詳細說明 仏官本發明能接受不同的 之特性已於圖式中經由每 ^文及可任擇的形式，但其 ^以顯示並將詳加說明。然 7 200818450 而’應瞭解的是並不意欲將本發明限定在所說明的特定具 體實施例上。相反地，意欲包含所有的修改、等效物及可 任擇方案，其係涵蓋於由附加的申請專利範圍所界定的本 發明之範疇内。 5 +本發明咸信可適驗複數之包含疊積式晶粒結構的積 體電路及方法。儘管本發明並不必需限定在該等應用上， 疋本t明之不同觀點的評論係在該一環境下經由對實例 的論述而有最佳的結果。 與本發明之一示範的具體實施例相一致， 曰 4 币一日日 10粒施以-塑膠或是相似間隔材料層。施加該間隔材料致使 八實貝上與一界面區域外切。一第二晶粒係配置位在第一 晶粒上方，致使該間隔材料係介於第一與第二晶粒之間。 第一與第二晶粒係接合至該間隔材料並藉由間隔材料及界 面區域而相互分離。間隔材料對於所完成的疊積式晶粒配 15 置提供結構上支撐。 ♦ 本發明之另一示範具體實施例包括二晶粒，每一晶粒 接合至一間隔材料層，致使間隔材料層將二晶粒分離。間 隔材料層實質上與一包含空氣並於二晶粒間擴展的界面區 域外切。所使用的特定類型之間隔材料具多樣化，但可包 20括熱塑性塑膠（能夠藉由溶化而多次地加以重新形成的塑 膠材料)或黏著劑，諸如鐵氟龍(Tefl〇n⑧）。於一較佳的具體 實施例中，黏著劑可為Hysol®QMI536TM或是 ABLESTIKTM2025D。Teflon® 係為杜邦公司（du P〇nt de Nemours and Company Corporation)的一註冊商標。 200818450 ABLESTIK商標係為國民澱粉化學股份有限公司（Nati〇nalThe above summary of the present invention is not intended to be construed as a The benefits and objectives, as well as a more complete understanding of the present invention, will be apparent and appreciated by the <RTIgt; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 15 is a diagram of a method for generating a die arrangement in the present invention; and a multi-overlapping product of a specific embodiment is shown in a view of the embodiment of the present invention. The stacked crystal teach produces the exemplary, exemplary process of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention is susceptible to various features which are shown in the drawings and are in the However, it is to be understood that the invention is not intended to be limited to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives, which are within the scope of the invention as defined by the appended claims. 5 + The integrated circuit and method comprising the stacked grain structure of the present invention. Although the present invention is not necessarily limited to such applications, the comments of the different views of the present invention have the best results in the context of the discussion of the examples. Consistent with an exemplary embodiment of an exemplary embodiment of the present invention, 曰4 coins are applied to a layer of plastic or a similarly spaced material layer. Application of the spacer material causes the scallop to be circumscribed with an interface region. A second die is disposed above the first die such that the spacer material is between the first and second die. The first and second die are bonded to the spacer material and separated from each other by a spacer material and an interface region. The spacer material provides structural support for the completed stacked die arrangement. ♦ Another exemplary embodiment of the invention includes two die, each die bonded to a layer of spacer material such that the spacer layer separates the two grains. The spacer material layer is substantially circumscribed with an interface region that contains air and expands between the two grains. The particular type of spacer material used is varied, but may comprise a thermoplastic (a plastic material that can be reformed many times by melting) or an adhesive such as Teflon (Tefl〇n8). In a preferred embodiment, the adhesive can be Hysol® QMI536TM or ABLESTIKTM 2025D. Teflon® is a registered trademark of Du P〇nt de Nemours and Company Corporation. 200818450 ABLESTIK trademark is National Starch Chemical Co., Ltd. (Nati〇nal
Starch and Chemical Company)的註冊商標。Hys〇l及QMI536 係為漢尚股份有限公司（Henkel Corporation)的註冊商標。 間隔材料k供結構支撐並亦藉由與界面區域外切而防 5止囊封劑進入界面區域。因此，間隔材料必需具足夠強度 用以支撐晶粒且必需充分地相關於囊封劑環繞界面區域。 例如，當施加至晶粒時，間隔材料能夠經施加用以針對相 對為薄的囊封劑具有小路徑進入界面區域（就流動性而 。）’以及針對相對為厚的一囊封劑具有較大路徑。再者， 1〇間隔材料具有足夠的結構強度，用以支撐晶粒上因熱及其 他力里所xe成的應力，並能夠在施加囊封劑的溫度下保持 結構支撐。 於一具體實施例中，界面區域係由晶粒接合至間隔材 料時於大氣中存在的氣體所組成。於該-具體實施例中， 15氣體容^晶粒因熱變化而膨脹及收縮，不致對晶粒施加過 度的力置。其他材料亦預想涵蓋於界面區域内。該-材料 之-重要特性係為材料之黏性或可彎性。理想地，材料應 /、有低‘1±或疋阿可_性用以將时體變化、熱變化而對 日日粒化加的力里減至最小。藉由讓疊積式晶粒配置，利用 20不同界面材#承叉熱變化而能夠確定所需的黏性或可彎 f生並針對曰曰粒承文破裂或相似非所欲問題確定界面材 料所而的黏或可曾性亦能夠以晶粒間不同的了⑶為一 四數力確&目為晶粒間的潛在應力係隨著TCE差異增 加而增加。 9 200818450 現參考該等圖式，第1圖係為一方塊圖圖示本發明之一 示範具體實施例的一疊積式晶粒配置的一橫截面。第i圖顯 不一第一晶粒108、一第二晶粒104、一塑膠層1〇6、一界面 區域114、接合線11〇、基板或導線架112以及囊封劑ι〇2。 5 第一及第二晶粒係為典型地執行不同功能的積體電 路。例如，第一晶粒108可為一具有—相對低的介電常數之 互補性氧化金屬半導體(CM0S)晶粒，同時第二晶粒丨〇4具 有相對高的介電常數。更特定言之，第一晶粒可為一使用 60奈米或9G奈米技術具有-低介電常數的㈤⑽晶粒。因 10此，該等晶粒就其之TCE而言具有顯著的差異性。 圖中所示層106係介於第一與第二晶粒之間。層1〇6可 為一非傳導性塑膠或是黏著性材料，其係配置位在接近疊 積式晶粒之相對表面的外部處。如此，層1〇6於晶粒間產生 一界面區域114。典型地，此間隙包含一氣體(例如，空氣 15或其他的氣體混合物）；然而，具有一低黏性及係為非傳導 性的其他物質亦能包含於界面區域114内。 於一例子中，疊積式晶粒配置係藉由一囊封劑102所圍 繞。囊封劑102—般而言較層106或界面區域114内的物質更 為堅硬。為此，較佳地，配置層1〇6用以防止囊封劑1〇2進 2〇入界面區域114，並用以減小介於層106與晶粒之邊緣間的 面積’如前頭116所示。再者，藉由施加層1〇6而能夠控制 面積116，俾便限制囊封劑1〇2覆蓋較不易受熱應力所影響 的晶粒之面積。 第2圖顯示本發明之不同具體實施例的多重疊積式晶 10 200818450 粒配置產生方法。第2圖圖示間隔材料2〇4及2〇8、晶粒2〇2 及210以及針206。 間隔材料204係為一施加至晶粒2〇2的預先形成材料。 於一例子中，間隔材料係為一熱塑性塑膠或黏著性(例如， 5 B階段環氧樹脂(B stage epoxy))材料。該材料係預先形成因 此其充分地固持其之形狀，同時配置在晶粒2〇2上。就熱塑 性塑膠而言，在熱塑性塑膠配置在第一晶粒上之後，第二 晶粒係配置位在熱塑性塑膠上。接著將熱塑性塑膠加熱用 以於晶粒與熱塑性㈣之間構成—接合。熱量亦有助於將 10熱塑性塑膠構形而更適當地圍住晶粒間的空間。就一黏著 劑而言，在黏著劑配置在第一晶粒上之後，第二晶粒係配 置位在黏著劑上。接著使用熱量或是其他方法將晶粒配置 固化，用以將晶粒接合至黏著劑。 彳任擇地，施加未經預先形成的_材料。例如，如 15圖所不，使用針2〇6將間隔材料2〇8施加至晶粒⑽。針观 施加間隔材料2_以圍住晶粒2_一部分。接著將一第 二晶粒配置在施加的間隔材料肅上，並且晶粒係接合至間 隔材料208。 使用上述的任一方法，晶粒係藉由間隔材料以及藉由 間隔材料圍住具有空氣或低黏性材料的-間隙而分離。除 圍曰曰粒之为外，能夠將未由間隔材料圍住或覆蓋 的晶粒之面積減至最小，用以降低配置於晶粒之間的囊封 劑量。 第3圖係為一視圖’圖示用以產生本發明之一示範具體 11 200818450 實施例的一疊積式晶粒配置的一示範方法。特別地，μ θ - 弟3圖 …頁示一糸列之用以產生本發明之一具體實施例的一聂 晶粒配置的步驟。 &積式 方塊302圖示將間隔材料配置在第一晶粒上。可執行不 5同的配置方法。例如，可將間隔材料預先形成為一圍住步 狀，諸如一圓圈、三角形、矩形或是其他形狀。可任擇地 可使用一針或是相似施加構件將間隔材料施加至第一曰 粒，俾便構成一圍住形狀。 曰 在施加間隔材料之後，材料可任擇地接合至第一曰 10粒，如方塊304所示。例如，能夠使用一化學反應、熱量或 壓力讓黏著劑接合。在配置第二晶粒之前或是期間，此接 合作業對於維持間隔材料之位置及形狀係為有利的。假若 由方塊304所示的接合作業並未實施或是一經完成方塊3〇4 之接合作業，則利用方塊3〇6所示的下一步驟繼續製程。 15 方塊306表示配置第二晶粒。特別地，第二晶粒經配置 致使將間隔材料定位在第一與第二晶粒之間。一般地，間 隔材料具有相對於第一晶粒之表面的一相一致高度。於一 例子中，該高度接近30微米至50微米。因此，第一與第二 晶粒經配置而相互垂直，並係隔開間隔材料之高度。 20 在方塊306中的配置作業之後，如方塊308中所示將晶 粒接合至間隔材料。可以複數之方式完成接合作業，包括 使用溫度、化學反應及壓力。接著，可任擇地將所完成的 晶粒疊積配置加以囊封，如步驟31〇所示。 僅經由圖解提供以上說明並於圖中顯示的不同具體實 12 200818450 施例’並且不應視為限定本發明。根據上述說明及圖解， 熟知此技藝之人士應可立即地確認可對本發明作不同的修 改及變化，而非完全地依循於此所圖示及說明的示範具體 實施例及應用。例如，除了CM〇S疊積式晶粒之外的應用， 能夠使用相似方法而實施。該等修改及變化並未背離於以 下申请專利範圍中所提出的本發明之確實範_。 【圖式簡單說明】Registered trademark of Starch and Chemical Company). Hys〇l and QMI536 are registered trademarks of Henkel Corporation. The spacer material k is supported by the structure and is also prevented from entering the interface region by circumscribing the interface region. Therefore, the spacer material must have sufficient strength to support the die and must be sufficiently correlated with the encapsulant surrounding the interface region. For example, when applied to a die, the spacer material can be applied to have a small path into the interfacial region (in terms of flowability for a relatively thin encapsulant) and for a relatively thick one encapsulant. Big path. Furthermore, the 1-inch spacer material has sufficient structural strength to support the stress on the die due to heat and other forces, and to maintain structural support at the temperature at which the encapsulant is applied. In one embodiment, the interfacial region is comprised of a gas present in the atmosphere when the die is bonded to the spacer material. In this embodiment, the 15 gas grains expand and contract due to thermal changes, and no excessive force is applied to the grains. Other materials are also envisioned to be included in the interface area. The important characteristic of this material is the viscosity or bendability of the material. Ideally, the material should have a low '1± or 疋Aco_ ity to minimize the force applied to the daily granulation by changing the time and heat. By arranging the stacked die, the 20 different interface materials can be used to determine the desired viscosity or bendability and determine the interface material for the rupture of the granules or similar undesired problems. The viscosity or the latitude of the film can also be different between the grains (3). The potential stress system between the grains increases with the increase of the TCE difference. 9 200818450 Reference is now made to the drawings, and FIG. 1 is a block diagram showing a cross section of a stacked die configuration of an exemplary embodiment of the present invention. The first figure shows a first die 108, a second die 104, a plastic layer 〇6, an interface region 114, a bonding wire 11A, a substrate or lead frame 112, and an encapsulant ι2. 5 The first and second die are integrated circuits that typically perform different functions. For example, the first die 108 can be a complementary metal oxide semiconductor (CMOS) die having a relatively low dielectric constant while the second die 丨〇4 has a relatively high dielectric constant. More specifically, the first die may be a (f) (10) die having a low dielectric constant using a 60 nm or 9G nanotechnology. Because of this, the grains have significant differences in terms of their TCE. The layer 106 shown is between the first and second dies. Layer 1 〇 6 can be a non-conductive plastic or an adhesive material that is disposed outside of the opposite surface of the stacked die. Thus, layer 1 〇 6 creates an interface region 114 between the dies. Typically, the gap contains a gas (e.g., air 15 or other gas mixture); however, other materials having a low viscosity and non-conductivity can also be included in the interface region 114. In one example, the stacked die configuration is surrounded by an encapsulant 102. The encapsulant 102 is generally more rigid than the material within the layer 106 or interface region 114. To this end, preferably, the layer 1 〇 6 is configured to prevent the encapsulant 1 〇 2 into 2 into the interface region 114 and to reduce the area between the layer 106 and the edge of the dies as the first 116 Show. Further, by applying the layer 1〇6, the area 116 can be controlled, and the encapsulant 1〇2 is restricted from covering the area of the crystal grains which are less susceptible to thermal stress. Figure 2 shows a method for producing a multi-overlapping product 10 200818450 particle configuration in accordance with various embodiments of the present invention. Fig. 2 shows the spacer materials 2〇4 and 2〇8, the crystal grains 2〇2 and 210, and the needle 206. The spacer material 204 is a preformed material applied to the die 2〇2. In one example, the spacer material is a thermoplastic or adhesive (eg, a 5 B stage epoxy) material. The material is formed in advance so that it sufficiently retains its shape while being disposed on the crystal grains 2〇2. In the case of a thermoplastic plastic, after the thermoplastic is disposed on the first die, the second die is disposed on the thermoplastic. The thermoplastic is then heated to form a bond between the die and the thermoplastic (4). The heat also helps to shape the 10 thermoplastics to more closely enclose the space between the grains. In the case of an adhesive, after the adhesive is disposed on the first die, the second die is disposed on the adhesive. The die configuration is then cured using heat or other means to bond the die to the adhesive. Optionally, apply unpre-formed material. For example, as shown in Fig. 15, the spacer material 2〇8 is applied to the die (10) using the needle 2〇6. The spacer material 2_ is applied to enclose a portion of the crystal grain 2_. A second die is then placed over the applied spacer material and the die bonds are bonded to the spacer material 208. Using either of the above methods, the die is separated by a spacer material and by a spacer material surrounding the gap having air or a low viscosity material. In addition to the cocoon particles, the area of the grains not surrounded or covered by the spacer material can be minimized to reduce the encapsulation dose disposed between the grains. Figure 3 is a diagram showing an exemplary method for producing a stacked die configuration of an exemplary embodiment of the present invention. In particular, μ θ - 。 3 shows a sequence of steps for producing a Nie die configuration of one embodiment of the present invention. & block 302 illustrates the placement of the spacer material on the first die. Can perform the same configuration method. For example, the spacer material can be preformed into a surrounding step, such as a circle, triangle, rectangle, or other shape. Optionally, a spacer or similar application member can be used to apply the spacer material to the first particle, which forms a surrounding shape.材料 After application of the spacer material, the material can optionally be joined to the first 10, as indicated by block 304. For example, a chemical reaction, heat or pressure can be used to bond the adhesive. This bonding is advantageous for maintaining the position and shape of the spacer material before or during the configuration of the second die. If the joining operation shown by block 304 is not implemented or the joining operation of block 3〇4 is completed, the process is continued using the next step shown in block 3〇6. Block 306 represents the configuration of the second die. In particular, the second die is configured to position the spacer material between the first and second dies. Typically, the spacer material has a uniform height relative to the surface of the first die. In one example, the height is approximately 30 microns to 50 microns. Thus, the first and second dies are configured to be perpendicular to one another and are spaced apart by the height of the spacer material. 20 After the configuration job in block 306, the grain is bonded to the spacer material as shown in block 308. Bonding can be done in a number of ways, including temperature, chemical reaction, and pressure. The completed die stack configuration can then optionally be encapsulated as shown in step 31. The above description is provided by way of illustration only and is not intended to limit the invention. Based on the above description and illustration, those skilled in the art should be able to devise various modifications and changes to the present invention, and do not fully follow the exemplary embodiments and applications illustrated and described herein. For example, applications other than CM〇S stacked dies can be implemented using similar methods. Such modifications and variations do not depart from the true scope of the invention as set forth in the scope of the claims below. [Simple description of the map]
弟1圖係為一方塊圖說明本發明之一示範具體實施例 的一疊積式晶粒配置； 第2圖係為本發明之一示範具體實施例的多重疊積式 晶粒配置產生方法；以及 第3圖係為一視圖，圖示用以產生本發明之一示範具體 實施例的一疊積式晶粒配置的一示範方法。 【主要元件符號說明】1 is a block diagram illustrating a stacked die configuration of an exemplary embodiment of the present invention; FIG. 2 is a method of generating a multi-overlapping product die configuration according to an exemplary embodiment of the present invention; And Figure 3 is a view illustrating an exemplary method for producing a stacked die configuration of an exemplary embodiment of the present invention. [Main component symbol description]
102··.囊封劑 104…第二晶粒 106…塑膠層 108…第一晶粒 no…接合線 112···基板或導線架 114·.·界面區域 116···箭頭/面積 202，210···晶粒 204，208…間隔材料 206···針 13102··. encapsulant 104...second die 106...plastic layer 108...first die no...bonding line 112···substrate or lead frame 114···interface area 116···arrow/area 202, 210··· Grain 204, 208... Spacer material 206···Needle 13