200810042 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種嵌埋有晶片之承載板結構及其製造 方法，尤指一種可改善非對稱增層所產生之板彎翹情況之 5 嵌埋有晶片之承載板結構及其製作方法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 10 (InteSratl0n)以及微型化（Miniaturization)的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由單層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connecti〇n)擴大電路板上可利用的佈線面積而 配合高電子密度之積體電路（Integrated circuh)需求。 b ’诉一般半導體裝置之製程，首先係由晶片載板製造業 2生產適用於該半導體裝置之晶片載板，如基板或導線 木。=後再將該些晶片載板交由半導體封裝業者進行置 晶、壓模、以及植球等製程。最後，方可完成用戶端所需 之電子功能之半導體裝置。期間涉及不同製造業者，因此 20於實際製造過程中不僅步驟繁瑣且界面整合不易。況且， 右客戶端欲進行變更功能設計時，其牵涉變更與整合層面 更疋複雜，亦不符合需求變更彈性與經濟效益。 另3知之半導體封裝結構是將半導體晶片黏貼於基板 頂面，進行打線接合（wire bonding)或覆晶接合（Flip chip) 5 200810042 封裝，再於基板之背面植以錫球以進行電性連接。如此， =可達到高腳數的目的。但是在更高頻使用時或高速操作 1其將因導線連接路徑過長而產生電氣特性之效能無法 提弄’而有所限制。另外，因傳統封農需要多次的連^介 5 面’相對地增加製程之複雜度。 為此，許多研究採用將晶片埋入封裝基板内，該嵌埋 於封裝基板中之晶片係可直接與外部電子元件導通，用以 縮短電性傳導路徑，並可減少訊號損失、訊號失真及提昇 高速操作之能力。 10 肷埋有晶片之承載板結構如圖1所示，包括··一載板 101，且該載板101形成有開口； 一晶片102，該晶片1〇2容 置於该開口中，且該晶片102之主動面形成有複數個電極墊 103 ; —形成於該嵌埋有晶片102之載板1〇1上，並對應顯露 出電極塾103之保護層104 ;複數個形成於電極墊1 〇3表面上 15 之金屬層1〇5;以及一形成於該承載板101及該晶片102表面 之線路增層結構10 6。其中’線路增層結構1 〇 6形成於晶片 102及載板101表面，並電性連接該載板1〇1及晶片ι〇2之電 極墊103。 目前，業界常用於嵌埋有晶片之承載板結構的載板1〇1 20 的材料為銅或 BT樹脂（Bismaleimide Triazine Resin)。然 而，以上述材料為載板101之材料時，嵌埋有晶片之承載板 結構在單面形成線路增層結構1 〇6的情況下，往往會因為線 路增層面與非增層面兩者應力不均而產生板彎翹問題，導 6 200810042 致生產不易’且其成品也會因為板彎翹過大而良率偏低、 可靠度不佳。 因此，為了降低嵌埋有晶片之承載板因單面增層而產 生的板彎翹情況，並提高生產良率，以銅或BT樹脂為材料 5 之載板已不能滿足使用要求。 【發明内容】 鑑於上述習知之缺點，本發明提供一種嵌埋有晶片之 承載板結構，包括：一第一鋁载板，具有一第一開口； 一 10第二鋁載板，具有一第二開口，且該第二開口之位置對應 該第-開口之位置；一介電層，係夾置於該第一鋁載板與 4第一鋁載板之間；一晶片，該晶片係嵌埋於該第一開口 與該第二開口中，並具有一主動面；至少-電極墊，該電 極塾係配置於該晶片之該主動面；以及至少一線路增層結 15構，該線路增層結構係配置於該第一銘載板之上表面、該 日日片之主動面與該電極塾之表面，其中，該線路增層結構 至少具有-對應於該電極塾之一導電結構，且至少一該導 電結構電性連接於該電極墊。 也就是說，有鑑於業界以銅或BT樹脂（Bismaleimide 20 Trlazlne Resin)作為嵌埋有晶片之承载板結構的載板時，承 載板在早面增層的情況下，常常產生嚴重的板彎赵情形。 本I月以紹」或「1呂合金」作為嵌埋有晶片之承 3結構的載板材料，可明顯改善板彎趣之情況，而解決 :、I ;生產k埋有晶片之承載板結構時，長久存在之問題。 7 200810042 另外，本發明除了以「鋁」<「鋁合金」作為嵌埋有 晶片之承載板結構的載板材料，來改善板彎翹情況之外。 亦可搭配不同實施方式（參閱實施例一至四），更進一步的改 善承載板的板彎翹，使承載板呈現平整之狀態。 15 20 本發明之嵌埋有晶片之承載板結構，其中，該第一銘 載板與第二銘載板之材料可為銘或銘合金，較佳係為銘合 2。另外，本發明之嵌埋有晶片之承載板結構，其中，該 弟一銘載板之上表面或下表面可選擇性的形成有一氧化銘 層。、同樣的，該第二銘載板之上表面或下表面可選擇性的 t成有-氧化銘層。該表面形成有氧化銘之第—銘載板或 銘载板可以任何氧化方式形成，較佳係以陽極氧化方 藉由表面氧化處卿叙氧化_呂複合材料載板 加載板之剛性’因此，可輪入式晶片封裝之核心 :材可進一步改善因非對稱增層結構所產生之板彎翹情 板盘第队埋有曰曰片之承載板結構’其中該第-鋁载 載板之氧油層厚度無特職制， 需要的剛性或韌性而定，而且該^ 亦盔胜茨乳化鋁層厚度的控制方法 …、特別限制，可藉由不同的氧化方法或條件達成。 載板2明之後埋有f片之承載板結構’其中’該第一紹 /、—鋁載板之厚度不限定，較佳為表面形 β線路增層結構之第—㈣板的厚度，小於第二柄 ，後埋有晶片之承載板結構尚未形:線路增層 〜略向第二銘載板之方㈣，而在形成線路； 8 200810042 _ 成結構之後，兩紹載板會因線路增層後而應力抵銷，俾使 嵌埋有晶片之承載板結構更為平整。 本發明之後埋有晶片之承載板結構，其中，該電極塾 之材質不限使用任何金屬，較佳地係為一鋁金屬或銅金屬。 5 本發明之欲埋有晶片之承載板結構，其中，該第一鋁 載板與該晶片之間、以及該第二鋁載板與該晶片之間復可 填充有一黏著材、或藉由前述夾設於兩鋁載板間之介電層 因擠壓而填充於晶片與兩鋁載板所生成之間隙中，以固 κ 該晶片於該第一開口與第二開口内。 10 本發明之嵌埋有晶片之承載板結構，其中，該線路增 層結構係包括有絕緣層、疊置於該絕緣層上之線路層、以 及至少一該導電結構，且至少一該導電結構係穿過該絕緣 層以供δ亥線路層電性連接至該絕緣層下方之線路層或電極 墊。 15 並且，該線路增層結構之絕緣層材料不限定，較佳地 係至少一選自由 ABF(Ajinomoto Build-up Film)、雙順丁醯 、j 二酸醯亞胺 /三氮阱（BT，Bismaleimide triazine)、聯二苯環丁 二烯0^112：〇叮1〇131^1^;3〇3)、液晶聚合物（1^_(1(^灿1 Polymer)、聚亞醯胺（polyimide ; ρι)、聚乙烯醚 20 (P〇ly(phenylene ether))、聚四 I 乙烯（p〇ly (她卜 fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃 纖維等材質中任一種所組成之群組。該線路層以及該導電 結構之材料不限定，較佳地係為銅、錫、鎳、鉻、鈦、銅/ 鉻合金或锡/錯合金。 9 200810042 • 本發明之嵌埋有晶片之承載板結構，復包括有複數個 焊料凸塊，且該線路增層結構中至少有一導電結構連接至 该焊料凸塊。 本發明之嵌埋有晶片之承載板結構，其中該第一鋁載 5板與第二鋁載板之氧化鋁層厚度無特別限制，視承載板所 而要的剛性或韌性而定，而且該氧化鋁層厚度的控制方法 亦無特別限制，可藉由不同的氧化方法或條件達成。 本發明之嵌埋有晶片之承載板結構，其中，該第一鋁 載板與第二鋁載板之厚度不限定，較佳為表面形成有形成 10有線路增層結構之第一铭载板的厚度，小於第二姑載板之 厚度。 另外，本發明也提供一種嵌埋有晶片之承載板之製造 方法，其步驟包括：（A)提供一第一鋁載板與一第二鋁載 板；（B)於該第一鋁載板形成一第一開口，及於該第二鋁載 15板形成-第二開口，且該第二開口之位置對應該第一開口 之位置；（B)將一晶片嵌入該第一開口與該第二開口中，其 中，該晶片之該主動面具有複數個電極墊；（c)壓合一介電 層於該第一銘載板、該第二銘載板、與該晶片之間，以固 定該第一鋁載板與該第二鋁載板，以及固定該晶片於嗜第 2〇 一開口與該第二開口中；以及P)於該第一鋁載板之上^表 面、該晶片之主動面與該電極墊之表面形成至少一線路增 層結構，其中，該線路增層結構至少具有一對應於該^ 塾之導電結構，且至少-該導電結構電性連接於該電極塾。 200810042 本發明之方法，係藉由「紹」或「銘合金」作為 有晶片之承載板結構的載板材料，可明顯改善板彎^情 況，而解決業料生產嵌埋有晶片之承载板結 ^ 存在之問題。 發明之嵌埋有晶片之㈣板之製造方法，其 + :謂合一介電層於該第一紹載板、該第二銘載板之間: 俾猎由前述夾設於兩_板間之介電層因擠壓而填充於晶200810042 IX. Description of the Invention: [Technical Field] The present invention relates to a carrier board embedded with a wafer and a method of manufacturing the same, and more particularly to a method for improving the bending of a board caused by asymmetric buildup. A carrier board structure in which a wafer is buried and a method of fabricating the same. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration degree 10 (InteSratl0n) and miniaturization (Miniturization), most active and passive components and circuit-connected circuit boards are provided, and gradually evolved from single-layer boards to multi-layer boards to make them limited. In the space, the interlayer wiring technology (Interlayer connection) is used to expand the wiring area available on the circuit board to meet the demand for integrated electrons with high electron density (Integrated Circuh). b </ </ RTI> The process of a general semiconductor device is firstly produced by a wafer carrier manufacturing 2 for a wafer carrier, such as a substrate or wire, suitable for the semiconductor device. Then, the wafer carriers are transferred to a semiconductor packager for crystallization, stamping, and ball placement. Finally, the semiconductor device for the electronic functions required by the client can be completed. During the period, different manufacturers are involved, so in the actual manufacturing process, not only the steps are cumbersome but the interface integration is not easy. Moreover, when the right client wants to change the function design, the change and integration level is more complicated, and it does not meet the elasticity of change of demand and economic benefits. Another known semiconductor package structure is to adhere a semiconductor wafer to the top surface of the substrate, perform wire bonding or Flip chip 5 200810042 package, and then implant a solder ball on the back surface of the substrate for electrical connection. In this way, = can achieve the goal of high number of feet. However, when it is used at a higher frequency or at a high speed, it is limited in that the performance of the electrical characteristics due to the long wire connection path cannot be lifted. In addition, due to the traditional closure of agriculture, it is necessary to repeatedly increase the complexity of the process. For this reason, many studies have buried the wafer in a package substrate, and the chip embedded in the package substrate can be directly connected to external electronic components to shorten the electrical conduction path and reduce signal loss, signal distortion and boost. The ability to operate at high speed. 10 肷 buried chip carrier structure shown in FIG. 1 , including a carrier 101 , and the carrier 101 is formed with an opening; a wafer 102 , the wafer 1 2 is accommodated in the opening, and the The active surface of the wafer 102 is formed with a plurality of electrode pads 103; formed on the carrier substrate 1〇1 embedded with the wafer 102, and corresponding to the protective layer 104 exposing the electrode 103; a plurality of electrodes are formed on the electrode pad 1 3 a metal layer 1〇5 on the surface 15; and a line build-up structure 106 formed on the surface of the carrier plate 101 and the wafer 102. The line build-up structure 1 〇 6 is formed on the surface of the wafer 102 and the carrier 101, and is electrically connected to the electrode pads 103 of the carrier 1〇1 and the wafer 〇2. At present, the material of the carrier 1〇1 20 which is commonly used in the carrier board structure in which the wafer is embedded is copper or BT resin (Bismaleimide Triazine Resin). However, when the above material is used as the material of the carrier 101, the carrier-embedded structure in which the wafer is embedded has a line-increasing structure 1 〇6 on one side, and the stress is not caused by both the line-increasing layer and the non-leveling layer. Both of them have a problem of bending the plate, and the guide 6 200810042 is not easy to produce, and the finished product will also have a low yield and a low reliability due to the excessive bending of the plate. Therefore, in order to reduce the warpage of the board in which the wafer-embedded board is embedded due to the one-side build-up, and to improve the production yield, the carrier board made of copper or BT resin 5 can no longer meet the requirements for use. SUMMARY OF THE INVENTION In view of the above disadvantages, the present invention provides a carrier board structure embedded with a wafer, comprising: a first aluminum carrier having a first opening; a 10 second aluminum carrier having a second Opening, and the position of the second opening corresponds to the position of the first opening; a dielectric layer is sandwiched between the first aluminum carrier and the first aluminum carrier; and a wafer is embedded In the first opening and the second opening, and having an active surface; at least an electrode pad disposed on the active surface of the wafer; and at least one line build-up layer 15 The structure is disposed on the upper surface of the first inscription board, the active surface of the dice and the surface of the electrode crucible, wherein the line build-up structure has at least one conductive structure corresponding to the electrode crucible, and at least A conductive structure is electrically connected to the electrode pad. That is to say, in view of the fact that in the industry, copper or BT resin (Bismaleimide 20 Trlazlne Resin) is used as a carrier plate in which a wafer-bearing carrier structure is embedded, the carrier plate often has a serious plate bending when it is layered on the early surface. situation. This I month, "Yu" or "1 Lu alloy" as the carrier material embedded in the 3 structure of the wafer can significantly improve the bending of the board, and solve: I; the production of the carrier plate structure with the wafer embedded When there is a long-standing problem. 7 200810042 In addition, the present invention not only uses "aluminum" <"aluminum alloy" as a carrier material for embedding a wafer-bearing carrier structure to improve the bending of the board. It can also be combined with different embodiments (see Embodiments 1 to 4) to further improve the bending of the board of the carrier board so that the carrier board is flat. 15 20 The substrate-embedded carrier structure of the present invention, wherein the material of the first inscription board and the second inscription board may be an alloy of Ming or Ming, preferably a Ming 2. Further, in the wafer carrier-embedded board structure of the present invention, the upper surface or the lower surface of the board is selectively formed with an oxide layer. Similarly, the upper surface or the lower surface of the second inscription plate can be selectively formed into an oxidized layer. The surface is formed with the oxidation of the first - the inscription plate or the inscription plate can be formed by any oxidation method, preferably by anodizing by the surface oxidation of the oxidation of the _ _ composite material carrier plate loading plate rigidity ', therefore, The core of the wheel-in-chip package: the material can further improve the plate bending plate caused by the asymmetric layer-added structure. The carrier plate structure in which the raft is buried, the oxygen of the first-aluminum carrier plate The thickness of the oil layer is not limited to the special requirements, the rigidity or toughness required, and the control method of the thickness of the emulsified aluminum layer of the helmet is particularly limited, and can be achieved by different oxidation methods or conditions. After the carrier board 2 is embossed, the load-bearing plate structure in which the f-piece is embedded is 'the thickness of the first-----aluminum carrier plate is not limited, and preferably the thickness of the (-)th plate of the surface-shaped β-line layer-increasing structure is smaller than The second handle, the carrier plate structure with the buried chip is not yet shaped: the line is added to the side of the second inscription board (4), and the line is formed; 8 200810042 _ After the structure, the two boards will increase due to the line After the layer, the stress is offset, so that the structure of the carrier plate embedded with the wafer is more flat. The present invention is embedded with a carrier structure of the wafer, wherein the material of the electrode is not limited to any metal, and is preferably an aluminum metal or a copper metal. The carrier board structure of the present invention, wherein the first aluminum carrier board and the wafer, and the second aluminum carrier board and the wafer are filled with an adhesive material, or by the foregoing A dielectric layer interposed between the two aluminum carrier plates is filled in the gap formed between the wafer and the two aluminum carrier plates by pressing to fix the wafer in the first opening and the second opening. The wafer-embedded carrier structure of the present invention, wherein the wiring build-up structure comprises an insulating layer, a wiring layer stacked on the insulating layer, and at least one of the conductive structures, and at least one of the conductive structures The insulating layer is passed through to electrically connect the circuit layer or the electrode pad under the insulating layer. 15, the insulating layer material of the line build-up structure is not limited, and preferably at least one selected from the group consisting of ABF (Ajinomoto Build-up Film), biscision oxime, j bisphosphonium imide / triazo trap (BT, Bismaleimide triazine), diphenylcyclobutadiene 0^112: 〇叮1〇131^1^; 3〇3), liquid crystal polymer (1^_(1(^灿1 Polymer), poly-decylene) Polyimide; ρι), polyvinyl ether 20 (P〇ly (phenylene ether)), polytetraethylene (p〇ly (her fluoroethylene)), aromatic nylon (Aramide), epoxy resin and glass fiber A group consisting of the circuit layer and the material of the conductive structure is not limited, and is preferably copper, tin, nickel, chromium, titanium, copper/chromium alloy or tin/stagger alloy. 9 200810042 • The present invention The carrier board structure embedded with the chip further includes a plurality of solder bumps, and at least one conductive structure of the line build-up structure is connected to the solder bumps. The wafer-mounted carrier board structure of the present invention, wherein the The thickness of the aluminum oxide layer of the first aluminum carrier 5 plate and the second aluminum carrier plate is not particularly limited, depending on the carrier plate The method of controlling the thickness of the aluminum oxide layer is not particularly limited, and can be achieved by different oxidation methods or conditions. The wafer-bearing carrier structure embedded in the present invention, wherein the first aluminum carrier The thickness of the plate and the second aluminum carrier is not limited, and preferably the surface is formed with a thickness of the first inscription plate forming the line-added structure, which is smaller than the thickness of the second auger plate. In addition, the present invention also provides a a manufacturing method of a carrier board embedded with a wafer, the method comprising: (A) providing a first aluminum carrier and a second aluminum carrier; (B) forming a first opening in the first aluminum carrier, and Forming a second opening in the second aluminum carrier 15 and the position of the second opening corresponds to the position of the first opening; (B) embedding a wafer in the first opening and the second opening, wherein The active surface of the wafer has a plurality of electrode pads; (c) pressing a dielectric layer between the first inscription board, the second inscription board, and the wafer to fix the first aluminum carrier board and The second aluminum carrier plate and the fixing of the wafer to the second opening and the And a surface of the first aluminum carrier; the active surface of the wafer and the surface of the electrode pad form at least one line build-up structure, wherein the line build-up structure has at least one corresponding to The conductive structure of the conductive structure, and at least - the conductive structure is electrically connected to the electrode 塾. 200810042 The method of the present invention is a carrier material having a wafer carrier structure by using "Shao" or "Ming Alloy". The problem of the bending of the board can be obviously improved, and the problem of the production of the carrier board embedded with the wafer is solved. The invention discloses a method for manufacturing a (four) board embedded with a wafer, wherein: + is a dielectric layer between the first carrier board and the second name carrier board: 俾 hunting is sandwiched between the two boards The dielectric layer is filled in the crystal by extrusion
片與兩銘載板所生成之間隙中，以固定該晶片於該第一= 口與第二開口内。 10 #树明之嵌埋有晶片之承載板之製造方法，其中，該 第一鋁載板與第二鋁载板之材料可為鋁或鋁合金，較佳係 為銘合金。另外，本發明之嵌埋有晶片之承載板之製造方 法-中，其中，该第一铭載板之上表面或下表面可選擇 性的形成有一氧化叙層。同樣的，該第二铭載板之上表面 15或下表面可選擇性的形成有一氧化紹層。該表面形成^氧 化鋁之第一鋁載板或第二鋁載板可以任何氧化方式形成， 》較佳係以陽極氧化方式形成。藉由表面氧化處理形成之氧 化鋁/鋁複合材料載板可增加載板之剛性，因此，可作為嵌 入式晶片封裝之核心基材可進一步改善因非對稱增層所產 20 生之板彎翹情況。 本發明之嵌埋有晶片之承載板之製造方法，其中，該 電極墊之材質不限使用任何金屬，較佳地係為一鋁金屬或 銅金屬。 11 200810042 之製造方法，其中，在 於該氧化鋁載板、該晶 本發明之嵌埋有晶片之承載板 製造該線路增層結構之步驟係為： 片之主動面、與該電極墊之表面形志 ❿成一絕緣層，且使該絕 緣層形成複數個絕緣層開口，Α中$小 ^ Λ ^ a 八甲至少一絕緣層開口係對 應於該晶片之該電極墊位置；於兮p^ b 且 ％ 4、纟巴緣層及該絕緣層開口 形成一圖案化阻層 口，其中，至少一 ，使該圖案化阻層形成複數個阻層開 阻層開口係對應至該晶片之該電極塾之 位置；於該複數個阻層開口電鍍_層電鑛金屬&;以及移 10 除該圖案化阻層，#中該電鍍金屬層至少包含有_線路層 及一導電結構。 曰 本發明之嵌埋有晶片之承載板之製造方法，其中，在 製造邊線路增層結構之步驟中，該絕緣層之材料不限定， 較佳係至少一選自由ABF(Ajinomoto Build-up Film)、雙順 丁 一 8夂 i&亞胺 /二氮拼（BT，Bismaleimide triazine)、聯二苯 15 環 丁二烯（benzocylobutene ; BCB)、液晶聚合物（Uquid Crystal P〇lymer)、聚亞醯胺（p〇lyimide; ρι)、聚 乙烯醚（Poly(phenylene ether))、聚四氟乙烯（poly (tetra- fluoroethylene))、芳香尼龍（Araniide)、環 氧樹脂以及玻璃纖維等材質中任一種所組成之群 20 組。 本發明之嵌埋有晶片之承載板之製造方法，其中，在製 造該線路增層結構之步驟中，該電鍍金屬層之材料並無特 殊限制，較佳地係為銅、錫、鎳、鉻、鈀、鈦、錫/鉛或其 合金，更佳地，係為鋼。 12 200810042 人+發明再提供-種嵌埋有晶片之承載板之 壓=步4包/⑷ί供一第-銘載板與-第二銘載板二B) ⑹於該複合銘載板形成-開口；⑼將-晶片礙：並固 疋於该開口中’其中’該晶片之主動面具有複數 以及⑻於該第—㈣板之上表面、該晶片之主㈣^該 :::::::::至少一線路增層結構，其中，該線路增 a" 夕/、有一對應於該電極墊之導電結構，且至小一 泫導電結構電性連接於該電極墊。 本發明之方法’係藉由「鋁」或「鋁人会你炎山 有晶片之承載板結構的載板材料，可明顯：善板弯二； 況’而解決業界於生產傲埋有晶片之承載板結構時2 存在之問題。 长久 15 本赉明之嵌埋有晶片之承載板之製造方法，其中，+ 驟（D)將-晶片|人並@定於該開卩巾後，復人 材藉以固定該晶片。 者 ★本發明之喪埋有晶片之承載板之製造方法，其中，該 第一紹載板與第二銘載板之材料可為铭或紹合金，較佳係 2〇為1呂合金。另外，本發明之㈣有晶片之承载板之製造方 ’:中其中’該第-鋁载板之上表面或下表面可選擇 性的形成有一氧化銘層。同樣的，該第二紹載板之上表面 或下表面可選擇性的形成有一氧化鋁層。該表面形成有氧 化鋁之第一鋁載板或第二鋁載板可以任何氧化方式形成， 13 200810042 .校佳係以陽極氧化方式形成。藉由表面氧化處理形成之氧 化鋁/鋁複合材料載板可增加載板之剛性，因此，可作為嵌 入式晶片封裝之核心基材可進一步改善因非對稱增層所產 生之板彎翹情況。 5 本發明之嵌埋有晶片之承載板之製造方法，其中，嗜 電極墊之材質不限使用任何金屬，較佳地係為一紹金屬= 銅金屬。 本發明之嵌埋有晶片之承載板之製造方法，其中，在 ' 製造該線路增層結構之步驟係為：於該氧化鋁載板、該晶 10片之主動面、與該電極墊之表面形成一絕緣層，且使該絕 緣層形成複數個絕緣層開口，其中至少一絕緣層開口係對 應於該晶片之該電極墊位置；於該絕緣層及該絕緣層開口 形成一圖案化阻層，使該圖案化阻層形成複數個阻層開 口，其中，至少一阻層開口係對應至該晶片之該電極墊之 15位置，於該複數個阻層開口電鍍一層電鍍金屬層；以及移 除該圖案化阻層，其中該電鍍金屬層至少包含有一線路層 j 及一導電結構。 曰 本發明之嵌埋有晶片之承載板之製造方法，其中，在 製造該線路增層結構之步驟中，該絕緣層之材料不限定， 20較佳係至少一選自由ABF(Ajinomoto Build-up Film)、雙順 丁醯二酸醯亞胺/三氮阱（BT，Bismaleimide triazine)、聯二苯 環 丁二烯（benZOCyl〇butene ; BCB)、液晶聚合物（LiquidThe gap between the sheet and the two mounting plates is used to fix the wafer in the first opening and the second opening. The manufacturing method of the carrier plate in which the wafer is embedded, wherein the material of the first aluminum carrier and the second aluminum carrier may be aluminum or an aluminum alloy, preferably an alloy. Further, in the method of manufacturing a wafer-embedded carrier plate of the present invention, the upper surface or the lower surface of the first inscription plate is selectively formed with an oxidized layer. Similarly, a surface layer 15 or a lower surface of the second inscription plate may be selectively formed with a layer of oxide. The first aluminum carrier or the second aluminum carrier on which the surface is formed of aluminum oxide may be formed by any oxidation, and is preferably formed by anodization. The alumina/aluminum composite carrier plate formed by surface oxidation treatment can increase the rigidity of the carrier plate. Therefore, it can be used as the core substrate of the embedded chip package to further improve the bending of the 20-year-old plate produced by the asymmetric layering. Happening. The method for manufacturing a wafer-embedded carrier plate according to the present invention, wherein the material of the electrode pad is not limited to any metal, and is preferably an aluminum metal or a copper metal. The manufacturing method of the method of the invention, wherein the step of manufacturing the line build-up structure of the alumina carrier plate and the wafer-embedded carrier plate of the present invention is: an active surface of the sheet, and a surface shape of the electrode pad The insulating layer is formed into an insulating layer, and the insulating layer is formed into a plurality of insulating layer openings, wherein at least one insulating layer opening corresponds to the position of the electrode pad of the wafer; And the opening of the insulating layer is formed by a patterning barrier layer, wherein at least one of the patterned resist layer forms a plurality of resistive layer opening layers corresponding to the electrode of the wafer Positioning the electroplated metal layer in the plurality of resist layers and removing the patterned resist layer, wherein the electroplated metal layer comprises at least a layer of a circuit and a conductive structure. The method for manufacturing a wafer-embedded carrier sheet according to the present invention, wherein the material of the insulating layer is not limited in the step of fabricating the edge-providing layer structure, and preferably at least one selected from the group consisting of ABF (Ajinomoto Build-up Film) ), bis, bis, bis, BT, Bismaleimide triazine, benzocylobutene (BCB), liquid crystal polymer (Uquid Crystal P〇lymer), poly Any of the materials such as p〇lyimide (ρι), polyvinyl (phenylene ether), poly(tetra-fluoroethylene), aromatic nylon (Araniide), epoxy resin, and glass fiber. A group consisting of 20 groups. The method for manufacturing a wafer-embedded carrier sheet according to the present invention, wherein the material of the electroplated metal layer is not particularly limited in the step of fabricating the wiring build-up structure, and is preferably copper, tin, nickel, chromium. , palladium, titanium, tin/lead or alloys thereof, more preferably, steel. 12 200810042 Person + invention re-provided - the pressure of the carrier plate embedded with the wafer = step 4 package / (4) ί for a first - name carrier plate and - second name carrier plate two B) (6) formed on the composite name carrier plate - Opening (9) the wafer is: and is fixed in the opening 'where the active surface of the wafer has a plurality and (8) the surface above the first (four) plate, the main (four) of the wafer ^:::::: ::: at least one line build-up structure, wherein the line is increased by a ", and there is a conductive structure corresponding to the electrode pad, and the conductive structure is electrically connected to the electrode pad. The method of the present invention is based on the "aluminum" or "aluminum man will have a carrier material for the carrier board structure of Yanshan, and it can be clearly: good board bending two; condition" to solve the industry's production of wafers There is a problem in the structure of the carrying board. 2. The manufacturing method of the carrier board in which the wafer is embedded in the long-term 15th, wherein the + (D) will be - the wafer|person and the @ 定 后 , Fixing the wafer. The method for manufacturing a carrier plate for burying a wafer according to the present invention, wherein the material of the first carrier plate and the second name carrier plate may be Ming or Shao alloy, preferably 2 is 1 In addition, in the fourth aspect of the present invention, in the manufacturing method of the carrier plate of the wafer, the upper surface or the lower surface of the first aluminum carrier may be selectively formed with an oxidized layer. Similarly, the second An aluminum oxide layer may be selectively formed on the upper surface or the lower surface of the carrier. The first aluminum carrier or the second aluminum carrier on which the surface is formed may be formed by any oxidation, 13 200810042. Formed by anodization, formed by surface oxidation treatment The aluminum/aluminum composite carrier can increase the rigidity of the carrier. Therefore, it can be used as the core substrate of the embedded chip package to further improve the bending of the board caused by the asymmetric layering. The manufacturing method of the carrier plate of the wafer, wherein the material of the electrode pad is not limited to any metal, and preferably is a metal = copper metal. The manufacturing method of the carrier plate embedded with the wafer of the present invention, wherein The step of manufacturing the line build-up structure is: forming an insulating layer on the alumina carrier, the active surface of the crystal 10, and the surface of the electrode pad, and forming the insulating layer to form a plurality of insulating layer openings, At least one of the insulating layer openings corresponds to the electrode pad position of the wafer; a patterned resist layer is formed on the insulating layer and the insulating layer opening, so that the patterned resist layer forms a plurality of resistive layer openings, wherein at least one The resist opening corresponds to the position of the electrode pad of the wafer, and the plating layer is plated with a plating metal layer; and the patterned resist layer is removed, wherein the plating metal layer is at least The invention comprises a circuit layer j and a conductive structure. The method for manufacturing a chip-embedded carrier plate according to the present invention, wherein in the step of manufacturing the line build-up structure, the material of the insulating layer is not limited, 20 is preferably At least one selected from the group consisting of ABF (Ajinomoto Build-up Film), bis(Bismaleimide triazine), biphenyl benzene butadiene (BCB), liquid crystal polymerization Liquid
Crystal P〇lymer)、聚亞醯胺（p〇lyimide; PI)、聚 乙烯醚（Poly(phenylene ether))、聚四氟乙烯（p〇ly 200810042 (tetra- fluoroethylene)、、竑 ^ .. 香尼龍（Aramide)、？财 虱樹脂以及玻璃纖維等材 ）％ 組。 T貝中任一種所組成之群 本發明之嵌埋有晶片之层番4 ^ , 乃之承载板之製造方法，i中，/ k該線路增層結構之步驟中，該電 ς 在 特殊限制，較佳地係為銅、锡：s材枓亚無 其合金，更佳地，係為鋼。錄、鉻，、鈦、錫/叙或 户 Η 【實施方式】 10 實施例1 言月參閱圖2a至2d，係為本實施例之嵌埋有 板結構製法之剖面示意圖。 如圖2a所示，首先提供_盆 ^ ^ X , 捉狄弟一鋁載板1〇與一第二鋁載 15 板11。該第一銘載板10與第二銘載板u各形成有一第—開 口 12與第二開口 13’並且’該第二開口之位置亦對應該第 一開口之位置。 隨之，如圖2b所示，然後，提供一介電材料於該第一 鋁載板10、與該第二鋁載板丨丨之間，然後將一已完成晶圓 積體電路製程並切割成型之晶片21嵌埋入第一開口 12與第 20 二開口 13中再施以壓合。其中，晶片21的主動面22上具有 複數個電極墊23，此電極墊23之材料為鋼。此介電層14在 壓合的過程中，介電層14會由該第一銘載板1〇、與該第二 铭載板11之間溢出’使晶片21固定於第一開口 12與第二開 口 13中’同時固定該第一銘載板1 〇與該第二銘載板〗丨。最 15 200810042 • 後形成一介電層14於該第一鋁載板1〇、該第二鋁載板u、 與該晶片21之間，其結構如圖2c所示。在本實施例中，晶 片21之非主動面24裸露有利於晶片散熱。 另外，在本實施例中，第一鋁載板1〇的厚度小於 5第二鋁載板11的厚度（D2)。所以，嵌埋有晶片之承載板結 構尚未形成線路增層結構31之前（如圖2C所示），該承載板會 略向下彎翹。 元成上述步驟後，如圖2d所示，於第一銘载板之上 表面15、晶片21的主動面22、與電極墊23表面形成一線路 10 增層結構31。此線路增層結構31之形成方法如圖3所示，於 第一銘載板11之下表面15、晶片21的主動面22、與電極墊 23表面形成一絕緣層32，此絕緣層32之材料為 ABF(Ajinomoto Build-up Film)材料，並以雷射鑽孔於該絕 緣層32形成複數個絕緣層開口 33，其中至少一絕緣層開口 15 對應於晶片21之電極墊23位置，惟當利用雷射鑽孔的技術 時，復需進行除膠渣（De-smear)作業以移除因鑽孔所殘留於 該介電層開口内的膠渣。然後，於絕緣層32上形成圖案化 阻層34，該圖案化阻層34以曝光、顯影方式形成複數個阻 層開口 35，並且至少一阻層開口 35係對應至該晶片21之電 20 極墊23之位置。再於該複數個阻層開口 35電鍍一層電鍍金 屬層36 ;以及移除該阻層34，此線路增層結構3 1可使用增 層技術依所需要之層數層疊上去製作多層之結構。圖2(1所 示之線路增層結構31係使用增層技術依所需要之層數層疊 上去製作多層之結構，其中，該電鍍金屬層36包含有線路 16 200810042 • 層37及與晶片21之電極墊23連接之導電結構38。 最後，再於該增層結構31表面形成圖案化防焊層，並 ^該圖案化防焊層顯露出增層結構31之電性連接墊處形成 稷數個焊料凸塊39,即並完成本實施例之嵌埋有晶片之承 5 載板。 本實施例之嵌埋有晶片之承載板結構係為單面增層， 口此肷埋有晶片之承載板結構尚未形成線路增層結構3 ^ 之前（如圖2c所示）會略向下彎翹，而在形成線路增成結構μ 之後（如圖2d所示），彎翹會扳回，形成平整之 1。承載板結構。 片之 實施例二 請參閱圖4a至4d，係為本實施例之嵌埋有晶片之承载 板結構製法之剖面示意圖。 15 如圖4a所示，首先提供一第一鋁載板40與一第二鋁載 板41。再提供一介電材料於該第一鋁載板與一第二鋁載 ^ 板41之間，並施以壓合。藉此，介電層42會固定該第一鋁 載板40與一第二鋁載板41，而形成一複合載板43。 隨之，如圖4b所示，爾後於該複合載板43形成一貫穿 20開口 44。然後，將一已完成晶圓積體電路製程並切割成型 之晶片21嵌埋入複合載板43之開口料中。此晶片21，Crystal P〇lymer), polyplyimide (PI), poly(phenylene ether), polytetrafluoroethylene (p〇ly 200810042 (tetra-fluoroethylene), 竑^.. Nylon (Aramide), financial resin and fiberglass (%). A group consisting of any of the T-shells of the present invention is a method for manufacturing a carrier layer in which a wafer is embedded, and in the step of adding a layer structure in the circuit of i, the power is limited in a special manner. Preferably, it is copper, tin: s material, no alloy, and more preferably steel. Recording, Chromium, Titanium, Tin/Symbol or Embodiments [Embodiment] 10 Embodiment 1 Referring to Figures 2a to 2d, a schematic cross-sectional view of a method for embedding a plate structure of the present embodiment is shown. As shown in Fig. 2a, first, a basin of ^ ^ X is provided, and a second aluminum carrier plate 11 and a second aluminum carrier 15 plate 11 are captured. The first inscription carrier 10 and the second inscription carrier u are each formed with a first opening 12 and a second opening 13' and the position of the second opening also corresponds to the position of the first opening. Then, as shown in FIG. 2b, a dielectric material is then provided between the first aluminum carrier 10 and the second aluminum carrier, and then a completed wafer integrated circuit process and cutting is performed. The molded wafer 21 is embedded in the first opening 12 and the 20th opening 13 and then pressed. The active surface 22 of the wafer 21 has a plurality of electrode pads 23, and the material of the electrode pads 23 is steel. During the pressing process of the dielectric layer 14, the dielectric layer 14 is caused to overflow between the first inscription board 1 and the second inscription board 11 to fix the wafer 21 to the first opening 12 and the first In the two openings 13 'the first name carrier board 1 〇 and the second name carrier board 固定 are fixed at the same time. Most 15 200810042 • A dielectric layer 14 is formed between the first aluminum carrier 1 , the second aluminum carrier u , and the wafer 21 , and its structure is as shown in FIG. 2 c . In this embodiment, the inactive surface 24 of the wafer 21 is exposed to facilitate heat dissipation from the wafer. Further, in the present embodiment, the thickness of the first aluminum carrier 1 小于 is smaller than the thickness (D2) of the second aluminum carrier 11 . Therefore, before the carrier-embedded structure in which the wafer is embedded has not yet formed the line build-up structure 31 (as shown in Fig. 2C), the carrier plate is slightly bent downward. After the above steps, as shown in Fig. 2d, a line 10 buildup structure 31 is formed on the surface 15 of the first inscription board, the active surface 22 of the wafer 21, and the surface of the electrode pad 23. The method for forming the line build-up structure 31 is as shown in FIG. 3, and an insulating layer 32 is formed on the lower surface 15 of the first inscription board 11, the active surface 22 of the wafer 21, and the surface of the electrode pad 23. The material is an ABF (Ajinomoto Build-up Film) material, and a plurality of insulating layer openings 33 are formed by laser drilling on the insulating layer 32, wherein at least one insulating layer opening 15 corresponds to the position of the electrode pad 23 of the wafer 21, When using the technology of laser drilling, a de-smear operation is required to remove the slag remaining in the opening of the dielectric layer due to the drilling. Then, a patterned resist layer 34 is formed on the insulating layer 32. The patterned resist layer 34 forms a plurality of resistive openings 35 in an exposure and development manner, and at least one resist opening 35 corresponds to the electric pole 20 of the wafer 21. The position of the pad 23. Further, a plurality of resistive layer openings 35 are plated with an electroplated metal layer 36; and the resist layer 34 is removed, and the line build-up structure 31 can be laminated to form a multi-layer structure using a layering technique according to a desired number of layers. The circuit build-up structure 31 shown in FIG. 2 is formed by stacking layers according to the required number of layers using a build-up technique, wherein the plated metal layer 36 includes the line 16 200810042 • the layer 37 and the wafer 21 The conductive pad 38 is connected to the conductive pad 38. Finally, a patterned solder resist layer is formed on the surface of the build-up structure 31, and the patterned solder resist layer exposes a plurality of electrical connection pads of the build-up structure 31. The solder bumps 39, that is, the carrier plates embedded with the wafers of the embodiment are completed. The carrier-embedded board structure embedded with the wafers in this embodiment is a single-sided build-up layer, and the carrier board of the wafer is buried therein. The structure has not yet formed the line build-up structure 3 ^ before (as shown in Figure 2c) will bend slightly downward, and after forming the line build-up structure μ (as shown in Figure 2d), the bend will be pulled back to form a flat 1. Carrying board structure. Embodiment 2 of the chip, please refer to FIG. 4a to FIG. 4d, which are schematic cross-sectional views showing the manufacturing method of the embedded carrier board of the embodiment. 15 As shown in FIG. 4a, a first aluminum is first provided. a carrier 40 and a second aluminum carrier 41. A dielectric material is further provided The first aluminum carrier plate and the second aluminum carrier plate 41 are pressed together, whereby the dielectric layer 42 fixes the first aluminum carrier plate 40 and the second aluminum carrier plate 41. A composite carrier 43 is formed. Accordingly, as shown in FIG. 4b, a through opening 20 is formed in the composite carrier 43. Then, a wafer 21 having completed the wafer integrated circuit process and being cut and formed is embedded. Buried into the opening material of the composite carrier 43. This wafer 21,
曰 Q 片22的主動面22上具有複數個電極墊23，此電極墊之材料 為銅。接著，將黏著材25填入複合載板43與晶片21之間的 空隙，使晶片21固定於複合載板43的開口 44中，其結構如 17 200810042 •圖4c。其中該黏著材25可為環氧樹酯。而在本實施例中， 晶片21之非主動面24裸露有利於晶片散熱。 另外，在本實施例中，第一鋁载板4〇的厚度⑴丨）小於 第二鋁載板41的厚度（D2)。所以，嵌埋有晶片之承載板社 5構尚未形成線路增層、结構31之前(如圖4c所示），該承載板^ 略向下彎翹。 曰 完成上述步驟後，如圖4d所示，於第一鋁載板扣之上 表面45、晶片21的主動面22、與電極墊23表面形成一線路 增層結構31。此線路增層結構31包含有線路層”及與晶片 1〇 21之電極墊23連接之導電結構38，其形成方法與實施例一 相同。最後，再於該增層結構31表面形成圖案化防焊層， 並於該圖案化防焊層顯露出增層結構31之電性連接塾處形 成複數個焊料凸塊39,即並完成本實施例之嵌埋有晶片之 承載板。 15 本實施例之嵌埋有晶片之承載板結構係為單面增層， 因此，嵌埋有晶片之承載板結構尚未形成線路增層結構31 之刖（如圖4c所不）會略向下彎赵，而在形成線路增成結構η 之後3 Μ έ扳回，形成平整之嵌埋有晶片之承載板結構。 20 實施例三 本見施例之敗埋有晶片之承載板之製造方法與實施例 非兩相似⑨了第_銘載板與第二铭載板的上表面與下 表面都已、、工過氧化各开)成有一氧化銘層之外，其餘步轉與 實施例一大致相同。 200810042 晶片之承載 請參_5a至5e，係為本實施例之嵌埋有 板結構製法之剖面示意圖。 如圖Sa所示，首先接供 ,,ςι ^卜 杈仏弟一鋁载板5〇與一第二鋁載 Γ進载板50與第二㈣板51置於-電解槽 上表面：矣使第一紹載板50與—第二銘載板51之 中===氧化形成氧化㈣56，且兩層氧化㈣ 中間自“地夾置有-紹層57。在本實施例中，第— 10 15 20 第^載板51係置於—電解槽中，進行陽極氧化反 應，並藉由調整陽極氧化時間，來控制氧化_56之厚度。 然後，如圖5b所示，於該第一銘載板5〇與第二銘载板 叫形成有-第-開Π52與第二開⑶，並且，該第二開 口之位置亦對應該第一開口之位置。 隨之，如圖Μ示，。然;後，提供一介電材料於該第 鋁載板50、與该第二鋁載板51之間，然後將一已完成晶 圓積體電路製程並切割成型之晶片21嵌埋入第一開口 Μ盥 第二開口 53中再施以壓合。其中，晶片。的主動面22上工 有複數個電極墊23，此電極塾之材料為銅。此介電層邮 壓合的過程中’介電層54會由該第一鋁載板5〇、與該第二 鋁载板51之間溢出，使晶片21固定於第一開口 ^與第二開 口 53中’同a夺固定該第一紹載板5〇與該第二紹載板^。最 後形成一介電層54於該第一鋁載板5〇、該第二鋁載板51、 與該晶片21之間，其結構如圖5d所示。在本實施例中，晶 片21之非主動面24裸露有利於晶片散熱。在本實施例中， 第一鋁載板50的厚度（D1)等於第二鋁載板51的厚度（D2)。 19 200810042 - 元成上述步驟後，如圖5e所示，於第一銘載板5〇之上 表面55、晶片21的主動面22、與電極墊23表面形成一線路 增層結構31，包含有線路層37及與晶片21之電極墊以連接 之導電結構38，其形成方法與實施例一相同。最後，再於 5該增層結構31表面形成圖案化防焊層，並於該圖案化防焊 層顯露出增層結構31之電性連接墊處形成複數個焊料凸塊 39，即並完成本實施例之嵌埋有晶片之承載板。 由於第一鋁載板50與第二鋁載板51均以氧化方式形成 有氧化鋁層56(氧化鋁為陶瓷材料），因此，可增加第一鋁載 10板5〇與第二鋁載板51的剛性。此故，雖然本實施例之嵌埋 有晶片之承載板結構係為單面增層，依然可以形成平整之 甘欠埋有晶片之承載板結構。 實施例四 15 本實施例之嵌埋有晶片之承載板之製造方法與實施例 -非常相似，除了第-㈣板與第二銘載板的上表面斑下 ，表面都已經過氧化各形成有一氧化銘層之外，其餘步驟與 實施例二大致相同。 請參閱圖6a至6d，係為本實施例之嵌埋有晶片之承載 2〇 板結構製法之剖面示意圖。 如圖6a所示，首先提供一第一鋁載板6〇與一第二鋁載 板61。將此第一鋁載板6〇與第二鋁載板6ι置於一電解槽 中，進行氧化反應，使第一銘載板6〇與一第二紹載伽: t表面與下表面均氧化形成氧化鋁層66，且兩層氧化㈣ 25巾間自然地夾置有—銘層67。在本實施例中，第—銘載板 20 200810042 -60與H載板61係置於—電解槽中，進行陽極氧化反 應，並藉由調整陽極氧化時間，來控制氧化鋁層“之厚度。 然後’如圖6b所示’爾後於該複合載板63上形成一貫 穿開口64。然後，將一已完成晶圓積體電路製程並切割成 5型之晶片21嵌埋入複合載板43之開口 64中。此晶片21，在 晶片22的主動面22上具有複數個電極墊23，此電極墊之材 料為銅。接著，將黏著材25填入複合載板63與晶片Μ之間 的空隙，使晶片21固定於複合載板63的開口料中，其結構 如圖6c。其中該黏著材25可為環氧樹g|。而在本實施例、;， 1〇晶片21之非主動面24裸露有利於晶片散熱。在本實施例 中’第-㈣板60的厚度（D1)等於第二㈣板6() (D2)。 完成上述步驟後，如圖6d所示，於第一紹載板1〇之上 表面…晶片21的主動面22、與電極塾⑽面形成一線路 15增層結構31 ’包含有線路層37及與晶片21之電極塾^連接 之導電結構38，其形成方法與實施例一相同。最後，再於 ，該增層結構31表面形成圖案化防焊層，並於該圖案化防焊 層顯露出增層結構31之電性連接塾處形成複數個焊料凸塊 39，即並完成本實施例之嵌埋有晶片之承載板。 扣 纟於第呂載板6〇與第二㈣板61均以氧化方式形成 有氧化銘層66(氧化紹為冑究材料），因此，可增加第一銘截 板6曰〇與第二銘載板61的剛性。此故，雖然本實施例之後埋 有曰a片之承載板結構係為單面增層，依然可以形成平整之 嵌埋有晶片之承載板結構。 21 200810042 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以中請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖⑽係為習知嵌埋有晶片之承載板之電性連接結構之剖The active surface 22 of the 曰 Q sheet 22 has a plurality of electrode pads 23, the material of which is copper. Next, the adhesive 25 is filled into the gap between the composite carrier 43 and the wafer 21 to fix the wafer 21 in the opening 44 of the composite carrier 43 as shown in Fig. 7 200810042 • Fig. 4c. Wherein the adhesive material 25 can be an epoxy resin. In the present embodiment, the inactive surface 24 of the wafer 21 is exposed to facilitate heat dissipation from the wafer. Further, in the present embodiment, the thickness (1) 丨) of the first aluminum carrier 4〇 is smaller than the thickness (D2) of the second aluminum carrier 41. Therefore, the carrier board embedded with the wafer has not formed a line build-up layer before the structure 31 (as shown in Fig. 4c), and the carrier board is slightly bent downward.曰 After the above steps are completed, as shown in FIG. 4d, a line build-up structure 31 is formed on the surface 45 of the first aluminum carrier, the active surface 22 of the wafer 21, and the surface of the electrode pad 23. The line build-up structure 31 includes a circuit layer and a conductive structure 38 connected to the electrode pad 23 of the wafer 1 21, and the formation method is the same as that of the first embodiment. Finally, a patterning prevention is formed on the surface of the build-up structure 31. The solder layer is formed, and a plurality of solder bumps 39 are formed at the electrical connection of the patterned solder resist layer to expose the build-up structure 31, that is, the carrier board embedded with the wafer of the embodiment is completed. The carrier board structure in which the wafer is embedded is a single-sided build-up layer. Therefore, the structure of the carrier board in which the wafer is embedded has not yet formed the line build-up structure 31 (not shown in FIG. 4c), and the curve is slightly bent downward. After the formation of the line addition structure η, 3 Μ έ is pulled back to form a flat carrier-embedded board structure. 20 Embodiment 3 The manufacturing method and embodiment of the carrier board with the wafer buried in the embodiment are not two. Similarly, the first step and the lower surface of the first and second inscription plates have been formed into an oxide layer, and the remaining steps are substantially the same as in the first embodiment. 200810042 For the bearer, please refer to _5a to 5e, which is the embodiment. A schematic cross-sectional view of a method for forming a plate structure is embedded. As shown in Sa, the first supply is provided, ςι^卜杈仏弟 an aluminum carrier plate 5〇 and a second aluminum carrier plate 50 and a second (four) plate 51 Placed on the upper surface of the electrolyzer: 矣 矣 第一 第一 第一 第一 第一 与 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = . In the present embodiment, the first carrier plate 51 is placed in an electrolytic cell to perform an anodizing reaction, and the thickness of the oxidation_56 is controlled by adjusting the anodization time. Then, as shown in FIG. 5b, the first inscription board 5 and the second inscription board are formed with a - opening - opening 52 and a second opening (3), and the position of the second opening is also corresponding to the first The position of the opening. Then, as shown in the figure. Then, a dielectric material is provided between the first aluminum carrier 50 and the second aluminum carrier 51, and then a wafer 21 that has been completed and integrated into the wafer integrated circuit process is embedded in the first The opening Μ盥 second opening 53 is further pressed. Among them, the wafer. The active surface 22 is provided with a plurality of electrode pads 23, the material of which is copper. During the dielectric layer bonding process, the dielectric layer 54 overflows between the first aluminum carrier 5 and the second aluminum carrier 51, so that the wafer 21 is fixed to the first opening ^ and the second In the opening 53, the same carrier plate 5 and the second carrier plate are fixed. Finally, a dielectric layer 54 is formed between the first aluminum carrier 5, the second aluminum carrier 51, and the wafer 21, and its structure is as shown in FIG. 5d. In this embodiment, the inactive surface 24 of the wafer 21 is exposed to facilitate heat dissipation from the wafer. In the present embodiment, the thickness (D1) of the first aluminum carrier 50 is equal to the thickness (D2) of the second aluminum carrier 51. 19 200810042 - After the above steps, as shown in FIG. 5e, a line build-up structure 31 is formed on the upper surface 55 of the first inscription board 5, the active surface 22 of the wafer 21, and the surface of the electrode pad 23, including The circuit layer 37 and the conductive structure 38 connected to the electrode pads of the wafer 21 are formed in the same manner as in the first embodiment. Finally, a patterned solder resist layer is formed on the surface of the build-up structure 31, and a plurality of solder bumps 39 are formed at the electrical connection pads of the patterned solder resist layer exposing the build-up structure 31, that is, the present invention is completed. The carrier plate embedded with the wafer of the embodiment. Since the first aluminum carrier 50 and the second aluminum carrier 51 are formed with an aluminum oxide layer 56 (aluminum is a ceramic material) in an oxidized manner, the first aluminum carrier 10 plate 5 〇 and the second aluminum carrier plate can be added. 51 rigidity. Therefore, although the carrier-embedded board structure in which the wafer is embedded in this embodiment is a single-sided build-up layer, it is possible to form a flat carrier board structure in which the wafer is buried. Embodiment 4 15 The manufacturing method of the wafer-embedded carrier plate of this embodiment is very similar to that of the embodiment. Except for the upper surface of the first (four) plate and the second inscription plate, the surface is formed by peroxidation. The remaining steps are substantially the same as in the second embodiment except for the oxidation of the inscription layer. Please refer to FIG. 6a to FIG. 6d, which are schematic cross-sectional views showing a method for fabricating a wafer-bearing 2 板 plate structure of the present embodiment. As shown in Fig. 6a, a first aluminum carrier 6〇 and a second aluminum carrier 61 are first provided. The first aluminum carrier 6〇 and the second aluminum carrier 61 are placed in an electrolytic cell to perform an oxidation reaction, so that the first inscription plate 6〇 and the second surface carrier are both oxidized. The aluminum oxide layer 66 is formed, and the two layers of the oxidized (four) 25 sheets are naturally interposed with the inscription layer 67. In the present embodiment, the first mounting plate 20 200810042 - 60 and the H carrier 61 are placed in an electrolytic cell for anodizing, and the thickness of the aluminum oxide layer is controlled by adjusting the anodizing time. Then, a through-opening 64 is formed on the composite carrier 63 as shown in FIG. 6b. Then, a wafer 21 having completed the wafer integrated circuit process and cut into a type 5 is embedded in the composite carrier 43. In the opening 64, the wafer 21 has a plurality of electrode pads 23 on the active surface 22 of the wafer 22. The electrode pad is made of copper. Then, the adhesive 25 is filled into the gap between the composite carrier 63 and the wafer cassette. The wafer 21 is fixed in the opening material of the composite carrier 63, and its structure is as shown in FIG. 6c. The adhesive material 25 may be an epoxy tree g|. In this embodiment, the non-active surface of the wafer 21 is The bareness of 24 is advantageous for heat dissipation of the wafer. In the present embodiment, the thickness (D1) of the 'fourth (four) plate 60 is equal to the second (four) plate 6 () (D2). After the above steps are completed, as shown in Fig. 6d, The upper surface of the carrier 1 is... the active surface 22 of the wafer 21 and the surface of the electrode 塾 (10) form a line 15 buildup structure 31 The conductive structure 38 including the circuit layer 37 and the electrode 塾 of the wafer 21 is formed in the same manner as in the first embodiment. Finally, a patterned solder resist layer is formed on the surface of the build-up structure 31, and The patterned solder mask reveals a plurality of solder bumps 39 at the electrical connection of the build-up structure 31, that is, the carrier board embedded with the wafer of the embodiment is completed. The second (four) plate 61 is formed with an oxidized inscription layer 66 (oxidized as a research material) by oxidation, so that the rigidity of the first inscribed plate 6曰〇 and the second inscription plate 61 can be increased. After the embodiment, the carrier board structure in which the 曰a sheet is embedded is a single-sided build-up layer, and the flat carrier-embedded board structure can still be formed. 21 200810042 The above embodiments are merely exemplified for convenience of description, and the present invention is The scope of the claims is based on the scope of the patent application, and is not limited to the above embodiments. [Simplified description of the drawings] Figure (10) is an electrical connection structure of a conventional carrier plate embedded with a wafer. Section
10 15 圖2a至2d係本發明-較佳實施例之喪埋有晶片之承载板之 製造方法之剖面示意圖； 圖3a至域本發明-較佳實_之線路增層結構之製造方 法之剖面示意圖； " 片之承載板 圖4a至4d係本發明另一較佳實施例之嵌埋有晶 之製造方法之剖面示意圖； 圖5a至5e係本發明再一較佳實施例之嵌埋有晶片之 之製造方法之剖面示意圖，以及 之承載板 圖6a至6d係本發明又一較佳實施例之嵌埋有晶片 之製造方法之剖面示意圖。 2〇 【主要元件符號說明】 第一鋁載板10,40,50,60 第一開口 12,52 介電層 14,42,54, 62 第二鋁載板11，41，51，61 第二開口 13,53 上表面 15, 45,55, 65 22 200810042 晶片21 電極墊23 黏著材25 線路增層結構31 絕緣層開口 33 阻層開口 35 線路層37 焊料凸塊39 開口 44,64 鋁層57,67 晶片102 保護層104 線路增層結構106 主動面22 非主動面24 絕緣層32 圖案化阻層34 電鍍金屬層36 導電結構3 8 複合載板43,63 氧化鋁層56,66 載板101 電極墊103 金屬層10510a to 2d are schematic cross-sectional views showing a method of manufacturing a carrier plate in which a wafer is buried according to a preferred embodiment of the present invention; and FIG. 3a to FIG. 3a to a cross section of a method for manufacturing a line build-up structure of the present invention. FIG. 4a to FIG. 4d are schematic cross-sectional views showing a method of manufacturing embedded crystal according to another preferred embodiment of the present invention; FIGS. 5a to 5e are embedded in another preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6a to 6d are schematic cross-sectional views showing a method of fabricating a wafer in accordance with still another preferred embodiment of the present invention. 2〇【Main component symbol description】 First aluminum carrier 10, 40, 50, 60 First opening 12, 52 Dielectric layer 14, 42, 54, 62 Second aluminum carrier 11, 41, 51, 61 Second Opening 13, 53 Upper surface 15, 45, 55, 65 22 200810042 Wafer 21 Electrode pad 23 Adhesive material 25 Line build-up structure 31 Insulation layer opening 33 Resistive layer opening 35 Circuit layer 37 Solder bump 39 Opening 44, 64 Aluminum layer 57 67 wafer 102 protective layer 104 line build-up structure 106 active surface 22 inactive surface 24 insulating layer 32 patterned resist layer 34 electroplated metal layer 36 conductive structure 3 8 composite carrier 43, 63 aluminum oxide layer 56, 66 carrier 101 Electrode pad 103 metal layer 105
23twenty three