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TW200807675A - Packaging structure and method for fabricating the same - Google Patents

Packaging structure and method for fabricating the same Download PDF

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Publication number
TW200807675A
TW200807675A TW095128016A TW95128016A TW200807675A TW 200807675 A TW200807675 A TW 200807675A TW 095128016 A TW095128016 A TW 095128016A TW 95128016 A TW95128016 A TW 95128016A TW 200807675 A TW200807675 A TW 200807675A
Authority
TW
Taiwan
Prior art keywords
conductive
layer
disposed
package structure
substrate
Prior art date
Application number
TW095128016A
Other languages
Chinese (zh)
Inventor
Sting Kuo
Original Assignee
Sting Kuo
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sting Kuo filed Critical Sting Kuo
Priority to TW095128016A priority Critical patent/TW200807675A/en
Publication of TW200807675A publication Critical patent/TW200807675A/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

According to the present invention, a packaging structure is provided to include: a substrate; a component mounted on the substrate; a conductive connector formed close to the peripheral of the substrate; a molding layer formed over the substrate so as to overlie the component, but expose a contact portion of the conductive connector; a conductive layer formed on the molding layer, preferably in contact with the contact portion of the conductive connector. The conductive layer can be made of material selected from polyaniline (PAn), polypyrrole (PPy), poly-para-phenylene (PPP), polythiophene (PT), conductive ink, or thin film metal. Moreover, the conductive layer can be formed on the molding layer by printing, spraying, sputtering, depositing or thermal coating.

Description

200807675 九、發明說明: 【發明所屬之技術領域】 右明ί有關於電子微小構裝技術,特別是有關於一種具 有月r電防護、電磁隔離、以及抗氧化之封裝結構及其製造方法。 【先前技術】 現今模組積體電路封裝SIP(System in package) ic (/曰=伽Clrcuits)方式,不論是單—晶片、抑或是整合 古且(m〇dule),大抵係採用鑄模(molding component) p ^著模組積體電路技術的進步,模組積體電路日益微小 化:即f越來越多的技術問題尚須克服,而主要的技術問題有 ς ·二是靜電防護的問題,由於電子树的縮小化趨勢漸漸明 以兀件所承受的靜電傷害的預防也要加強;二是電 欠由於元件的縮小化,所以電磁干擾也要特別的處理, =以=止電磁波訊號彼此之間的干擾;三s封裝接點氧化的 二由於兀件的縮小,元件的輸入/輸出接點氧化問 會造成量產良率無法提昇。 j就解決電磁干擾-事,習知技術係在模組频電路所設 、舟#電路板上,利用金屬零組件將模組積體電路包覆其内,以 ^蔽方式(shielding)獲致電磁隔離之效。惟,金屬遮]罩係用 於包覆模組積體電路,面積必須比模組積體電路大;又,金. J罩需按模組積體電路的尺寸另行製造,故生產成本亦二再 孟屬遮罩僅解決電磁干擾的問題,卻無法靜電 氧化的問題。 ' 【發明内容】 電 、因此,本發明之一目的,在於提供一種具有靜電防護 磁隔離、以及抗氧化之微小封裝結構及其製造方法。' 200807675 n上述目的,本發明可藉由提供一種 構包括:一基底’·至少—零件,設置於基底上^ 上方设置鄰近於基底邊緣處;—包覆層,設置於基底 於署件,並露出導電接點之接觸部;以及,-導電層, ί電声d!上t並與導電接點之接觸部呈電性柄接。表面的 同樣ϋί㈣接‘时時不需要剌雜祕也可達到 =尚可提供裝結構之製造方 【實施方式】 理適用。 电峪对衣結構,或疋多晶片封裝亦可同 而输—聰_的頂視圖; 和第二圖所示,標號10^!=圖即顯示於第二圖。第一圖 FR4,、LTcc、FR5或是底’此基底3(3可以是ΒΤ、 0.1mm〜Ιιμ或更厚。板材質所構成,厚度約為 組積體電路晶片%日=二代表,,可以是模 11C係固定於基底10上。1電谷,、’,此等苓件11A、UB-、 pad),設置於基底1〇 6A怠"1^儿12代表導電接點(conductive P ) 絲1Q喊_域,通常錢接维也電位。 200807675 層(mQldinglayer),可以利用模組積體電路 ^匕覆材貝或疋其它的絕緣材制構成,覆於基底lG之全般 ΓΓ之Γ、Λβ、llc等覆蓋起來,惟需將導、電接點 ^口^刀路出,疋為接觸部15。標號14代表導電層 !Tr)、,覆蓋於包覆層13表面及侧面;較佳而 L曰讀導電接點12之接觸部15呈電性連接;此 屬由,膠、導電油墨、導電碳粉、或是金 P〇lypyr;〇le fPPy)^Sp^R- ' 1, yj P〇ly-para-phenylene (PPP)、 P$〇 (PT)等。較佳而言,若導電層14採用導電油 5質為佳塑電,粉等材質,與包覆層13附著性較金屬 蔣徂ί3好;另外,導電油墨、導電塑膠、專電碳 扣#了以k供較金屬為佳的抗氧化性。 根據本發明,先在固定雷 、 電接點12,後續在覆土 ^邊、、彖處設置有導 接點1?上復層13,再接者做切割時露出導電 13之全“ ^,ίίΓ 15,然後將導電層14形成於包覆層 之王瓜表面,而與導電接點12之接觸部15成總. 靜電防護的效果’·又’導電層 ^ 分不易歲^匕, 可ΐί略fr圖所不之導電接點12係屬選擇性組成要件,亦 割道(scribe line) 32 ^為®^個^'「基f 30上,係按切 34D f^ 30 ρΓΓτ^ ?〇34A'34B'34C ' 構成’厚度約為 8 200807675 件料元區域輝内設有;=耗==有零 基底30之方式,可以焊接、表 午、6D❿各零件固設於 之插座等方式為之。第三财,“若於基底 基底上’位於切割道μ處,此導fC38設置於 物it材質構成,可以是長條狀或片狀等犬金屬、導電 將絕緣材質覆蓋基底3Q表面 式(moWmg) 覆; ;ί;^ 40A-40D〇 ^200807675 IX. Description of the invention: [Technical field to which the invention pertains] 右明ί relates to electronic micro-architecture technology, and in particular to a package structure having a monthly electrical protection, electromagnetic isolation, and oxidation resistance, and a method of manufacturing the same. [Prior Art] Today's module integrated circuit package SIP (System in package) ic (/曰 = gamma Clrcuits), whether it is single-wafer, or integrated ancient (m〇dule), is basically a mold (molding Component) p ^ The advancement of modular integrated circuit technology, the modular integrated circuit is increasingly miniaturized: that is, more and more technical problems have to be overcome, and the main technical problems are ς · Second, the problem of static protection As the shrinking trend of the electronic tree is gradually becoming clear, the prevention of static damage caused by the components is also strengthened. Second, the electrical owing is reduced due to the reduction of components, so the electromagnetic interference must be specially treated. Interference between the three s package contacts oxidation due to the shrinkage of the components, the input / output contact oxidation of the component will cause mass production yield can not be improved. j solves the electromagnetic interference-things, the conventional technology is in the module frequency circuit set, the boat # circuit board, the metal integrated circuit is used to cover the module integrated circuit, and the electromagnetic is obtained by shielding. The effect of isolation. However, the metal cover is used to cover the integrated circuit of the module, and the area must be larger than the integrated circuit of the module; in addition, the gold cover must be separately manufactured according to the size of the integrated circuit of the module, so the production cost is also two. The Monzon mask only solves the problem of electromagnetic interference, but it cannot solve the problem of electrostatic oxidation. SUMMARY OF THE INVENTION [Electricity] Therefore, it is an object of the present invention to provide a micro-package structure having electrostatic protection magnetic isolation and oxidation resistance and a method of manufacturing the same. '200807675 n The above object, the present invention can provide a structure comprising: a substrate 'at least a part, disposed on the substrate ^ disposed adjacent to the edge of the substrate; - a cladding layer, disposed on the substrate, and Exposing the contact portion of the conductive contact; and, the conductive layer, is electrically connected to the contact portion of the conductive contact. The same 表面 ( 四 四 四 四 四 四 四 四 四 时 时 时 时 时 时 时 时 时 时 = = = = = = = = = = = = = The top view of the electric pick-up structure, or the multi-chip package, can also be transferred to the same. As shown in the second figure, the figure 10^!= is shown in the second figure. The first figure FR4, LTcc, FR5 or the bottom 'this substrate 3 (3 can be ΒΤ, 0.1mm~Ιιμ or thicker. The plate material is composed, the thickness is about the assembly circuit wafer %% = two represents, The die 11C may be fixed on the substrate 10. 1 electric valley, ', these pieces 11A, UB-, pad) are disposed on the substrate 1〇6A怠"1^儿12 represents a conductive contact (conductive P ) Silk 1Q shouts _ domain, usually money is also connected to the potential. 200807675 layer (mQldinglayer), can be constructed by using the module integrated circuit ^ 匕 材 疋 or other insulating materials, covering the entire substrate lG ΓΓ Λ, Λ β, llc, etc., but the need to guide, electricity The contact ^ mouth ^ knife exits, and the contact portion 15. Reference numeral 14 denotes a conductive layer! Tr), covering the surface and the side surface of the cladding layer 13; preferably, the contact portion 15 of the L-reading conductive contact 12 is electrically connected; the genus, the adhesive, the conductive ink, the conductive carbon Powder, or gold P〇lypyr; 〇le fPPy)^Sp^R- ' 1, yj P〇ly-para-phenylene (PPP), P$〇(PT), etc. Preferably, if the conductive layer 14 is made of conductive oil, it is preferably made of plastic, powder or the like, and the adhesion to the coating layer 13 is better than that of the metal 徂 徂 3 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; It is better to use zinc for better oxidation resistance. According to the present invention, the fixed lightning and electrical contacts 12 are first provided, and then the guiding points 1 and the upper layer 13 are disposed at the side of the covering soil, and the upper layer 13 is exposed, and then the whole of the conductive 13 is exposed when cutting. ^, ίίΓ 15, then the conductive layer 14 is formed on the surface of the king layer of the cladding layer, and the contact portion 15 with the conductive contact 12 is formed. The effect of the electrostatic protection '·and the conductive layer ^ is not easy to be old, can be slightly The conductive contacts 12 of the fr diagram are optional components, and the scribe line 32 ^ is ® ^ ^ ' on the base f 30, the system is cut 34D f^ 30 ρΓΓτ^ ? 34A' 34B'34C 'construction' thickness is about 8 200807675. The material area is provided in the area; = consumption == there is zero base 30, which can be welded, noon, 6D, each part is fixed in the socket. The third fiscal, "if the base substrate" is located at the cutting path μ, the guide fC38 is set in the material of the material it can be a long strip or sheet of dog metal, conductive covering the base material 3Q surface type (moWmg );; ί;^ 40A-40D〇 ^

StiitiJ 38!f m 34A # 34B 38 ^ 接點與_之導電 間之導電接點38經切割範圍34C與34D 後’可藉由切割所產生二,38D °經過切割處理 部分,諸如:經由溝槽42募^42=4=6露出導電接點抑之 溝槽44可露出導^&4328==電接點观和38B,經由 接點38C和38D等等。 和38C ’經由溝槽46可露‘出導電 之上_48編咖惠_ 48 438A4V«R46 " 〇 ^ ? ^ 等呈電性_。此導電層 =是 200807675 導電碳粉、或是金屬等材質所構成;導電塑膠可以是 polyaniline (PAn) 、 polypyrrole (PPy) 、 poly-para-phenylene (PPP)、p〇lythiophene (PT)等,並可 以喷鑛(spraying)、濺銀(sputtering)、蒸鑛(evap〇rati〇n)、 沈積(deposition)、塗佈(coating)、或印刷(printing)等方 ,,成。接著,按照各切割道32的位置進行切割處理,將 單Try區域範圍34A-34D予以切割分離成為獨立之封裝結往 參照第七圖,即是單元區域範圍34B之封裝結構。 月 因此,如第七圖所示,根據本發明製造方法所得之:士 構’士係在目定電子零狀基底3〇雜處設置有導電接點^ 後績在覆上包覆層權時露出導電接點38β之部分 〇,,將導電層48覆蓋於於包覆層_之表面 接點38Β之接觸部50成電性接觸。由於導電 ϊί,位,故可將靜電導出,獲致靜電防護的效果;ii 蔽面,可獲致電磁隔離之J 屏 撕、識、38C、38D等之形成步驟3即中可接點38.、 【圖式簡單說明】 圖;第一圖係顯報據本發明縣結構—較㈣施例之頂視 第二圖係顯示第一圖之ii-ii綠 面ίίΓ第七_示根據本發明封裝 200807675 【主要元件符號說明】 1〜封裝結構;10〜基底;11A、11B、11C〜零件;12〜導電接 點;13〜包覆層;14〜導電層;15〜接觸部;30〜基底;3ν2〜切割 道;34Α、34Β、34C、34D〜單元區域範圍;36Α、36Β、36C、36D〜 零件;38、38Α、38Β、38C、38D〜導電接點;40、40Α、40Β、 40C、40D〜包覆層;42、44、46〜溝槽;48〜導電層;以及,50〜 接觸部。StiitiJ 38!fm 34A # 34B 38 ^ The conductive contact 38 between the junction and the conductive layer 38 is cut by the range 34C and 34D, which can be generated by cutting. The 38D ° passes through the cutting processing part, such as via the groove 42. The recruitment of 42=4=6 exposes the conductive contacts and the trenches 44 can expose the junctions & 4328 == electrical junctions and 38B, via junctions 38C and 38D, and the like. And 38C ' can be exposed through the trench 46 ‘Outside the conductive _48 编咖惠 _ 48 438A4V «R46 " 〇 ^ ? ^ and so on. The conductive layer is composed of 200807675 conductive carbon powder or metal; the conductive plastic may be polyaniline (PAn), polypyrrole (PPy), poly-para-phenylene (PPP), p〇lythiophene (PT), etc. It can be sprayed, sputtered, evaporated, deposited, coated, or printed. Next, the dicing process is performed in accordance with the position of each dicing street 32, and the single Try region ranges 34A-34D are diced and separated into individual package junctions. Referring to the seventh figure, the package structure of the cell region range 34B. Therefore, as shown in the seventh figure, according to the manufacturing method of the present invention, the conductive structure is provided in the noisy portion of the electronic zero-shaped substrate 3, and the performance is exposed when the cladding layer is covered. The portion of the conductive contact 38β is electrically connected to the contact portion 50 of the surface contact 38 of the cladding layer. Due to the conductive ϊ, position, the static electricity can be derived, and the electrostatic protection effect can be obtained; ii, the shielding surface can be obtained, and the J screen tearing, the identification, the 38C, the 38D, etc. forming the electromagnetic isolation can be formed in the step 3, that is, the medium contact point 38. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a report showing the structure of the county according to the present invention - the top view of the fourth embodiment shows the ii-ii green face of the first figure ίίΓ seventh_showing the package according to the present invention 200807675 [Description of main components] 1~ package structure; 10~ substrate; 11A, 11B, 11C~ parts; 12~ conductive contacts; 13~ cladding layer; 14~ conductive layer; 15~ contact part; 30~ substrate; 3ν2 ~Cleaning track; 34Α, 34Β, 34C, 34D~ unit area range; 36Α, 36Β, 36C, 36D~ parts; 38, 38Α, 38Β, 38C, 38D~ conductive contacts; 40, 40Α, 40Β, 40C, 40D~ Coating layer; 42, 44, 46~ trench; 48~ conductive layer; and, 50~ contact portion.

Claims (1)

200807675 申請專利範圍·· 1 一種封裝結構,包括: 一基底; 至少一零件,設置於上述基底上; 一導電接點,設置鄰近於上述基底邊緣處; 並露出上 一包覆層,設置於上述基底上方覆蓋上述零件 述導電接點之一接觸部;以及 一導電層,設置於上述包覆層上。 2.如申請專利範圍第1項所述之封裝結構,其中,土述導 電層之材質係選自由導電塑膠、導電油墨、導電碳粉和金屬所 構成之群組。 3·如申請專利範圍第2項所述之封裝結構,其中,上述導 ^ ^ polyaniline (PAn) > polypyrr〇ie (PPy) ^ (PPP)、以及 PQlythiC)Phene (ΡΤ)所組 4·申請專利範圍第i項所述之封裝结構 層係與上料電接狀上賴觸部呈Γ巾,上述導電 5· —種封裝結構之製造方法,包括下列步驟: 每一上 提供一基底,按切割道區分為複數單元區域 述單7L區域範圍内設置有至少一零件; 圍, 在上述切割道上設置一導電接點; 電接^述基底表面設置—_,並覆蓋上述零件和上料 根據上述切割道定義上述包覆層形成溝槽,用以% .路、出上述 12 200807675 導電接點; 在上述包覆層上與上述溝槽内設置一導電層,.使上述導電 層與上述露出之導電接點呈電性耦接。 6·如申请專利範圍第5項所述之封裝結構之製造方法,尚 包括:根據上述切割道,區分出複數封裝結構。 7·申請專利範圍第5項所述之封骏結構之製造方法,其 中,上述導電層之材質係選自由導電塑膠、導電油墨、導電碳 粉和金屬所構成之群組。 ' “、8·如申請專利範圍第7項所述之封裝結構,其中,上述導 電』膠係遥自由p〇lyaniiine (PAn)、p〇iypy汀〇ie (ppy)、 P〇ly-para-phenylene (PPP)、以及 polythiophene (PT)所組 成之群組。 9·申請專利範圍第5項所述之封裝結構之製造方法,其 中,上述導電層係與上述導電接點之上述接觸部呈電性耦接。。 …10·申請專利範圍第5項所述之封裝結構之製造方法,其 中"又置上述導電層係以喷鑛、濺锻、蒸链、沈積、塗佈、以及 印刷等方式中之一者為之。 11· 一種封裝結構,包括·· 一基底; 至夕一零件,設置於上述基底上; 包覆層’設置於上述基底上方覆蓋上述零件·,以及 一導電層,設置於上述包覆層上。 13 200807675 12·申清專利範圍第11項戶斤述之封褒結構’其中,上述導 電層之材質係選自由導電塑膠、導電油墨、導電碳粉和金屬所 構成之群組。 13·如申請專利範圍第12項所述之封裝結構,其中,上述 導電塑膠係選自由 p〇lyaniline (pAn)、polypyrrole (ppy)、 poly-para-phenylene (ppp)、以及 polythiophene (PT)所組 成之群組。 14· 一種封裝結構之製造方法,包括下列步驟·· 提供一基底,按切割道區分為複數單元區域範圍,每一上 述單元區域範圍内設置有至少一零件; 在上述基底表面設置一包覆層,並覆蓋上述零件; 根據上述切割道定義上述包覆層形成溝槽;以及 在上述包覆層上與上述溝槽内設置一導電層。 15·如申請專利範圍第14項所述之封裝結構之製造方法, 尚包括:根據上述切割道,區分出複數封裝結構。 16·申請專利範圍第14項所述之封裝結構之製造方法,其 中’上述導電層之材質係選自由導電塑膠、導電油墨、.導電破 粉和金屬所構成之群組。 Π.如申請專利範圍第16項所述之封裝結構,其中,上述 導電塑膠係選自由 polyaniline (PAn)、p〇iypyrr〇ie (ppy)、 poly-para-phenylene (PPP)、以及 polythiophene (PT)所組 成之群組。 18·申請專利範圍第14項所述之封裝結構之製造方法,其 14 200807675 中設置上述導電層係以喷鍍、濺鍍、蒸鍍、沈積、塗佈、以及 印刷等方式中之一者為之。 15200807675 Patent Application Range·1 A package structure comprising: a substrate; at least one component disposed on the substrate; a conductive contact disposed adjacent to the edge of the substrate; and exposing an upper cladding layer disposed on The substrate is covered with a contact portion of the conductive contact; and a conductive layer is disposed on the cladding. 2. The package structure of claim 1, wherein the material of the conductive layer is selected from the group consisting of conductive plastic, conductive ink, conductive carbon powder, and metal. 3. The package structure according to item 2 of the patent application scope, wherein the above-mentioned guide ^ ^ polyaniline (PAn) > polypyrr〇ie (PPy) ^ (PPP), and PQlythiC) Phene (ΡΤ) The package structure layer and the charging contact portion of the patented item are in the form of a wipe, and the manufacturing method of the above-mentioned conductive package includes the following steps: The cutting channel is divided into a plurality of unit regions, and at least one component is disposed in the 7L region; a conductive contact is disposed on the cutting channel; the substrate surface is set to -_, and the above parts are covered and loaded according to The dicing street defines the cladding layer to form a trench for the conductive layer of the above-mentioned 12 200807675; and a conductive layer is disposed on the cladding layer and the trench to expose the conductive layer and the above-mentioned conductive layer The conductive contacts are electrically coupled. 6. The method of manufacturing a package structure according to claim 5, further comprising: distinguishing the plurality of package structures according to the dicing track. 7. The method of manufacturing a seal structure according to claim 5, wherein the material of the conductive layer is selected from the group consisting of conductive plastic, conductive ink, conductive carbon powder, and metal. The packaging structure described in the seventh aspect of the patent application, wherein the above-mentioned conductive gel is freely p〇lyaniiine (PAn), p〇iypy Tingyi (ppy), P〇ly-para- A method of manufacturing a package structure according to the invention of claim 5, wherein the conductive layer is electrically connected to the contact portion of the conductive contact The coupling method of the package structure described in claim 5, wherein the conductive layer is sprayed, splashed, steamed, deposited, coated, printed, etc. One of the modes is: 11. A package structure comprising: a substrate; a part of the eve, disposed on the substrate; a cladding layer disposed over the substrate to cover the component, and a conductive layer It is disposed on the above-mentioned coating layer. 13 200807675 12·Shenqing Patent Area No. 11 item of the sealing structure of the households, wherein the material of the above conductive layer is selected from conductive plastic, conductive ink, conductive carbon powder and metal Group of constituents. 1 3. The package structure of claim 12, wherein the conductive plastic is selected from the group consisting of p〇lyaniline (pAn), polypyrrole (ppy), poly-para-phenylene (ppp), and polythiophene (PT). a group of components. 14) A method of manufacturing a package structure, comprising the steps of: providing a substrate, which is divided into a plurality of unit regions by a cutting lane, and at least one component is disposed in each of the unit regions; a coating layer is disposed on the surface and covers the component; the cladding layer is formed according to the dicing channel; and a conductive layer is disposed on the cladding layer and the trench. 15 The method for manufacturing a package structure according to the above aspect, further comprising: distinguishing a plurality of package structures according to the dicing channel. 16) A method for manufacturing a package structure according to claim 14, wherein the material of the conductive layer is selected A group of free conductive plastics, conductive inks, conductive powders, and metals. 封装. The package structure of claim 16 is The conductive plastic is selected from the group consisting of polyaniline (PAn), p〇iypyrr〇ie (ppy), poly-para-phenylene (PPP), and polythiophene (PT). In the manufacturing method of the package structure, the above-mentioned conductive layer is provided in one of the methods of sputtering, sputtering, vapor deposition, deposition, coating, and printing. 15
TW095128016A 2006-07-31 2006-07-31 Packaging structure and method for fabricating the same TW200807675A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI447888B (en) * 2011-06-13 2014-08-01 Advanced Semiconductor Eng Semiconductor structure with recess and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI447888B (en) * 2011-06-13 2014-08-01 Advanced Semiconductor Eng Semiconductor structure with recess and manufacturing method thereof

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