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TW200807436A - Write protect controller and control method thereof - Google Patents

Write protect controller and control method thereof Download PDF

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Publication number
TW200807436A
TW200807436A TW95126198A TW95126198A TW200807436A TW 200807436 A TW200807436 A TW 200807436A TW 95126198 A TW95126198 A TW 95126198A TW 95126198 A TW95126198 A TW 95126198A TW 200807436 A TW200807436 A TW 200807436A
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Taiwan
Prior art keywords
pin
write protection
resistor
unit
write
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Application number
TW95126198A
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Chinese (zh)
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TWI300940B (en
Inventor
Min-Jye Chen
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Benq Corp
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Publication of TWI300940B publication Critical patent/TWI300940B/en

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Abstract

Write protect controller comprises a connector comprising a connection detection terminal, a switch unit, and a microprocessor. When the connection detection terminal is in first state, the switch unit operates in first mode. When the connection detection terminal is in second state, the switch unit operates in second mode. When the switch unit operates in the first mode and the microprocessor is enabled, the potential of a write protect pin of a memory unit is controlled by the microprocessor. When the switch unit operates in the second mode and the microprocessor is disabled, the write protect pin is assigned a reference potential and the memory unit can be read/write normally.

Description

200807436 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種寫入保護控制裝置,耦接於晶片 的寫入保護腳位,用以控制該晶片的寫入保護功能。 【先前技術】 電子系統通常具有至少一個記憶單元,例如可編程唯 讀記憶體(Programmable Read Only Memory, PROM)、可抹 除可編程唯讀記憶體(Erasable Programmable Read Only Memory,EPROM)、或電子式可抹除可編程唯讀記憶體 (Electrically Erasable Programmable Read Only Memory, EEPROM)…等。廠商可將軟體燒錄在該記憶單元中,作為 該電子系統之韌體;亦可將該電子系统之參數燒錄在該記 憶單元中。該記憶單元通常具有一寫入保護腳位,用以啟 動或關閉該記憶單元之寫入保護功能。若該寫入保護腳值 之電壓等於一參考電位,則該記憶單元可被寫入資料;若 不等於該苓考電位,則該記憶單元不允許使用者將資料寫 入其中。 ^ 在傳統的電子系統製作過程中,'主要採用「:硬體控制」 或「軟體控制」兩種方式來決定該寫入保護腳位之電位。」 「硬體控制」直接以線路將該寫入保護腳位耦接至=表土 電位,使該記憶單元-直輯在可寫人資_狀態二二 體控制」將該舄入保護腳位輕接至一處理留 , --、1—斗—,> 处王丁兀,由該處理 單7L決疋該舄入保|隻腳位之電位。 0535-A21333TWF(N2);A05599;GLOR|〇US 6 200807436 「硬體控制」的優點是不需要使用其他裝置(如「軟體 控制」所使用的處理單.元)即可將資料寫入該記憶單元二= 點是可能會發生資料誤寫的情況。以顯示器為例,若該顯 示益使用頒示資料通道指令介面⑼刪叮 Channel/Command Interface, DDC/CI)、並且以「硬體控制 將該記憶單元維持在可寫入資料的狀態,則儲存於該記情 單元内的資料报有可能會被DDC/CI覆蓋。使用「軟體控 制」,以處理單元控制該記憶單元之寫入保護功能,即可 瞻 降低上述記憶單元被DDC/CI誤寫的狀況發生。然而,必 須另行提供電源給該處理單元方能將資料燒錄於該記憶單 元中。因此,該「軟體控制」技術會增加生產流程與工廠 環境的複雜度。我們需要一種新的技術來克服上述「硬體 控制」與「軟體控制」所會面臨的問題。 【發明内容】 本發明提供一種寫入保護控制裝置,耦接於一記情罝 • 如入保護腳位,以控制該記憶單元之寫入保護功能: 該種寫入保護控制裝置可以防止該記憶單元被誤寫、簡化 電子系統的生產流程、並且使工廠作業環境單純化。 本發明所提出的該種寫入保護控制裝置中包括一連接 單元、一切換單元、以及一處理單元。該連接單元具 偵測腳位。該切換單元耦接於該偵測腳位與—記憶單元的 :寫入保護腳位之間。該處理單_接該寫人保護腳位。 當該偵測腳位處於一第一狀態時,該切換單元以一第一模 0535-A21333TWF(N2);A05599;GLORI〇US 7 200807436 式運作。.當該偵測腳位處於一第二狀態時,該接換單元以 一第二模式運作。在該切換單元以該第一模式運作時,若 有電源供電給該處理單元,則該記憶單元之寫入保護功能 由邊處理早元控制。在該切換單元以該第二模式運作時, 若沒有電源供電給該處理單元,則該寫入保護腳位被該切 換皁元連接至一參考電位,該記憶單元可被正常讀寫;反 之,若名%源供電給該處理單元,則該寫入保護腳位的電 位由該處理單元控制。200807436 IX. Description of the Invention: [Technical Field] The present invention relates to a write protection control device coupled to a write protection pin of a wafer for controlling a write protection function of the wafer. [Prior Art] An electronic system usually has at least one memory unit, such as Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), or electronic Elastically Erasable Programmable Read Only Memory (EEPROM), etc. can be erased. The manufacturer can burn the software in the memory unit as the firmware of the electronic system; the parameters of the electronic system can also be burned in the memory unit. The memory unit typically has a write protection pin to activate or deactivate the write protection function of the memory unit. If the voltage of the write protection pin value is equal to a reference potential, the memory unit can be written to the data; if not equal to the reference potential, the memory unit does not allow the user to write data into it. ^ In the traditional electronic system production process, 'mainly adopts ": hardware control" or "software control" to determine the potential of the write protection pin. "Hardware Control" directly connects the write protection pin to the = topsoil potential by the line, so that the memory unit - direct compilation in the writable person_state two-body control" will be light into the protection pin Connected to a treatment to stay, --, 1 - bucket -, > at the Department of Wang Ding, by the processing of the single 7L 疋 疋 舄 | 只 只 只 | 0535-A21333TWF(N2);A05599;GLOR|〇US 6 200807436 The advantage of "hardware control" is that you can write data to this memory without using other devices (such as the processing unit used in "Software Control"). Unit 2 = Point is a situation in which data miswriting may occur. Taking the display as an example, if the display uses the presentation data channel command interface (9) to delete the Channel/Command Interface, DDC/CI), and the hardware control unit maintains the memory unit in the state of writable data, the storage is saved. The datagram in the quotation unit may be overwritten by DDC/CI. Using the "software control" to control the write protection function of the memory unit by the processing unit, the memory unit can be mis-written by DDC/CI. The situation happened. However, power must be supplied to the processing unit to burn the data into the memory unit. Therefore, this “software control” technology increases the complexity of the production process and the factory environment. We need a new technology to overcome the problems faced by the above "hardware control" and "software control". SUMMARY OF THE INVENTION The present invention provides a write protection control device coupled to a memory device to control a write protection function of the memory unit: the write protection control device can prevent the memory The unit is miswritten, simplifies the production process of the electronic system, and simplifies the factory operating environment. The write protection control device proposed by the present invention includes a connection unit, a switching unit, and a processing unit. The connection unit has a detection position. The switching unit is coupled between the detection pin and the write protection pin of the memory unit. The processing unit is connected to the write protection pin. When the detecting pin is in a first state, the switching unit operates as a first mode 0535-A21333TWF(N2); A05599; GLORI〇US 7 200807436. When the detecting pin is in a second state, the switching unit operates in a second mode. When the switching unit operates in the first mode, if a power supply is supplied to the processing unit, the write protection function of the memory unit is controlled by the edge processing. When the switching unit operates in the second mode, if no power is supplied to the processing unit, the write protection pin is connected to a reference potential by the switching soap unit, and the memory unit can be read and written normally; If the name source is powered to the processing unit, the potential of the write protection pin is controlled by the processing unit.

該舄入保f隻腳位被耦接至一參考電位時,該記憶單元 可被正常讀寫1切換單元包括—開關。該關位於該寫 護腳位與一參考電位之間。當該切換單元以該第一模 式k作時,破開關不导通。當該切換單元以該第二模式運 作時’該開關導通並且將該寫人保護腳㈣接至該參^ 位。 ’ 該開關可為一電晶體。該切換單元更包括一第一電 :、-第二電阻、以及一第三電阻。該第—電阻耦接在該 偵測腳位與該電晶體之基極之間。該第二電阻轉第三泰 :且之第-端皆輕接至一電源。該第二電阻與該第三電阻: 二一齡聽接至該電㈣之餘與該偵測腳位。該雷晶 脸之杲極與射極分職接該寫人保護腳位與該參考雷位。 該偵測腳位結接至該參考電位時處於該第—狀態: _位在浮接時處於該第二狀態。該切換單元更可包括二 2二極體。該齊納二極體之陽極與陰極分油接至鮮 考电位以及該偵測腳位。該參考電位可為該電源之地端:When the pin is connected to a reference potential, the memory unit can be read and written normally. The switching unit includes a switch. The switch is located between the write protector and a reference potential. When the switching unit is in the first mode k, the break switch is not turned on. When the switching unit operates in the second mode, the switch is turned on and the write protector (4) is connected to the reference. The switch can be a transistor. The switching unit further includes a first electric:, a second resistor, and a third resistor. The first resistor is coupled between the detecting pin and the base of the transistor. The second resistor is turned to the third: and the first end is lightly connected to a power source. The second resistor and the third resistor: the second one is connected to the electric (four) and the detecting pin. The thunder and face of the thunder and the ejector are connected to the write protection foot and the reference ray position. The detection pin is in the first state when it is connected to the reference potential: the _ bit is in the second state when floating. The switching unit may further include a two-two diode. The anode and cathode of the Zener diode are connected to the fresh potential and the detection pin. The reference potential can be the ground of the power supply:

〇535-A21333TWF(N2);A05599;GLOR|〇US 200807436 位。該記憶單元為 令舍明亦利用上述寫入保護控制裝置發展由一種雷子 祕。該f電子系統中包括—記憶單元、以及上述寫乂保 瘦,制裝j。該寫人保護控制裝置乃絲控制該記憶單元 之舄入irw又功此,使該電子系統得以根據該偵測插拔端之 信號、以及該處理單元之電源供電與否來決定如何操作該 記憶單元之寫入保護功能。〇 535-A21333TWF (N2); A05599; GLOR | 〇 US 200807436. The memory unit is developed by the above-mentioned write protection control device so that it is developed by a kind of mine. The f-electronic system includes a memory unit, and the above-mentioned write file is thinned, and the package j is mounted. The write protection control device controls the input of the memory unit into the irw, so that the electronic system can determine how to operate the memory according to the signal of the detection plug and the power supply of the processing unit. Unit write protection.

該種電子系統可為一影像顯示裝置或一影音顯示裝 置,該连接單元可為一 D-sub、一數位視覺介面(Digitai VisualInterfaCe,DVI)連接器、或一高解析多媒體影音端子 (High Definition Multimedia Interface,HDMI)。 ) 本發明亦提供一種控制方法,用以控制電子系統之記 憶單元的寫入保護腳位。該寓入保護腳位之電位等於一表 考電位時,該記憶單元可被讀寫。在沒有電源供電給該電 子系統時,該種控制方法可藉由外接該電子系統的一電腦 系統提供電源給電子系統中之記憶單元,並且藉由電子气 統中的一切換單元將該記憶單元的寫入保護腳值連接至該 參考電位,使外接該電子系統的一電腦系統仍得以讀寫該 §己憶單元。若有電源供電給該電子系統的一處理單元,則 該種控制方法會令該處理單元控制該記憶單元的寫入保罐 腳位,以決定是否讀寫該記憶單元。 ' 上述控制方法所提到的參考電位可為一接地端 (ground)。該電子系統啟動且正常使用下,若電子系統外产 0535-A21333TWF(N2);A05599;GLORIOUS 9 200807436 至該電腦系統,該電子系統的偵測腳位會接地,該切換單 元的電晶體會關閉。此時,若提供電源給該電子系統的兮 處理單元,則該記憶體的寫入保護腳位由該處理單元控 制。在工廠端’將電子系統外接一電腦系统,欲將雪腦系 統的資料燒錄至該電子系統的記憶早元時,若停止提供雷 源給該電子系統且將該電子系統的該偵測腳位改為浮接, 則該切換單元的電晶體導通,使得該電子裝置的寫入保譁 腳位接地。此時,該記憶單元之電源由該電腦系統提供, 在此狀況下,即使停止提供電源給該電子系統,該雷腦系 統仍可讀寫該電子系統之記憶單元。 【實施方式】 第1圖乃本發明所提出的寫入保護控制裝晉夕舍於 例,用以解說本發明之技術如何使用在一電子系統中二二 電子系統可為一影像顯示裝置或一影音顯示裝置。兮恭茨 系統之連接單元可為一 D_sub、——數位視覺介面連接=、 或一高解析多媒體影音端子。此實施例以—D_sub 電子系統之連接單元。 人 一寫入保護控制裝置包括一偵測腳位1〇 —切捧單The electronic system can be an image display device or a video display device, and the connection unit can be a D-sub, a digital visual interface (Digitai Visual InterfaCe, DVI) connector, or a high-resolution multimedia audio and video terminal (High Definition Multimedia). Interface, HDMI). The present invention also provides a control method for controlling the write protection pin of the memory unit of the electronic system. The memory unit can be read and written when the potential of the protection pin is equal to a reference potential. When there is no power supply to the electronic system, the control method can provide power to a memory unit in the electronic system by a computer system externally connected to the electronic system, and the memory unit is replaced by a switching unit in the electronic system The write protection pin value is connected to the reference potential, so that a computer system externally connected to the electronic system can still read and write the § memory unit. If a power source is supplied to a processing unit of the electronic system, the control method causes the processing unit to control the write tank position of the memory unit to determine whether to read or write the memory unit. The reference potential mentioned in the above control method can be a ground. When the electronic system is activated and in normal use, if the electronic system produces 0535-A21333TWF(N2); A05599; GLORIOUS 9 200807436 to the computer system, the detection pin of the electronic system is grounded, and the transistor of the switching unit is turned off. . At this time, if power is supplied to the processing unit of the electronic system, the write protection pin of the memory is controlled by the processing unit. At the factory end, the electronic system is externally connected to a computer system, and when the data of the snow-brain system is to be burned to the memory of the electronic system, if the supply of the lightning source is stopped to the electronic system and the detection of the electronic system is performed, When the bit is changed to float, the transistor of the switching unit is turned on, so that the writing pin of the electronic device is grounded. At this time, the power of the memory unit is provided by the computer system. In this case, even if power supply to the electronic system is stopped, the lightning system can read and write the memory unit of the electronic system. [Embodiment] FIG. 1 is an example of a write protection control device proposed by the present invention for explaining how the technology of the present invention can be used in an electronic system. The two-two electronic system can be an image display device or a Audio and video display device. The connection unit of the system can be a D_sub, a digital visual interface connection =, or a high resolution multimedia audio and video terminal. This embodiment is a connection unit of the -D_sub electronic system. A write protection control device includes a detection pin 1〇

元104、以及一處理器106。微處理器1〇6 A 茨包子糸統中 的處理單元。偵測腳位102即D_sub(108)之偵測插拔腳位。 切換早元104輕接於债測腳位1〇2與一記憶單元^ 入保護腳位WP之間。寫入保護腳位wp亦耦接微處 106。該寫入保護控制裝置乃用來控制記憶單元的寫:Element 104, and a processor 106. The processing unit in the microprocessor 1〇6 A 包包子糸. The detection pin 102 is the detection pin of the D_sub (108). Switching early 104 is lightly connected between the debt measuring pin 1〇2 and a memory unit ^input protection pin WP. The write protection pin wp is also coupled to the micro 106. The write protection control device is used to control the writing of the memory unit:

0535-'A21333TWF(N2);A05599;GLORiOUS 200807436 保護功能。本實施例所使用的記憶單元1ι〇為一種泰子弋 可抹除可編程唯讀記憶體(臓OM)、項將;護; 位WP接地,方能正常讀寫記憶單元11〇。 二·:⑽鳩接一主機.(未顯示在_中)並且輕接該主 威之龟源poweri。微處理器106所需要 . 〕楚源必須由電子 π…元之%源p〇Wer2提供。電源p0weri與p〇wer9 一 土之一 會負責提供電源給記憶單元110。電源端點112與了 14所 耦接的電源與記憶單元110所使用的電源相同。D_sub(i〇8)0535-'A21333TWF(N2); A05599; GLORiOUS 200807436 protection function. The memory unit 1 ι used in this embodiment is a kind of taizi 弋 erasable programmable read only memory (臓OM), item will be protected; bit WP is grounded, and the memory unit 11 can be read and written normally. Two: (10) Connected to a host. (Not shown in _) and lightly connected to the main source of the turtle. Required by the microprocessor 106.] Chu source must be provided by the source of the electronic π... element p〇Wer2. One of the power sources p0weri and p〇wer9 will be responsible for supplying power to the memory unit 110. The power supply terminal 112 and the power source coupled to the 14 are the same as those used by the memory unit 110. D_sub(i〇8)

之腳位116與118分別耦接至記憶單元11〇之腳位SCL與 SDA。 切換罩元104中包括一開關(即電晶體qi)、一第一電 阻R1、一第二電阻R2、一第三電阻R3、以及一齊納二極 體Z1。電晶體qi之集極與射極分別耦接寫入保護腳位 WP與一參考電位(此例中,參考電位為地端groimd)。第一 電阻R1.耦接在偵測腳位1〇2與電晶體Q1之基極之間。第 二電阻R2與第三電阻R3之第一端皆耦接至電源端點 112。第二電阻R2與第三電阻R3之第二端分別耦接電晶 體Q1之集極與偵測腳位102。齊納二極體Z1之陽極接地、 陰極耦接偵測腳位102。 當D-sub(108)所連接的主機為一種影像輸出裝置(例如 個人電腦/PC)時,該影像輸出裝置會將偵测插拔腳位(即 1〇2)輕接至地端(ground),以標示該電子系統已搞接至該影 像輸出裝置,該偵測腳位102乃處於一第一狀態,切換單 元104會以一第一模式運作,電晶體qi不導通。此時, 0535-A21333TWF(N2);A05599;GLORIOUS 11 200807436 若微處理器之電源power2處於供電狀態,記憶單元11〇 之寫入保護功能乃由微處理器1〇6控制。 當D-sub( 108)所連接的主機為一實驗平台(例如工廠中 的機台,用以燒錄出廠程式於記憶單元11〇)時,D_sub(1〇g) 之偵測插拔腳位為浮接,該偵測腳位1〇2處於一第二狀 態,切換單元104以一第二模式運作,電晶體Q1導通並 且將寫入係護腳位WP接地。此時,即使微處理器之電源 power2停止供電,記憶單元11〇仍可被正常讀寫。為了浮 | 接該偵測腳位,必須拔除該實驗平台之連接單元中對應該 D-sub(108)之偵測插拔腳位的針腳。 在第1圖中,切換單元104可以其他電路代替,只要 該電路在該第二模式運作時,能將寫入保護 至該參考電位,在該第一模式運作時,能將寫入 WP的控制權交還給微處理器106。 个發明所提出的舄入保護控制裝置並非僅侷限在影音 電子系統的應用,亦可應用在其他種類的電子系統中:二 _ 疋茜要叨換其5己早元之寫入保護腳位之控制^法的雷7 系統,皆可將本發明之技術應用在其中,並且,任何 本技術的電子系統皆屬於本說明書所欲保護的範疇。 0535-A21333TWF(N2);A05599;GLORI〇US 12 200807436 【圖式簡單說明】 第1圖為本發明之實施例。 【主要元件符號說明】 102〜偵測腳位; 104〜切換單元; 106〜微處理器; 108〜D-sub ; _ 110〜記憶單元; 112、114〜電源端點; 116、118〜D-sub 腳位; powerl〜D-sub(108)所連接之主機所提供的電源; power2〜微處理器106所使用的電源;The pins 116 and 118 are respectively coupled to the pins SCL and SDA of the memory unit 11 . The switching cover unit 104 includes a switch (i.e., transistor qi), a first resistor R1, a second resistor R2, a third resistor R3, and a Zener diode Z1. The collector and the emitter of the transistor qi are respectively coupled to the write protection pin WP and a reference potential (in this example, the reference potential is the ground groimd). The first resistor R1 is coupled between the detecting pin 1〇2 and the base of the transistor Q1. The first ends of the second resistor R2 and the third resistor R3 are coupled to the power supply terminal 112. The second ends of the second resistor R2 and the third resistor R3 are coupled to the collector and the detection pin 102 of the electric crystal Q1, respectively. The anode of the Zener diode Z1 is grounded and the cathode is coupled to the detection pin 102. When the host connected to the D-sub (108) is an image output device (such as a personal computer/PC), the image output device will lightly connect the detection pin (ie, 1 〇 2) to the ground (ground). To indicate that the electronic system has been connected to the image output device, the detection pin 102 is in a first state, the switching unit 104 operates in a first mode, and the transistor qi is not turned on. At this time, 0535-A21333TWF(N2); A05599; GLORIOUS 11 200807436 If the power supply 2 of the microprocessor is in the power supply state, the write protection function of the memory unit 11 is controlled by the microprocessor 1〇6. When the host connected to the D-sub (108) is an experimental platform (for example, a machine in the factory for burning the factory program in the memory unit 11), the detection pin of the D_sub (1〇g) is Floating, the detecting pin 1 〇 2 is in a second state, the switching unit 104 operates in a second mode, the transistor Q1 is turned on and the writing keeper pin WP is grounded. At this time, even if the power supply 2 of the microprocessor stops supplying power, the memory unit 11 can be normally read and written. In order to float the pin, the pin of the connection unit of the experimental platform corresponding to the detection pin of the D-sub (108) must be removed. In FIG. 1, the switching unit 104 can be replaced by other circuits, as long as the circuit can protect the write to the reference potential when the second mode is operated, and can write the control of the WP when the first mode is operated. The right is returned to the microprocessor 106. The intrusion protection control device proposed by the invention is not limited to the application of the audio-visual electronic system, but can also be applied to other kinds of electronic systems: the second _ 叨 叨 其 5 5 5 5 5 5 The Ray 7 system of the control method can be applied to the technology of the present invention, and any electronic system of the present technology belongs to the scope of the present specification. 0535-A21333TWF(N2); A05599; GLORI〇US 12 200807436 [Simplified Schematic] FIG. 1 is an embodiment of the present invention. [Main component symbol description] 102~Detecting pin position; 104~Switching unit; 106~Microprocessor; 108~D-sub; _110~memory unit; 112,114~power terminal; 116,118~D- Sub pin; power supply provided by the host connected to powerl~D-sub(108); power2~ power supply used by microprocessor 106;

Rl、R2、R3〜第一、第二、第三電阻; Q1〜電晶體; Z1〜背納二極體。 * 0535-A21333TWF(N2);A05599;GLORIOUS 13Rl, R2, R3 ~ first, second, third resistance; Q1 ~ transistor; Z1 ~ back nano diode. * 0535-A21333TWF(N2); A05599; GLORIOUS 13

Claims (1)

200807436 十、申請專利範圍: ^一種寫人保護控制裝置,用以控制-記憶單元的寫 入保諼功能,其中該寫人保護控制裝置包括: ’ 一连接單元,係具有一偵測腳位; 一/刀換單元,耦接於該偵測腳位與該記憶單元的—合 入1缦聊攸之間;以及 Μ .處α早元,輕接該寫入係護腳位; 一=1’該偵測聊位處於—第—狀態時,該切換單元以 一 ΐ 一料3^作’此時’若有電源供電給該處理單元,則 該馬^保護腳位由該處理單姑制;該偵測腳位處於―第 二狀㈣,該切換單元以—第二模式運作,此時,若没^ 電源供電給該處理單S,則該寫人保護腳位由該切換單元 υ>反之|有包源供電給該處理單元之狀態,則該寫 入保護腳位由該處理單元控制。 〜”、 料利範圍第1項所述之寫人保護控制裝置, =吳早凡包括—開關,該開關位於該寫人保護腳位 與一麥L之間,當該切換單μ該第—模^ 該,關不料」料讀單元㈣第二模式運作時,該開 關導通亚且將該寫人保護腳位_接至該參考· ·呈击, 該寫入保護腳位_接至該參考 ^、^’ 正常讀寫。 成忑早兀可被 甘士^如中租專利乾圍帛2項所述之寫人係護控制F m, p 且執接在該债 該第 ,、忒開關為一電晶體,該切換單元更包括二呈 一第二電阻、以及一第三電阻 龟阻 0535-A21333TWF(N2);A05599;GLORIOUS 14 200807436 腳位與該電晶體之基極之間,該第二電阻與該第三電阻之 第一端皆耦接至一電源.,該第二電阻與該第三電阻之第二 端分別耦接至該電晶體之集極與該偵測腳位,該電晶體之 集極與射極分別耦接該寫入保護腳位與該參考電位。 4·如申請專利範圍第3項所述之寫入保護控制裝置, 其中該切換單元更包括一齊納二極體,該齊納二極體之陽 極與陰極分別耦接至該參考電位以及該偵測腳位。 5·如申‘寸利乾圍弟2項所述之寫入保護控制裝置, _ 其中該參考電位可為一接地端(gTOUnd)。 6·如申請專利範圍第丨項所述之寫入保護控制裝置, 該偵測腳位耦接至該參考電位時處於該第_ · 腳位為浮接時處於該第二狀態。 …“貝4 7·如申請專利範圍第i項所述之寫入保護控制裝置, 其中喊圮億早元為一電子式可抹除可編程唯讀記懷體。 8·如申請專利範圍第丨項所述之寫入保護控制妒置, 可設置於-電子系統中,該電子系統可為_影像顯^裝置 ’或一影音顯示裝置,該連接單元可為一 D_sub、一數位視 覺介面連接器、或一高解析多媒體影音端子。 9· 一種寫入保護控制方法,用以控制一記憶單元的寫 入保瘦功能,其中包括_偵測腳位、.一切換單元、一記情 體之一寫入保護腳位以及一處理單元,其方法包括:〜 當該偵測腳位處於浮接狀態沒有電源供電給該處理單 7G時,藉由該切換單元將該寫入保護腳位連接至一參考雷 位,使該記鮮元仍可被讀寫,其中,該寫人保護腳位^ 0535- A21333TWF(N2);A05599;GL〇R1〇US 200807436 電位等於該參考電位時,該記憶單元可被讀寫;以及 t該侧驗處於浮錄態並且有電源供電給該處理 單元時,則由該處理單元控制該寫入保護腳位,以決定是 否讀寫該記憶單元。 10·如申請專利範圍第9項所述之寫入保護控制方法, 其中當該镇測腳位連接至一參考電位必且有電源供電給該 處理單元時,由該處理單元控制該寫入保護腳位,以決定 是否讀寫該記憶單元。 • Π·如申請寻利範圍第9項所述之寫入保護控制方法, 其中更包括-連接單元,用以外接一電腦系統,該偵測腳 位設置於該連接單元上。 12·如申請專利範圍第9項所述之寫入保護控制方法, 其中該切換早元包括一電晶體、一第一電阻、一第二電阻、 以及一第二電阻,該第一電阻韓接在該偵測腳位與該電晶 體之基極之間,該第二電阻與該第三電阻之第一端皆耦接 主一電源,緣第二電阻與該第三電阻之第二端分別耦接至 書 該電晶體之集極與該偵測腳位,該電晶體之集極與射極分 別耦接該寫入保護腳位與該參考電位。 13·如申請專利範圍第12項所述之寫入保護控制方 法,可藉由浮接該偵測腳位令該電晶體導通,使該寫入保 護腳位連接至該參考電位。 14·如申請專利範圍第9項所述之寫入保護控制方法, 其中上述參考電位即一接地端(ground)。 0535-A21333TWF(N2);A05599;GLORiOUS 16200807436 X. Patent application scope: ^ A write protection control device for controlling the write protection function of the memory unit, wherein the write protection control device comprises: 'a connection unit having a detection pin position; a / knife changing unit, coupled between the detecting pin and the memory unit - into a chat; and Μ at a early element, lightly connected to the writing system foot; a = 1 'When the detection chat bit is in the -state state, the switching unit uses the same material 3^ as 'this time'. If there is power supply to the processing unit, the protection pin is processed by the processing unit. The detection pin is in the second shape (four), and the switching unit operates in the second mode. At this time, if the power supply is not supplied to the processing unit S, the writer protection pin is controlled by the switching unit. On the other hand, if there is a state in which the packet source is supplied to the processing unit, the write protection pin is controlled by the processing unit. ~", the profit protection range mentioned in item 1 of the protection protection device, = Wu Zaofan includes - switch, the switch is located between the writer protection pin and a wheat L, when the switch single μ the first mode ^ In the second mode of operation, the switch is turned on and the write protection pin is connected to the reference. The write protection pin is connected to the reference ^, ^' Normal reading and writing. Cheng Yu early can be replaced by the Gans ^ ^ as the patent of the Chinese patent for the second-party patent, the control system F m, p and the connection to the debt, the switch is a transistor, the switching unit The second resistor and the third resistor are respectively included in the second resistor and the third resistor, and the third resistor is 0535-A21333TWF (N2); A05599; GLORIOUS 14 200807436 is between the pin and the base of the transistor. The first end is coupled to a power source, and the second end of the second resistor and the second end of the third resistor are respectively coupled to the collector of the transistor and the detecting pin, the collector and the emitter of the transistor The write protection pin and the reference potential are respectively coupled. 4. The write protection control device according to claim 3, wherein the switching unit further comprises a Zener diode, and the anode and the cathode of the Zener diode are respectively coupled to the reference potential and the Detector Measuring foot position. 5. For example, the write protection control device described in the 2nd article of the Instinct, _ wherein the reference potential can be a ground terminal (gTOUnd). 6. The write protection control device as described in claim 2, wherein the detection pin is coupled to the reference potential and is in the second state when the first pin is floating. ..."Bei 4 7 · The write protection control device described in item i of the patent application scope, wherein the shouting is as long as an electronic erasable programmable read-only memory. The write protection control device described in the above item may be disposed in an electronic system, and the electronic system may be an image display device or a video display device, and the connection unit may be a D_sub, a digital visual interface connection. Or a high-resolution multimedia audio and video terminal. 9. A write protection control method for controlling the write-storing function of a memory unit, including _detecting a pin, a switching unit, and a genre a write protection pin and a processing unit, the method comprising: - when the detection pin is in a floating state and no power is supplied to the processing unit 7G, the write protection pin is connected to the switch unit by the switching unit A reference lightning position, so that the fresh element can still be read and written, wherein the write protection pin ^ 0535- A21333TWF (N2); A05599; GL 〇 R1 〇 US 200807436 when the potential is equal to the reference potential, the memory unit Can be read and written; and t the side When in the floating state and power is supplied to the processing unit, the write protection pin is controlled by the processing unit to determine whether to read or write the memory unit. 10. Write as described in claim 9 The protection control method, wherein when the test pin is connected to a reference potential and a power supply is supplied to the processing unit, the write protection pin is controlled by the processing unit to determine whether to read or write the memory unit. The write protection control method described in claim 9 of the application for profit detection, which further includes a connection unit, which is connected to a computer system, and the detection pin is disposed on the connection unit. The write protection control method of claim 9, wherein the switching element comprises a transistor, a first resistor, a second resistor, and a second resistor, wherein the first resistor is connected to the detection pin The first end of the second resistor and the third resistor are coupled to the main power source, and the second end of the second resistor and the second end of the third resistor are respectively coupled to the book. The collector of the crystal Detecting a pin, the collector and the emitter of the transistor are respectively coupled to the write protection pin and the reference potential. 13· The write protection control method described in claim 12 of the patent can be floated Connecting the detection pin to turn on the transistor to connect the write protection pin to the reference potential. The write protection control method according to claim 9, wherein the reference potential is a ground Ground. 0535-A21333TWF(N2);A05599;GLORiOUS 16
TW95126198A 2006-07-18 2006-07-18 Write protect controller and control method thereof TWI300940B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI451424B (en) * 2009-04-17 2014-09-01 Mstar Semiconductor Inc Protecting circuit and power supply system for flash memory
CN106779025A (en) * 2016-12-09 2017-05-31 杭州佩安科技有限公司 A kind of new non-volatile anti-alterable storage

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI451424B (en) * 2009-04-17 2014-09-01 Mstar Semiconductor Inc Protecting circuit and power supply system for flash memory
CN106779025A (en) * 2016-12-09 2017-05-31 杭州佩安科技有限公司 A kind of new non-volatile anti-alterable storage
CN106779025B (en) * 2016-12-09 2024-04-19 杭州佩安科技有限公司 Novel nonvolatile anti-rewriting memory

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