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TW200746949A - Method of manufacturing terminal set of circuit board - Google Patents

Method of manufacturing terminal set of circuit board

Info

Publication number
TW200746949A
TW200746949A TW096109872A TW96109872A TW200746949A TW 200746949 A TW200746949 A TW 200746949A TW 096109872 A TW096109872 A TW 096109872A TW 96109872 A TW96109872 A TW 96109872A TW 200746949 A TW200746949 A TW 200746949A
Authority
TW
Taiwan
Prior art keywords
terminals
circuit board
terminal group
solder
layer
Prior art date
Application number
TW096109872A
Other languages
Chinese (zh)
Other versions
TWI328985B (en
Inventor
Kazuo Inoue
Takashi Fujimura
Original Assignee
Nippon Mektron Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2006106128A external-priority patent/JP4936771B2/en
Priority claimed from JP2006138215A external-priority patent/JP4831819B2/en
Application filed by Nippon Mektron Kk filed Critical Nippon Mektron Kk
Publication of TW200746949A publication Critical patent/TW200746949A/en
Application granted granted Critical
Publication of TWI328985B publication Critical patent/TWI328985B/zh

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

To provide a terminal group manufacturing method of a circuit board which equalizes thickness of solder precoat layer formed on each terminal front surface in the terminal group even for the terminals with narrow pitch, in the method of forming a solder precoat layer on the front surface of the terminal group consisting of two or more terminals for mounting components prepared in the circuit board. An interconnect portion 10 composed of the same material as the material of terminals 2a and 2b is formed beforehand so as to connect respectively the terminals 2a and 2b which face each other on an insulating substrate 1. A solder layer 5 is formed on the surface of the terminal group including this interconnect portion 10. A solder precoat layer 6 is formed by heating and melting this solder layer 5, and then the unnecessary portion between the terminals 2a and 2b is cut and removed.
TW096109872A 2006-04-07 2007-03-22 Method of manufacturing terminal set of circuit board TW200746949A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006106128A JP4936771B2 (en) 2006-04-07 2006-04-07 Circuit board terminal group manufacturing method
JP2006138215A JP4831819B2 (en) 2006-05-17 2006-05-17 Circuit board terminal group manufacturing method

Publications (2)

Publication Number Publication Date
TW200746949A true TW200746949A (en) 2007-12-16
TWI328985B TWI328985B (en) 2010-08-11

Family

ID=45074451

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096109872A TW200746949A (en) 2006-04-07 2007-03-22 Method of manufacturing terminal set of circuit board

Country Status (1)

Country Link
TW (1) TW200746949A (en)

Also Published As

Publication number Publication date
TWI328985B (en) 2010-08-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees