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TW200741921A - Chip package and method for fabricating the same - Google Patents

Chip package and method for fabricating the same

Info

Publication number
TW200741921A
TW200741921A TW096107211A TW96107211A TW200741921A TW 200741921 A TW200741921 A TW 200741921A TW 096107211 A TW096107211 A TW 096107211A TW 96107211 A TW96107211 A TW 96107211A TW 200741921 A TW200741921 A TW 200741921A
Authority
TW
Taiwan
Prior art keywords
metal pad
bonded
chip package
another case
fabricating
Prior art date
Application number
TW096107211A
Other languages
Chinese (zh)
Other versions
TWI427718B (en
Inventor
Chien-Kang Chou
Chiu-Ming Chou
Li-Ren Lin
Hsin-Jung Lo
Original Assignee
Megica Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megica Corp filed Critical Megica Corp
Publication of TW200741921A publication Critical patent/TW200741921A/en
Application granted granted Critical
Publication of TWI427718B publication Critical patent/TWI427718B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate, In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In, another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.
TW096107211A 2006-03-02 2007-03-02 Chip package and method for fabricating the same TWI427718B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76708006P 2006-03-02 2006-03-02

Publications (2)

Publication Number Publication Date
TW200741921A true TW200741921A (en) 2007-11-01
TWI427718B TWI427718B (en) 2014-02-21

Family

ID=48087818

Family Applications (2)

Application Number Title Priority Date Filing Date
TW096107211A TWI427718B (en) 2006-03-02 2007-03-02 Chip package and method for fabricating the same
TW096107214A TWI376758B (en) 2006-03-02 2007-03-02 Chip package and method for fabricating the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW096107214A TWI376758B (en) 2006-03-02 2007-03-02 Chip package and method for fabricating the same

Country Status (1)

Country Link
TW (2) TWI427718B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7615407B1 (en) * 2008-07-02 2009-11-10 National Semiconductor Corporation Methods and systems for packaging integrated circuits with integrated passive components

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI317548B (en) * 2003-05-27 2009-11-21 Megica Corp Chip structure and method for fabricating the same

Also Published As

Publication number Publication date
TWI376758B (en) 2012-11-11
TWI427718B (en) 2014-02-21
TW200741922A (en) 2007-11-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees